W981616AH 512K x 2 BANKS x 16 BITS SDRAM GENERAL DESCRIPTION W981616AH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 512K words x 2 banks x 16 bits. Using pipelined architecture and 0.20 m process technology, W981616AH delivers a data bandwidth of up to 332M bytes per second (-6). For different applications the W981616AH is sorted into the following speed grades: -6, -7, and -8. Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time. By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W981616AH is ideal for main memory in high performance applications. FEATURES * * * * * * 3.3V 0.3V power supply Up to 166 MHz clock frequency 524,288 words x 2 banks x 16 bits organization Auto Refresh and Self Refresh CAS latency: 2 and 3 Burst Length: 1, 2, 4, 8, and full page * * * * * * Burst read, Single Write Mode Byte data controlled by UDQM and LDQM Auto-precharge and controlled precharge 4K refresh cycles/64 mS Interface: LVTTL Packaged in 50-pin, 400 mil TSOP II PIN CONFIGURATION VCC 1 50 VSS DQ0 2 49 DQ15 DQ1 3 48 DQ14 VSS Q 4 47 VSS Q DQ2 5 46 DQ13 DQ3 6 45 DQ12 VCCQ 7 44 VCCQ DQ4 8 43 DQ11 DQ5 9 42 DQ10 VSS Q 10 41 VSS Q DQ6 11 40 DQ9 DQ7 12 39 DQ8 VCCQ 13 38 VCC Q LDQM 14 37 NC WE 15 36 UDQM CAS 16 35 CLK RAS 17 34 CKE CS 18 33 NC BA 19 32 A9 A10 20 31 A8 A0 21 30 A7 A1 22 29 A6 A2 23 28 A5 A3 24 27 A4 VCC 25 26 V SS -1- Publication Release Date: February 2000 Revision A2 W981616AH PIN DESCRIPTION PIN NUMBER 20-24, 27-32 19 PIN NAME FUNCTION DESCRIPTION A0-A10 Address BA Bank Select Multiplexed pins for row and column address. Row address: A0-A10. Column address: A0-A7. Select bank to activate during row address latch time, or bank to read/write during column address latch time. 2, 3, 5, 6, 8, 9, DQ0-DQ15 11, 12, 39, 40, 42, 43, 45, 46, 48, 49 Data Input/ Output Multiplexed pins for data input and output. 18 CS Chip Select Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. 17 RAS Row Address Strobe 16 CAS 15 WE Write Enable Referred to RAS UDQM/ LDQM Input/Output Mask The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. 35 CLK Clock Inputs System clock used to sample inputs on the rising edge of clock. 34 CKE Clock Enable CKE controls the clock activation and deactivation. W hen CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. 1, 25 VCC Power (+3.3V) Power for input buffers and logic circuit inside DRAM. 26, 50 VSS 36, 14 Command input. When sampled at the rising edge of the clock, RAS , CAS and WE define the operation to be executed. Column Referred to RAS Address Strobe Ground Ground for input buffers and logic circuit inside DRAM. 7, 13, 38, 44, VCCQ Power (+3.3V) Separated power from VCC, used for output buffers to for I/O buffer improve noise immunity. 4, 10, 41, 47 VSSQ Ground for I/O Separated ground from VSS, used for output buffers buffer to improve noise immunity. 33, 37 NC No Connection No connection -2- W981616AH BLOCK DIAGRAM CLK CLOCK BUFFER CKE CS CONTROL SIGNAL RAS CAS GENERATOR COMMAND DECODER COLUMN DECODER R O W CELL ARRAY D E C O D E R WE BANK #0 SENSE AMPLIFIER A10 MODE REGISTER A0 A9 BA ADDRESS BUFFER DQ BUFFER DATA CONTROL CIRCUIT DQ0 DQ15 LDQM UDQM REFRESH COUNTER COLUMN COUNTER COLUMN DECODER R O W D E C O D E R CELL ARRAY BANK #1 SENSE AMPLIFIER Note: The cell array configuration is 2048 * 256 * 16 -3- Publication Release Date: February 2000 Revision A2 W981616AH FUNCTIONAL DESCRIPTION Power Up and Initialization The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs during power up, all VCC and VCCQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power up voltage must not exceed VCC +0.3V on any of the input pins or VCC supplies. After power up, an initial pause of 200 S is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation. Programming Mode Register After initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS , CAS , CS and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table. Bank Activate Command The Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank-to-Bank delay time (tRRD). The maximum time that each bank can be held active is specified as tRAS(max.). Read and Write Access Modes After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level defines whether the access cycle is a read operation ( WE high), or a write operation ( WE low). The address inputs determine the starting column address. Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle. -4- W981616AH Burst Read Command The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequence mode. Burst Write Command The Burst Write command is initiated by applying logic low level to CS , CAS and WE while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored. Read Interrupted by a Read A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command the is satisfied. Read Interrupted by a Write To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed. Write Interrupted by a Write A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. Write Interrupted by a Read A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored. Burst Stop Command A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst -5- Publication Release Date: February 2000 Revision A2 W981616AH Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock. The data DQs go to a high impedance state after a delay, which is equal to the CAS Latency in a burst read cycle, interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored. Addressing Sequence of Sequential Mode A column access is performed by increasing the address from the column address, which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2. Table 2 Address Sequence of Sequential Mode DATA Access Address Burst Length Data 0 n BL = 2 (disturb address is A0) Data 1 n+1 No address carry from A0 to A1 Data 2 n+2 BL = 4 (disturb addresses are A0 and A1) Data 3 n+3 No address carry from A1 to A2 Data 4 n+4 Data 5 n+5 BL = 8 (disturb addresses are A0, A1 and A2) Data 6 n+6 No address carry from A2 to A3 Data 7 n+7 Addressing Sequence of Interleave Mode A column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3. Table 3 Address Sequence of Interleave Mode DATA Access Address Bust Length Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 2 Data 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 2 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 3 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 4 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 5 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 6 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 7 A8 A7 A6 A5 A4 A3 A2 A1 A0 -6- BL = 4 BL = 8 W981616AH Auto-precharge Command If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS latency. A Read or Write Command with auto-precharge can not be interrupted before the entire burst operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-Precharge command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation one clock delay from the last burst write cycle. This delay is referred to as Write tDPL. The bank undergoing auto-precharge can not be reactivated until tDPL and tRP are satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tDPL + tRP). When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS(min). Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when CS , RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, and BA, are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP). Self Refresh Command The Self-Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self-Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self-Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self-Refresh Operation to save power. The device will exit Self-Refresh operation after CKE is returned high. Any subsequent commands can be issued after tRC from the end of Self Refresh command. If, during normal operation, Auto-Refresh cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 Auto-Refresh cycles should be completed just prior to entering and just after exiting the Self-Refresh mode. Power Down Mode The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations; therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the device. -7- Publication Release Date: February 2000 Revision A2 W981616AH The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on tCK. The input buffers need to be enabled with CKE held high for a period equal to tCES(min) + tCK(min). No Operation Command The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS , CAS , and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. Deselect Command The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS , CAS , and WE signals become don't cares. Clock Suspend Mode During normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. There is a one-clock delay between the registration of CKE low and the time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one-clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. -8- W981616AH TABLE OF OPERATING MODES Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands. TABLE 1 TRUTH TABLE (NOTE 1, 2) Command Device State CKEn-1 CKEn DQM BA A10 A9-0 CS RAS CAS WE V V L L H H Bank Active Idle H X X V Bank Precharge Any H X X V L X L L H L Precharge All Any H X X X H X L L H L Write Active (3) H X X V L V L H L L Write with Autoprecharge Active (3) H X X V H V L H L L Read Active (3) H X X V L V L H L H Read with Autoprecharge Active (3) H X X V H V L H L H Mode Register Set Idle H X X V V V L L L L No-Operation Any H X X X X X L H H H Active (4) H X X X X X L H H L Device Deselect Any H X X X X X H X X X Auto-Refresh Idle H H X X X X L L L H Self-Refresh Entry Idle H L X X X X L L L H Self-Refresh Exit Idle (S.R) L L H H X X X X X X X X H L X H X H X X Clock Suspend Mode Entry Active H L X X X X X X X X Idle Active (5) H H L L X X X X X X X X H L X H X H X X Clock Suspend Mode Exit Active L H X X X X X X X X Power Down Mode Exit Any (Power down) L L H H X X X X X X X X H X X X L H H X Data Write/Output Enable Active H X L X X X X X X X Data Write/Output Disable Active X H X X X X X X X Burst Stop Power Down Mode Entry H Notes: (1) V = Valid, X = Don't care, L = Low Level, H = High Level (2) CKEn signal is input level when commands are provided. (3) These are state of bank designated by BA signals. (4) Device state is full page burst operation. (5) Power Down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode. -9- Publication Release Date: February 2000 Revision A2 W981616AH ABSOLUTE MAXIMUM RATINGS PARAMETER Input, Output Voltage SYMBOL VIN, VOUT RATING Power Supply Voltage VCC, VCCQ Operating Temperature TOPR Storage Temperature TSTG -0.3 - 4.6 -0.3 - 4.6 Soldering Temperature (10s) TSOLDER 0 - 70 -55 - 150 260 Power Dissipation Short Circuit Output Current PD IOUT 1 50 UNIT V NOTES 1 V 1 C 1 C 1 C 1 W mA 1 1 Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. RECOMMENDED DC OPERATING CONDITIONS (TA = 0 to 70C) PARAMETER SYM. MIN. TYP. MAX. UNIT NOTES VCC 3.0 3.3 3.6 V 2 VCCQ 3.0 3.3 3.6 V 2 Input High Voltage VIH 2.0 - VCC +0.3 V 2 Input Low Voltage VIL -0.3 - 0.8 V 2 Power Supply Voltage Power Supply Voltage (for I/O Buffer) Note: VIH (max.) = VCC/VCCQ +1.2V for pulse width < 5 nS VIL (min.) = VSS/VSSQ -1.2V for pulse width < 5 nS CAPACITANCE (VCC = 3.3V, TA = 25 C, f = 1MHz) PARAMETER Input Capacitance (A0 to A10, BA, CS , RAS , CAS , WE , UDQM, LDQM, CKE) SYM. MIN. MAX. UNIT CI - 4 pf - 4 pf - 6.5 pf Input Capacitance (CLK) Input/Output capacitance (DQ0 to DQ15) CIO Note: These parameters are periodically sampled and not 100% tested - 10 - W981616AH DC CHARACTERISTICS (VCC = 3.3V 0.3V, TA = 0~70C) PARAMETER Operating Current tCK = min., t RC = min. Active precharge command cycling without burst operation Standby Current SYM. 1 bank operation ICC1 -6 MAX. 100 -7 MAX. 90 -8 MAX. 80 UNIT NOTES mA 3 CKE = VIH ICC2 50 45 40 3 CKE = VIL ICC2P 2 2 2 3 CKE = VIH ICC2S 10 8 6 CKE = VIL ICC2PS 2 2 2 CKE = VIH ICC3 55 50 45 CKE = VIL ICC3P 5 5 5 ICC4 130 110 100 3, 4 ICC5 90 80 70 3 ICC6 2 2 2 tCK = min., CS = VIH VIH /L = VIH (min.) /VIL (max.) Bank: inactive state (Power down mode) Standby Current CLK = VIL, CS = VIH VIH/L = VIH (min.) /V IL (max.) Bank: inactive state (Power down mode) No Operating Current tCK = min., CS = VIH (min.) Bank: active state (2 banks) (Power Down mode) Burst Operating Current (t CK = min.) Read/ Write command cycling Auto Refresh Current (t CK = min.) Auto refresh command cycling Self Refresh Current (CKE = 0.2V) Self refresh mode SYM. MIN. MAX. UNIT Input Leakage Current (0V VIN VCC, all other pins not under test = 0V) PARAMETER II(L) -5 5 A Output Leakage Current (Output disable , 0V VOUT VCCQ ) IO(L) -5 5 A LVTTL OutputT H Level Voltage (I OUT = -2 mA) VOH 2.4 - V LVTTL Output L Level Voltage (I OUT = 2 mA) VOL - 0.4 V - 11 - NOTES Publication Release Date: February 2000 Revision A2 W981616AH AC CHARACTERISTICS (VCC = 3.3V 0.3V, VSS = 0V, TA = 0 to 70 C, Notes: 5, 6, 7, 8) PARAMETER SYM. -6 MIN. -7 MAX. MIN. -8 MAX. MAX. Ref/Active to Ref/Active Command Period tRC 60 Active to Precharge Command Period tRAS 42 Active to Read/Write Command Delay Time tRCD 18 20 20 Read/Write(a) to Read/Write(b)Command Period tCCD 1 1 1 Cycle Precharge to Active(b) Command Period tRP 18 20 20 nS Active(a) to Active(b) Command Period tRPD 12 14 16 Write Recovery Time tWR 10 10 10 6 7 8 CL* = 2 CL* = 3 CLK Cycle Time CL* = 2 tCK CL* = 3 70 MIN. UNIT 100000 48 72 100000 48 1000 10 1000 10 1000 6 1000 7 1000 8 1000 tCH 2.5 3 3 CLK Low Level Width tCL 2.5 3 3 CL* = 2 100000 10 CLK High Level Width Access Time from CLK nS tAC CL* = 3 7 7 7 5.5 5.5 6 Output Data Hold Time tOH 2 2.5 Output Data High Impedance Time tHZ 2 Output Data Low Impedance Time tLZ 0 Power Down Mode Entry Time tSB 0 6 0 7 0 8 Transition Time of CLK (Rise and Fall) tT 0.3 10 0.3 10 0.3 10 Data-in-Set-up Time tDS 1.5 2 2 Data-in Hold Time tDH 1 1 1 Address Set-up Time tAS 1.5 2 2 Address Hold Time tAH 1 1 1 CKE Set-up Time tCKS 1.5 2 2 CKE Hold Time tCKH 1 1 1 Command Set-up Time tCMS 1.5 2 2 Command Hold Time tCMH 1 1 1 Refresh Time tREF Mode Register Set Cycle Time tRSC 6 2.5 - 12 - 7 0 64 12 3 3 0 64 14 8 64 16 mS nS W981616AH Notes: 1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices. 2. All voltages are referenced to VSS 3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of tCK and tRC. 4. These parameters depend on the output loading conditions. Specified values are obtained with output open. 5. Power up sequence is further described in the "Functional Description" section. 6. AC test conditions. PARAMETER CONDITIONS Output Reference Level 1.4V/1.4V Output Load See diagram below Input Signal Levels 2.4V/0.4V Transition Time (Rise and Fall) of Input Signal 2 nS Input Reference Level 1.4V 1.4 V 50 ohms output Z = 50 ohms 30pF AC TEST LOAD 7. Transition times are measured between VIH and VIL. 8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level. - 13 - Publication Release Date: February 2000 Revision A2 W981616AH TIMING WAVEFORMS Command Input Timing tCL tCK tCH V IH CLK V IL tT t CMS t CMH tCMS tCMH tCMS tCMH t CMS tCMH tAS tAH tCMH CS RAS CAS WE A0-A10 BA tCKS tCKH tCKS tCKH tCKS CKE - 14 - tCKH tT tCMS W981616AH Read Timing Read CAS Latency CLK CS RAS CAS WE A0-A10 BA tAC t AC tLZ tHZ tOH tOH Valid Data-Out Valid Data-Out DQ Read Command Burst Length - 15 - Publication Release Date: February 2000 Revision A2 W981616AH Control Timing of Input/Output Data Input Data (Word Mask) CLK tCMS t CMH t CMH t CMS DQM t DS tDH t DS Valid Data-in DQ0 -15 t DH tDS Valid Data-in tDH t DS Valid Data-in tDH Valid Data-in (Clock Mask) CLK t CKH t CKS tDH tDS tCKH t CKS CKE tDS DQ0 -15 Valid Data-in tDH t DS Valid Data-in tDH t DS Valid Data-in tDH Valid Data-in Output Data (Output Enable) CLK tCMS tCMH tCMH tCMS DQM tAC tOH tOH tHZ tAC tOH Valid Data-Out DQ0 -15 Valid Data-Out tAC t LZ tAC tOH Valid Data-Out OPEN (Clock Mask) CLK tCKH tCKS tCKH t CKS CKE t AC tOH DQ0 -15 tAC t AC t OH tOH Valid Data-Out Valid Data-Out - 16 - tAC tOH Valid Data-Out W981616AH Mode Reqister Set Cycle tRSC CLK t CMS tCMH t CMS t CMH t CMS t CMH tCMS t CMH CS RAS CAS WE tAS A0-A10 BA tAH Register set data A0 A1 Burst Length A2 A3 Addressing Mode A4 A5 CAS Latency A6 A7 A0 "0" (Test Mode) A8 "0" Reserved A9 A0 WriteA0 Mode A10 "0" BA "0" Reserved A0 A2 0 0 0 0 1 1 1 1 A1 A0 0 A0 0 A0 1 A0 1 A0 0 A0 0 A0 1 A0 1 A0 0 1 0 1 0 1 0 1 next command Burst Length A0 A0 Sequential Interleave 1 1 2 2 4 4 A0 8 8 Reserved Reserved FullA0 Page A3 A0 0 A0 1 Addressing Mode Sequential Interleave A0 A4 A6 A5 0 0A0 0 0 0 1 0 1 0 0 1 1 1 0 0 CAS Latency Reserved A0 Reserved 2 3 Reserved A9 0 1 Single Write Mode Burst read and Burst write Burst read and single write - 17 - Publication Release Date: February 2000 Revision A2 W981616AH Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC RAS tRAS tRP tRAS tRAS tRP tRP tRAS CAS WE BA tRCD A10 RAa A0-A9 RAa tRCD tRCD RBb CBx RBb CAw tRCD RAc RBd RAc CAy RAe RBd CBz RAe DQM CKE tAC tAC DQ aw0 tRRD Bank #0 Active Bank #1 aw1 aw2 aw3 Precharge Active bx1 bx2 bx3 Active - 18 - cy1 cy2 cy3 tRRD Precharge Read Precharge Read tAC cy0 tRRD tRRD Read tAC bx0 Active Read Active W981616AH Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 11 10 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC RAS tRAS tRP tRAS tRAS tRP tRP tRAS CAS WE BA tRCD A10 RAa A0-A9 RAa tRCD tRCD RBb CAw tRCD CBx RBb RAe RBd RAc CAy RAc CBz RBd RAe DQM CKE tAC DQ t RRD Bank #0 Bank #1 Active aw1 aw2 aw3 bx0 Active AP* Active bx1 bx2 bx3 tAC cy0 cy1 tRRD tRRD Read tAC tAC aw0 cy3 dz0 tRRD Read AP* Read cy2 AP* Active Active Read * AP is the internal precharge start timing - 19 - Publication Release Date: February 2000 Revision A2 W981616AH Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CLK CS tRC tRC t RC RAS tRAS tRP tRAS t RP tRAS tRP CAS WE BA tRCD A10 A0-A9 tRCD RAa RAa tRCD RAc RBb CAx RBb CBy RAc CAz DQM CKE tAC DQ tAC ax0 ax1 tRRD Bank #0 Bank #1 Active ax2 ax3 ax4 ax6 by0 by1 by4 by5 by6 by7 tRRD Read Precharge ax5 tAC Precharge Active Read - 20 - Active Read Precharge CZ0 22 23 W981616AH Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK t RC CS tRC RAS tRAS tRP tRAS tRAS tRP CAS WE BA tRCD A10 RAa A0-A9 RAa tRCD tRCD RBb CAx RAc RBb RAc CBy CAz DQM CKE tCAC tCAC DQ ax0 ax1 ax2 tRRD Bank #0 Bank #1 Active ax3 ax4 ax5 ax6 ax7 by0 by1 tCAC by4 by5 by6 CZ0 tRRD AP* Read Active Active Read Read AP* * AP is the internal precharge start timing - 21 - Publication Release Date: February 2000 Revision A2 W981616AH Interleaved Bank Write (Burst Length = 8) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRAS tRP tRP tRAS CAS tRCD tRCD tRCD WE BA A10 A0-A9 RBb RAa RAa CAx RAc RBb CBy RAc CAz DQM CKE DQ ax0 ax1 ax4 ax5 ax6 ax7 by0 tRRD Bank #0 Bank #1 Active by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD Precharge Write Active Write - 22 - Active Write Precharge W981616AH Interleaved Bank Write (Burst Length = 8, Autoprecharge) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRP tRAS tRAS CAS WE BA tRCD A10 RAa A0-A9 RAa tRCD tRCD RBb CAx RAb CBy RBb CAz RAb DQM CKE DQ ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 tRRD Bank #0 Active Bank #1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD AP* Write Active Active Write AP* Write * AP is the internal precharge start timing - 23 - Publication Release Date: February 2000 Revision A2 W981616AH Page Mode Read (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CLK tCCD tCCD tCCD CS tRAS tRP tRAS tRP RAS CAS WE BA tRCD A10 RAa A0-A9 RAa tRCD RBb CAI RBb CBx CAm CAy CBz DQM CKE tAC DQ tAC tAC a0 a1 a2 a3 bx0 bx1 Ay0 tAC Ay1 Ay2 tAC am0 am1 am2 bz0 bz1 tRRD Bank #0 Bank #1 Active Read Read Active Read Read Precharge Read * AP is the internal precharge start timing - 24 - AP* bz2 bz3 23 W981616AH Page Mode Read/Write (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRAS tRP RAS CAS WE BA tRCD A10 A0-A9 RAa RAa CAx CAy DQM CKE tAC DQ tWR ax0 Q Q Bank #0 Active ax1 ax3 ax2 Q Q ax5 ax4 Q Q Read ay1 ay0 D D Write ay2 D ay4 ay3 D D Precharge Bank #1 - 25 - Publication Release Date: February 2000 Revision A2 W981616AH AutoPrecharge Read (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) CLK 0 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS tRC tRC RAS t RAS tRP tRAS t RP CAS WE BA t RCD A10 RAa A0-A9 RAa t RCD RAb CAw RAb CAx DQM CKE tAC DQ Bank #0 tAC aw0 Active Read aw1 AP* aw2 aw3 bx0 Active Read Bank #1 * AP is the internal precharge start timing - 26 - bx1 AP* bx2 bx3 W981616AH AutoPrecharge Write (Burst Length = 4) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC RAS tRAS tRP tRAS tRP CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11 RAa tRCD RAb CAw RAb RAc CAx RAc DQM CKE DQ Bank #0 aw0 Active Write aw1 aw2 bx0 aw3 AP* Active bx1 Write bx2 bx3 AP* Active Bank #1 Bank #2 Idle Bank #3 * AP is the internal precharge start timing - 27 - Publication Release Date: February 2000 Revision A2 W981616AH AutoRefresh Cycle (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK tRP tRC tRC CS RAS CAS WE BA A10 A0-A9 DQM CKE DQ All Banks Prechage Auto Refresh Auto Refresh (Arbitrary Cycle) - 28 - 21 22 23 W981616AH SelfRefresh Cycle (CLK = 100 MHz) 0 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRP RAS CAS WE BA A10 A0-A9 DQM tCKS tCKS tSB CKE tCKS DQ tRC Self Refresh Cycle All Banks Precharge No Operation Cycle Self Refresh Entry Arbitrary Cycle - 29 - Publication Release Date: February 2000 Revision A2 W981616AH Bust Read and Single Write (Burst Lenght = 4, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 6 5 7 8 9 11 10 12 13 14 15 16 17 18 19 21 20 CLK CS RAS CAS tRCD WE BA A10 RBa A0-A9 RBa CBv CBw CBx CBy CBz DQM CKE tAC tAC DQ av0 Q Bank #0 Active Bank #1 av1 Q av2 av3 aw0 ax0 ay0 az0 az1 az2 az3 Q Q D D D Q Q Q Q Read Single Write - 30 - Read 22 23 W981616AH PowerDown Mode (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS WE BA A10 RAa A0-A9 RAa RAa CAa RAa CAx DQM tSB tSB CKE tCKS tCKS ax0 Active tCKS tCKS DQ ax1 ax2 NOP Read ax3 Precharge NOP Active Precharge Standby Power Down mode Active Standby Power Down mode Note: The PowerDown Mode is entered by asserting CKE "low". All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode. When CKE goes high, command input must be No operation at next CLK rising edge. - 31 - Publication Release Date: February 2000 Revision A2 W981616AH Autoprecharge Timing (Read Cycle) 0 1 Read AP 2 3 4 5 6 7 8 9 10 11 (1) CAS Latency=2 ( a ) burst length = 1 Command Act tRP DQ Q0 ( b ) burst length = 2 Command Read AP Act tRP DQ Q0 Q1 ( c ) burst length = 4 Command Read AP Act tRP DQ Q0 Q1 Q2 Q3 ( d ) burst length = 8 Command AP Read Q0 DQ Q1 Q2 Q3 Q4 Q5 Q6 Act tRP Q7 (2) CAS Latency=3 ( a ) burst length = 1 Command Read AP Act tRP Q0 DQ ( b ) burst length = 2 Command Read AP Act tRP Q0 DQ Q1 ( c ) burst length = 4 Command Read AP Act tRP Q0 DQ Q1 Q2 Q3 ( d ) burst length = 8 Command Read AP DQ Q0 Q1 Q2 Q3 Q4 Q5 Act tRP Q6 Q7 Note: Read represents the Read with Auto precharge command. AP represents the start of internal precharging. Act represents the Bank Activate command. When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least tRAS(min). - 32 - W981616AH Autoprecharge Timing (Write Cycle) 0 1 2 3 4 5 6 7 8 9 10 11 (1) CAS Latency = 2 ( a ) burst length = 1 Command Write AP Act tWR DQ tRP D0 ( b ) burst length = 2 Command Write AP Act tWR DQ D0 tRP D1 ( c ) burst length = 4 Command Write AP tWR DQ D0 D1 D2 Act tRP D3 ( d ) burst length = 8 Command Write AP tWR DQ D0 D1 D2 D3 D4 D5 D6 Act tRP D7 (2) CAS Latency = 3 ( a ) burst length = 1 Command Write AP Act tWR DQ ( b ) burst length = 2 Command tRP D0 Write Act AP tWR DQ D0 tRP D1 ( c ) burst length = 4 Command Write Act AP tWR DQ D0 D1 D2 tRP D3 ( d ) burst length = 8 Command AP Write tWR DQ D0 D1 D2 D3 D4 D5 D6 Act t RP D7 Note: Write represents the Write with Auto precharge command. AP represents the start of internal precharging. Act represents the Bank Activate command. When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least tRAS (min) . - 33 - Publication Release Date: February 2000 Revision A2 W981616AH Timing Chart of Write-to-Read Cycle In the case of Burst Length = 4 0 1 2 Write Read 3 4 5 6 7 8 9 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 6 7 8 10 11 (1) CAS Latency = 2 ( a ) Command DQM D0 DQ ( b ) Command Read Write DQM DQ D0 D1 Write Read (2) CAS Latency = 3 ( a ) Command DQM D0 DQ Write ( b ) Command Read DQM D0 DQ D1 Q3 Timing Chart of Burst Stop Cycle (Burst Stop Command) 0 1 2 3 4 5 (3) Read cycle ( a ) CAS latency =2 Command Read BST DQ Q0 Q1 Q2 Q3 Q4 ( b ) CAS latency = 3 Command BST Read Q0 DQ Q1 Q2 Q3 (2) Write cycle Command DQ BST Write D0 Note: D1 BST D2 D3 D4 represents the Burst stop command - 34 - Q4 9 10 11 W981616AH Timing Chart of Burst Stop Cycle (Prechare Command) (In the case of Burst Length = 8) 0 1 2 3 4 5 6 7 8 9 10 11 (1) Read cycle ( a ) CAS latency = 2 Commad Read PRCG Q0 DQ Q1 Q3 Q2 Q4 ( b ) CAS latency = 3 Commad PRCG Read Q0 DQ Q2 Q1 Q3 Q4 (2) Write cycle ( a ) CAS latency = 2 Commad PRCG tWR Write DQM DQ D0 D1 D2 D3 D4 ( b ) CAS latency = 3 Commad PRCG tWR Write DQM DQ D0 Note: D1 PRCG D2 D3 D4 represents the Precharge command - 35 - Publication Release Date: February 2000 Revision A2 W981616AH CK/DQM Input Timing (Write Cycle) CLK cycle No. 1 2 3 D1 D2 D3 4 5 6 7 External CLK Internal CKE DQM DQ D5 DQM MASK D6 CKE MASK (1) CLK cycle No. 1 2 3 D1 D2 D3 4 5 6 7 External CLK Internal CKE DQM DQ DQM MASK D5 D6 5 6 7 D4 D5 D6 CKE MASK (2) CLK cycle No. 1 2 3 D1 D2 D3 4 External CLK Internal CKE DQM DQ CKE MASK (3) - 36 - W981616AH CK/DQM Input Timing (Read Cycle) CLK cycle No. 1 2 3 4 Q1 Q2 Q3 Q4 5 6 7 External CLK Internal CKE DQ M DQ Q6 Open Open (1) CLK cycle No. 1 2 3 Q1 Q2 Q3 4 5 6 7 External CLK Internal CKE DQM DQ Q6 Q4 Open (2) CLK cycle No. 1 2 Q1 Q2 3 4 5 6 7 Q4 Q5 Q6 External CLK Internal CKE DQ M DQ Q3 (3) - 37 - Publication Release Date: February 2000 Revision A2 W981616AH Self Refresh/Power Down Mode Exit Timing Asynchronous Control Input Buffer turn on time ( Power down mode exit time ) is specified by tCKS (min) + tCK (min) A ) tCK < tCKS(min)+tCK(min) tCK CLK CKE tCKS(min)+tCK(min) NOP Command Command Input Buffer Enable B) tCK >= tCKS(min) + tCK (min) tCK CLK tCKS(min)+tCK(min) CKE Command Command Input Buffer Enable Note: All Input Buffer(Include CLK Buffer) are turned off in the Power Down mode and Self Refresh mode NOP Command Represents the No-Operation command Represents one command - 38 - W981616AH PACKAGE DIMENSIONS 50L-TSOP (II) 400 mill 50 26 E 1 HE 25 e b C D q L A2 A L1 A1 ZD SEATING PLANE Y Controlling Dimension: Millimeters DIMENSION (INCH) DIMENSION(MM) SYM. MIN. NOM. A MAX. MIN. NOM. MAX. A1 0.05 0.10 1.20 0.15 0.002 0.004 0.047 0.006 A2 b 0.90 1.00 1.10 0.035 0.039 0.043 0.15 0.45 0.20 0.012 0.004 0.006 0.018 0.008 c 0.30 0.10 D 20.82 20.95 21.08 0.820 0.825 0.830 E 10.03 10.16 10.29 0.395 0.400 0.405 HE 11.56 11.76 11.96 0.455 0.463 0.471 0.80 e L 0.40 0.50 L1 0.80 Y ZD 0.88 0.031 0.60 0.016 0.020 0.10 0o 0.024 0.031 0.004 0.031 o 10 0o - 39 - 10 o Publication Release Date: February 2000 Revision A2 W981616AH Headquarters Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 40 - Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798