W981616AH
512K × 2 BANKS × 16 BITS SDRAM
Publication Release Date: February 2000
- 1 - Revision A2
GENERAL DESCRIPTION
W981616AH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words × 2 banks × 16 bits. Using pipelined architecture and 0.20 µm process technology,
W981616AH delivers a data bandwidth of up to 332M bytes per second (-6). For different applications
the W981616AH is sorted into the following speed grades: -6, -7, and -8.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W981616AH is ideal for main memory in
high performance applications.
FEATURES
• 3.3V ±0.3V power supply
• Up to 166 MHz clock frequency
• 524,288 words x 2 banks x 16 bits organization
• Auto Refresh and Self Refresh
• CAS latency: 2 and 3
• Burst Length: 1, 2, 4, 8, and full page
• Burst read, Single Write Mode
• Byte data controlled by UDQM and LDQM
• Auto-precharge and controlled precharge
• 4K refresh cycles/64 mS
• Interface: LVTTL
• Packaged in 50-pin, 400 mil TSOP II
PIN CONFIGURATION
46
47
48
49
50
42
43
44
45
38
39
40
41
V
SS
1
2
3
4
5
DQ0
6
7
8
9
10
11
12
13
CS
NC
24
15
14
19
18
17
16
22
21
20
23
25
VCC
DQ1
V Q
SS
DQ2
DQ3
V Q
CC
DQ4
DQ5
V Q
SS
DQ6
DQ7
V Q
CC
WE
CAS
RAS
LDQM
BA
A1
A2
A3
A0
A10
VCC 26
27
28
36
37
32
33
34
35
29
30
31
DQ15
DQ14
V Q
SS
DQ13
DQ12
V Q
CC
DQ11
DQ10
V Q
SS
DQ9
DQ8
V Q
CC
UDQM
NC
CLK
CKE
A9
A6
A5
A4
A7
A8
VSS
W981616AH
- 2 -
PIN DESCRIPTION
PIN NUMBER
PIN NAME FUNCTION DESCRIPTION
20−24,
27−32 A0−A10 Address Multiplexed pins for row and column address.
Row address: A0−A10. Column address: A0−A7.
19 BA Bank Select Select bank to activate during row address latch time,
or bank to read/write during column address latch
time.
2, 3, 5, 6, 8, 9,
11, 12, 39, 40,
42, 43, 45, 46,
48, 49
DQ0−DQ15
Data Input/
Output Multiplexed pins for data input and output.
18 CS Chip Select Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
17 RAS Row Address
Strobe Command input. When sampled at the rising edge of
the clock, RAS, CAS and WE define the operation to
be executed.
16 CAS Column
Address Strobe
Referred to RAS
15 WE Write Enable Referred to RAS
36, 14 UDQM/
LDQM Input/Output
Mask The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
35 CLK Clock Inputs System clock used to sample inputs on the rising
edge of clock.
34 CKE Clock Enable
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
1, 25 VCC Power (+3.3V)
Power for input buffers and logic circuit inside DRAM.
26, 50 VSS Ground Ground for input buffers and logic circuit inside
DRAM.
7, 13, 38, 44, VCCQ Power (+3.3V)
for I/O buffer Separated power from VCC, used for output buffers to
improve noise immunity.
4, 10, 41, 47 VSSQ Ground for I/O
buffer Separated ground from VSS, used for output buffers
to improve noise immunity.
33, 37 NC No Connection
No connection
W981616AH
Publication Release Date: February 2000
- 3 - Revision A2
BLOCK DIAGRAM
CLK
CKE
A10
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #0
R
O
W
D
E
C
O
D
E
R
DQ0
DQ15
LDQM
UDQM
DQ
BUFFER
CS
RAS
CAS
WE
DATA CONTROL
CIRCUIT
Note: The cell array configuration is 2048 * 256 * 16
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #1
A0
A9
BA
R
O
W
D
E
C
O
D
E
R
W981616AH
- 4 -
FUNCTIONAL DESCRIPTION
Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs during power up, all VCC and VCCQ pins must be ramp up simultaneously to the
specified voltage when the input signals are held in the "NOP" state. The power up voltage must not
exceed VCC +0.3V on any of the input pins or VCC supplies. After power up, an initial pause of 200 µS
is required followed by a precharge of all banks using the precharge command. To prevent data
contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high
during the initial pause period. Once all banks have been precharged, the Mode Register Set
Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles
(CBR) are also required before or after programming the Mode Register to ensure proper subsequent
operation.
Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of
RAS
,
CAS
,
CS
and
WE
at the positive edge of the clock. The address input data during
this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new
command may be issued following the mode register set command once a delay equal to tRSC has
elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to
RAS
activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and
vice versa) is the Bank-to-Bank delay time (tRRD). The maximum time that each bank can be held
active is specified as tRAS(max.).
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be followed. This is accomplished by
setting
RAS
high and
CAS
low at the clock rising edge after minimum of tRCD delay.
WE
pin voltage
level defines whether the access cycle is a read operation (
WE
high), or a write operation (
WE
low).
The address inputs determine the starting column address. Reading or writing to a different row within
an activated bank requires the bank be precharged and a new Bank Activate command be issued.
When more than one bank is activated, interleaved bank Read or Write operations are possible. By
using the programmed burst length and alternating the access and precharge operations between
multiple banks, seamless data access operation among many different pages can be realized. Read
or Write Commands can also be issued to the same bank or between active banks on every clock
cycle.
W981616AH
Publication Release Date: February 2000
- 5 - Revision A2
Burst Read Command
The Burst Read command is initiated by applying logic low level to
CS
and
CAS
while holding
RAS
and
WE
high at the rising edge of the clock. The address inputs determine the starting column
address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequence mode.
Burst Write Command
The Burst Write command is initiated by applying logic low level to
CS
,
CAS
and
WE
while holding
RAS
high at the rising edge of the clock. The address inputs determine the starting column address.
Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the
Write Command is issued. The remaining data inputs must be supplied on each subsequent rising
clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be
ignored.
Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS latency from the
interrupting Read Command the is satisfied.
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When
the previous burst is interrupted, the remaining addresses are overridden by the new address and
data will be written into the device until the programmed burst length is satisfied.
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.
Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank
open for future Read or Write Commands to the same page of the active bank, if the burst length is
full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst
W981616AH
- 6 -
Stop Command is defined by having
RAS
and
CAS
high with
CS
and
WE
low at the rising edge of
the clock. The data DQs go to a high impedance state after a delay, which is equal to the
CAS
Latency in a burst read cycle, interrupted by Burst Stop. If a Burst Stop Command is issued during a
full page burst write operation, then any residual data from the burst write cycle will be ignored.
Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address, which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2.
Table 2 Address Sequence of Sequential Mode
DATA Access Address Burst Length
Data 0 n BL = 2 (disturb address is A0)
Data 1 n + 1 No address carry from A0 to A1
Data 2 n + 2 BL = 4 (disturb addresses are A0 and A1)
Data 3 n + 3 No address carry from A1 to A2
Data 4 n + 4
Data 5 n + 5 BL = 8 (disturb addresses are A0, A1 and A2)
Data 6 n + 6 No address carry from A2 to A3
Data 7 n + 7
Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
DATA
Access Address
Bust Length
Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 2
Data 1 A8 A7 A6 A5 A4 A3 A2 A1
A0
Data 2 A8 A7 A6 A5 A4 A3 A2
A1
A0 BL = 4
Data 3 A8 A7 A6 A5 A4 A3 A2
A1
A0
Data 4 A8 A7 A6 A5 A4 A3
A2
A1 A0 BL = 8
Data 5 A8 A7 A6 A5 A4 A3
A2
A1
A0
Data 6 A8 A7 A6 A5 A4 A3
A2
A1
A0
Data 7
A8 A7 A6 A5 A4 A3
A2
A1
A0
W981616AH
Publication Release Date: February 2000
- 7 - Revision A2
Auto-precharge Command
If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is
entered. During auto-precharge, a Read Command will execute as normal with the exception that the
active bank will begin to precharge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled
burst cycle. The number of clocks is determined by
CAS
latency.
A Read or Write Command with auto-precharge can not be interrupted before the entire burst
operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during
a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot
be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-Precharge command is
illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write
with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation
one clock delay from the last burst write cycle. This delay is referred to as Write tDPL. The bank
undergoing auto-precharge can not be reactivated until tDPL and tRP are satisfied. This is referred to as
tDAL, Data-in to Active delay (tDAL = tDPL + tRP). When using the Auto-precharge Command, the interval
between the Bank Activate Command and the beginning of the internal precharge operation must
satisfy tRAS(min).
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command is entered when
CS
,
RAS
and
WE
are low and
CAS
is high at the rising edge
of the clock. The Precharge Command can be used to precharge each bank separately or all banks
simultaneously. Three address bits, A10, and BA, are used to define which bank(s) is to be
precharged when the command is issued. After the Precharge Command is issued, the precharged
bank must be reactivated before a new read or write access can be executed. The delay between the
Precharge Command and the Activate Command must be greater than or equal to the Precharge
time (tRP).
Self Refresh Command
The Self-Refresh Command is defined by having
CS
,
RAS
,
CAS
and CKE held low with
WE
high
at the rising edge of the clock. All banks must be idle prior to issuing the Self-Refresh Command.
Once the command is registered, CKE must be held low to keep the device in Self-Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are
disabled. The clock is internally disabled during Self-Refresh Operation to save power. The device
will exit Self-Refresh operation after CKE is returned high. Any subsequent commands can be issued
after tRC from the end of Self Refresh command.
If, during normal operation, Auto-Refresh cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 Auto-Refresh cycles should be completed just prior to entering and just
after exiting the Self-Refresh mode.
Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations;
therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the
device.
W981616AH
- 8 -
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on tCK. The input buffers need to be
enabled with CKE held high for a period equal to tCES(min) + tCK(min).
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when
CS
is low with
RAS
,
CAS
, and
WE
held high at the rising edge of the
clock. A No Operation Command will not terminate a previous operation that is still executing, such
as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when
CS
is brought high, the
RAS
,
CAS
, and
WE
signals become don't cares.
Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one-clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one-clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
W981616AH
Publication Release Date: February 2000
- 9 - Revision A2
TABLE OF OPERATING MODES
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.
TABLE 1 TRUTH TABLE (NOTE 1, 2)
Command Device
State CKEn-1
CKEn DQM BA
A10 A9-0
CS RAS
CAS
WE
Bank Active Idle H X X V V V L L H H
Bank Precharge Any H X X V L X L L H L
Precharge All Any H X X X H X L L H L
Write Active (3) H X X V L V L H L L
Write with
Autoprecharge Active (3) H X X V H V L H L L
Read Active (3) H X X V L V L H L H
Read with
Autoprecharge Active (3) H X X V H V L H L H
Mode Register Set Idle H X X V V V L L L L
No-Operation Any H X X X X X L H H H
Burst Stop Active (4) H X X X X X L H H L
Device Deselect Any H X X X X X H X X X
Auto-Refresh Idle H H X X X X L L L H
Self-Refresh Entry Idle H L X X X X L L L H
Self-Refresh Exit Idle
(S.R) L
L H
H X
X X
X X
X X
X H
L X
H X
H X
X
Clock Suspend Mode
Entry Active H L X X X X X X X X
Power Down Mode
Entry Idle
Active (5) H
H L
L X
X X
X X
X X
X H
L X
H X
H X
X
Clock Suspend Mode
Exit Active L H X X X X X X X X
Power Down Mode Exit Any
(Power
down)
L
L H
H X
X X
X X
X X
X H
L X
H X
H X
X
Data Write/Output
Enable Active H X L X X X X X X X
Data Write/Output
Disable Active H X H X X X X X X X
Notes:
(1) V = Valid, X = Don't care, L = Low Level, H = High Level
(2) CKEn signal is input level when commands are provided.
(3) These are state of bank designated by BA signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
W981616AH
- 10 -
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTES
Input, Output Voltage VIN, VOUT -0.3 − 4.6 V 1
Power Supply Voltage VCC, VCCQ -0.3 − 4.6 V 1
Operating Temperature TOPR 0 − 70 °C 1
Storage Temperature TSTG -55 − 150 °C 1
Soldering Temperature (10s) TSOLDER 260 °C 1
Power Dissipation PD 1 W 1
Short Circuit Output Current IOUT 50 mA 1
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0 to 70°C)
PARAMETER SYM. MIN. TYP. MAX. UNIT NOTES
Power Supply Voltage VCC 3.0 3.3 3.6 V 2
Power Supply Voltage (for I/O
Buffer) VCCQ 3.0 3.3 3.6 V 2
Input High Voltage VIH 2.0 - VCC +0.3 V 2
Input Low Voltage VIL -0.3 - 0.8 V 2
Note: VIH (max.) = VCC/VCCQ +1.2V for pulse width < 5 nS
VIL (min.) = VSS/VSSQ -1.2V for pulse width < 5 nS
CAPACITANCE
(VCC = 3.3V, TA = 25 °C, f = 1MHz)
PARAMETER SYM. MIN. MAX. UNIT
Input Capacitance (A0 to A10, BA,
CS
,
RAS
,
CAS
,
WE
,
UDQM, LDQM, CKE) CI - 4 pf
Input Capacitance (CLK) - 4 pf
Input/Output capacitance (DQ0 to DQ15) CIO - 6.5 pf
Note: These parameters are periodically sampled and not 100% tested
W981616AH
Publication Release Date: February 2000
- 11 - Revision A2
DC CHARACTERISTICS
(VCC = 3.3V ±0.3V, TA = 0°~70°C)
PARAMETER SYM. -6
MAX. -7
MAX. -8
MAX. UNIT NOTES
Operating Current
tCK = min., tRC = min.
Active precharge command
cycling without burst
operation
1 bank operation ICC1 100 90 80 mA 3
Standby Current
tCK = min., CS = VIH
VIH /L = VIH (min.) /VIL (max.)
Bank: inactive state
CKE = VIH ICC2 50 45 40 3
CKE = VIL
(Power down mode) ICC2P 2 2 2 3
Standby Current
CLK = VIL, CS = VIH
VIH/L = VIH (min.) /VIL (max.)
Bank: inactive state
CKE = VIH
ICC2S 10 8 6
CKE = VIL
(Power down mode) ICC2PS 2 2 2
No Operating Current
tCK = min., CS = VIH (min.)
Bank: active state (2 banks)
CKE = VIH ICC3 55 50 45
CKE = VIL
(Power Down mode) ICC3P 5 5 5
Burst Operating Current (tCK = min.)
Read/ Write command cycling ICC4 130 110 100 3, 4
Auto Refresh Current (tCK = min.)
Auto refresh command cycling ICC5 90 80 70 3
Self Refresh Current (CKE = 0.2V)
Self refresh mode ICC6 2 2 2
PARAMETER SYM. MIN. MAX. UNIT NOTES
Input Leakage Current
(0V ≤ VIN ≤ VCC, all other pins not under test = 0V) II(L) -5 5 µA
Output Leakage Current
(Output disable , 0V ≤ VOUT ≤ VCCQ ) IO(L) -5 5 µA
LVTTL OutputT ″H″ Level Voltage
(IOUT = -2 mA) VOH 2.4 - V
LVTTL Output ″L″ Level Voltage
(IOUT = 2 mA) VOL - 0.4 V
W981616AH
- 12 -
AC CHARACTERISTICS
(VCC = 3.3V ±0.3V, VSS = 0V, TA = 0 to 70 °C, Notes: 5, 6, 7, 8)
PARAMETER SYM.
-6 -7 -8 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Ref/Active to Ref/Active Command Period tRC 60 70 72 nS
Active to Precharge Command Period tRAS 42 100000
48 100000
48 100000
Active to Read/Write Command Delay
Time tRCD 18 20 20
Read/Write(a) to Read/Write(b)Command
Period tCCD 1 1 1 Cycle
Precharge to Active(b) Command Period tRP 18 20 20 nS
Active(a) to Active(b) Command Period tRPD 12 14 16
Write Recovery Time CL* = 2 tWR 10 10 10
CL* = 3 6 7 8
CLK Cycle Time CL* = 2 tCK 10 1000 10 1000 10 1000
CL* = 3 6 1000 7 1000 8 1000
CLK High Level Width tCH 2.5 3 3
CLK Low Level Width tCL 2.5 3 3
Access Time from CLK CL* = 2 tAC 7 7 7
CL* = 3 5.5 5.5 6
Output Data Hold Time tOH 2 2.5 3
Output Data High Impedance Time tHZ 2 6 2.5 7 3 8
Output Data Low Impedance Time tLZ 0 0 0
Power Down Mode Entry Time tSB 0 6 0 7 0 8
Transition Time of CLK (Rise and Fall) tT 0.3 10 0.3 10 0.3 10
Data-in-Set-up Time tDS 1.5 2 2
Data-in Hold Time tDH 1 1 1
Address Set-up Time tAS 1.5 2 2
Address Hold Time tAH 1 1 1
CKE Set-up Time tCKS 1.5 2 2
CKE Hold Time tCKH 1 1 1
Command Set-up Time tCMS 1.5 2 2
Command Hold Time tCMH 1 1 1
Refresh Time tREF 64 64 64 mS
Mode Register Set Cycle Time tRSC 12 14 16 nS
W981616AH
Publication Release Date: February 2000
- 13 - Revision A2
Notes:
1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the
devices.
2. All voltages are referenced to VSS
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the
minimum values of tCK and tRC.
4. These parameters depend on the output loading conditions. Specified values are obtained with
output open.
5. Power up sequence is further described in the "Functional Description" section.
6. AC test conditions.
PARAMETER CONDITIONS
Output Reference Level 1.4V/1.4V
Output Load See diagram below
Input Signal Levels 2.4V/0.4V
Transition Time (Rise and Fall) of Input Signal 2 nS
Input Reference Level 1.4V
50 ohms
1.4 V
Z = 50 ohmsoutput
AC TEST LOAD
30pF
7. Transition times are measured between VIH and VIL.
8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced
to output level.
W981616AH
- 14 -
TIMING WAVEFORMS
Command Input Timing
t
CK
CLK
A0-A10
BA
V
IH
V
IL
t
CMH
t
CMS
t
CH
t
CL
t
T
t
T
t
CKS
t
CKH
t
CKH
t
CKS
t
CKS
t
CKH
CS
RAS
CAS
WE
CKE
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
AS
t
AH
W981616AH
Publication Release Date: February 2000
- 15 - Revision A2
Read Timing
Read CAS Latency
tAC
tLZ
tAC
tOH
tHZ
tOH
Burst Length
Read Command
CLK
CS
RAS
CAS
WE
A0-A10
BA
DQ
Valid
Data-Out Valid
Data-Out
W981616AH
- 16 -
Control Timing of Input/Output Data
tCMH tCMS tCMH tCMS
tDS tDH tDS tDH tDS tDH tDS tDH
Valid
Data-Out Valid
Data-Out Valid
Data-Out
Valid
Data-in Valid
Data-in Valid
Data-in Valid
Data-in
tCKH tCKS tCKH tCKS
tDS tDH tDS tDH tDH
tDS tDS tDH
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
tCMH tCMS tCMH tCMS
tOH tAC tOHtAC tOHtHZ
OPEN
tLZ tAC tOH tAC
tCKH tCKS tCKH tCKS
tOHtAC tOH tAC tOH tAC tOH tAC
Valid
Data-Out Valid
Data-Out
Valid
Data-Out
CLK
DQM
DQ0 -15
(Word Mask)
(Clock Mask)
CLK
CKE
DQ0 -15
CLK
Input Data
Output Data
(Output Enable)
(Clock Mask)
DQM
DQ0 -15
CKE
CLK
DQ0 -15
W981616AH
Publication Release Date: February 2000
- 17 - Revision A2
Mode Reqister Set Cycle
A0
A1
A2
A3
A4
A5
A6
Burst Length
Addressing Mode
CAS Latency
(Test Mode)
A8 Reserved
A0A7
A0A9 A0Write Mode
A10
BA
"0"
"0"
A3 Addressing Mode
A0
0Sequential
A0
1Interleave
A9 Single Write Mode
0Burst read and Burst write
1Burst read and single write
A2 A1 A0
A00 0 0
A00 0 1
A00 1 0
A00 1 1
A01 0 0
A0
1 0 1
A01 1 0
A01 1 1
Burst Length
A0
Sequential A0
Interleave
1 1
2 2
4 4
A0
8 8
Reserved Reserved
A0
Full Page
CAS Latency
Reserved
A0
Reserved
2
3
Reserved
A0
A6 A5 A4
A00 0 0
0 1 0
0 1 1
1 0 0
0 0 1
tRSC
tCMS tCMH
tCMS tCMH
tCMS tCMH
tCMS tCMH
tAS tAH
CLK
CS
RAS
CAS
WE
A0-A10
BA Register
set data
next
command
A0Reserved
"0"
"0"
W981616AH
- 18 -
Interleaved Bank Read
(Burst Length = 4, CAS Latency = 3)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9
A10
BA
WE
CAS
RAS
CS tRC tRC
tRC tRC
tRAS tRP tRAS tRP
tRP
tRAS tRAS
tRCD tRCD tRCD tRCD
tAC tAC tAC tAC
tRRD tRRD tRRD tRRD
Active Read
Active Read
Active
Active
Active
Read
Read
Precharge
Precharge
Precharge
RAa RBb RAc RBd RAe
RAa CAw RBb CBx RAc CAy RBd CBz RAe
aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3
Bank #0
Bank #1
W981616AH
Publication Release Date: February 2000
- 19 - Revision A2
Interleaved Bank Read
(Burst Length = 4, CAS Latency = 3, Autoprecharge)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
(CLK = 100 MHz)
CLK
CKE
DQM
A0-A9
A10
BA
WE
CAS
RAS
CS
t
RC
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RAS
t
RP
t
RAS
t
RCD
t
RCD
t
RCD
t
RCD
t
AC
t
AC
t
AC
t
AC
t
RRD
t
RRD
t
RRD
t
RRD
Active Read
Active Read
Active
Active
Active
Read
Read
t
RC
RAa RAc RBd RAe
DQ
aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 dz0
* AP is the internal precharge start timing
Bank #0
Bank #1 AP*
AP* AP*
RAa CAw RBb CBx RAc CAy RBd RAe
CBz
RBb
W981616AH
- 20 -
Interleaved Bank Read
(Burst Length = 8, CAS Latency = 3)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
tRC tRC
tRC
tRAS tRP tRAS
tRP tRAS tRP
tRCD tRCD tRCD
tRRD tRRD
RAa
RAa CAx
RBb
RBb CBy
RAc
RAc CAz
ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 CZ0
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9
A10
WE
CAS
RAS
CS
BA
Active Read
Precharge Active Read
Precharge Active
tAC tAC
Read
Precharge
tAC
Bank #0
Bank #1
W981616AH
Publication Release Date: February 2000
- 21 - Revision A2
Interleaved Bank Read
(Burst Length = 8, CAS Latency = 3, Autoprecharge)
01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RAS
t
RP
t
RCD
t
RCD
t
RCD
t
RRD
t
RRD
ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 by5 by6 CZ0
RAa
RAa
CAx
RBb
RBb CBy
(CLK = 100 MHz)
RAc
RAc CAz
* AP is the internal precharge start timing
Active Read
Active
Active Read
t
CAC
t
CAC
t
CAC
CLK
DQ
CKE
DQM
A0-A9
A10
BA
WE
CAS
RAS
CS
Bank #0
Bank #1 Read
AP*
AP*
W981616AH
- 22 -
Interleaved Bank Write
(Burst Length = 8)
01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RCD
t
RCD
t
RCD
t
RRD
t
RRD
RAa
RAa CAx
RBb
RBb CBy
RAc
RAc CAz
ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2
(CLK = 100 MHz)
Write
Precharge
Active
Active Write
Precharge
Active Write
CLK
DQ
CKE
DQM
A0-A9
A10
WE
CAS
RAS
CS
BA
Bank #0
Bank #1
t
RAS
W981616AH
Publication Release Date: February 2000
- 23 - Revision A2
Interleaved Bank Write
(Burst Length = 8, Autoprecharge)
Bank #0
Bank #1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
tRC
tRAS tRP
tRAS
tRCD tRCD tRCD
tRRD tRRD
RAa
RAa CAx
RBb
RBb CBy
RAb
RAb
ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2
CAz
(CLK = 100 MHz)
* AP is the internal precharge start timing
CLK
DQ
CKE
DQM
A0-A9
A10
WE
CAS
RAS
CS
Active Write Write
Active
AP*
Active Write AP*
BA
W981616AH
- 24 -
Page Mode Read
(Burst Length = 4, CAS Latency = 3)
0123456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
tCCD tCCD tCCD
tRAS tRP
tRAS tRP
tRCD tRCD
tRRD
RAa
RAa CAI
RBb
RBb CBx CAy CAm CBz
a0 a1 a2 a3 bx0 bx1 Ay0 Ay1 Ay2 am0 am1 am2 bz0 bz1 bz2 bz3
(CLK = 100 MHz)
* AP is the internal precharge start timing
CLK
DQ
CKE
DQM
A0-A9
A10
WE
CAS
RAS
CS
BA
Active Read
Active Read
Read Read
Read
Precharge
tAC
tAC
tAC
tAC
tAC
Bank #0
Bank #1 AP*
W981616AH
Publication Release Date: February 2000
- 25 - Revision A2
Page Mode Read/Write
(Burst Length = 4, CAS Latency = 3)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
tRAS tRP
tRCD
tWR
RAa
RAa CAx CAy
ax0 ax1 ax2 ax3 ax4 ax5 ay1
ay0 ay2 ay4
ay3
Q Q Q Q Q Q D DD
D
D
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9
A10
WE
CAS
RAS
CS
BA
Active Read Write Precharge
tAC
Bank #0
Bank #1
W981616AH
- 26 -
AutoPrecharge Read
(Burst Length = 4, CAS Latency = 3)
0123456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9
A10
BA
WE
CAS
RAS
CS
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RCD
t
RCD
t
AC
t
AC
Active Read AP* Active Read AP*
RAa RAb
RAa CAw RAb CAx
aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3
* AP is the internal precharge start timing
Bank #0
Bank #1
W981616AH
Publication Release Date: February 2000
- 27 - Revision A2
AutoPrecharge Write
(Burst Length = 4)
0123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS1
WE
CS
BS0
tRC tRC
tRAS tRP tRAS tRP
RAa
tRCD tRCD
RAb RAc
RAa CAw RAb CAx RAc
aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3
Active
Active Write AP* Active Write AP*
* AP is the internal precharge start timing
Bank #0
Idle
Bank #1
Bank #2
Bank #3
RAS
CAS
W981616AH
- 28 -
AutoRefresh Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
(CLK = 100 MHz)
All Banks
Prechage Auto
Refresh Auto Refresh (Arbitrary Cycle)
tRC
tRP tRC
CLK
DQ
CKE
DQM
A0-A9
A10
WE
CAS
RAS
CS
BA
W981616AH
Publication Release Date: February 2000
- 29 - Revision A2
SelfRefresh Cycle
0123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9
A10
BA
WE
CAS
RAS
CS
t
CKS
t
SB
t
CKS
t
CKS
All Banks
Precharge Self Refresh
Entry Arbitrary Cycle
t
RP
Self Refresh Cycle
t
RC
No Operation Cycle
W981616AH
- 30 -
Bust Read and Single Write
(Burst Lenght = 4, CAS Latency = 3)
0123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
RAS
CAS
WE
BA
A10
A0-A9
DQM
CKE
DQ
(CLK = 100 MHz)
tRCD
RBa
RBa CBv CBw CBx CBy CBz
av0 av1 av2 av3 aw0 ax0 ay0 az0 az1 az2 az3
Q Q Q Q D DD Q Q Q Q
tAC tAC
Read Read
Single WriteActive
Bank #0
Bank #1
W981616AH
Publication Release Date: February 2000
- 31 - Revision A2
PowerDown Mode
01234567 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
(CLK = 100 MHz)
RAa CAa RAa CAx
RAa RAa
ax0 ax1 ax2 ax3
t
SB
t
CKS
t
CKS
t
CKS
t
SB
t
CKS
Active Standby
Power Down mode Precharge Standby
Power Down mode
Active NOP Precharge NOPActive
Note: The PowerDown Mode is entered by asserting CKE "low".
All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode.
When CKE goes high, command input must be No operation at next CLK rising edge.
CLK
DQ
CKE
DQM
A0-A9
A10
BA
WE
CS
Read
RAS
CAS
W981616AH
- 32 -
Autoprecharge Timing
(Read Cycle)
Read AP
0 1110987654321
Q0
Q0
Read AP Act
Q1
Read AP Act
Q1 Q2
AP Act
Read
Act
Q0
Q3
(1) CAS Latency=2
Read
Act
AP
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at least tRAS(min).
represents the Read with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
Note:
tRP
tRP
tRP
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
tRP
Q0
Read AP Act
Q0
Read AP Act
Q1
Q0
Read AP Act
Q1 Q2 Q3
Read AP Act
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
(2) CAS Latency=3
tRP
tRP
tRP
tRP
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
W981616AH
Publication Release Date: February 2000
- 33 - Revision A2
Autoprecharge Timing
(Write Cycle)
0 1110987654321
Act
AP
AP
AP
Write ActAP
D0
D0
D0
AP Act
D1
AP Act
D1 D2 D3
AP Act
Write
Write
Write
D0
D0 D1 D2 D3 D4 D5 D6 D7
AP
Act
D1
D0
Act
D1 D2 D3
Act
D0 D1 D2 D3 D4 D5 D6 D7
Write
Write
Write
Write
D0
(1) CAS Latency = 2
(2) CAS Latency = 3
Write
Act
AP
When the Auto precharge command is asserted, the period from Bank Activate
command to the start of internal precgarging must be at least tRAS(min).
represents the Write with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
Note:
tRP
tWR
tRP
tWR
tRP
tWR
tRP
tWR
tRP
tWR
tRP
tWR
tRP
tWR
tRP
tWR
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
W981616AH
- 34 -
Timing Chart of Write-to-Read Cycle
In the case of Burst Length = 4
01110987654321
Q0
Read
Q1 Q2 Q3
Read
Write
Write
D0 D1
DQ
DQ
( a ) Command
( b ) Command
DQM
DQM
(2) CAS Latency = 3
Q0 Q1 Q2 Q3D0
Read
Write
Read
Write
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
( a ) Command
DQ
DQ
DQM
( b ) Command
DQM
(1) CAS Latency = 2
D0
D0 D1
Timing Chart of Burst Stop Cycle
(Burst Stop Command)
Read BST
0 1110987654321
DQ
DQ
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Read BST
( a ) CAS latency =2
Command
( b ) CAS latency = 3
Command
(3) Read cycle
Q4
Q4
DQ D0 D1 D2 D3
Write BST
Command
(2) Write cycle
D4
Note: represents the Burst stop command
BST
W981616AH
Publication Release Date: February 2000
- 35 - Revision A2
Timing Chart of Burst Stop Cycle (Prechare Command)
(In the case of Burst Length = 8)
Note: represents the Precharge commandPRCG
Read PRCG
0 1110987654321
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Read PRCG
Q4
Q4
( a ) CAS latency = 2
( b ) CAS latency = 3
DQ
DQ
(1) Read cycle
(2) Write cycle
Commad
Commad
Write PRCG
D0 D1 D2 D3
D0 D1 D2 D3
Write PRCG
D4
D4
( b ) CAS latency = 3
DQ
( a ) CAS latency = 2
DQM
DQM
DQ
tWR
tWR
Commad
Commad
W981616AH
- 36 -
CK/DQM Input Timing
(Write Cycle)
7
6
5432
1
CKE MASK
( 1 )
D1 D6D5D3D2
CLK cycle No.
External
Internal
CKE
DQM
DQ
7
6
5432
1
( 2 )
D1 D6
D5
D3D2
76
5432
1
( 3 )
D1 D6D5D4
D3D2
CLK cycle No.
External
CKE
DQM
DQ
DQM MASK
DQM MASK CKE MASK
CKE MASK
Internal
CLK
CLK cycle No.
External
Internal
CKE
DQM
DQ
CLK
CLK
W981616AH
Publication Release Date: February 2000
- 37 - Revision A2
CK/DQM Input Timing
(Read Cycle)
7
6
5432
1
( 1 )
Q1 Q6
Q4Q3Q2
CLK cycle No.
External
Internal
CKE
DQ
M
DQ Open Open
7
6
5432
1
Q1 Q6
Q3
Q2
CLK cycle No.
External
Internal
CKE
DQM
DQ Open
( 2 )
765432
1
Q1 Q6
Q3
Q2
CLK cycle No.
External
Internal
CKE
DQ
M
DQ Q5Q4
( 3 )
Q4
CLK
CLK
CLK
W981616AH
- 38 -
Self Refresh/Power Down Mode Exit Timing
Asynchronous Control
Input Buffer turn on time ( Power down mode exit time ) is specified by tCKS(min) + tCK(min)
Command
NOP
CLK
CKE
Command
A ) tCK < tCKS(min)+tCK(min)
Input Buffer Enable
Command
CLK
CKE
Command
B) tCK >= tCKS(min) + tCK (min)
Input Buffer Enable
Note:
Command
NOP
All Input Buffer(Include CLK Buffer) are turned off in the Power Down mode
and Self Refresh mode
Represents the No-Operation command
Represents one command
tCK
tCK
tCKS(min)+tCK(min)
tCKS(min)+tCK(min)
W981616AH
Publication Release Date: February 2000
- 39 - Revision A2
PACKAGE DIMENSIONS
50L-TSOP (II) 400 mill
SEATING PLANE
D
A2
A1
A
eb
ZD
125
50 26
EHE
L
C
L1
q
ZD 0.88 0.031
0.035
0.002
0.012
MAX.MIN. NOM.
A2
b
A
A1
0.30
0.90 1.00
0.05
1.10
0.45
1.20
0.15
SYM.
DIMENSION(MM)
MAX.MIN. NOM.
e0.80 0.031
0.016
L0.40 0.50 0.60 0.020 0.024
0.395
E10.03 10.16 10.29 0.400 0.405
0.820
D20.9520.82 21.08 0.825 0.830
0.039 0.043
0.018
0.047
0.006
DIMENSION(INCH)
0.10 0.004
L1 0.80 0.031
0.004c0.200.10 0.008
0.15 0.006
0.455
11.76
11.56 11.96 0.463 0.471
HE
Y
θ
0.10
0o10o0o10o
0.004
Controlling Dimension: Millimeters
Y
W981616AH
- 40 -
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Note: All data and specifications are subject to change without notice.
