A3P1000L-1FG144 - Actel Corporation

February 2009 I

ProASIC3L Low-Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

• Dramatic Reduction in Dynamic and Static Power Savings

• 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power

• Low Power Consumption in Flash*Freeze Mode Allows for

Instantaneous Entry to / Exit from Low-Power Flash*Freeze

Mode

• Supports Single-Voltage System Operation

• Low-Impedance Switches

High Capacity

• 250 k to 3 M System Gates

• Up to 504 kbits of True Dual-Port SRAM

• Up to 620 User I/Os

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

High Performance

• 350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System

Performance

• 3.3 V, 66 MHz, 66-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit

PCI (1.2 V systems)

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

•FlashLock

® to Secure FPGA Contents

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

• High-Performance, Low-Skew Global Network

• Architecture Supports Ultra-High Utilization

Advanced and Pro (Professional) I/Os

• 700 Mbps DDR, LVDS-Capable I/Os

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 8 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and

LVCMOS 2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS

• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II (A3PE3000L only)

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold-Sparing I/Os Programmable

Output Slew Rate and Drive Strength

• Programmable Input Delay (A3PE3000L only)

• Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC®3L Family

(except PQ208)

Clock Conditioning Circuit (CCC) and PLL

• Six CCC Blocks, One with Integrated PLL (ProASIC3L) and All

with Integrated PLL (ProASIC3EL)

• Configurable Phase Shift, Multiply/Divide, Delay

Capabilities, and External Feedback

• Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V

systems) and 350 MHz (1.5 V systems))

SRAMs and FIFOs

• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,

and ×18 organizations available)

• True Dual-Port SRAM (except ×18)

• 24 SRAM and FIFO Configurations with Synchronous

Operation:

– 250 MHz: For 1.2 V systems

– 350 MHz: For 1.5 V systems

ARM® Processor Support in ProASIC3L FPGAs

• ARM Cortex™-M1 Soft Processor Available with or without

Debug

Table 1 • ProASIC3 Low-Power Product Family

ProASIC3L Devices A3P250L A3P600L A3P1000L A3PE3000L

ARM Cortex-M1 Devices 1M1A3P600L M1A3P1000L M1A3PE3000L

System Gates 250 k 600 k 1 M 3 M

VersaTiles (D-flip-flops) 6,144 13,824 24,576 75,264

RAM kbits (1,024 bits) 36 108 144 504

4,608-Bit Blocks 8 24 32 112

FlashROM Bits 1 k1 k1 k1 k

Secure (AES) ISP 2Yes Yes Yes Yes

Integrated PLL in CCCs 31116

VersaNet Globals 18 18 18 18

I/O Banks 4448

Maximum User I/Os 157 235 300 620

Package Pins

VQFP

PQFP

FBGA

VQ100

PQ208

FG144, FG256

PQ208

FG144, FG256, FG484

PQ208

FG144, FG256, FG484

PQ208 3

FG324, FG484, FG896

Notes:

1. Refer to the Cortex-M1 product brief for more information.

2. AES is not available for ARM-enabled ProASIC3L devices.

3. For the A3PE3000L, the PQ208 package has six CCCs and two PLLs.

v1.3

II v1.3

I/Os Per Package 1

ProASIC3L

Low-Power

Devices A3P250L 2A3P600L A3P1000L A3PE3000L

ARM

Cortex-M1

Devices M1A3P600L M1A3P1000L M1A3PE3000L 3

Package

I/O Type

Single-

Ended I/O 4Differential

I/O Pairs

Single-

Ended I/O 4Differential

I/O Pairs

Single-

Ended I/O 4Differential

I/O Pairs

Single-

Ended I/O 4Differential

I/O Pairs

VQ100 68 13 – – – – –

PQ208 151 34 154 35 154 35 147 65

FG144 97 24 97 25 97 25

FG256 157 38 177 43 177 44 – –

FG324 ––––––221110

FG484 – – 235 60 300 74 341 168

FG896 ––––––620310

Notes:

1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the

datasheet to ensure you are complying with design and board migration requirements.

2. For A3P250L devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15.

3. ARM Cortex-M1 support is TBD on this device.

4. Each used differential I/O pair reduces the number of single-ended I/Os available by two.

5. FG256 and FG484 are footprint-compatible packages.

6. "G" indicates RoHS-compliant packages. Refer to "ProASIC3L Ordering Information" on page III for the location of the

"G" in the part number.

7. For A3PE3000L devices, the usage of certain I/O standards is limited as follows:

– SSTL3(I) and (II): up to 40 I/Os per north or south bank

– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank

– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank

8. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-

ended user I/Os available is reduced by one.

Table 2 • ProASIC3L FPGAs Package Sizes Dimensions

Package VQ100 PQ208 FG144 FG256 FG324 FG484 FG896

Length × Width

(mm\mm)

14 × 14 28 × 28 13 × 13 17 × 17 19 × 19 23 × 23 31 × 31

Nominal Area

(mm2)

196 784 169 289 361 529 961

Pitch (mm) 0.5 0.5 1.0 1.0 1.0 1.0 1.0

Height (mm) 1.00 3.40 1.45 1.60 1.63 2.23 2.23

ProASIC3L Low-Power Flash FPGAs

v1.3 III

ProASIC3L Ordering Information

Speed Grade

Blank = Standard

1 = 15% Faster than Standard

A3P1000L FG

Part Number

ProASIC3L Devices

Package Type

VQ =Very Thin Quad Flat Pack (0.5 mm pitch)

144 I

Package Lead Count

Lead-Free Packaging

Application (Temperature Range)

Blank = Commercial (0°C to +70°C Ambient Temperature)

I= Industrial (

–

40°C to +85°C Ambient Temperature)

Blank = Standard Packaging

G= RoHS-Compliant (Green) Packaging

250,000 System Gates

A3P250L =

600,000 System Gates

A3P600L =

1,000,000 System Gates

A3P1000L =

3,000,000 System Gates

A3PE3000L =

ProASIC3L Devices with Cortex-M1

600,000 System Gates

M1A3P600L =

1,000,000 System Gates

M1A3P1000L =

3,000,000 System Gates

M1A3PE3000L =

PQ =Plastic Quad Flat Pack (0.5 mm pitch)

FG=Fine Pitch Ball Grid Array (1.0 mm pitch)

IV v1.3

Temperature Grade Offerings

Speed Grade and Temperature Grade Matrix

Contact your local Actel representative for device availability:

http://www.actel.com/contact/default.aspx.

Package A3P250L A3P600L A3P1000L A3PE3000L

ARM Cortex-M1 Devices M1A3P600L M1A3P1000L M1A3PE3000L

VQ100 C, I – –

PQ208 C, IC, IC, IC, I

FG144 C, I C, I C, I

FG256 C, I C, I C, I

FG324 –––C, I

FG484 – C, I C, I C, I

FG896 –––C, I

Notes:

1. C = Commercial temperature range: 0°C to 70°C ambient temperature.

2. I = Industrial temperature range: –40°C to 85°C ambient temperature.

Temperature Grade Std. –1

C 1✓✓

I 2✓✓

Notes:

1. C = Commercial temperature range: 0°C to 70°C ambient temperature.

2. I = Industrial temperature range: –40°C to 85°C ambient temperature.

v1.3 1-1

1 – ProASIC3L Device Family Overview

General Description

The ProASIC3L family of Actel flash FPGAs dramatically reduces dynamic power consumption by

40% and static power by 50%. These power savings are coupled with performance, density, true

single-chip, 1.2 V to 1.5 V core and I/O operation as low as 1.2 V, reprogrammability, and advanced

features.

Using Actel's proven Flash*Freeze technology enables users to shut off dynamic power

instantaneously and switch the device to static mode without the need to switch off clocks or

power supplies while retaining internal states of the device. This greatly simplifies power

management on a board done through I/Os and clocks. In addition, optimized software tools using

power-driven layout provide instant push-button power reduction.

Nonvolatile flash technology gives ProASIC3L devices the advantage of being a secure, low-power,

single-chip solution that is live at power-up (LAPU). ProASIC3L offers dramatic dynamic power

savings giving the FPGA users flexibility to combine low power with high performance.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

ProASIC3L devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well

as clock conditioning circuitry (CCC) based on an integrated phase-locked loop (PLL). ProASIC3L

devices support devices from 250 k system gates to 3 million system gates with up to 504 kbits of

true dual-port SRAM and 620 user I/Os.

M1 ProASIC3L devices support the high-performance, 32-bit Cortex-M1 processor developed by

ARM for implementation in FPGAs. ARM Cortex-M1 is a soft processor that is fully implemented in

the FPGA fabric. It has a three-stage pipeline that offers a good balance between low-power

consumption and speed when implemented in an M1 ProASIC3L device. The processor runs the

ARMv6-M instruction set, has a configurable nested interrupt controller, and can be implemented

with or without the debug block. ARM Cortex-M1 is available for free from Actel for use in M1

ProASIC3L FPGAs.

The ARM-enabled devices have Actel ordering numbers that begin with M1 and do not support

AES decryption.

Flash*Freeze Technology

The ProASIC3L devices offer Actel's proven Flash*Freeze technology, which allows instantaneous

switching from an active state to a static state. ProASIC3L devices do not need additional

components to turn off I/Os or clocks while retaining the design information, SRAM content, and

registers. Flash*Freeze technology is combined with in-system programmability, which enables

users to quickly and easily upgrade and update their designs in the final stages of manufacturing

or in the field. The ability of ProASIC3L devices to support a wide range core voltage (1.2 V to 1.5 V)

allows for an even greater reduction in power consumption, which enables low total system power.

When the ProASIC3L device enters Flash*Freeze mode, the device automatically shuts off the clocks

and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and

data is retained.

The availability of low-power modes, combined with a reprogrammable, single-chip, single-voltage

solution, make ProASIC3L devices suitable for low-power data transfer and manipulation in

portable media, secure communications, radio applications as well as high performance portable,

industrial, test, scientific, and medical applications.

ProASIC3L Device Family Overview

1-2 v1.3

Flash Advantages

Low Power

The ProASIC3L family of Actel flash-based FPGAs provide a low-power advantage, and when

coupled with high performance, enables designers to make power-smart choices using a single-

chip, reprogrammable, and live-at-power-up device.

ProASIC3L devices offer 40% dynamic power and 50% static power savings by reducing the core

operating voltage to 1.2 V. In addition, the Power Driven Layout (PDL) feature in Libero®

Integrated Design Environment (IDE) offers up to 30% additional power reduction. With

Flash*Freeze technology, ProASIC3L is able to retain device SRAM and logic while dynamic power is

reduced to a minimum, without the need to stop clock or power supplies. Combining these

features provides a low-power, feature-rich and high-performance solution.

Security

Nonvolatile, flash-based ProASIC3L devices do not require a boot PROM, so there is no vulnerable

external bitstream that can be easily copied. ProASIC3L devices incorporate FlashLock, which

provides a unique combination of reprogrammability and design security without external

overhead, advantages that only an FPGA with nonvolatile flash programming can offer.

ProASIC3L devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed

intellectual property and configuration data. In addition, all FlashROM data in ProASIC3L devices

can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher

encryption standard. AES was adopted by the National Institute of Standards and Technology

(NIST) in 2000 and replaces the 1977 DES standard. ProASIC3L devices have a built-in AES

decryption engine and a flash-based AES key that make them the most comprehensive

programmable logic device security solution available today. ProASIC3L devices with AES-based

security allow for secure, remote field updates over public networks such as the Internet, and

ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP

thieves. The contents of a programmed device cannot be read back, although secure design

verification is possible.

Security, built into the FPGA fabric, is an inherent component of the ProASIC3L family. The flash

cells are located beneath seven metal layers, and many device design and layout techniques have

been used to make invasive attacks extremely difficult. The ProASIC3L family, with FlashLock and

AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your

valuable IP is protected and secure, making remote ISP possible. A ProASIC3L device provides the

most impenetrable security for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed,

the configuration data is an inherent part of the FPGA structure, and no external configuration

data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based

ProASIC3L FPGAs do not require system configuration components such as EEPROMs or

microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB

area, and increases security and system reliability.

Live at Power-Up

The Actel flash-based ProASIC3L devices support Level 0 of the LAPU classification standard. This

feature helps in system component initialization, execution of critical tasks before the processor

wakes up, setup and configuration of memory blocks, clock generation, and bus activity

management. The LAPU feature of flash-based ProASIC3L devices greatly simplifies total system

design and reduces total system cost, often eliminating the need for CPLDs and clock generation

PLLs. In addition, glitches and brownouts in system power will not corrupt the ProASIC3L device's

flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when

system power is restored. This enables the reduction or complete removal of the configuration

PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB

design. Flash-based ProASIC3L devices simplify total system design and reduce cost and design risk

while increasing system reliability and improving system initialization time.

ProASIC3L Low-Power Flash FPGAs

v1.3 1-3

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike

SRAM-based FPGAs, flash-based ProASIC3L devices allow all functionality to be live at power-up; no

external boot PROM is required. On-board security mechanisms prevent access to all the

programming information and enable secure remote updates of the FPGA logic. Designers can

perform secure remote in-system reprogramming to support future design iterations and field

upgrades with confidence that valuable intellectual property cannot be compromised or copied.

Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3L family

device architecture mitigates the need for ASIC migration at higher user volumes. This makes the

ProASIC3L family a cost-effective ASIC replacement solution, manipulation in portable media and

secure communications, radio applications as well as high performance portable Industrial, test,

scientific and medical applications.

Firm-Error Immunity

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere,

strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way.

These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be

a complete system failure. Firm errors do not exist in the configuration memory of ProASIC3L flash-

based FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3L FPGAs

cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft)

errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error

detection and correction (EDAC) circuitry built into the FPGA fabric.

Advanced Flash Technology

The ProASIC3L family offers many benefits, including nonvolatility and reprogrammability, through

an advanced flash-based, 130-nm LVCMOS process with 7 layers of metal. Standard CMOS design

techniques are used to implement logic and control functions. The combination of fine granularity,

enhanced flexible routing resources, and abundant flash switches allows for very high logic

utilization without compromising device routability or performance. Logic functions within the

device are interconnected through a four-level routing hierarchy.

Advanced Architecture

The proprietary ProASIC3L architecture provides granularity comparable to standard-cell ASICs. The

ProASIC3L device consists of five distinct and programmable architectural features (Figure 1-1 on

page 1-4 and Figure 1-2 on page 1-4):

• FPGA VersaTiles

• Dedicated FlashROM

• Dedicated SRAM/FIFO memory

• Extensive CCCs and PLLs

• I/O structure

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input

logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate

flash switch interconnections. The versatility of the ProASIC3L core tile, as either a three-input

lookup table (LUT) equivalent or a D-flip-flop/latch with enable, allows for efficient use of the

FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation-

architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy.

Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable

interconnect programming. Maximum core utilization is possible for virtually any design.

In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V)

programming of ProASIC3L devices via an IEEE 1532 JTAG interface.

ProASIC3L Device Family Overview

1-4 v1.3

Figure 1-1 • ProASIC3L Device Architecture Overview with Four I/O Banks (A3P250L, A3P600L, and A3P1000L)

Figure 1-2 • ProASIC3EL Device Architecture Overview

ISP AES

Decryption*

User Nonvolatile

FlashRom

Flash*Freeze

Technology

Charge

Pumps

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

(A3P600L and A3P1000L)

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

VersaTile

CCC

I/Os

Bank 0

Bank 3Bank 3

Bank 1Bank 1

Bank 2

4,608-Bit Dual-Port SRAM

or FIFO Block

VersaTile

RAM Block

CCC

Pro I/Os

4,608-Bit Dual-Port SRAM

or FIFO Block

RAM Block

ISP AES

Decryption*

User Nonvolatile

FlashRom

Flash*Freeze

Technology

Charge

Pumps

ProASIC3L Low-Power Flash FPGAs

v1.3 1-5

Flash*Freeze Technology

The ProASIC3L devices offer Actel's proven Flash*Freeze technology, which enables designers to

instantaneously shut off dynamic power consumption while retaining all SRAM and register

information. Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit

Flash*Freeze mode by activating the Flash*Freeze (FF) pin while all power supplies are kept at their

original values. In addition, I/Os and global I/Os can still be driven and can be toggling without

impact on power consumption; clocks can still be driven or can be toggling without impact on

power consumption; and the device retains all core registers, SRAM information, and states. I/O

states are tristated during Flash*Freeze mode or can be set to a certain state using weak pull-up or

pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or

PLL. Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying

the power management of the device.

The FF pin (active low) can be routed internally to the core to allow the user's logic to decide when

it is safe to transition to this mode. It is also possible to use the FF pin as a regular I/O if

Flash*Freeze mode usage is not planned, which is advantageous because of the inherent low-

power static and dynamic capabilities of the ProASIC3L device. Refer to Figure 1-3 for an

illustration of entering/exiting Flash*Freeze mode.

VersaTiles

The ProASIC3L core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS®

core tiles. The ProASIC3L VersaTile supports the following:

• All 3-input logic functions—LUT-3 equivalent

• Latch with clear or set

• D-flip-flop with clear or set

• Enable D-flip-flop with clear or set

Refer to Figure 1-4 for VersaTile configurations.

Figure 1-3 • ProASIC3L Flash*Freeze Mode

Actel ProASIC3L

FPGA

Flash*Freeze

Mode Control

Flash*Freeze Pin

Figure 1-4 • VersaTile Configurations

LUT-3

Data Y

CLK

Enable

CLR

D-FF

Data Y

CLK

CLR

D-FF

LUT-3 Equivalent D-Flip-Flop with Clear or Set Enable D-Flip-Flop with Clear or Set

ProASIC3L Device Family Overview

1-6 v1.3

User Nonvolatile FlashROM

Actel ProASIC3L devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The

FlashROM can be used in diverse system applications:

• Internet Protocol addressing (wireless or fixed)

• System calibration settings

• Device serialization and/or inventory control

• Subscription-based business models (for example, set-top boxes)

• Secure key storage for secure communications algorithms

• Asset management/tracking

• Date stamping

• Version management

The FlashROM is written using the standard ProASIC3L IEEE 1532 JTAG programming interface.The

core can be individually programmed (erased and written), and on-chip AES decryption can be used

selectively to securely load data over public networks, as in security keys stored in the FlashROM for

a user design.

The FlashROM can be programmed via the JTAG programming interface, and its contents can be

read back either through the JTAG programming interface or via direct FPGA core addressing. Note

that the FlashROM can only be programmed from the JTAG interface and cannot be programmed

from the internal logic array.

The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-

byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8

banks and which of the 16 bytes within that bank are being read. The three most significant bits

(MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of

the FlashROM address define the byte.

The Actel ProASIC3L development software solutions, Libero IDE and Designer, have extensive

support for the FlashROM. One such feature is auto-generation of sequential programming files

for applications requiring a unique serial number in each part. Another feature allows the inclusion

of static data for system version control. Data for the FlashROM can be generated quickly and

easily using Actel Libero IDE and Designer software tools. Comprehensive programming file

support is also included to allow for easy programming of large numbers of parts with differing

FlashROM contents.

SRAM and FIFO

ProASIC3L devices have embedded SRAM blocks along their north and south sides. Each variable-

aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9,

1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be

configured with different bit widths on each port. For example, data can be sent through a 4-bit

port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device

JTAG port (ROM emulation mode) using the UJTAG macro.

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the

SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The

FIFO width and depth are programmable. The FIFO also features programmable Almost Empty

(AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The

embedded FIFO control unit contains the counters necessary for generation of the read and write

address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

ProASIC3L devices provide designers with flexible clock conditioning circuit (CCC) capabilities. Each

member of the ProASIC3L family contains six CCCs. One CCC (center west side) has a PLL.

The six CCC blocks are located at the four corners and the centers of the east and west sides. One

CCC (center west side) has a PLL.

All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay

operations as well as clock spine access.

ProASIC3L Low-Power Flash FPGAs

v1.3 1-7

The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs

located near the CCC that have dedicated connections to the CCC block.

The CCC block has these key features:

• Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz

• Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz

• 2 programmable delay types for clock skew minimization

• Clock frequency synthesis

Additional CCC specifications:

• Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output

divider configuration.

• Output duty cycle = 50% ± 1.5% or better

• Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single

global network used

• Maximum acquisition time is 300 µs

• Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns

• Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /

fOUT_CCC

Global Clocking

ProASIC3L devices have extensive support for multiple clocking domains. In addition to the CCC

and PLL support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three

quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the

core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for

rapid distribution of high-fanout nets.

I/Os with Advanced I/O Standards

The ProASIC3L family of FPGAs features a flexible I/O structure, supporting a range of voltages

(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). ProASIC3L FPGAs support different I/O

standards, including single-ended, differential, and voltage-referenced (ProASIC3EL only). The I/Os

are organized into banks, with two, four, or eight (ProASIC3EL only) banks per device. The

configuration of these banks determines the I/O standards supported. For ProASIC3EL, each I/O

bank is subdivided into VREF minibanks, which are used by voltage-referenced I/Os. VREF minibanks

contain 8 to 18 I/Os. All the I/Os in a given minibank share a common VREF line. Therefore, if any I/O

in a given VREF minibank is configured as a VREF pin, the remaining I/Os in that minibank will be

able to use that reference voltage.

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of the following:

• Single-data-rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)

• Double-data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point

communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II).

ProASIC3L banks support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can support up to

20 loads.

Wide Range I/O Support

Actel ProASIC3L devices support JEDEC-defined wide range I/O operation. ProASIC3L devices

support both the JESD8-B specification, covering 3 V and 3.3 V supplies, for an effective operating

range of 2.7 V to 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating

range of 1.14 V to 1.575 V.

Wider I/O range means designers can eliminate power supplies or power conditioning components

from the board or move to less costly components with greater tolerances. Wide range eases I/O

bank management and provides enhanced protection from system voltage spikes, while providing

the flexibility to easily run custom voltage applications.

ProASIC3L Device Family Overview

1-8 v1.3

Part Number and Revision Date

Part Number 51700100-001-4

Revised February 2009

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous Version Changes in Current Version (v1.3) Page

v1.2

(February 2009)

The "I/Os Per Package 1" table was revised to change the number of differential

I/O pairs for A3PE3000L from 300 to 310.

Table 2 · ProASIC3L FPGAs Package Sizes Dimensions is new. II

v1.1

(July 2008)

The "Advanced and Pro (Professional) I/Os" section was revised to add two

bullets regarding wide range power supply voltage support.

3.0 V wide range was added to the list of supported voltages in the "I/Os with

Advanced I/O Standards" section. The "Wide Range I/O Support" section is new.

1-7

v1.0

(April 2008)

As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core

voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to

1.5 V.

N/A

51700100-001-1

(April 2008)

This document was divided into two sections and given a version number,

starting at v1.0. The first section of the document includes features, benefits,

ordering information, and temperature and speed grade offerings. The second

section is a device family overview.

N/A

51700100-001-0

(January 2008)

Reference to M1A3P250L was removed from Table 1 · ProASIC3 Low-Power

Product Family, the "I/Os Per Package 1" table, the "ProASIC3L Ordering

Information" section, and the "Temperature Grade Offerings" table. The table

note regarding M1A3P250L was removed from the "I/Os Per Package 1" table.

I, II, III, IV

ProASIC3L Low-Power Flash FPGAs

v1.3 1-9

Datasheet Categories

Categories

In order to provide the latest information to designers, some datasheets are published before data

has been fully characterized. Datasheets are designated as "Product Brief," "Advance,"

"Preliminary," and "Production." The definitions of these categories are as follows:

Product Brief

The product brief is a summarized version of a datasheet (advance or production) and contains

general product information. This document gives an overview of specific device and family

information.

Advance

This version contains initial estimated information based on simulation, other products, devices, or

speed grades. This information can be used as estimates, but not for production. This label only

applies to the DC and Switching Characteristics chapter of the datasheet and will only be used

when the data has not been fully characterized.

Preliminary

The datasheet contains information based on simulation and/or initial characterization. The

information is believed to be correct, but changes are possible.

Unmarked (production)

This version contains information that is considered to be final.

Export Administration Regulations (EAR)

The products described in this document are subject to the Export Administration Regulations

(EAR). They could require an approved export license prior to export from the United States. An

export includes release of product or disclosure of technology to a foreign national inside or

outside the United States.

Actel Safety Critical, Life Support, and High-Reliability

Applications Policy

The Actel products described in this advance status document may not have completed Actel’s

qualification process. Actel may amend or enhance products during the product introduction and

qualification process, resulting in changes in device functionality or performance. It is the

responsibility of each customer to ensure the fitness of any Actel product (but especially a new

product) for a particular purpose, including appropriateness for safety-critical, life-support, and

other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability

exclusions relating to life-support applications. A reliability report covering all of Actel’s products is

available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also

offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your

local Actel sales office for additional reliability information.

Advance v0.6 2-1

2 – ProASIC3L DC and Switching Characteristics

General Specifications

Operating Conditions

Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or

any other conditions beyond those listed under the Recommended Operating Conditions specified

in Table 2-2 on page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol Parameter Limits Units

VCC DC core supply voltage –0.3 to 1.65 V

VJTAG JTAG DC voltage –0.3 to 3.75 V

VPUMP Programming voltage –0.3 to 3.75 V

VCCPLL Analog power supply (PLL) –0.3 to 1.65 V

VCCI and

VMV 3DC I/O buffer supply voltage –0.3 to 3.75 V

VI I/O input voltage –0.3 V to 3.6 V (when I/O hot insertion mode is enabled)

–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower

(when I/O hot-insertion mode is disabled)

TSTG 2Storage temperature –65 to +150 °C

TJ2Junction temperature +125 °C

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input

signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.

2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for

recommended operating limits, refer to Table 2-2 on page 2-2.

3. VMV pins must be connected to the corresponding VCCI pins. See Pin Descriptions for further information.

ProASIC3L DC and Switching Characteristics

2-2 Advance v0.6

Table 2-2 • Recommended Operating Conditions 1

Symbol Parameter Commercial Industrial Units

TAAmbient temperature 0 to +70 –40 to +85 °C

TJJunction Temperature 0 to + 85 –40 to +100 °C

VCC 21.2 V–1.5 V wide range core voltage 1.14 to 1.575 1.14 to 1.575 V

VJTAG JTAG DC voltage 1.4 to 3.6 1.4 to 3.6 V

VPUMP 3Programming voltage Programming Mode 3.15 to 3.45 3.15 to 3.45 V

Operation 30 to 3.45 0 to 3.45 V

VCCPLL 6Analog power supply (PLL) 1.2 V–1.5 V wide range

core voltage

1.14 to 1.575 1.14 to 1.575 V

VCCI and VMV 51.2 V DC supply voltage4 1.14 to 1.26 1.14 to 1.26 V

1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V

1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V

2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V

3.3 V wide range DC supply voltage7 2.7 to 3.6 2.7 to 3.6 V

3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V

LVDS differential I/O 2.375 to 2.625 2.375 to 2.625 V

LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V

Notes:

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each

I/O standard are given in Table 2-13 on page 2-10. VCCI should be at the same voltage within a given I/O

bank.

3. VPUMP can be left floating during normal operation (not programming mode).

4. For ProASIC®3L devices, VCCI

≥

VCC.

5. VMV pins must be connected to the corresponding VCCI pins. See Pin Descriptions for further information.

6. VCCPLL pins should be tied to VCC pins. See Pin Descriptions for further information.

7. 3.3 V wide range is compliant to the JDEC8a specification and supports 3.0 V VCCI operation.

Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature1

Product Grade

Programming

Cycles

Program Retention

(biased/unbiased)

Maximum Storage

Temperature TSTG (°C) 2

Maximum Operating

Junction Temperature TJ (°C) 2

Commercial 500 20 years 110 100

Industrial 500 20 years 110 100

Notes:

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device

operating conditions and absolute limits.

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-3

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every ProASIC3 device. These

circuits ensure easy transition from the powered-off state to the powered-up state of the device.

The many different supplies can power up in any sequence with minimized current spikes or surges.

In addition, the I/O will be in a known state through the power-up sequence. The basic principle is

shown in Figure 2-1 on page 2-4 and Figure 2-2 on page 2-5.

There are five regions to consider during power-up.

ProASIC3 I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4 and

Figure 2-2 on page 2-5).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This

specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note

the following:

• During programming, I/Os become tristated and weakly pulled up to VCCI.

• JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

Table 2-4 • Overshoot and Undershoot Limits 1

VCCI

Average VCCI–GND Overshoot or Undershoot

Duration as a Percentage of Clock Cycle2Maximum Overshoot/

Undershoot2

2.7 V or less 10% 1.4 V

5% 1.49 V

3 V 10% 1.1 V

5% 1.19 V

3.3 V 10% 0.79 V

5% 0.88 V

3.6 V 10% 0.45 V

5% 0.54 V

Notes:

1. Based on reliability requirements at junction temperature at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at

one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.

3. This table does not provide PCI overshoot/undershoot limits.

ProASIC3L DC and Switching Characteristics

2-4 Advance v0.6

PLL Behavior at Brownout Condition

Actel recommends using monotonic power supplies or voltage regulators to ensure proper

powerup behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed

brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1

and Figure 2-2 on page 2-5 for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V

± 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the

Power-Up/-Down Behavior of Low-Power Flash Devices chapter of the handbook for information

on clock and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

Output buffers, after 200 ns delay from input buffer activation.

Figure 2-1 • V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

but slower because VCCI/VCC are below

specification. For the same reason, input

buffers do not meet VIH/VIL levels, and

output buffers do not meet VOH/VOL levels.

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

VCC

VCC = 1.425 V

Region 1: I/O Buffers are OFF

Activation trip point:

Va = 0.85 V ± 0.25 V

Deactivation trip point:

Vd = 0.75 V ± 0.25 V

Activation trip point:

Va = 0.9 V ± 0.3 V

Deactivation trip point:

Vd = 0.8 V ± 0.3 V

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, VIH/VIL , VOH/VOL , etc.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

but slower because VCCI is

below specification. For the

same reason, input buffers do not

meet VIH/VIL levels, and output

buffers do not meet VOH/VOL levels.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCCI

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

VCC = VCCI + VT

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-5

Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

but slower because V

CCI

are below

specification. For the same reason, input

buffers do not meet V

levels, and

output buffers do not meet V

levels.

Min V

CCI

datasheet specification

voltage at a selected I/O

standard; i.e., 1.14 V,1.425 V, 1.7 V,

2.3 V, or 3.0 V

= 1.14 V

Region 1: I/O Buffers are OFF

Activation trip point:

= 0.85 V ± 0.2 V

Deactivation trip point:

= 0.75 V ± 0.2 V

Activation trip point:

= 0.9 V ± 0.15 V

Deactivation trip point:

= 0.8 V ± 0.15 V

= 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, V

, V

, etc.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

but slower because V

CCI

below specification. For the

same reason, input buffers do not

meet V

levels, and output

buffers do not meet V

levels.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

CCI

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the V

is below specification.

= V

CCI

+ VT

ProASIC3L DC and Switching Characteristics

2-6 Advance v0.6

Thermal Characteristics

Introduction

The temperature variable in the Actel Designer software refers to the junction temperature, not

the ambient temperature. This is an important distinction because dynamic and static power

consumption cause the chip junction temperature to be higher than the ambient temperature.

EQ 2-1 can be used to calculate junction temperature.

TJ = Junction Temperature = ΔT + TA

EQ 2-1

where:

TA = Ambient Temperature

ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θja * P

θja = Junction-to-ambient of the package. θja numbers are located in Table 2-5.

P = Power dissipation

Package Thermal Characteristics

The device junction-to-case thermal resistivity is θjc and the junction-to-ambient air thermal

resistivity is θja. The thermal characteristics for θja are shown for two air flow rates. The absolute

maximum junction temperature is 100°C. EQ 2-2 shows a sample calculation of the absolute

maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and

in still air.

EQ 2-2

Maximum Power Allowed Max. junction temp. (°C) Max. ambient temp. (°C)–

θja(°C/W)

--------------------------------------------------------------------------------------------------------------------------------------- 100°C70°C–

20.5°C/W

------------------------------------ 1 . 4 6 3 W===

Table 2-5 • Package Thermal Resistivities

Package Type Device Pin Count θjc

θja

UnitsStill Air 200 ft./min. 500 ft./min.

Very Thin Quad Flat Pack (VQFP) All devices 100 10.0 35.3 29.4 27.1 C/W

Plastic Quad Flat Pack (PQFP) All devices 208 8.0 26.1 22.5 20.8 C/W

PQFP with embedded heatspreader All devices 208 3.8 16.2 13.3 11.9 C/W

Fine Pitch Ball Grid Array (FBGA) A3P250L 144 12.2 43.8 37.7 35.8 C/W

A3P600L 144 8.3 35.8 30.2 28.3 C/W

A3P1000L 144 6.3 31.6 26.2 24.2 C/W

A3P250L 256 12.0 38.6 34.7 33.0 C/W

A3P600L 256 8.5 32.0 27.5 25.8 C/W

A3P1000L 256 6.6 28.1 24.4 22.7 C/W

AGLE3000 324 TBD TBD TBD TBD C/W

A3P600L 484 9.5 27.5 21.9 20.2 C/W

A3P1000L 484 8.0 23.3 19.0 16.7 C/W

A3PE3000L 484 4.7 20.6 15.7 14.0 C/W

A3PE3000L 896 2.4 13.6 10.4 9.4 C/W

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-7

Temperature and Voltage Derating Factors

Calculating Power Dissipation

Quiescent Supply Current

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to TJ = 70°C, VCC = 1.14 V)

Array Voltage VCC (V)

Junction Temperature (°C)

–40°C 0°C 25°C 70°C 85°C 110°C

1.14 0.90 0.94 0.96 1.00 1.01 1.03

1.2 0.870.900.920.960.970.99

1.26 0.83 0.86 0.88 0.92 0.93 0.85

1.3 0.810.840.860.900.910.93

1.35 0.78 0.81 0.83 0.87 0.88 0.89

1.4 0.750.780.800.830.840.86

1.425 0.74 0.77 0.78 0.82 0.83 0.85

1.5 0.700.720.740.770.790.80

1.575 0.67 0.70 0.72 0.75 0.76 0.77

Table 2-7 • Quiescent Supply Current (IDD) Characteristics, ProASIC3L Flash*Freeze Mode*

Core Voltage A3P250L A3P600L A3P1000L A3PE3000L Units

Typical (25°C) 1.2 V 0.33 0.55 0.88 2.75 mA

1.5 V mA

*IDD includes VCC, VPUMP, VCCI, VJTAG , and VCCPLL currents. Values do not include I/O static contribution (PDC6

and PDC7).

Table 2-8 • Quiescent Supply Current (IDD) Characteristics, ProASIC3L Sleep Mode (VCC = 0 V)*

Core Voltage A3P250L A3P600L A3P1000L A3PE3000L Units

VCCI / VJTAG = 1.2 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 1.7 1.7 1.7 1.7 µA

VCCI / VJTAG = 1.5 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 1.8 1.8 1.8 1.8 µA

VCCI / VJTAG = 1.8 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 1.9 1.9 1.9 1.9 µA

VCCI / VJTAG = 2.5 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 2.2 2.2 2.2 2.2 µA

VCCI / VJTAG = 3.3 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 2.5 2.5 2.5 2.5 µA

*IDD includes VCC , VPUMP, and VCCPLL currents. Values do not include I/O static contribution (PDC6 and PDC7).

Table 2-9 • Quiescent Supply Current (IDD) Characteristics, Shutdown Mode (VCC, VCCI = 0 V)

Core Voltage A3PE3000L Units

Typical (25°C) 1.2 V / 1.5 V 0 µA

*IDD includes VCC , VPUMP, VCCI, VJTAG, and VCCPLL currents. Values do not include I/O static contribution (PDC6

and PDC7).

ProASIC3L DC and Switching Characteristics

2-8 Advance v0.6

Table 2-10 • Quiescent Supply Current (IDD), No ProASIC3L Flash*Freeze Mode1

Core Voltage A3P250L A3P600L A3P1000L A3PE3000L Units

ICCA Current2

Typical (25°C) 1.2 V 0.33 0.55 0.88 2.75 mA

1.5 V mA

ICCI or IJTAG Current3, 4

VCCI / VJTAG = 1.2 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 1.7 1.7 1.7 1.7 µA

VCCI / VJTAG = 1.5 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 1.8 1.8 1.8 1.8 µA

VCCI / VJTAG = 1.8 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 1.9 1.9 1.9 1.9 µA

VCCI / VJTAG = 2.5 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 2.2 2.2 2.2 2.2 µA

VCCI / VJTAG = 3.3 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 2.5 2.5 2.5 2.5 µA

Notes:

1. To calculate total device IDD, multiply the number of banks used by ICCI and add ICCA contribution.

2. Includes VCC , VCCPLL, and VPUMP currents.

3. Per VCCI or VJTAG bank.

4. Values do not include I/O static contribution (PDC6 and PDC7).

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-9

Power per I/O Pin

Table 2-11 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to Pro I/O Banks

VCCI (V)

Static Power

PDC6 (mW)1Dynamic Power

PAC9 (µW/MHz)2

Single-Ended

3.3 V LVTTL/LVCMOS 3.3 – 16.34

3.3 V LVTTL/LVCMOS – Schmitt trigger 3.3 – 24.49

2.5 V LVCMOS 2.5 – 4.71

2.5 V LVCMOS – Schmitt trigger 2.5 – 6.13

1.8 V LVCMOS 1.8 – 1.66

1.8 V LVCMOS – Schmitt trigger 1.8 – 1.78

1.5 V LVCMOS (JESD8-11) 1.5 – 1.01

1.5 V LVCMOS (JESD8-11) – Schmitt trigger 1.5 – 0.97

1.2 V LVCMOS 1.2 – 0.60

1.2 V LVCMOS – Schmitt trigger 1.2 – 0.53

3.3 V PCI 3.3 – 17.76

3.3 V PCI – Schmitt trigger 3.3 – 19.10

3.3 V PCI-X 3.3 – 17.76

3.3 V PCI-X – Schmitt trigger 3.3 – 19.10

Voltage-Referenced

3.3 V GTL 3.3 2.90 7.07

2.5 V GTL 2.5 2.13 3.62

3.3 V GTL+ 3.3 2.81 2.97

2.5 V GTL+ 2.5 2.57 2.55

HSTL (I) 1.5 0.17 0.85

HSTL (II) 1.5 0.17 0.85

SSTL2 (I) 2.5 1.38 3.30

SSTL2 (II) 2.5 1.38 3.30

SSTL3 (I) 3.3 3.21 8.08

SSTL3 (II) 3.3 3.21 8.08

Differential

LVDS 2.5 2.26 0.95

LVPECL 3.3 5.71 1.62

Notes:

1. PDC6 is the static power (where applicable) measured on VCCI.

2. PAC9 is the total dynamic power measured on VCCI.

ProASIC3L DC and Switching Characteristics

2-10 Advance v0.6

Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings1

Applicable to Advanced I/O Banks

VCCI (V)

Static Power

PDC6 (mW)2Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 16.22

2.5 V LVCMOS 2.5 – 4.65

1.8 V LVCMOS 1.8 – 1.65

1.5 V LVCMOS (JESD8-11) 1.5 – 0.98

1.2 V LVCMOS 1.2 – 0.61

3.3 V PCI 3.3 – 17.64

3.3 V PCI-X 3.3 – 17.64

Differential

LVDS 2.5 2.26 0.95

LVPECL 3.3 5.72 1.63

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output

slew.

2. PDC6 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to Standard Plus I/O Banks

VCCI (V)

Static Power

PDC6 (mW)1Dynamic Power

PAC9 (µW/MHz)2

Single-Ended

3.3 V LVTTL /

3.3 V LVCMOS

3.3 – 16.23

2.5 V LVCMOS 2.5 – 4.66

1.8 V LVCMOS 1.8 – 1.64

1.5 V LVCMOS (JESD8-11) 1.5 – 0.99

1.2 V LVCMOS 1.2 – 0.58

3.3 V PCI 3.3 – 17.64

3.3 V PCI-X 3.3 – 17.64

Notes:

1. PDC6 is the static power (where applicable) measured on VCCI.

2. PAC9 is the total dynamic power measured on VCCI.

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-11

Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1

Applicable to Pro I/Os

CLOAD (pF) VCCI (V)

Static Power

PDC7 (mW)2Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL/LVCMOS 5 3.3 – 148.00

2.5 V LVCMOS 5 2.5 – 83.23

1.8 V LVCMOS 5 1.8 – 54.58

1.5 V LVCMOS (JESD8-11) 5 1.5 – 37.05

1.2 V LVCMOS 5 1.2 – 17.94

3.3 V PCI 10 3.3 – 204.61

3.3 V PCI-X 10 3.3 – 204.61

Voltage-Referenced

3.3 V GTL 10 3.3 – 24.08

2.5 V GTL 10 2.5 – 13.52

3.3 V GTL+ 10 3.3 – 24.10

2.5 V GTL+ 10 2.5 – 13.54

HSTL (I) 20 1.5 7.08 26.22

HSTL (II) 20 1.5 13.88 27.22

SSTL2 (I) 30 2.5 16.69 105.56

SSTL2 (II) 30 2.5 25.91 116.60

SSTL3 (I) 30 3.3 26.02 114.87

SSTL3 (II) 30 3.3 42.21 131.76

Differential

LVDS – 2.5 7.70 89.62

LVPECL – 3.3 19.42 168.02

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output

slew.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

ProASIC3L DC and Switching Characteristics

2-12 Advance v0.6

Table 2-15 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1

Applicable to Advanced I/O Banks

CLOAD (pF) VCCI (V)

Static Power

PDC7 (mW)2Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 5 3.3 – 141.97

2.5 V LVCMOS 5 2.5 – 79.98

1.8 V LVCMOS 5 1.8 – 52.26

1.5 V LVCMOS (JESD8-11) 5 1.5 – 35.62

1.2 V LVCMOS 5 1.2 – 21.29

3.3 V PCI 10 3.3 – 201.02

3.3 V PCI-X 10 3.3 – 201.02

Differential

LVDS – 2.5 7.74 89.71

LVPECL – 3.3 19.54 167.54

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output

slew.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

Table 2-16 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1

Applicable to Standard Plus I/O Banks

CLOAD (pF) VCCI (V)

Static Power

PDC7 (mW)2Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 5 3.3 – 125.97

2.5 V LVCMOS 5 2.5 – 70.82

1.8 V LVCMOS 5 1.8 – 36.39

1.5 V LVCMOS (JESD8-11) 5 1.5 – 25.34

1.2 V LVCMOS 5 1.2 – 16.24

3.3 V PCI 10 3.3 – 184.92

3.3 V PCI-X 10 3.3 – 184.92

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output

slew.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-13

Power Consumption of Various Internal Resources

Table 2-17 • Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at

1.2 V VCC

Parameter Definition

Device Specific Dynamic Power (µW/MHz)

A3PE3000L A3P1000L A3P600L A3P250L

PAC1 Clock contribution of a Global Rib 12.61 9.28 8.19 7.07

PAC2 Clock contribution of a Global Spine 2.66 1.59 1.19 1.01

PAC3 Clock contribution of a VersaTile row 0.56 0.52

PAC4 Clock contribution of a VersaTile used as a sequential

module

0.07

PAC5 First contribution of a VersaTile used as a sequential

module

0.05

PAC6 Second contribution of a VersaTile used as a

sequential module

0.19

PAC7 Contribution of a VersaTile used as a combinatorial

Module

0.11

PAC8 Average contribution of a routing net 0.45

PAC9 Contribution of an I/O input pin (standard-dependent) See Table 2-11 on page 2-9. through

Table 2-13 on page 2-10.

PAC10 Contribution of an I/O output pin (standard-

dependent)

See Table 2-14 on page 2-11 through

Table 2-16 on page 2-12.

PAC11 Average contribution of a RAM block during a read

operation

25.00

PAC12 Average contribution of a RAM block during a write

operation

30.00

PAC13 Dynamic contribution for PLL 1.74

*For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet

calculator or SmartPower tool in Libero IDE.

ProASIC3L DC and Switching Characteristics

2-14 Advance v0.6

Table 2-18 • Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at

1.5 V VCC

Parameter Definition

Device Specific Dynamic Power (µW/MHz)

A3PE3000L A3P1000L A3P600L A3P250L

PAC1 Clock contribution of a Global Rib 19.7 14.50 12.80 11.00

PAC2 Clock contribution of a Global Spine 4.16 2.48 1.85 1.58

PAC3 Clock contribution of a VersaTile row 0.88 0.81

PAC4 Clock contribution of a VersaTile used as a sequential

module

0.12

PAC5 First contribution of a VersaTile used as a sequential

module

0.07

PAC6 Second contribution of a VersaTile used as a

sequential module

0.29

PAC7 Contribution of a VersaTile used as a combinatorial

Module

0.29

PAC8 Average contribution of a routing net 0.70

PAC9 Contribution of an I/O input pin (standard-

dependent)

See Table 2-11 on page 2-9. through

Table 2-13 on page 2-10.

PAC10 Contribution of an I/O output pin (standard-

dependent)

See Table 2-14 on page 2-11 through

Table 2-16 on page 2-12.

PAC11 Average contribution of a RAM block during a read

operation

25.00

PAC12 Average contribution of a RAM block during a write

operation

30.00

PAC13 Dynamic contribution for PLL 2.60

*For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet

calculator or SmartPower tool in Libero IDE.

Table 2-19 • Different Components Contributing to the Static Power Consumption in ProASIC3L Devices

Parameter Definition

Device Specific Dynamic Power (µW)

A3PE3000L A3P1000L A3P600L A3P250L

PDC1 Array static power in Active mode See Table 2-10 on page 2-8.

PDC2 Array static power in Static (Idle) mode See Table 2-8 on page 2-7.

PDC3 Array static power in Flash*Freeze mode See Table 2-7 on page 2-7.

PDC4 Static PLL contribution at 1.2 V core (operating

mode only)

1.42 mW

Static PLL contribution at 1.5 V core (operating

mode only)

2.55 mW

PDC5 Bank quiescent power (VCCI-dependent) See Table 2-7 on page 2-7, Table 2-8 on

page 2-7, Table 2-10 on page 2-8.

PDC6 I/O input pin static power (standard-dependent) See Table 2-11 on page 2-9 through

Table 2-13 on page 2-10.

PDC7 I/O output pin static power (standard-dependent) See Table 2-14 on page 2-11 through

Table 2-16 on page 2-12.

*For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet

calculator or SmartPower tool in Libero IDE.

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-15

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For

more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE

software.

The power calculation methodology described below uses the following variables:

• The number of PLLs as well as the number and the frequency of each output clock

generated

• The number of combinatorial and sequential cells used in the design

•The internal clock frequencies

• The number and the standard of I/O pins used in the design

• The number of RAM blocks used in the design

• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-20 on

page 2-17.

• Enable rates of output buffers—guidelines are provided for typical applications in

Table 2-21 on page 2-17.

• Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-21 on page 2-17. The calculation should be repeated for each clock domain defined

in the design.

Methodology

Total Power Consumption—PTOTAL

PTOTAL = PSTAT + PDYN

PSTAT is the total static power consumption.

PDYN is the total dynamic power consumption.

Total Static Power Consumption—PSTAT

PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS* PDC5 + NINPUTS* PDC6 + NOUTPUTS* PDC7

NINPUTS is the number of I/O input buffers used in the design.

NOUTPUTS is the number of I/O output buffers used in the design.

NBANKS is the number of I/O banks powered in the design.

Total Dynamic Power Consumption—PDYN

PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL

Global Clock Contribution—PCLOCK

PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK

NSPINE is the number of global spines used in the user design—guidelines are provided

in Table 2-20 on page 2-17.

NROW is the number of VersaTile rows used in the design—guidelines are provided in

Table 2-20 on page 2-17.

FCLK is the global clock signal frequency.

NS-CELL is the number of VersaTiles used as sequential modules in the design.

PAC1, PAC2, PAC3, and PAC4 are device-dependent.

Sequential Cells Contribution—PS-CELL

PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design. When a

multi-tile sequential cell is used, it should be accounted for as 1.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-20 on

page 2-17.

FCLK is the global clock signal frequency.

ProASIC3L DC and Switching Characteristics

2-16 Advance v0.6

Combinatorial Cells Contribution—PC-CELL

PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-20 on

page 2-17.

FCLK is the global clock signal frequency.

Routing Net Contribution—PNET

PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design.

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-20 on

page 2-17.

FCLK is the global clock signal frequency.

I/O Input Buffer Contribution—PINPUTS

PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK

NINPUTS is the number of I/O input buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-20 on page 2-17.

FCLK is the global clock signal frequency.

I/O Output Buffer Contribution—POUTPUTS

POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK

NOUTPUTS is the number of I/O output buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-20 on page 2-17.

β1 is the I/O buffer enable rate—guidelines are provided in Table 2-21 on page 2-17.

FCLK is the global clock signal frequency.

RAM Contribution—PMEMORY

PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3

NBLOCKS is the number of RAM blocks used in the design.

FREAD-CLOCK is the memory read clock frequency.

β2 is the RAM enable rate for read operations.

FWRITE-CLOCK is the memory write clock frequency.

β3 is the RAM enable rate for write operations—guidelines are provided in Table 2-21

on page 2-17.

PLL Contribution—PPLL

PPLL = PDC4 + PAC13 *FCLKOUT

FCLKOUT is the output clock frequency.1

1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its

corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution.

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-17

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage.

If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency.

Below are some examples:

• The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at

half of the clock frequency.

• The average toggle rate of an 8-bit counter is 25%:

– Bit 0 (LSB) = 100%

– Bit 1 = 50%

– Bit 2 = 25%

–…

– Bit 7 (MSB) = 0.78125%

– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled.

When nontristate output buffers are used, the enable rate should be 100%.

Table 2-20 • Toggle Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

α1Toggle rate of VersaTile outputs 10%

α2I/O buffer toggle rate 10%

Table 2-21 • Enable Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

β1I/O output buffer enable rate 100%

β2RAM enable rate for read operations 12.5%

β3RAM enable rate for write operations 12.5%

ProASIC3L DC and Switching Characteristics

2-18 Advance v0.6

User I/O Characteristics

Timing Model

Figure 2-3 • Timing Model

Operating Conditions: –1 Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case

VCC =1.14V

DQ DQ

Combinational Cell

I/O Module

(Registered)

I/O Module

(Non-Registered)

I/O Module

(Registered)

I/O Module

(Non-Registered)

LVPECL (Applicable to

Advanced I/O Banks Only)L

LVPECL

(Applicable

to Advanced

I/O Banks only)

LVDS,

BLVDS,

M-LVDS

(Applicable for

Advanced I/O

Banks only)

LVTTL 3.3 V Output drive

strength = 12 mA High slew rate

Combinational Cell

I/O Module

(Non-Registered)

LVTTL Output drive strength = 8 mA

High slew rate

I/O Module

(Non-Registered)

LVCMOS 1.5 V Output drive strength = 4 mA

High slew rate

LVTTL Output drive strength = 12 mA

High slew rate

I/O Module

(Non-Registered)

Input LVTTL

Clock

Input LVTTL

Clock

Input LVTTL

Clock

tPD = 0.56 ns tPD = 0.49 ns

tDP = 1.34 ns

tPD = 0.87 ns tDP = 2.64 ns (Advanced I/O Banks)

tPD = 0.47 ns

tDP = 3.66 ns (Advanced I/O Banks)

tPD = 0.47 ns tDP = 3.97 ns (Advanced I/O Banks)

tPD = 0.47 ns

tPY = 0.76 ns

(Advanced I/O Banks)

tCLKQ = 0.55 ns tOCLKQ = 0.59 ns

tSUD = 0.43 ns tOSUD = 0.31 ns

tDP = 2.64 ns

(Advanced I/O Banks)

tPY = 0.76 ns (Advanced I/O Banks)

tPY = 1.20 ns

tCLKQ = 0.55 ns

tSUD = 0.43 ns

tPY = 0.76 ns

(Advanced I/O Banks)

tICLKQ = 0.24 ns

tISUD = 0.26 ns

tPY = 1.05 ns

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-19

Figure 2-4 • Input Buffer Timing Model and Delays (example)

tPY

(R)

PAD

Vtrip

GND tPY

(F)

Vtrip

50%

VIH

VCC

VIL

tDOUT

(R)

DIN

GND tDOUT

(F)

50%50%

VCC

PAD Y

tPY

CLK

I/O Interface

DIN

tDIN

To Array

tPY = MAX(tPY(R), tPY(F))

tDIN = MAX(tDIN(R), tDIN(F))

ProASIC3L DC and Switching Characteristics

2-20 Advance v0.6

Figure 2-5 • Output Buffer Model and Delays (example)

tDP

(R)

PAD VOL

tDP

(F)

Vtrip

VOH

VCC

D50%50%

VCC

0 V

DOUT 50%50%0 V

tDOUT

(R)

tDOUT

(F)

From Array

PAD

tDP

Std

Load

CLK

I/O Interface

DOUT

tDOUT

tDP = MAX(tDP(R), tDP(F))

tDOUT = MAX(tDOUT(R), tDOUT(F))

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-21

Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example)

CLK

10% V

CCI

trip

50%

90% V

CCI

trip

50%50%t

50%

EOUT

PAD

E50%

EOUT (R)

50%

EOUT (F)

PAD

DOUT

EOUT

I/O Interface

EOUT

ZLS

trip

50%

ZHS

trip

50%

EOUT

PAD

E50%50%

EOUT (R)

EOUT (F)

50%

CCI

, t

ZLS

, t

ZHS

EOUT

= MAX(t

EOUT

(r), t

EOUT

(f))

ProASIC3L DC and Switching Characteristics

2-22 Advance v0.6

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-22 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Pro I/O

I/O Standard

Drive

Strength

Slew

Rate

VIL VIH VOL VOH IOL1IOH1

Min, V Max, V Min, V Max, V Max, V Min, V mA mA

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12

3.3 V LVCMOS

Wide Range

Any2High –0.3 0.8 2 3.6 0.2 VCCI – 0.2 0.1 0.1

2.5 V LVCMOS 12 mA High –0.3 0.7 1.7 2.7 0.7 1.7 12 12

1.8 V LVCMOS 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 12 12

1.5 V LVCMOS 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12

1.2 V LVCMOS 2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 22

3.3 V PCI Per PCI Specification

3.3 V PCI-X Per PCI-X Specification

3.3 V GTL 25 mA3 High –0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 – 25 25

2.5 V GTL 25 mA3High –0.3 VREF – 0.05 VREF + 0.05 2.7 0.4 – 25 25

3.3 V GTL+ 35 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 – 51 51

2.5 V GTL+ 33 mA High –0.3 VREF – 0.1 VREF + 0.1 2.7 0.6 – 40 40

HSTL (I) 8 mA High –0.3 VREF – 0.1 VREF + 0.1 1.575 0.4 VCCI – 0.4 8 8

HSTL (II) 15 mA3 High –0.3 VREF – 0.1 VREF + 0.1 1.575 0.4 VCCI – 0.4 15 15

SSTL2 (I) 15 mA High –0.3 VREF – 0.2 VREF + 0.2 2.7 0.54 VCCI – 0.62 15 15

SSTL2 (II) 18 mA High –0.3 VREF – 0.2 VREF + 0.2 2.7 0.35 VCCI – 0.43 18 18

SSTL3 (I) 14 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6 0.7 VCCI – 1.1 14 14

SSTL3 (II) 21 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6 0.5 VCCI – 0.9 21 21

Notes:

1. Currents are measured at 85°C junction temperature.

2. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specificied in the JDEC8a specification.

3. Output drive strength is below JEDEC specification.

4. Output slew rate can be extracted using the IBIS Models.

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-23

Table 2-23 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Advanced I/O Banks

I/O Standard

Drive

Strength

Slew

Rate

VIL VIH VOL VOH IOL1IOH1

Min, V Max, V Min, V Max, V Max, V Min, V mA mA

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12

3.3 V LVCMOS

Wide Range

Any3High –0.3 0.8 2 3.6 0.2 VCCI – 0.2 0.1 0.1

2.5 V LVCMOS 12 mA High –0.3 0.7 1.7 2.7 0.7 1.7 12 12

1.8 V LVCMOS 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI –

0.45

12 12

1.5 V LVCMOS 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 *

VCCI

0.75 *

VCCI

12 12

1.2 V LVCMOS 2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 *

VCCI

0.75 *

VCCI

3.3 V PCI Per PCI specifications

3.3 V PCI-X Per PCI-X specifications

Notes:

1. Currents are measured at 85°C junction temperature.

2. Output slew rate can be extracted using the IBIS Models

3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specificied in the JDEC8a specification.

Table 2-24 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Standard Plus I/O Banks

I/O Standard

Drive

Strength

Slew

Rate

VIL VIH VOL VOH IOL1IOH1

Min, V Max, V Min, V Max, V Max, V Min, V mA mA

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12

3.3 V LVCMOS

Wide Range

Any3High –0.3 0.8 2 3.6 0.2 VCCI – 0.2 0.1 0.1

2.5 V LVCMOS 12 mA High –0.3 0.7 1.7 2.7 0.7 1.7 12 12

1.8 V LVCMOS 8 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 8 8

1.5 V LVCMOS 4 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 4 4

1.2 V LVCMOS 2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 22

3.3 V PCI Per PCI specifications

3.3 V PCI-X Per PCI-X specifications

Notes:

1. Currents are measured at 85°C junction temperature.

2. Output slew rate can be extracted using the IBIS Models.

3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specificied in the JDEC8a specification.

ProASIC3L DC and Switching Characteristics

2-24 Advance v0.6

Table 2-25 • Summary of Maximum and Minimum DC Input Levels

Applicable to Commercial and Industrial Conditions

DC I/O Standard

Commercial1Industrial2

IIL IIH IIL IIH

µA µA µA µA

3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15

3.3 V LVCMOS Wide Range 10 10 15 15

2.5 V LVCMOS 10 10 15 15

1.8 V LVCMOS 10 10 15 15

1.5 V LVCMOS 10 10 15 15

1.2 V LVCMOS 10 10 15 15

3.3 V PCI 10 10 15 15

3.3 V PCI-X 10 10 15 15

3.3 V GTL 10 10 15 15

2.5 V GTL 10 10 15 15

3.3 V GTL+ 10 10 15 15

2.5 V GTL+ 10 10 15 15

HSTL (I) 10 10 15 15

HSTL (II) 10 10 15 15

SSTL2 (I) 10 10 15 15

SSTL2 (II) 10 10 15 15

SSTL3 (I) 10 10 15 15

SSTL3 (II) 10 10 15 15

Notes:

1. Commercial range (0°C < TA < 70°C)

2. Industrial range (–40°C < TA < 85°C)

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-25

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 2-26 • Summary of AC Memory Points

Standard

Input Reference Voltage

(VREF_TYP)

Board Termination

Voltage (VTT_REF)

Measuring Trip Point

(Vtrip)

3.3 V LVTTL /

3.3 V LVCMOS

– – 1.4 V

3.3 V LVCMOS Wide

Range

– – 1.4 V

2.5 V LVCMOS – – 1.2 V

1.8 V LVCMOS – – 0.90 V

1.5 V LVCMOS – – 0.75 V

1.2 V LVCMOS – – 0.6V

3.3 V PCI – – 0.285 * VCCI (RR)

0.615 * VCCI (FF))

3.3 V PCI-X – – 0.285 * VCCI (RR)

0.615 * VCCI (FF)

3.3 V GTL 0.8 V 1.2 V VREF

2.5 V GTL 0.8 V 1.2 V VREF

3.3 V GTL+ 1.0 V 1.5 V VREF

2.5 V GTL+ 1.0 V 1.5 V VREF

HSTL (I) 0.75 V 0.75 V VREF

HSTL (II) 0.75 V 0.75 V VREF

SSTL2 (I) 1.25 V 1.25 V VREF

SSTL2 (II) 1.25 V 1.25 V VREF

SSTL3 (I) 1.5 V 1.485 V VREF

SSTL3 (II) 1.5 V 1.485 V VREF

LVDS – – Cross point

LVPECL – – Cross point

Table 2-27 • I/O AC Parameter Definitions

Parameter Parameter Definition

tDP Data to Pad delay through the Output Buffer

tPY Pad to Data delay through the Input Buffer

tDOUT Data to Output Buffer delay through the I/O interface

tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface

tDIN Input Buffer to Data delay through the I/O interface

tHZ Enable to Pad delay through the Output Buffer—HIGH to Z

tZH Enable to Pad delay through the Output Buffer—Z to HIGH

tLZ Enable to Pad delay through the Output Buffer—LOW to Z

tZL Enable to Pad delay through the Output Buffer—Z to LOW

tZHS Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH

tZLS Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW

ProASIC3L DC and Switching Characteristics

2-26 Advance v0.6

1.5 V DC Core Voltage

Table 2-28 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425V, Worst Case VCCI

Pro I/O Banks

Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

External Resistor (Ω)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tPYS (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

Units

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High 5 – 0.50 1.89 0.03 1.34 1.85 0.33 1.93 1.42 2.51 2.77 3.64 3.13 ns

2.5 V LVCMOS 12 mA High 5 – 0.50 1.92 0.03 1.58 1.97 0.33 1.96 1.59 2.58 2.68 3.67 3.30 ns

1.8 V LVCMOS 12 mA High 5 – 0.50 2.14 0.03 1.53 2.17 0.33 2.18 1.76 2.86 3.24 3.89 3.47 ns

1.5 V LVCMOS 12 mA High 5 – 0.50 2.46 0.03 1.69 2.36 0.33 2.51 2.04 3.03 3.35 4.22 3.75 ns

3.3 V PCI Per

PCI

spec.

High 5 – 0.50 2.15 0.03 2.10 2.84 0.33 2.19 1.53 2.51 2.77 3.90 3.24 ns

3.3 V PCI-X Per

PCI-X

spec.

High 10 25 0.50 2.15 0.03 2.10 2.84 0.33 2.19 1.53 2.51 2.77 3.90 3.24 ns

3.3 V GTL 25 mA High 10 25 0.50 1.59 0.03 1.80 – 0.33 1.56 1.59 – – 3.27 3.30 ns

2.5 V GTL 25 mA High 10 25 0.50 1.63 0.03 1.75 – 0.33 1.66 1.63 – – 3.37 3.34 ns

3.3 V GTL+ 35 mA High 10 25 0.50 1.57 0.03 1.80 – 0.33 1.60 1.57 – – 3.31 3.29 ns

2.5 V GTL+ 33 mA High 10 25 0.50 1.69 0.03 1.75 – 0.33 1.72 1.61 – – 3.43 3.32 ns

HSTL (I) 8 mA High 20 25 0.50 2.43 0.03 2.12 – 0.33 2.48 2.41 – – 4.19 4.12 ns

HSTL (II) 15 mA High 20 50 0.50 2.32 0.03 2.12 – 0.33 2.36 2.08 – – 4.07 3.79 ns

SSTL2 (I) 15 mA High 30 25 0.50 1.63 0.03 1.61 – 0.33 1.66 1.41 – – 1.66 1.41 ns

SSTL2 (II) 18 mA High 30 50 0.50 1.66 0.03 1.61 – 0.33 1.69 1.36 – – 1.69 1.36 ns

SSTL3 (I) 14 mA High 30 25 0.50 1.77 0.03 1.54 – 0.33 1.80 1.41 – – 1.80 1.41 ns

SSTL3 (II) 21 mA High 30 50 0.50 1.58 0.03 1.54 – 0.33 1.61 1.28 – – 1.61 1.28 ns

LVDS 24 mA High --0.501.400.031.85–––––––– ns

LVPECL 24 mA High --0.501.400.031.67–––––––– ns

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on

page 2-75 for connectivity. This resistor is not required during normal operation.

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-27

Table 2-29 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI

Advanced I/O Banks

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

External Resistor (Ω)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

Units

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High 5pF – 0.46 1.83 0.03 0.78 0.33 1.87 1.39 2.46 2.74 3.58 3.10 ns

2.5 V LVCMOS 12 mA High 5 pF – 0.46 1.85 0.03 1.00 0.33 1.88 1.55 2.53 2.63 3.59 3.26 ns

1.8 V LVCMOS 12 mA High 5 pF – 0.46 2.04 0.03 0.93 0.33 2.08 1.73 2.83 3.12 3.79 3.45 ns

1.5 V LVCMOS 12 mA High 5 pF – 0.46 2.33 0.03 1.10 0.33 2.37 2.01 3.02 3.22 4.08 3.72 ns

3.3 V PCI Per PCI spec. High 5 pF 25 2 0.46 2.05 0.03 0.66 0.33 2.09 1.49 2.46 2.74 3.80 3.21 ns

3.3 V PCI-X Per PCI-X spec. High 10 pF 25 2 0.46 2.05 0.03 0.64 0.33 2.09 1.49 2.46 2.74 3.80 3.21 ns

LVDS 24 mA High – – 0.46 1.40 0.03 1.23 N/A N/A N/A N/A N/A N/A N/A ns

LVPECL 24 mA High – – 0.46 1.38 0.03 1.08 N/A N/A N/A N/A N/A N/A N/A ns

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on

page 2-75 for connectivity. This resistor is not required during normal operation.

Table 2-30 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI =3.0V

Standard Plus I/O Banks

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

External Resistor

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

Units

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High 5pF – 0.46 1.56 0.03 0.77 0.33 1.59 1.20 2.14 2.47 3.30 2.91 ns

2.5 V LVCMOS 12 mA High 5pF – 0.46 1.59 0.03 0.99 0.33 1.61 1.32 2.16 2.38 3.33 3.03 ns

1.8 V LVCMOS 8 mA High 5pF – 0.46 1.59 0.03 0.99 0.33 1.61 1.32 2.16 2.38 3.33 3.03 ns

1.5 V LVCMOS 4 mA High 5pF – 0.46 2.15 0.03 1.09 0.33 2.19 1.82 2.32 2.40 3.90 3.53 ns

3.3 V PCI Per PCI spec. High 10 pF 25

2 0.46 1.77 0.03 0.65 0.33 1.80 1.31 2.14 2.47 3.51 3.02 ns

3.3 V PCI-X Per PCI-X spec. High 10 pF 25 2 0.46 1.77 0.03 0.64 0.33 1.80 1.31 2.14 2.47 3.51 3.02 ns

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on

page 2-75 for connectivity. This resistor is not required during normal operation.

ProASIC3L DC and Switching Characteristics

2-28 Advance v0.6

1.2 V DC Core Voltage

Table 2-31 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.14 V, Worst Case VCCI

Pro I/O Banks

Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

External Resistor (Ω)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tPYS (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

Units

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High 5 – 0.66 1.89 0.04 1.34 1.85 0.43 1.93 1.42 2.51 2.77 3.64 3.13 ns

2.5 V LVCMOS 12 mA High 5 – 0.66 1.92 0.04 1.58 1.97 0.43 1.96 1.59 2.58 2.68 3.67 3.30 ns

1.8 V LVCMOS 12 mA High 5 – 0.66 2.14 0.04 1.53 2.17 0.43 2.18 1.76 2.86 3.24 3.89 3.47 ns

1.5 V LVCMOS 12 mA High 5 – 0.66 2.46 0.04 1.69 2.36 0.43 2.51 2.04 3.03 3.35 4.22 3.75 ns

1.2 V LVCMOS 2 mA High 5 – 0.66 4.12 0.04 2.02 2.99 0.43 3.83 3.37 4.06 3.84 5.48 5.02 ns

3.3 V PCI Per

PCI

spec.

High 10 – 0.662.150.042.102.840.432.191.532.512.773.903.24 ns

3.3 V PCI-X Per

PCI-X

spec.

High 10 25 0.66 2.15 0.04 2.10 2.84 0.43 2.19 1.53 2.51 2.77 3.90 3.24 ns

3.3 V GTL 25 mA High 10 25 0.66 1.59 0.04 1.80 – 0.43 1.56 1.59 – – 3.27 3.30 ns

2.5 V GTL 25 mA High 10 25 0.66 1.63 0.04 1.75 – 0.43 1.66 1.63 – – 3.37 3.34 ns

3.3 V GTL+ 35 mA High 10 25 0.66 1.57 0.04 1.80 – 0.43 1.60 1.57 – – 3.31 3.29 ns

2.5 V GTL+ 33 mA High 10 25 0.66 1.69 0.04 1.75 – 0.43 1.72 1.61 – – 3.43 3.32 ns

HSTL (I) 8 mA High 20 25 0.66 2.43 0.04 2.12 – 0.43 2.48 2.41 – – 4.19 4.12 ns

HSTL (II) 15 mA High 20 50 0.66 2.32 0.04 2.12 – 0.43 2.36 2.08 – – 4.07 3.79 ns

SSTL2 (I) 15 mA High 30 25 0.66 1.63 0.04 1.61 – 0.43 1.66 1.41 – – 1.66 1.41 ns

SSTL2 (II) 18 mA High 30 50 0.66 1.66 0.04 1.61 – 0.43 1.69 1.36 – – 1.69 1.36 ns

SSTL3 (I) 14 mA High 30 25 0.66 1.77 0.04 1.54 – 0.43 1.80 1.41 – – 1.80 1.41 ns

SSTL3 (II) 21 mA High 30 50 0.66 1.58 0.04 1.54 – 0.43 1.61 1.28 – – 1.61 1.28 ns

LVDS 24 mA High --0.661.430.041.85–––––––– ns

LVPECL 24 mA High --0.661.370.041.67–––––––– ns

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on

page 2-75 for connectivity. This resistor is not required during normal operation.

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-29

Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.14 V, Worst Case VCCI

Advanced I/O Banks

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

External Resistor (Ω)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

Units

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High 5pF – 0.60 1.83 0.04 0.78 0.43 1.87 1.39 2.46 2.74 3.58 3.10 ns

2.5 V LVCMOS 12 mA High 5 pF – 0.60 1.85 0.04 1.00 0.43 1.88 1.55 2.53 2.63 3.59 3.26 ns

1.8 V LVCMOS 12 mA High 5 pF – 0.60 2.04 0.04 0.93 0.43 2.08 1.73 2.83 3.12 3.79 3.45 ns

1.5 V LVCMOS 12 mA High 5 pF – 0.60 2.33 0.04 1.10 0.43 2.37 2.01 3.02 3.22 4.08 3.72 ns

1.2 V LVCMOS 2 mA High 5pF – 0.60 3.17 0.04 1.55 0.43 2.11 1.76 2.38 2.46 3.76 3.41 ns

3.3 V PCI Per PCI spec. High 10 pF 25 2 0.60 2.05 0.04 0.66 0.43 2.09 1.49 2.46 2.74 3.80 3.21 ns

3.3 V PCI-X Per PCI-X spec. High 10 pF 25 2 0.60 2.05 0.04 0.64 0.43 2.09 1.49 2.46 2.74 3.80 3.21 ns

LVDS 24 mA High – – 0.60 1.40 0.04 1.23 N/A N/A N/A N/A N/A N/A N/A ns

LVPECL 24 mA High – – 0.60 1.38 0.04 1.08 N/A N/A N/A N/A N/A N/A N/A ns

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on

page 2-75 for connectivity. This resistor is not required during normal operation.

ProASIC3L DC and Switching Characteristics

2-30 Advance v0.6

Detailed I/O DC Characteristics

Table 2-33 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.14 V, Worst Case VCCI =3.0V

Standard Plus I/O Banks

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

External Resistor

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

Units

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High 5pF – 0.60 1.56 0.04 0.77 0.43 1.59 1.20 2.14 2.47 3.30 2.91 ns

2.5 V LVCMOS 12 mA High 5pF – 0.60 1.59 0.04 0.99 0.43 1.61 1.32 2.16 2.38 3.33 3.03 ns

1.8 V LVCMOS 8 mA High 5pF – 0.60 1.59 0.04 0.99 0.43 1.61 1.32 2.16 2.38 3.33 3.03 ns

1.5 V LVCMOS 4 mA High 5pF – 0.60 2.15 0.04 1.09 0.43 2.19 1.82 2.32 2.40 3.90 3.53 ns

1.2 V LVCMOS 2 mA High 5pF – 0.60 3.54 0.04 1.56 0.43 2.37 2.11 3.60 3.87 4.02 3.76 ns

3.3 V PCI Per PCI spec. High 10 pF 25

2 0.60 1.77 0.04 0.65 0.43 1.80 1.31 2.14 2.47 3.51 3.02 ns

3.3 V PCI-X Per PCI-X spec. High 10 pF 25 2 0.60 1.77 0.04 0.64 0.43 1.80 1.31 2.14 2.47 3.51 3.02 ns

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on

page 2-75 for connectivity. This resistor is not required during normal operation.

Table 2-34 • Input Capacitance

Symbol Definition Conditions Min. Max. Units

CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF

CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-31

Table 2-35 • I/O Output Buffer Maximum Resistances1

Applicable to Pro I/Os

Standard Drive Strength

RPULL-DOWN

(Ω) 2

RPULL-UP

(Ω)3

3.3 V LVTTL / 3.3 V LVCMOS 4 mA 100 300

8 mA 50 150

12 mA 25 75

16 mA 17 50

24 mA 11 33

2.5 V LVCMOS 4 mA 100 200

8 mA 50 100

12 mA 25 50

16 mA 20 40

24 mA 11 22

1.8 V LVCMOS 2 mA 200 225

4 mA 100 112

6 mA 50 56

8 mA 50 56

12 mA 20 22

16 mA 20 22

1.5 V LVCMOS 2 mA 200 224

4 mA 100 112

6 mA 67 75

8 mA 33 37

12 mA 33 37

1.2 V LVCMOS 2 mA TBD TBD

3.3 V PCI/PCI-X Per PCI/PCI-X

specification

25 75

3.3 V GTL 25 mA 11 –

2.5 V GTL 25 mA 14 –

3.3 V GTL+ 35 mA 12 –

2.5 V GTL+ 33 mA 15 –

HSTL (I) 8 mA 50 50

HSTL (II) 15 mA 25 25

SSTL2 (I) 15 mA 27 31

SSTL2 (II) 18 mA 13 15

SSTL3 (I) 14 mA 44 69

SSTL3 (II) 21 mA 18 32

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on VCCI, drive strength selection, temperature, and process. For board design considerations

and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at

http://www.actel.com/download/ibis/default.aspx.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

ProASIC3L DC and Switching Characteristics

2-32 Advance v0.6

Table 2-36 • I/O Output Buffer Maximum Resistances1

Applicable to Advanced I/O Banks

Standard Drive Strength

RPULL-DOWN

(Ω)2

RPULL-UP

(Ω)3

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300

4 mA 100 300

6 mA 50 150

8 mA 50 150

12 mA 25 75

16 mA 17 50

24 mA 11 33

2.5 V LVCMOS 2 mA 100 300

4 mA 100 300

6 mA 50 150

8 mA 50 150

12 mA 25 75

16 mA 17 50

24 mA 11 33

1.8 V LVCMOS 2 mA 100 200

4 mA 100 200

6 mA 50 100

8 mA 50 100

12 mA 25 50

16 mA 20 40

1.5 V LVCMOS 2 mA 200 224

4 mA 100 112

6 mA 67 75

8 mA 33 37

12 mA 33 37

1.2 V LVCMOS 2 mA TBD TBD

3.3 V PCI/PCI-X Per PCI/PCI-X

specification

25 75

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on VCCI, drive strength selection, temperature, and process. For board design considerations

and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at

http://www.actel.com/download/ibis/default.aspx.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-33

Table 2-37 • I/O Output Buffer Maximum Resistances1

Applicable to Standard Plus I/O Banks

Standard Drive Strength

RPULL-DOWN

(Ω)2

RPULL-UP

(Ω)3

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300

4 mA 100 300

6 mA 50 150

8 mA 50 150

12 mA 25 75

16 mA 25 75

2.5 V LVCMOS 2 mA 100 200

4 mA 100 200

6 mA 50 100

8 mA 50 100

12 mA 25 50

1.8 V LVCMOS 2 mA 200 225

4 mA 100 112

6 mA 50 56

8 mA 50 56

1.5 V LVCMOS 2 mA 200 224

4 mA 100 112

1.2 V LVCMOS 2 mA TBD TBD

3.3 V PCI/PCI-X Per PCI/PCI-X

specification

25 75

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on VCCI, drive strength selection, temperature, and process. For board design considerations

and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at

http://www.actel.com/download/ibis/default.aspx.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

ProASIC3L DC and Switching Characteristics

2-34 Advance v0.6

Table 2-38 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

VCCI

R(WEAK PULL-UP)1

(Ω)

R(WEAK PULL-DOWN)2

(Ω)

Min. Max. Min. Max.

3.3 V 10 k 45 k 10 k 45 k

2.5 V 11 k 55 k 12 k 74 k

1.8 V 18 k 70 k 17 k 110 k

1.5 V 19 k 90 k 19 k 140 k

1.2 V LVCMOS TBD TBD TBD TBD

Notes:

1. R(WEAK PULL-UP-MAX) = (VOLspec) / I(WEAK PULL-UP-MIN)

2. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN)

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-35

Table 2-39 • I/O Short Currents IOSH/IOSL

Applicable to Pro I/Os

Drive Strength IOSL (mA)* IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 4 mA 25 27

8 mA 51 54

12 mA 103 109

16 mA 132 127

24 mA 268 181

2.5 V LVCMOS 4 mA 16 18

8 mA 32 37

12 mA 65 74

16 mA 83 87

24 mA 169 124

1.8 V LVCMOS 2 mA 9 11

4 mA 17 22

6 mA 35 44

8 mA 45 51

12 mA 91 74

16 mA 91 74

1.5 V LVCMOS 2 mA 13 16

4 mA 25 33

6 mA 32 39

8 mA 66 55

12 mA 66 55

1.2 V LVCMOS 2 mA TBD TBD

3.3 V PCI/PCIX Per PCI/PCI-X

Specification

Per PCI Curves

3.3 V GTL 25 mA 268 181

2.5 V GTL 25 mA 169 124

3.3 V GTL+ 35 mA 268 181

2.5 V GTL+ 33 mA 169 124

HSTL (I) 8 mA 32 39

HSTL (II) 15 mA 66 55

SSTL2 (I) 15 mA 83 87

SSTL2 (II) 18 mA 169 124

SSTL3 (I) 14 mA 51 54

*TJ = 100°C

ProASIC3L DC and Switching Characteristics

2-36 Advance v0.6

Table 2-40 • I/O Short Currents IOSH/IOSL

Applicable to Advanced I/O Banks

Drive Strength IOSL (mA)* IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 25 27

4 mA 25 27

6 mA 51 54

8 mA 51 54

12 mA 103 109

16 mA 132 127

24 mA 268 181

2.5 V LVCMOS 2 mA 16 18

4 mA 16 18

6 mA 32 37

8 mA 32 37

12 mA 65 74

16 mA 83 87

24 mA 169 124

1.8 V LVCMOS 2 mA 9 11

4 mA 17 22

6 mA 35 44

8 mA 45 51

12 mA 91 74

16 mA 91 74

1.5 V LVCMOS 2 mA 13 16

4 mA 25 33

6 mA 32 39

8 mA 66 55

12 mA 66 55

1.2 V LVCMOS 2 mA TBD TBD

3.3 V PCI/PCI-X Per PCI/PCI-X specification 103 109

*TJ = 100°C

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-37

The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The

reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 110°C, the short current condition would have to be sustained for more than three

months to cause a reliability concern. The I/O design does not contain any short circuit protection,

but such protection would only be needed in extremely prolonged stress conditions.

Table 2-41 • I/O Short Currents IOSH/IOSL

Applicable to Standard Plus I/O Banks

Drive Strength IOSL (mA)* IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 25 27

4 mA 25 27

6 mA 51 54

8 mA 51 54

12 mA 103 109

16 mA 103 109

2.5 V LVCMOS 2 mA 16 18

4 mA 16 18

6 mA 32 37

8 mA 32 37

12 mA 65 74

1.8 V LVCMOS 2 mA 9 11

4 mA 17 22

6 mA 35 44

8 mA 35 44

1.5 V LVCMOS 2 mA 13 16

4 mA 25 33

1.2 V LVCMOS 2 mA TBD TBD

3.3 V PCI/PCI-X Per PCI/PCI-X specification 103 109

*TJ = 100°C

Table 2-42 • Schmitt Trigger Input Hysteresis, Hysteresis Voltage Value (Typ) for Schmitt Mode Input Buffers

Input Buffer Configuration Hysteresis Value (typ.)

3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode) 240 mV

2.5 V LVCMOS (Schmitt trigger mode) 140 mV

1.8 V LVCMOS (Schmitt trigger mode) 80 mV

1.5 V LVCMOS (Schmitt trigger mode) 60 mV

1.2 V LVCMOS (Schmitt trigger mode) 40 mV

ProASIC3L DC and Switching Characteristics

2-38 Advance v0.6

Table 2-43 • Duration of Short Circuit Event before Failure

Temperature Time before Failure

–40°C > 20 years

0°C > 20 years

25°C > 20 years

70°C 5 years

85°C 2 years

100°C 6 months

110°C 3 months

Table 2-44 • I/O Input Rise Time, Fall Time, and Related I/O Reliability

Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability

LVTTL/LVCMOS No requirement 10 ns * 20 years (110°C)

LVDS/B-LVDS/

M-LVDS/LVPECL

No requirement 10 ns * 10 years (100°C)

*The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low,

then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the

rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity

evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-39

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer. Furthermore, all LVCMOS

3.3 V software macros comply with LVCMOS 3.3 V wide range as specified in the JESD8a

specification.

Table 2-45 • Minimum and Maximum DC Input and Output Levels

Applicable to Pro I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10

6 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10

8 mA –0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 10 10

12 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 132 127 10 10

16 mA –0.3 0.8 2 3.6 0.4 2.4 24 24 268 181 10 10

24 mA –0.3 0.8 2 3.6 0.4 2.4 24 24 27 25 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-46 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10

4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10

6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10

8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10

12 mA –0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 10 10

16 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 132 127 10 10

24 mA –0.3 0.8 2 3.6 0.4 2.4 24 24 268 181 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

ProASIC3L DC and Switching Characteristics

2-40 Advance v0.6

Table 2-47 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10

4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10

6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10

8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10

12 mA –0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 10 10

16 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 103 109 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-48 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range

Applicable to Pro, Advanced, and Standard Plus I/O Banks

3.3 V LVCMOS Wide

Range VIL VIH VOL VOH IOL IOH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA µA2µA2

All2–0.3 0.8 2 3.6 0.2 VCCI – 0.2 0.1 0.1 10 10

Notes:

1. Currents are measured at 85°C junction temperature.

2. All LVMCOS 3.3 V software macros supports LVCMOS 3.3 V wide range as specificied in the JDEC8a

specification

Figure 2-7 • AC Loading

Table 2-49 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

03.31.45

*Measuring point = Vtrip. See Table 2-26 on page 2-25 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-41

Timing Characteristics

1.5 V DC Core Voltage

Table 2-50 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Pro I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.59 5.48 0.04 1.58 2.17 0.38 5.58 4.40 2.42 2.20 7.60 6.42 ns

–1 0.50 4.66 0.03 1.34 1.85 0.33 4.75 3.75 2.06 1.87 6.46 5.46 ns

8 mA Std. 0.59 4.48 0.04 1.58 2.17 0.38 4.56 3.76 2.73 2.76 6.57 5.78 ns

–1 0.50 3.81 0.03 1.34 1.85 0.33 3.88 3.20 2.33 2.35 5.59 4.91 ns

12 mA Std. 0.59 3.77 0.04 1.58 2.17 0.38 3.84 3.28 2.95 3.12 5.85 5.29 ns

–1 0.50 3.21 0.03 1.34 1.85 0.33 3.27 2.79 2.51 2.65 4.98 4.50 ns

16 mA Std. 0.59 3.57 0.04 1.58 2.17 0.38 3.63 3.18 2.99 3.22 5.64 5.19 ns

–1 0.50 3.03 0.03 1.34 1.85 0.33 3.09 2.70 2.54 2.74 4.80 4.41 ns

24 mA Std. 0.59 3.46 0.04 1.58 2.17 0.38 3.52 3.19 3.05 3.57 5.54 5.20 ns

–1 0.50 2.94 0.03 1.34 1.85 0.33 3.00 2.71 2.59 3.03 4.71 4.42 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-51 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Pro I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.59 3.08 0.04 1.58 2.17 0.38 3.14 2.36 2.42 2.33 5.15 4.38 ns

–1 0.50 2.62 0.03 1.34 1.85 0.33 2.67 2.01 2.06 1.98 4.38 3.72 ns

8 mA Std. 0.59 2.53 0.04 1.58 2.17 0.38 2.58 1.89 2.74 2.89 4.59 3.90 ns

–1 0.50 2.16 0.03 1.34 1.85 0.33 2.20 1.61 2.33 2.46 3.91 3.32 ns

12 mA Std. 0.59 2.22 0.04 1.58 2.17 0.38 2.27 1.67 2.95 3.25 4.28 3.68 ns

–1 0.50 1.89 0.03 1.34 1.85 0.33 1.93 1.42 2.51 2.77 3.64 3.13 ns

16 mA Std. 0.59 2.17 0.04 1.58 2.17 0.38 2.21 1.63 3.00 3.35 4.23 3.64 ns

–1 0.50 1.85 0.03 1.34 1.85 0.33 1.88 1.38 2.55 2.85 3.59 3.09 ns

24 mA Std. 0.59 2.19 0.04 1.58 2.17 0.38 2.24 1.57 3.05 3.71 4.25 3.58 ns

–1 0.50 1.87 0.03 1.34 1.85 0.33 1.90 1.33 2.59 3.16 3.61 3.05 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

ProASIC3L DC and Switching Characteristics

2-42 Advance v0.6

Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.54 5.11 0.04 0.91 0.38 5.21 4.33 2.38 2.21 7.22 6.34 ns

–1 0.46 4.35 0.03 0.78 0.33 4.43 3.68 2.02 1.88 6.14 5.40 ns

6 mA Std. 0.54 4.30 0.04 0.91 0.38 4.38 3.75 2.68 2.74 6.39 5.76 ns

–1 0.46 3.66 0.03 0.78 0.33 3.73 3.19 2.28 2.33 5.44 4.90 ns

8 mA Std. 0.54 4.30 0.04 0.91 0.38 4.38 3.75 2.68 2.74 6.39 5.76 ns

–1 0.46 3.66 0.03 0.78 0.33 3.73 3.19 2.28 2.33 5.44 4.90 ns

12 mA Std. 0.54 3.68 0.04 0.91 0.38 3.75 3.32 2.89 3.07 5.76 5.33 ns

–1 0.46 3.13 0.03 0.78 0.33 3.19 2.82 2.45 2.62 4.90 4.53 ns

16 mA Std. 0.54 3.50 0.04 0.91 0.38 3.56 3.21 2.93 3.16 5.57 5.23 ns

–1 0.46 2.97 0.03 0.78 0.33 3.03 2.73 2.49 2.69 4.74 4.45 ns

24 mA Std. 0.54 3.39 0.04 0.91 0.38 3.45 3.25 2.99 3.50 5.47 5.26 ns

–1 0.46 2.88 0.03 0.78 0.33 2.94 2.76 2.54 2.97 4.65 4.48 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.54 2.90 0.04 0.91 0.38 2.96 2.28 2.38 2.35 4.97 4.29 ns

–1 0.46 2.47 0.03 0.78 0.33 2.52 1.94 2.03 2.00 4.23 3.65 ns

6 mA Std. 0.54 2.41 0.04 0.91 0.38 2.46 1.84 2.69 2.88 4.47 3.85 ns

–1 0.46 2.05 0.03 0.78 0.33 2.09 1.57 2.29 2.45 3.80 3.28 ns

8 mA Std. 0.54 2.41 0.04 0.91 0.38 2.46 1.84 2.69 2.88 4.47 3.85 ns

–1 0.46 2.05 0.03 0.78 0.33 2.09 1.57 2.29 2.45 3.80 3.28 ns

12 mA Std. 0.54 2.16 0.04 0.91 0.38 2.20 1.63 2.89 3.22 4.21 3.64 ns

–-1 0.46 1.83 0.03 0.78 0.33 1.87 1.39 2.46 2.74 3.58 3.10 ns

16 mA Std. 0.54 2.11 0.04 0.91 0.38 2.15 1.59 2.94 3.31 4.17 3.61 ns

–-1 0.46 1.80 0.03 0.78 0.33 1.83 1.36 2.50 2.82 3.54 3.07 ns

24 mA Std. 0.54 2.14 0.04 0.91 0.38 2.17 1.55 2.99 3.65 4.19 3.56 ns

–1 0.46 1.82 0.03 0.78 0.33 1.85 1.32 2.54 3.11 3.56 3.03 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-43

Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.54 4.61 0.04 0.90 0.38 4.70 3.91 2.05 1.99 6.71 5.92 ns

–1 0.46 3.92 0.03 0.77 0.33 4.00 3.32 1.74 1.69 5.71 5.04 ns

6 mA Std. 0.54 3.80 0.04 0.90 0.38 3.87 3.40 2.32 2.47 5.88 5.41 ns

–1 0.46 3.23 0.03 0.77 0.33 3.29 2.89 1.98 2.10 5.00 4.60 ns

8 mA Std. 0.54 3.80 0.04 0.90 0.38 3.87 3.40 2.32 2.47 5.88 5.41 ns

–1 0.46 3.23 0.03 0.77 0.33 3.29 2.89 1.98 2.10 5.00 4.60 ns

12 mA Std. 0.54 3.22 0.04 0.90 0.38 3.28 3.00 2.51 2.77 5.30 5.01 ns

–1 0.46 2.74 0.03 0.77 0.33 2.79 2.55 2.14 2.36 4.51 4.27 ns

16 mA Std. 0.54 3.22 0.04 0.90 0.38 3.28 3.00 2.51 2.77 5.30 5.01 ns

–1 0.46 2.74 0.03 0.77 0.33 2.79 2.55 2.14 2.36 4.51 4.27 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-55 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.54 2.51 0.04 0.90 0.38 2.56 2.01 2.05 2.10 4.57 4.02 ns

–1 0.46 2.14 0.03 0.77 0.33 2.18 1.71 1.74 1.79 3.89 3.42 ns

6 mA Std. 0.54 2.05 0.04 0.90 0.38 2.09 1.61 2.32 2.59 4.10 3.62 ns

–1 0.46 1.74 0.03 0.77 0.33 1.78 1.37 1.97 2.20 3.49 3.08 ns

8 mA Std. 0.54 2.05 0.04 0.90 0.38 2.09 1.61 2.32 2.59 4.10 3.62 ns

–1 0.46 1.74 0.03 0.77 0.33 1.78 1.37 1.97 2.20 3.49 3.08 ns

12 mA Std. 0.54 1.83 0.04 0.90 0.38 1.86 1.41 2.51 2.90 3.88 3.42 ns

–1 0.46 1.56 0.03 0.77 0.33 1.59 1.20 2.14 2.47 3.30 2.91 ns

16 mA Std. 0.54 1.83 0.04 0.90 0.38 1.86 1.41 2.51 2.90 3.88 3.42 ns

–1 0.46 1.56 0.03 0.77 0.33 1.59 1.20 2.14 2.47 3.30 2.91 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

ProASIC3L DC and Switching Characteristics

2-44 Advance v0.6

1.2 V DC Core Voltage

Table 2-56 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Pro I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.77 5.48 0.05 1.58 2.17 0.50 5.58 4.40 2.42 2.20 7.60 6.42 ns

–1 0.66 4.66 0.04 1.34 1.85 0.43 4.75 3.75 2.06 1.87 6.46 5.46 ns

8 mA Std. 0.77 4.48 0.05 1.58 2.17 0.50 4.56 3.76 2.73 2.76 6.57 5.78 ns

–1 0.66 3.81 0.04 1.34 1.85 0.43 3.88 3.20 2.33 2.35 5.59 4.91 ns

12 mA Std. 0.77 3.77 0.05 1.58 2.17 0.50 3.84 3.28 2.95 3.12 5.85 5.29 ns

–1 0.66 3.21 0.04 1.34 1.85 0.43 3.27 2.79 2.51 2.65 4.98 4.50 ns

16 mA Std. 0.77 3.57 0.05 1.58 2.17 0.50 3.63 3.18 2.99 3.22 5.64 5.19 ns

–1 0.66 3.03 0.04 1.34 1.85 0.43 3.09 2.70 2.54 2.74 4.80 4.41 ns

24 mA Std. 0.77 3.46 0.05 1.58 2.17 0.50 3.52 3.19 3.05 3.57 5.54 5.20 ns

–1 0.66 2.94 0.04 1.34 1.85 0.43 3.00 2.71 2.59 3.03 4.71 4.42 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-57 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Pro I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.77 3.08 0.05 1.58 2.17 0.50 3.14 2.36 2.42 2.33 5.15 4.38 ns

–1 0.66 2.62 0.04 1.34 1.85 0.43 2.67 2.01 2.06 1.98 4.38 3.72 ns

8 mA Std. 0.77 2.53 0.05 1.58 2.17 0.50 2.58 1.89 2.74 2.89 4.59 3.90 ns

–1 0.66 2.16 0.04 1.34 1.85 0.43 2.20 1.61 2.33 2.46 3.91 3.32 ns

12 mA Std. 0.77 2.22 0.05 1.58 2.17 0.50 2.27 1.67 2.95 3.25 4.28 3.68 ns

–1 0.66 1.89 0.04 1.34 1.85 0.43 1.93 1.42 2.51 2.77 3.64 3.13 ns

16 mA Std. 0.77 2.17 0.05 1.58 2.17 0.50 2.21 1.63 3.00 3.35 4.23 3.64 ns

–1 0.66 1.85 0.04 1.34 1.85 0.43 1.88 1.38 2.55 2.85 3.59 3.09 ns

24 mA Std. 0.77 2.19 0.05 1.58 2.17 0.50 2.24 1.57 3.05 3.71 4.25 3.58 ns

–1 0.66 1.87 0.04 1.34 1.85 0.43 1.90 1.33 2.59 3.16 3.61 3.05 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-45

Table 2-58 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.70 5.11 0.05 0.91 0.50 5.21 4.33 2.38 2.21 7.22 6.34 ns

–1 0.60 4.35 0.04 0.78 0.43 4.43 3.68 2.02 1.88 6.14 5.40 ns

6 mA Std. 0.70 4.30 0.05 0.91 0.50 4.38 3.75 2.68 2.74 6.39 5.76 ns

–1 0.60 3.66 0.04 0.78 0.43 3.73 3.19 2.28 2.33 5.44 4.90 ns

8 mA Std. 0.70 4.30 0.05 0.91 0.50 4.38 3.75 2.68 2.74 6.39 5.76 ns

–1 0.60 3.66 0.04 0.78 0.43 3.73 3.19 2.28 2.33 5.44 4.90 ns

12 mA Std. 0.70 3.68 0.05 0.91 0.50 3.75 3.32 2.89 3.07 5.76 5.33 ns

–1 0.60 3.13 0.04 0.78 0.43 3.19 2.82 2.45 2.62 4.90 4.53 ns

16 mA Std. 0.70 3.50 0.05 0.91 0.50 3.56 3.21 2.93 3.16 5.57 5.23 ns

–1 0.60 2.97 0.04 0.78 0.43 3.03 2.73 2.49 2.69 4.74 4.45 ns

24 mA Std. 0.70 3.39 0.05 0.91 0.50 3.45 3.25 2.99 3.50 5.47 5.26 ns

–1 0.60 2.88 0.04 0.78 0.43 2.94 2.76 2.54 2.97 4.65 4.48 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-59 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.70 2.90 0.05 0.91 0.50 2.96 2.28 2.38 2.35 4.97 4.29 ns

–1 0.60 2.47 0.04 0.78 0.43 2.52 1.94 2.03 2.00 4.23 3.65 ns

6 mA Std. 0.70 2.41 0.05 0.91 0.50 2.46 1.84 2.69 2.88 4.47 3.85 ns

–1 0.60 2.05 0.04 0.78 0.43 2.09 1.57 2.29 2.45 3.80 3.28 ns

8 mA Std. 0.70 2.41 0.05 0.91 0.50 2.46 1.84 2.69 2.88 4.47 3.85 ns

–1 0.60 2.05 0.04 0.78 0.43 2.09 1.57 2.29 2.45 3.80 3.28 ns

12 mA Std. 0.70 2.16 0.05 0.91 0.50 2.20 1.63 2.89 3.22 4.21 3.64 ns

–-1 0.60 1.83 0.04 0.78 0.43 1.87 1.39 2.46 2.74 3.58 3.10 ns

16 mA Std. 0.70 2.11 0.05 0.91 0.50 2.15 1.59 2.94 3.31 4.17 3.61 ns

–-1 0.60 1.80 0.04 0.78 0.43 1.83 1.36 2.50 2.82 3.54 3.07 ns

24 mA Std. 0.70 2.14 0.05 0.91 0.50 2.17 1.55 2.99 3.65 4.19 3.56 ns

–1 0.60 1.82 0.04 0.78 0.43 1.85 1.32 2.54 3.11 3.56 3.03 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

ProASIC3L DC and Switching Characteristics

2-46 Advance v0.6

Table 2-60 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.70 4.61 0.05 0.90 0.50 4.70 3.91 2.05 1.99 6.71 5.92 ns

–1 0.60 3.92 0.04 0.77 0.43 4.00 3.32 1.74 1.69 5.71 5.04 ns

6 mA Std. 0.70 3.80 0.05 0.90 0.50 3.87 3.40 2.32 2.47 5.88 5.41 ns

–1 0.60 3.23 0.04 0.77 0.43 3.29 2.89 1.98 2.10 5.00 4.60 ns

8 mA Std. 0.70 3.80 0.05 0.90 0.50 3.87 3.40 2.32 2.47 5.88 5.41 ns

–1 0.60 3.23 0.04 0.77 0.43 3.29 2.89 1.98 2.10 5.00 4.60 ns

12 mA Std. 0.70 3.22 0.05 0.90 0.50 3.28 3.00 2.51 2.77 5.30 5.01 ns

–1 0.60 2.74 0.04 0.77 0.43 2.79 2.55 2.14 2.36 4.51 4.27 ns

16 mA Std. 0.70 3.22 0.05 0.90 0.50 3.28 3.00 2.51 2.77 5.30 5.01 ns

–1 0.60 2.74 0.04 0.77 0.43 2.79 2.55 2.14 2.36 4.51 4.27 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-61 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.70 2.51 0.05 0.90 0.50 2.56 2.01 2.05 2.10 4.57 4.02 ns

–1 0.60 2.14 0.04 0.77 0.43 2.18 1.71 1.74 1.79 3.89 3.42 ns

6 mA Std. 0.70 2.05 0.05 0.90 0.50 2.09 1.61 2.32 2.59 4.10 3.62 ns

–1 0.60 1.74 0.04 0.77 0.43 1.78 1.37 1.97 2.20 3.49 3.08 ns

8 mA Std. 0.70 2.05 0.05 0.90 0.50 2.09 1.61 2.32 2.59 4.10 3.62 ns

–1 0.60 1.74 0.04 0.77 0.43 1.78 1.37 1.97 2.20 3.49 3.08 ns

12 mA Std. 0.70 1.83 0.05 0.90 0.50 1.86 1.41 2.51 2.90 3.88 3.42 ns

–1 0.60 1.56 0.04 0.77 0.43 1.59 1.20 2.14 2.47 3.30 2.91 ns

16 mA Std. 0.70 1.83 0.05 0.90 0.50 1.86 1.41 2.51 2.90 3.88 3.42 ns

–1 0.60 1.56 0.04 0.77 0.43 1.59 1.20 2.14 2.47 3.30 2.91 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-47

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.

Table 2-62 • Minimum and Maximum DC Input and Output Levels

Applicable to Pro I/Os

2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

4 mA –0.3 0.7 1.7 2.7 0.7 1.7 4 4 16 18 10 10

8 mA –0.3 0.7 1.7 2.7 0.7 1.7 8 8 32 37 10 10

12 mA –0.3 0.7 1.7 2.7 0.7 1.7 12 12 65 74 10 10

16 mA –0.3 0.7 1.7 2.7 0.7 1.7 16 16 83 87 10 10

24 mA –0.3 0.7 1.7 2.7 0.7 1.7 24 24 169 124 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-63 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

2 mA –0.3 0.7 1.7 2.7 0.7 1.7 2 2 16 18 10 10

4 mA –0.3 0.7 1.7 2.7 0.7 1.7 4 4 16 18 10 10

6 mA –0.3 0.7 1.7 2.7 0.7 1.7 6 6 32 37 10 10

8 mA –0.3 0.7 1.7 2.7 0.7 1.7 8 8 32 37 10 10

12 mA –0.3 0.7 1.7 2.7 0.7 1.7 12 12 65 74 10 10

16 mA –0.3 0.7 1.7 2.7 0.7 1.7 16 16 83 87 10 10

24 mA –0.3 0.7 1.7 2.7 0.7 1.7 24 24 169 124 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

ProASIC3L DC and Switching Characteristics

2-48 Advance v0.6

Table 2-64 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

2.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

2 mA –0.3 0.7 1.7 2.7 0.7 1.7 2 2 16 18 10 10

4 mA –0.3 0.7 1.7 2.7 0.7 1.7 4 4 16 18 10 10

6 mA –0.3 0.7 1.7 2.7 0.7 1.7 6 6 32 37 10 10

8 mA –0.3 0.7 1.7 2.7 0.7 1.7 8 8 32 37 10 10

12 mA –0.3 0.7 1.7 2.7 0.7 1.7 12 12 65 74 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 2-8 • AC Loading

Table 2-65 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

02.51.25

*Measuring point = Vtrip. See Table 2-26 on page 2-25 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-49

Timing Characteristics

1.5 V DC Core Voltage

Table 2-66 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Pro I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.59 6.24 0.04 1.86 2.31 0.38 6.36 5.30 2.45 1.98 8.37 7.31 ns

–1 0.50 5.31 0.03 1.58 1.97 0.33 5.41 4.51 2.08 1.68 7.12 6.22 ns

8 mA Std. 0.59 5.10 0.04 1.86 2.31 0.38 5.20 4.49 2.79 2.64 7.21 6.50 ns

–1 0.50 4.34 0.03 1.58 1.97 0.33 4.42 3.82 2.37 2.24 6.13 5.53 ns

12 mA Std. 0.59 4.29 0.04 1.86 2.31 0.38 4.37 3.91 3.03 3.05 6.39 5.92 ns

–1 0.50 3.65 0.03 1.58 1.97 0.33 3.72 3.32 2.58 2.60 5.43 5.04 ns

16 mA Std. 0.59 4.05 0.04 1.86 2.31 0.38 4.12 3.78 3.08 3.17 6.13 5.79 ns

–1 0.50 3.44 0.03 1.58 1.97 0.33 3.51 3.22 2.62 2.70 5.22 4.93 ns

24 mA Std. 0.59 3.94 0.04 1.86 2.31 0.38 4.01 3.80 3.15 3.60 6.03 5.81 ns

–1 0.50 3.35 0.03 1.58 1.97 0.33 3.41 3.23 2.68 3.06 5.13 4.94 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-67 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Pro I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.59 3.18 0.04 1.86 2.31 0.38 3.24 2.84 2.45 2.06 5.25 4.85 ns

–1 0.50 2.71 0.03 1.58 1.97 0.33 2.76 2.42 2.08 1.75 4.47 4.13 ns

8 mA Std. 0.59 2.61 0.04 1.86 2.31 0.38 2.65 2.19 2.79 2.73 4.67 4.20 ns

–1 0.50 2.22 0.03 1.58 1.97 0.33 2.26 1.86 2.37 2.32 3.97 3.57 ns

12 mA Std. 0.59 2.26 0.04 1.86 2.31 0.38 2.30 1.86 3.03 3.15 4.32 3.88 ns

–1 0.50 1.92 0.03 1.58 1.97 0.33 1.96 1.59 2.58 2.68 3.67 3.30 ns

16 mA Std. 0.59 2.20 0.04 1.86 2.31 0.38 2.24 1.80 3.08 3.26 4.26 3.82 ns

–1 0.50 1.87 0.03 1.58 1.97 0.33 1.91 1.54 2.62 2.77 3.62 3.25 ns

24 mA Std. 0.59 2.21 0.04 1.86 2.31 0.38 2.25 1.73 3.15 3.70 4.27 3.74 ns

–1 0.50 1.88 0.03 1.58 1.97 0.33 1.92 1.47 2.68 3.14 3.63 3.18 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

ProASIC3L DC and Switching Characteristics

2-50 Advance v0.6

Table 2-68 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.54 5.79 0.04 1.18 0.38 5.90 5.18 2.41 1.98 7.91 7.19 ns

–1 0.46 4.92 0.03 1.00 0.33 5.01 4.40 2.05 1.69 6.73 6.11 ns

6 mA Std. 0.54 4.84 0.04 1.18 0.38 4.93 4.43 2.74 2.60 6.94 6.44 ns

–1 0.46 4.11 0.03 1.00 0.33 4.19 3.77 2.33 2.21 5.90 5.48 ns

8 mA Std. 0.54 4.84 0.04 1.18 0.38 4.93 4.43 2.74 2.60 6.94 6.44 ns

–1 0.46 4.11 0.03 1.00 0.33 4.19 3.77 2.33 2.21 5.90 5.48 ns

12 mA Std. 0.54 4.13 0.04 1.18 0.38 4.21 3.92 2.97 2.99 6.22 5.93 ns

–1 0.46 3.52 0.03 1.00 0.33 3.58 3.33 2.53 2.54 5.29 5.04 ns

16 mA Std. 0.54 3.91 0.04 1.18 0.38 3.98 3.80 3.02 3.09 5.99 5.81 ns

–1 0.46 3.32 0.03 1.00 0.33 3.39 3.23 2.57 2.63 5.10 4.94 ns

24 mA Std. 0.54 3.85 0.04 1.18 0.38 3.87 3.85 3.09 3.48 5.88 5.87 ns

–1 0.46 3.28 0.03 1.00 0.33 3.29 3.28 2.63 2.96 5.01 4.99 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-69 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.54 2.97 0.04 1.18 0.38 3.03 2.74 2.41 2.07 5.04 4.75 ns

–1 0.46 2.53 0.03 1.00 0.33 2.58 2.33 2.05 1.76 4.29 4.04 ns

6 mA Std. 0.54 2.44 0.04 1.18 0.38 2.49 2.12 2.74 2.70 4.50 4.13 ns

–1 0.46 2.08 0.03 1.00 0.33 2.12 1.80 2.33 2.30 3.83 3.51 ns

8 mA Std. 0.54 2.44 0.04 1.18 0.38 2.49 2.12 2.74 2.70 4.50 4.13 ns

–1 0.46 2.08 0.03 1.00 0.33 2.12 1.80 2.33 2.30 3.83 3.51 ns

12 mA Std. 0.54 2.17 0.04 1.18 0.38 2.21 1.82 2.97 3.09 4.22 3.83 ns

–1 0.46 1.85 0.03 1.00 0.33 1.88 1.55 2.53 2.63 3.59 3.26 ns

16 mA Std. 0.54 2.12 0.04 1.18 0.38 2.16 1.76 3.03 3.19 4.17 3.78 ns

–1 0.46 1.81 0.03 1.00 0.33 1.84 1.50 2.57 2.72 3.55 3.21 ns

24 mA Std. 0.54 2.13 0.04 1.18 0.38 2.17 1.71 3.09 3.60 4.19 3.72 ns

–1 0.46 1.81 0.03 1.00 0.33 1.85 1.45 2.63 3.06 3.56 3.16 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-51

Table 2-70 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.54 5.27 0.04 1.17 0.38 5.37 4.68 2.03 1.79 7.38 6.69 ns

–1 0.46 4.49 0.03 0.99 0.33 4.57 3.98 1.73 1.52 6.28 5.69 ns

6 mA Std. 0.54 4.32 0.04 1.17 0.38 4.40 4.03 2.33 2.35 6.42 6.04 ns

–1 0.46 3.68 0.03 0.99 0.33 3.75 3.43 1.98 2.00 5.46 5.14 ns

8 mA Std. 0.54 4.32 0.04 1.17 0.38 4.40 4.03 2.33 2.35 6.42 6.04 ns

–1 0.46 3.68 0.03 0.99 0.33 3.75 3.43 1.98 2.00 5.46 5.14 ns

12 mA Std. 0.54 3.66 0.04 1.17 0.38 3.73 3.56 2.54 2.71 5.74 5.57 ns

–1 0.46 3.12 0.03 0.99 0.33 3.17 3.03 2.16 2.30 4.89 4.74 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-71 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.54 2.60 0.04 1.17 0.38 2.65 2.39 2.03 1.87 4.66 4.40 ns

–1 0.46 2.21 0.03 0.99 0.33 2.25 2.03 1.72 1.59 3.96 3.74 ns

6 mA Std. 0.54 2.10 0.04 1.17 0.38 2.14 1.83 2.33 2.44 4.16 3.84 ns

–1 0.46 1.79 0.03 0.99 0.33 1.82 1.56 1.98 2.07 3.54 3.27 ns

8 mA Std. 0.54 2.10 0.04 1.17 0.38 2.14 1.83 2.33 2.44 4.16 3.84 ns

–1 0.46 1.79 0.03 0.99 0.33 1.82 1.56 1.98 2.07 3.54 3.27 ns

12 mA Std. 0.54 1.86 0.04 1.17 0.38 1.90 1.55 2.54 2.80 3.91 3.57 ns

–1 0.46 1.59 0.03 0.99 0.33 1.61 1.32 2.16 2.38 3.33 3.03 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

ProASIC3L DC and Switching Characteristics

2-52 Advance v0.6

1.2 V DC Core Voltage

Table 2-72 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Pro I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.77 6.24 0.05 1.86 2.31 0.50 6.36 5.30 2.45 1.98 8.37 7.31 ns

–1 0.66 5.31 0.04 1.58 1.97 0.43 5.41 4.51 2.08 1.68 7.12 6.22 ns

8 mA Std. 0.77 5.10 0.05 1.86 2.31 0.50 5.20 4.49 2.79 2.64 7.21 6.50 ns

–1 0.66 4.34 0.04 1.58 1.97 0.43 4.42 3.82 2.37 2.24 6.13 5.53 ns

12 mA Std. 0.77 4.29 0.05 1.86 2.31 0.50 4.37 3.91 3.03 3.05 6.39 5.92 ns

–1 0.66 3.65 0.04 1.58 1.97 0.43 3.72 3.32 2.58 2.60 5.43 5.04 ns

16 mA Std. 0.77 4.05 0.05 1.86 2.31 0.50 4.12 3.78 3.08 3.17 6.13 5.79 ns

–1 0.66 3.44 0.04 1.58 1.97 0.43 3.51 3.22 2.62 2.70 5.22 4.93 ns

24 mA Std. 0.77 3.94 0.05 1.86 2.31 0.50 4.01 3.80 3.15 3.60 6.03 5.81 ns

–1 0.66 3.35 0.04 1.58 1.97 0.43 3.41 3.23 2.68 3.06 5.13 4.94 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-73 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Pro I/Os

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.77 3.18 0.05 1.86 2.31 0.50 3.24 2.84 2.45 2.06 5.25 4.85 ns

–1 0.66 2.71 0.04 1.58 1.97 0.43 2.76 2.42 2.08 1.75 4.47 4.13 ns

8 mA Std. 0.77 2.61 0.05 1.86 2.31 0.50 2.65 2.19 2.79 2.73 4.67 4.20 ns

–1 0.66 2.22 0.04 1.58 1.97 0.43 2.26 1.86 2.37 2.32 3.97 3.57 ns

12 mA Std. 0.77 2.26 0.05 1.86 2.31 0.50 2.30 1.86 3.03 3.15 4.32 3.88 ns

–1 0.66 1.92 0.04 1.58 1.97 0.43 1.96 1.59 2.58 2.68 3.67 3.30 ns

16 mA Std. 0.77 2.20 0.05 1.86 2.31 0.50 2.24 1.80 3.08 3.26 4.26 3.82 ns

–1 0.66 1.87 0.04 1.58 1.97 0.43 1.91 1.54 2.62 2.77 3.62 3.25 ns

24 mA Std. 0.77 2.21 0.05 1.86 2.31 0.50 2.25 1.73 3.15 3.70 4.27 3.74 ns

–1 0.66 1.88 0.04 1.58 1.97 0.43 1.92 1.47 2.68 3.14 3.63 3.18 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-53

Table 2-74 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/Os

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.70 5.79 0.05 1.18 0.50 5.90 5.18 2.41 1.98 7.91 7.19 ns

–1 0.60 4.92 0.04 1.00 0.43 5.01 4.40 2.05 1.69 6.73 6.11 ns

6 mA Std. 0.70 4.84 0.05 1.18 0.50 4.93 4.43 2.74 2.60 6.94 6.44 ns

–1 0.60 4.11 0.04 1.00 0.43 4.19 3.77 2.33 2.21 5.90 5.48 ns

8 mA Std. 0.70 4.84 0.05 1.18 0.50 4.93 4.43 2.74 2.60 6.94 6.44 ns

–1 0.60 4.11 0.04 1.00 0.43 4.19 3.77 2.33 2.21 5.90 5.48 ns

12 mA Std. 0.70 4.13 0.05 1.18 0.50 4.21 3.92 2.97 2.99 6.22 5.93 ns

–1 0.60 3.52 0.04 1.00 0.43 3.58 3.33 2.53 2.54 5.29 5.04 ns

16 mA Std. 0.70 3.91 0.05 1.18 0.50 3.98 3.80 3.02 3.09 5.99 5.81 ns

–1 0.60 3.32 0.04 1.00 0.43 3.39 3.23 2.57 2.63 5.10 4.94 ns

24 mA Std. 0.70 3.85 0.05 1.18 0.50 3.87 3.85 3.09 3.48 5.88 5.87 ns

–1 0.60 3.28 0.04 1.00 0.43 3.29 3.28 2.63 2.96 5.01 4.99 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-75 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/Os

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.70 2.97 0.05 1.18 0.50 3.03 2.74 2.41 2.07 5.04 4.75 ns

–1 0.60 2.53 0.04 1.00 0.43 2.58 2.33 2.05 1.76 4.29 4.04 ns

6 mA Std. 0.70 2.44 0.05 1.18 0.50 2.49 2.12 2.74 2.70 4.50 4.13 ns

–1 0.60 2.08 0.04 1.00 0.43 2.12 1.80 2.33 2.30 3.83 3.51 ns

8 mA Std. 0.70 2.44 0.05 1.18 0.50 2.49 2.12 2.74 2.70 4.50 4.13 ns

–1 0.60 2.08 0.04 1.00 0.43 2.12 1.80 2.33 2.30 3.83 3.51 ns

12 mA Std. 0.70 2.17 0.05 1.18 0.50 2.21 1.82 2.97 3.09 4.22 3.83 ns

–1 0.60 1.85 0.04 1.00 0.43 1.88 1.55 2.53 2.63 3.59 3.26 ns

16 mA Std. 0.70 2.12 0.05 1.18 0.50 2.16 1.76 3.03 3.19 4.17 3.78 ns

–1 0.60 1.81 0.04 1.00 0.43 1.84 1.50 2.57 2.72 3.55 3.21 ns

24 mA Std. 0.70 2.13 0.05 1.18 0.50 2.17 1.71 3.09 3.60 4.19 3.72 ns

–1 0.60 1.81 0.04 1.00 0.43 1.85 1.45 2.63 3.06 3.56 3.16 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

ProASIC3L DC and Switching Characteristics

2-54 Advance v0.6

Table 2-76 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus I/Os

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.70 5.27 0.05 1.17 0.50 5.37 4.68 2.03 1.79 7.38 6.69 ns

–1 0.60 4.49 0.04 0.99 0.43 4.57 3.98 1.73 1.52 6.28 5.69 ns

6 mA Std. 0.70 4.32 0.05 1.17 0.50 4.40 4.03 2.33 2.35 6.42 6.04 ns

–1 0.60 3.68 0.04 0.99 0.43 3.75 3.43 1.98 2.00 5.46 5.14 ns

8 mA Std. 0.70 4.32 0.05 1.17 0.50 4.40 4.03 2.33 2.35 6.42 6.04 ns

–1 0.60 3.68 0.04 0.99 0.43 3.75 3.43 1.98 2.00 5.46 5.14 ns

12 mA Std. 0.70 3.66 0.05 1.17 0.50 3.73 3.56 2.54 2.71 5.74 5.57 ns

–1 0.60 3.12 0.04 0.99 0.43 3.17 3.03 2.16 2.30 4.89 4.74 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-77 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus I/Os

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.70 2.60 0.05 1.17 0.50 2.65 2.39 2.03 1.87 4.66 4.40 ns

–1 0.60 2.21 0.04 0.99 0.43 2.25 2.03 1.72 1.59 3.96 3.74 ns

6 mA Std. 0.70 2.10 0.05 1.17 0.50 2.14 1.83 2.33 2.44 4.16 3.84 ns

–1 0.60 1.79 0.04 0.99 0.43 1.82 1.56 1.98 2.07 3.54 3.27 ns

8 mA Std. 0.70 2.10 0.05 1.17 0.50 2.14 1.83 2.33 2.44 4.16 3.84 ns

–1 0.60 1.79 0.04 0.99 0.43 1.82 1.56 1.98 2.07 3.54 3.27 ns

12 mA Std. 0.70 1.86 0.05 1.17 0.50 1.90 1.55 2.54 2.80 3.91 3.57 ns

–1 0.60 1.59 0.04 0.99 0.43 1.61 1.32 2.16 2.38 3.33 3.03 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-55

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 2-78 • Minimum and Maximum DC Input and Output Levels

Applicable to Pro I/Os

1.8 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 2 2 9 11 10 10

4 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 4 4 17 22 10 10

6 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 6 6 35 44 10 10

8 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 8 8 45 51 10 10

12 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 12 12 91 74 10 10

16 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 16 16 91 74 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-79 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.8 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 2 2 9 11 10 10

4 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 4 4 17 22 10 10

6 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 6 6 35 44 10 10

8 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 8 8 45 51 10 10

12 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 12 12 91 74 10 10

16 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 16 16 91 74 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

ProASIC3L DC and Switching Characteristics

2-56 Advance v0.6

Table 2-80 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O I/O Banks

1.8 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Max.,

mA1Max.,

mA1µA2µA2

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 2 2 9 11 10 10

4 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 4 4 17 22 10 10

6 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 6 6 35 44 10 10

8 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 8 8 35 44 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 2-9 • AC Loading

Table 2-81 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

01.80.95

*Measuring point = Vtrip. See Table 2-26 on page 2-25 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-57

Timing Characteristics

1.5 V DC Core Voltage

Table 2-82 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Pro I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.59 8.32 0.04 1.80 2.55 0.38 8.48 6.99 2.50 1.42 10.49 9.00 ns

–1 0.50 7.08 0.03 1.53 2.17 0.33 7.21 5.95 2.13 1.21 8.92 7.66 ns

4 mA Std. 0.59 6.85 0.04 1.80 2.55 0.38 6.98 5.89 2.93 2.50 8.99 7.90 ns

–1 0.50 5.83 0.03 1.53 2.17 0.33 5.94 5.01 2.49 2.12 7.65 6.72 ns

6 mA Std. 0.59 5.81 0.04 1.80 2.55 0.38 5.92 5.13 3.21 3.02 7.93 7.15 ns

–1 0.50 4.94 0.03 1.53 2.17 0.33 5.03 4.37 2.73 2.57 6.75 6.08 ns

8 mA Std. 0.59 5.46 0.04 1.80 2.55 0.38 5.56 4.99 3.28 3.17 7.57 7.00 ns

–1 0.50 4.64 0.03 1.53 2.17 0.33 4.73 4.24 2.79 2.70 6.44 5.95 ns

12 mA Std. 0.59 5.36 0.04 1.80 2.55 0.38 5.46 4.99 3.37 3.70 7.47 7.01 ns

–1 0.50 4.56 0.03 1.53 2.17 0.33 4.64 4.25 2.86 3.14 6.35 5.96 ns

16 mA Std. 0.59 5.36 0.04 1.80 2.55 0.38 5.46 4.99 3.37 3.70 7.47 7.01 ns

–1 0.50 4.56 0.03 1.53 2.17 0.33 4.64 4.25 2.86 3.14 6.35 5.96 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-83 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Pro I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.59 3.76 0.04 1.80 2.55 0.38 3.83 3.68 2.50 1.47 5.84 5.70 ns

–1 0.50 3.20 0.03 1.53 2.17 0.33 3.26 3.13 2.13 1.25 4.97 4.85 ns

4 mA Std. 0.59 3.05 0.04 1.80 2.55 0.38 3.11 2.73 2.92 2.58 5.12 4.75 ns

–1 0.50 2.59 0.03 1.53 2.17 0.33 2.64 2.33 2.49 2.19 4.35 4.04 ns

6 mA Std. 0.59 2.61 0.04 1.80 2.55 0.38 2.66 2.27 3.21 3.12 4.67 4.28 ns

–1 0.50 2.22 0.03 1.53 2.17 0.33 2.26 1.93 2.73 2.65 3.98 3.64 ns

8 mA Std. 0.59 2.53 0.04 1.80 2.55 0.38 2.58 2.18 3.27 3.26 4.59 4.19 ns

–1 0.50 2.15 0.03 1.53 2.17 0.33 2.19 1.85 2.78 2.77 3.90 3.57 ns

12 mA Std. 0.59 2.52 0.04 1.80 2.55 0.38 2.56 2.07 3.36 3.81 4.58 4.08 ns

–1 0.50 2.14 0.03 1.53 2.17 0.33 2.18 1.76 2.86 3.24 3.89 3.47 ns

16 mA Std. 0.59 2.52 0.04 1.80 2.55 0.38 2.56 2.07 3.36 3.81 4.58 4.08 ns

–1 0.50 2.14 0.03 1.53 2.17 0.33 2.18 1.76 2.86 3.24 3.89 3.47 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

ProASIC3L DC and Switching Characteristics

2-58 Advance v0.6

Table 2-84 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.54 7.77 0.04 1.18 0.38 7.92 6.80 2.50 1.44 9.93 8.81 ns

–1 0.46 6.61 0.03 1.00 0.33 6.73 5.78 2.13 1.22 8.45 7.49 ns

4 mA Std. 0.54 6.38 0.04 1.18 0.38 6.50 5.78 2.91 2.46 8.51 7.79 ns

–1 0.46 5.43 0.03 1.00 0.33 5.53 4.91 2.47 2.09 7.24 6.63 ns

6 mA Std. 0.54 5.48 0.04 1.18 0.38 5.58 5.11 3.18 2.94 7.59 7.12 ns

–1 0.46 4.66 0.03 1.00 0.33 4.75 4.35 2.71 2.51 6.46 6.06 ns

8 mA Std. 0.54 5.17 0.04 1.18 0.38 5.26 4.97 3.24 3.07 7.27 6.98 ns

–1 0.46 4.40 0.03 1.00 0.33 4.48 4.23 2.76 2.61 6.19 5.94 ns

12 mA Std. 0.54 5.06 0.04 1.18 0.38 5.15 5.03 3.34 3.55 7.17 7.04 ns

–1 0.46 4.30 0.03 1.00 0.33 4.38 4.28 2.84 3.02 6.10 5.99 ns

16 mA Std. 0.54 5.06 0.04 1.18 0.38 5.15 5.03 3.34 3.55 7.17 7.04 ns

–1 0.46 4.30 0.03 1.00 0.33 4.38 4.28 2.84 3.02 6.10 5.99 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-85 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.54 3.60 0.04 1.10 0.38 3.66 3.52 2.49 1.49 5.68 5.53 ns

–1 0.46 3.06 0.03 0.93 0.33 3.12 3.00 2.12 1.27 4.83 4.71 ns

4 mA Std. 0.54 2.81 0.04 1.10 0.38 2.87 2.64 2.90 2.55 4.88 4.65 ns

–1 0.46 2.39 0.03 0.93 0.33 2.44 2.25 2.47 2.17 4.15 3.96 ns

6 mA Std. 0.54 2.47 0.04 1.10 0.38 2.51 2.21 3.18 3.04 4.53 4.22 ns

–1 0.46 2.10 0.03 0.93 0.33 2.14 1.88 2.70 2.59 3.85 3.59 ns

8 mA Std. 0.54 2.40 0.04 1.10 0.38 2.45 2.13 3.24 3.17 4.46 4.14 ns

–1 0.46 2.04 0.03 0.93 0.33 2.08 1.81 2.76 2.70 3.79 3.52 ns

12 mA Std. 0.54 2.39 0.04 1.10 0.38 2.44 2.04 3.33 3.67 4.45 4.05 ns

–1 0.46 2.04 0.03 0.93 0.33 2.08 1.73 2.83 3.12 3.79 3.45 ns

16 mA Std. 0.54 2.39 0.04 1.10 0.38 2.44 2.04 3.33 3.67 4.45 4.05 ns

–1 0.46 2.04 0.03 0.93 0.33 2.08 1.73 2.83 3.12 3.79 3.45 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-59

Table 2-86 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Plus I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.54 7.21 0.04 1.17 0.38 7.35 6.14 2.03 1.32 9.36 8.16 ns

–1 0.46 6.13 0.03 0.99 0.33 6.25 5.23 1.72 1.12 7.96 6.94 ns

4 mA Std. 0.54 5.81 0.04 1.17 0.38 5.92 5.26 2.39 2.25 7.93 7.27 ns

–1 0.46 4.94 0.03 0.99 0.33 5.03 4.47 2.03 1.91 6.74 6.19 ns

6 mA Std. 0.54 4.96 0.04 1.17 0.38 5.05 4.65 2.64 2.69 7.06 6.66 ns

–1 0.46 4.22 0.03 0.99 0.33 4.30 3.96 2.25 2.29 6.01 5.67 ns

8 mA Std. 0.54 4.96 0.04 1.17 0.38 5.05 4.65 2.64 2.69 7.06 6.66 ns

–1 0.46 4.22 0.03 0.99 0.33 4.30 3.96 2.25 2.29 6.01 5.67 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-87 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Plus I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.54 3.22 0.04 1.08 0.38 3.28 3.04 2.02 1.37 5.30 5.06 ns

–1 0.46 2.74 0.03 0.92 0.33 2.79 2.59 1.72 1.17 4.50 4.30 ns

4 mA Std. 0.54 2.48 0.04 1.08 0.38 2.53 2.25 2.38 2.34 4.54 4.26 ns

–1 0.46 2.11 0.03 0.92 0.33 2.15 1.92 2.03 1.99 3.86 3.63 ns

6 mA Std. 0.54 2.17 0.04 1.08 0.38 2.21 1.86 2.64 2.79 4.22 3.87 ns

–1 0.46 1.85 0.03 0.92 0.33 1.88 1.58 2.24 2.37 3.59 3.29 ns

8 mA Std. 0.54 2.17 0.04 1.08 0.38 2.21 1.86 2.64 2.79 4.22 3.87 ns

–1 0.46 1.85 0.03 0.92 0.33 1.88 1.58 2.24 2.37 3.59 3.29 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

ProASIC3L DC and Switching Characteristics

2-60 Advance v0.6

1.2 V DC Core Voltage

Table 2-88 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Pro I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.77 8.32 0.05 1.80 2.55 0.50 8.48 6.99 2.50 1.42 10.49 9.00 ns

–1 0.66 7.08 0.04 1.53 2.17 0.43 7.21 5.95 2.13 1.21 8.92 7.66 ns

4 mA Std. 0.77 6.85 0.05 1.80 2.55 0.50 6.98 5.89 2.93 2.50 8.99 7.90 ns

–1 0.66 5.83 0.04 1.53 2.17 0.43 5.94 5.01 2.49 2.12 7.65 6.72 ns

6 mA Std. 0.77 5.81 0.05 1.80 2.55 0.50 5.92 5.13 3.21 3.02 7.93 7.15 ns

–1 0.66 4.94 0.04 1.53 2.17 0.43 5.03 4.37 2.73 2.57 6.75 6.08 ns

8 mA Std. 0.77 5.46 0.05 1.80 2.55 0.50 5.56 4.99 3.28 3.17 7.57 7.00 ns

–1 0.66 4.64 0.04 1.53 2.17 0.43 4.73 4.24 2.79 2.70 6.44 5.95 ns

12 mA Std. 0.77 5.36 0.05 1.80 2.55 0.50 5.46 4.99 3.37 3.70 7.47 7.01 ns

–1 0.66 4.56 0.04 1.53 2.17 0.43 4.64 4.25 2.86 3.14 6.35 5.96 ns

16 mA Std. 0.77 5.36 0.05 1.80 2.55 0.50 5.46 4.99 3.37 3.70 7.47 7.01 ns

–1 0.66 4.56 0.04 1.53 2.17 0.43 4.64 4.25 2.86 3.14 6.35 5.96 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-89 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Pro I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.77 3.76 0.05 1.80 2.55 0.50 3.83 3.68 2.50 1.47 5.84 5.70 ns

–1 0.66 3.20 0.04 1.53 2.17 0.43 3.26 3.13 2.13 1.25 4.97 4.85 ns

4 mA Std. 0.77 3.05 0.05 1.80 2.55 0.50 3.11 2.73 2.92 2.58 5.12 4.75 ns

–1 0.66 2.59 0.04 1.53 2.17 0.43 2.64 2.33 2.49 2.19 4.35 4.04 ns

6 mA Std. 0.77 2.61 0.05 1.80 2.55 0.50 2.66 2.27 3.21 3.12 4.67 4.28 ns

–1 0.66 2.22 0.04 1.53 2.17 0.43 2.26 1.93 2.73 2.65 3.98 3.64 ns

8 mA Std. 0.77 2.53 0.05 1.80 2.55 0.50 2.58 2.18 3.27 3.26 4.59 4.19 ns

–1 0.66 2.15 0.04 1.53 2.17 0.43 2.19 1.85 2.78 2.77 3.90 3.57 ns

12 mA Std. 0.77 2.52 0.05 1.80 2.55 0.50 2.56 2.07 3.36 3.81 4.58 4.08 ns

–1 0.66 2.14 0.04 1.53 2.17 0.43 2.18 1.76 2.86 3.24 3.89 3.47 ns

16 mA Std. 0.77 2.52 0.05 1.80 2.55 0.50 2.56 2.07 3.36 3.81 4.58 4.08 ns

–1 0.66 2.14 0.04 1.53 2.17 0.43 2.18 1.76 2.86 3.24 3.89 3.47 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-61

Table 2-90 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.70 7.77 0.05 1.18 0.50 7.92 6.80 2.50 1.44 9.93 8.81 ns

–1 0.60 6.61 0.04 1.00 0.43 6.73 5.78 2.13 1.22 8.45 7.49 ns

4 mA Std. 0.70 6.38 0.05 1.18 0.50 6.50 5.78 2.91 2.46 8.51 7.79 ns

–1 0.60 5.43 0.04 1.00 0.43 5.53 4.91 2.47 2.09 7.24 6.63 ns

6 mA Std. 0.70 5.48 0.05 1.18 0.50 5.58 5.11 3.18 2.94 7.59 7.12 ns

–1 0.60 4.66 0.04 1.00 0.43 4.75 4.35 2.71 2.51 6.46 6.06 ns

8 mA Std. 0.70 5.17 0.05 1.18 0.50 5.26 4.97 3.24 3.07 7.27 6.98 ns

–1 0.60 4.40 0.04 1.00 0.43 4.48 4.23 2.76 2.61 6.19 5.94 ns

12 mA Std. 0.70 5.06 0.05 1.18 0.50 5.15 5.03 3.34 3.55 7.17 7.04 ns

–1 0.60 4.30 0.04 1.00 0.43 4.38 4.28 2.84 3.02 6.10 5.99 ns

16 mA Std. 0.70 5.06 0.05 1.18 0.50 5.15 5.03 3.34 3.55 7.17 7.04 ns

–1 0.60 4.30 0.04 1.00 0.43 4.38 4.28 2.84 3.02 6.10 5.99 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-91 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.70 3.60 0.05 1.10 0.50 3.66 3.52 2.49 1.49 5.68 5.53 ns

–1 0.60 3.06 0.04 0.93 0.43 3.12 3.00 2.12 1.27 4.83 4.71 ns

4 mA Std. 0.70 2.81 0.05 1.10 0.50 2.87 2.64 2.90 2.55 4.88 4.65 ns

–1 0.60 2.39 0.04 0.93 0.43 2.44 2.25 2.47 2.17 4.15 3.96 ns

6 mA Std. 0.70 2.47 0.05 1.10 0.50 2.51 2.21 3.18 3.04 4.53 4.22 ns

–1 0.60 2.10 0.04 0.93 0.43 2.14 1.88 2.70 2.59 3.85 3.59 ns

8 mA Std. 0.70 2.40 0.05 1.10 0.50 2.45 2.13 3.24 3.17 4.46 4.14 ns

–1 0.60 2.04 0.04 0.93 0.43 2.08 1.81 2.76 2.70 3.79 3.52 ns

12 mA Std. 0.70 2.39 0.05 1.10 0.50 2.44 2.04 3.33 3.67 4.45 4.05 ns

–1 0.60 2.04 0.04 0.93 0.43 2.08 1.73 2.83 3.12 3.79 3.45 ns

16 mA Std. 0.70 2.39 0.05 1.10 0.50 2.44 2.04 3.33 3.67 4.45 4.05 ns

–1 0.60 2.04 0.04 0.93 0.43 2.08 1.73 2.83 3.12 3.79 3.45 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

ProASIC3L DC and Switching Characteristics

2-62 Advance v0.6

Table 2-92 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7V

Applicable to Standard Plus I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.70 7.21 0.05 1.17 0.50 7.35 6.14 2.03 1.32 9.36 8.16 ns

–1 0.60 6.13 0.04 0.99 0.43 6.25 5.23 1.72 1.12 7.96 6.94 ns

4 mA Std. 0.70 5.81 0.05 1.17 0.50 5.92 5.26 2.39 2.25 7.93 7.27 ns

–1 0.60 4.94 0.04 0.99 0.43 5.03 4.47 2.03 1.91 6.74 6.19 ns

6 mA Std. 0.70 4.96 0.05 1.17 0.50 5.05 4.65 2.64 2.69 7.06 6.66 ns

–1 0.60 4.22 0.04 0.99 0.43 4.30 3.96 2.25 2.29 6.01 5.67 ns

8 mA Std. 0.70 4.96 0.05 1.17 0.50 5.05 4.65 2.64 2.69 7.06 6.66 ns

–1 0.60 4.22 0.04 0.99 0.43 4.30 3.96 2.25 2.29 6.01 5.67 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-93 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Plus I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.70 3.22 0.05 1.08 0.50 3.28 3.04 2.02 1.37 5.30 5.06 ns

–1 0.60 2.74 0.04 0.92 0.43 2.79 2.59 1.72 1.17 4.50 4.30 ns

4 mA Std. 0.70 2.48 0.05 1.08 0.50 2.53 2.25 2.38 2.34 4.54 4.26 ns

–1 0.60 2.11 0.04 0.92 0.43 2.15 1.92 2.03 1.99 3.86 3.63 ns

6 mA Std. 0.70 2.17 0.05 1.08 0.50 2.21 1.86 2.64 2.79 4.22 3.87 ns

–1 0.60 1.85 0.04 0.92 0.43 1.88 1.58 2.24 2.37 3.59 3.29 ns

8 mA Std. 0.70 2.17 0.05 1.08 0.50 2.21 1.86 2.64 2.79 4.22 3.87 ns

–1 0.60 1.85 0.04 0.92 0.43 1.88 1.58 2.24 2.37 3.59 3.29 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-63

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 2-94 • Minimum and Maximum DC Input and Output Levels

Applicable to Pro I/Os

1.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 2 2 13 16 10 10

4 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 4 4 25 33 10 10

6 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 6 6 32 39 10 10

8 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 8 8 66 55 10 10

12 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12 66 55 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-95 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 2 2 13 16 10 10

4 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 4 4 25 33 10 10

6 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 6 6 32 39 10 10

8 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 8 8 66 55 10 10

12 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12 66 55 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

ProASIC3L DC and Switching Characteristics

2-64 Advance v0.6

Table 2-96 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

1.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 2 2 13 16 10 10

4 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 4 4 25 33 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 2-10 • AC Loading

Table 2-97 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

01.50.755

*Measuring point = Vtrip. See Table 2-26 on page 2-25 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC3L DC and Switching Characteristics

Advance v0.6 2-65

Timing Characteristics

1.5 V DC Core Voltage

Table 2-98 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Pro I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.59 8.65 0.04 1.99 2.77 0.38 8.81 7.17 3.06 2.41 10.83 9.18 ns

–1 0.50 7.36 0.03 1.69 2.36 0.33 7.50 6.10 2.61 2.05 9.21 7.81 ns

4 mA Std. 0.59 7.40 0.04 1.99 2.77 0.38 7.53 6.26 3.39 3.02 9.55 8.27 ns

–1 0.50 6.29 0.03 1.69 2.36 0.33 6.41 5.33 2.89 2.57 8.12 7.04 ns

6 mA Std. 0.59 6.94 0.04 1.99 2.77 0.38 7.07 6.09 3.46 3.19 9.08 8.11 ns

–1 0.50 5.91 0.03 1.69 2.36 0.33 6.01 5.18 2.94 2.72 7.73 6.90 ns

8 mA Std. 0.59 6.85 0.04 1.99 2.77 0.38 6.98 6.10 3.57 3.80 8.99 8.11 ns

–1 0.50 5.83 0.03 1.69 2.36 0.33 5.94 5.19 3.04 3.23 7.65 6.90 ns

12 mA Std. 0.59 6.85 0.04 1.99 2.77 0.38 6.98 6.10 3.57 3.80 8.99 8.11 ns

–1 0.50 5.83 0.03 1.69 2.36 0.33 5.94 5.19 3.04 3.23 7.65 6.90 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-99 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Pro I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.59 3.55 0.04 1.99 2.77 0.38 3.62 3.22 3.05 2.51 5.63 5.23 ns

–1 0.50 3.02 0.03 1.69 2.36 0.33 3.08 2.74 2.60 2.14 4.79 4.45 ns

4 mA Std. 0.59 3.03 0.04 1.99 2.77 0.38 3.08 2.64 3.38 3.13 5.10 4.65 ns

–1 0.50 2.58 0.03 1.69 2.36 0.33 2.62 2.25 2.87 2.66 4.34 3.96 ns

6 mA Std. 0.59 2.93 0.04 1.99 2.77 0.38 2.98 2.53 3.45 3.30 4.99 4.54 ns

–1 0.50 2.49 0.03 1.69 2.36 0.33 2.54 2.15 2.93 2.81 4.25 3.86 ns

8 mA Std. 0.59 2.90 0.04 1.99 2.77 0.38 2.95 2.39 3.57 3.94 4.96 4.41 ns

–1 0.50 2.46 0.03 1.69 2.36 0.33 2.51 2.04 3.03 3.35 4.22 3.75 ns

12 mA Std. 0.59 2.90 0.04 1.99 2.77 0.38 2.95 2.39 3.57 3.94 4.96 4.41 ns

–1 0.50 2.46 0.03 1.69 2.36 0.33 2.51 2.04 3.03 3.35 4.22 3.75 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

ProASIC3L DC and Switching Characteristics

2-66 Advance v0.6

Table 2-100 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.54 8.00 0.04 1.18 0.38 8.15 7.01 3.06 2.38 10.16 9.02 ns

–1 0.46 6.80 0.03 1.00 0.33 6.93 5.96 2.60 2.02 8.64 7.68 ns

4 mA Std. 0.54 6.91 0.04 1.18 0.38 7.04 6.21 3.37 2.94 9.05 8.22 ns

–1 0.46 5.88 0.03 1.00 0.33 5.99 5.28 2.87 2.50 7.70 7.00 ns

6 mA Std. 0.54 6.51 0.04 1.18 0.38 6.63 6.05 3.45 3.09 8.64 8.06 ns

–1 0.46 5.54 0.03 1.00 0.33 5.64 5.15 2.93 2.63 7.35 6.86 ns

8 mA Std. 0.54 6.41 0.04 1.18 0.38 6.53 6.11 3.56 3.64 8.54 8.12 ns

–1 0.46 5.45 0.03 1.00 0.33 5.56 5.20 3.03 3.10 7.27 6.91 ns

12 mA Std. 0.54 6.41 0.04 1.18 0.38 6.53 6.11 3.56 3.64 8.54 8.12 ns

–1 0.46 5.45 0.03 1.00 0.33 5.56 5.20 3.03 3.10 7.27 6.91 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-101 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage