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FEATURES DESCRIPTION
APPLICATIONS
1
DBZP
bq2024
ACKAGE
(TOP VIEW)
SDQ
VSS
VSS
2
3
IDROM
(64bits)
EPROM
MEMORY
(1536bits)
EPROM
STATUS
(64bits)
SDQCommunications
Controllerand8-BitCRC
GenerationCircuit
Internal
Bus
RAM
Buffer
(8bytes)
SDQ 1
2VSS 3 VSS
NC
SDQ
VSS
1
2
3
LP PACKAGE
(BOTTOMVIEW)
bq2024
SLUS770 – MAY 2007
1.5K-BIT SERIAL EPROM WITH SDQ INTERFACE
•1536 Bits of One-Time Programmable (OTP)
The bq2024 is a 1.5K-bit serial EPROM containing aEPROM For Storage Of User-Programmable
factory-programmed, unique 48-bit identificationConfiguration Data
number, 8-bit CRC generation, and the 8-bit familycode (09h). A 64-bit status register controls write•Factory-Programmed Unique 64-Bit
protection and page redirection.Identification Number
The bq2024 SDQ™ interface requires only a single•Bus-Interface Architecture Allowing Multiple
connection and a ground return. The DATA pin isbq2024's Attached to a Single Host
also the sole power source for the bq2024. The bus•Single-Wire Interface to Reduce Circuit Board
architecture allows multiple SDQ devices to beRouting
connected to a single host.•Synchronous Communication Reduces Host
The small surface-mount package options savesInterrupt Overhead
printed-circuit-board space, while the low cost makes•No Standby Power Required
it ideal for applications such as battery packconfiguration parameters, record maintenance, asset•Address Space Backward Compatible With
tracking, product-revision status, and access-codebq2022A
security.•8-byte RAM Buffer for Faster Write•Page Address Redirection
ORDERING INFORMATION
(1)
•15KV IEC 61000-4-2 Air Charge on SDQ
PACKAGED DEVICES
(3)T
A
(2)•Available in a 3-Pin SOT23 Package and TO-92
PART NUMBER PACKAGE STATUSPackage
–20 °C to bq2024DBZR SOT23-3 Production70 °C
bq2024LPR TO-92 Preview
(1) For the most current package and ordering information, see•Security Encoding
the Package Option Addendum at the end of this document,•Inventory Tracking
or see the TI Web site at www.ti.com .(2) Device specified to communicate at –40 °C to 85 °C.•Product-Revision Maintenance
(3) The device is available only in tape and reel with a base•Battery-Pack Identification
quantity of 3000 units for the bq2024DBZR and 2000 units forthe bq2024LPR.
BLOCK DIAGRAM
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.SDQ is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains
Copyright © 2007, Texas Instruments IncorporatedPRODUCTION DATA information current as of publication date.Products conform to specifications per the terms of TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
AC SWITCHING CHARACTERISTCS
bq2024
SLUS770 – MAY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
over operating free-air temperature range unless otherwise noted
(1)
UNIT
V
PU
DC voltage applied to data –0.3 V to 7 VI
OL
Low-level output current 40 mAESD IEC 61000-4-2 Air discharge Data to V
SS,
V
SS
to data 15 kVT
A
Operating free-air temperature range –20 °C to 70 °CT
A(Comm)
Communication free-air temperature range Communication is specified by design –40 °C to 85 °CT
stg
Storage temperature range –55 °C to 125 °CLead temperature (soldering, 10 s) 260 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
T
A
= –20 °C to 70 °C; V
PU(min)
= 2.65 V
DC
to 5.5 V
DC
, all voltages relative to VSS
PARAMETER TEST CONDITION MIN TYP MAX UNIT
I
DATA
Supply current V
PU
= 5.5 V 20 µALogic 0, V
PU
= 5.5 V, I
OL
= 4 mA, SDQ pin 0.4V
OL
Low-level output voltage VLogic 0, V
PU
= 2.65 V, I
OL
= 2 mA 0.4V
OH
High-level output voltage Logic 1 V
PU
5.5I
OL
Low-level output current (sink) V
OL
= 0.4 V, SDQ pin 4 mAV
IL
Low-level input voltage Logic 0 0.8 VV
IH
High-level input voltage Logic 1 2.2 VV
PP
Programming voltage 11.5 12 V
T
A
= –20 °C to 70 °C; V
PU(min)
= 2.65 V
DC
to 5.5 V
DC
, all voltages relative to VSS
PARAMETER TEST CONDITION MIN TYP MAX UNIT
t
c
Bit cycle time
(1)
60 120 µst
WSTRB
Write start cycle
(1)
1 15 µst
WDSU
Write data setup
(1)
t
WSTRB
15 µst
WDH
Write data hold
(1) (2)
60 t
c
µs1t
rec
Recovery time
(1)
µsFor memory command only 5t
RSTRB
Read start cycle
(1)
1 13 µst
ODD
Output data delay
(1)
t
RSTRB
13 µst
ODHO
Output data hold
(1)
17 60 µst
RST
Reset time
(1)
480 µst
PPD
Presence pulse delay
(1)
15 60 µst
PP
Presence pulse
(1)
60 240 µst
EPROG
EPROM programming time 2500 µst
PSU
Program setup time 5 µst
PREC
Program recovery time 5 µs
(1) 5-k Ωseries resistor between SDQ pin and V
PU
. (See Figure 1 )(2) t
WDH
must be less than t
c
to account for recovery.
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FUNCTIONAL DESCRIPTION
GENERAL OPERATION
1536-BIT EPROM
bq2024
SLUS770 – MAY 2007
AC SWITCHING CHARACTERISTCS (continued)T
A
= –20 °C to 70 °C; V
PU(min)
= 2.65 V
DC
to 5.5 V
DC
, all voltages relative to VSS
PARAMETER TEST CONDITION MIN TYP MAX UNIT
t
PRE
Program rising-edge time 5 µst
PFE
Program falling-edge time 5 µst
RSTREC
480 µs
Terminal Functions
TERMINAL
I/O DESCRIPTIONNAME NO.
bq2024DBZR
SDQ 1 I DataVSS 2, 3 - Ground
bq2024LPR, bq2024LPFR
VSS 1 - GNDSDQ 2 I DataNC 3 - No connection
The block diagram on page 1 shows the relationships among the major control and memory sections of thebq2024. The bq2024 has three main data components: a 1536-bit factory-programmed ROM, including 8-bitfamily code, 48-bit identification number and 8-bit CRC value, EPROM, and EPROM STATUS bytes. Power forread and write operations is derived from the DATA pin. An internal capacitor stores energy while the signal lineis high and releases energy during the low times of the DATA pin, until the pin returns high to replenish thecharge on the capacitor. A special manufacturer's PROGRAM PROFILE BYTE can be read to determine theprogramming profile required to program the part.
Table 1 is a memory map of the 1536-bit EPROM section of the bq2024, configured as six pages of 32 byteseach. The 8-byte RAM buffers are additional registers used when programming the memory. Data are firstwritten to the RAM buffer and then verified by reading an 8-bit CRC from the bq2024 that confirms properreceipt of the data. If the buffer contents are correct, a programming command is issued and an 8-byte segmentof data is written into the selected address in memory. This process ensures data integrity when programmingthe memory. The details for reading and programming the 1536-bit EPROM portion of the bq2024 are in theMemory Function Commands section of this data sheet.
Table 1. 1536-BIT EPROM Data Memory Map
ADDRESS(HEX) PAGE
00A0-00BF Page 50080-009F Page 40060-007F Page 30040-005F Page 20020-003F Page 10000-001F Page 0
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EPROM STATUS MEMORY
Error Checking
Customizing the bq2024
Bus Termination
bq2024
SLUS770 – MAY 2007
In addition to the programmable 1536 bits of memory, there are 64 bits of status information contained in theEPROM STATUS memory. The STATUS memory is accessible with separate commands. The STATUS bits areEPROM and are read or programmed to indicate various conditions to the software interrogating the bq2024.The first byte of the STATUS memory contains the write protect page bits, that inhibit programming of thecorresponding page in the 1536-bit main memory area if the appropriate write-protection bit is programmed.Once a bit has been programmed in the write protect page byte, the entire 32-byte page that corresponds to thatbit can no longer be altered but may still be read. The write protect bits may be cleared by using the WRITESTATUS command.
The next six bytes of the EPROM STATUS memory contain the page address redirection bytes. Bits in theEPROM status bytes can indicate to the host what page is substituted for the page by the appropriateredirection byte. The hardware of the bq2024 makes no decisions based on the contents of the page addressredirection bytes. This feature allows the user's software to make a data patch to the EPROM by indicating thata particular page or pages should be replaced with those indicated in the page address redirection bytes. Theones complement of the new page address is written into the page address redirection byte that corresponds tothe original (replaced) page. If a page address redirection byte has an FFh value, the data in the main memorythat corresponds to that page are valid. If a page address redirection byte has some other hex value, the data inthe page corresponding to that redirection byte are invalid, and the valid data can now be found at the onescomplement of the page address indicated by the hexadecimal value stored in the associated page addressredirection byte. A value of FDh in the redirection byte for page 1, for example, indicates that the updated dataare now in page 2. The details for reading and programming the EPROM status memory portion of the bq2024are given in the Memory Function Commands section.
Table 2. EPROM Status Bytes
ADDRESS (HEX) PAGE
Write protection bitsBIT0 - write protect page 0BIT1 - write protect page 1BIT2 - write protect page 200h
BIT3 - write protect page 3BIT4 -write protect page 4BIT5 -write protect page 5BIT6 to 7 -bitmap of used pages01h Redirection byte for page 002h Redirection byte for page 103h Redirection byte for page 204h Redirection byte for page 305h Redirection byte for page 406h Redirection byte for page 507h Factory programmed 00h
To validate the data transmitted from the bq2024, the host generates a CRC value from the data as they arereceived. This generated value is compared to the CRC value transmitted by the bq2024. If the two CRC valuesmatch, the transmission is error-free. The equivalent polynomial function of this CRC is X
8
+ X
5
+ X
4
+ 1. Detailsare found in the CRC Generation Section of this data sheet.
The 64-bit ID identifies each bq2024. The 48-bit serial number is unique and programmed by Texas Instruments.The default 8-bit family code is 09h; however, a different value can be reserved on an individual customer basis.Contact your Texas Instruments sales representative for more information.
Because the drive output of the bq2024 is an open-drain, N-channel MOSFET, the host must provide a sourcecurrent or a 5-k Ωexternal pullup, as shown in the typical application circuit in Figure 1 .
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SDQI
SDQO
VSS
Communications
Controller CPU
HOST
bq2024
VPU
2
1
3
VSS
SDQ
Serial Communication
Initialization
ROM COMMANDS
READ ROM
0
11 00011 CRC (1 BYTE)
Reset
and
Presence
Signals
Read ROM (33h) Family Code and Identification
Number (7 BYTES)
bq2024
SLUS770 – MAY 2007
Figure 1. Typical Applications Circuit
A host reads, programs, or checks the status of the bq2024 through the hierarchical command structure of theSDQ interface. Figure 2 shows that the host must first issue a ROM command before the EPROM memory orstatus can be read or modified. The ROM command either selects a specific device when multiple devices areon the SDQ bus, or skips the selection process in single SDQ device applications.
Initialization ROM Command Sequence Memory/Status Command Sequence
Figure 2. General Command Sequence
Initialization consists of two pulses, the RESET and the PRESENCE pulses. The host generates the RESETpulse, while the bq2024 responds with the PRESENCE pulse. The host resets the bq2024 by driving the DATAbus low for at least 480 µs. For more details, see the RESET section under SDQ Signaling.
The READ ROM command sequence is the fastest sequence that allows the host to read the 8-bit family codeand 48-bit identification number. It is used if only one SDQ slave device is attached to the bus. The READ ROMsequence starts with the host generating the RESET pulse of at least 480 µs. The bq2024 responds with aPRESENCE pulse. Next, the host continues by issuing the READ ROM command, 33h, and then reads theROM and CRC byte using the READ signaling (see the READ and WRITE signals section) during the dataframe.
Figure 3. READ ROM Sequence
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MATCH ROM
1 10 0 01 1 CRC (1 BYTE)
0
Reset
and
Presence
Signals
Match ROM (55h) Family Code and Identification
Number (7 BYTES)
SEARCH ROM
BIT0
Reset
and
Presence
Signals 0 0 0 0 1 1 1 1 BITn BIT63
Search ROM (F0h) Data Read
bq2024
SLUS770 – MAY 2007
The MATCH ROM command, 55h, is used by the host to select a specific SDQ device when the family code andidentification number is known. The host issues the MATCH ROM command followed by the family code, ROMnumber, and the CRC byte. Only the device that matches the 64-bit ROM sequence is selected and available toperform subsequent Memory/Status Function commands.
Figure 4. MATCH ROM Sequence
The SEARCH ROM command, F0h, is used to obtain the 8-bit family code and the 48-bit identification numberand 8-bit CRC of any SDQ device when it is unknown. All devices on the bus are read under the SEARCH ROMcommand with the use of a collision-detect and device-decode method. Figure 5 shows the SEARCH ROMsequence started by the host, generating the RESET pulse of at least 480 µs. The bq2024 responds with aPRESENCE pulse. The host then issues the command in the command frame by writing an F0h. During theDATA READ of the SEARCH ROM sequence, each bit is transmitted three times. The bq2024 transmits the bitfollowed by the complement of the bit. The host in turn retransmits the bit just read. Collision detection isperformed by comparing the bit and bit complement time-slots. If they are both zero, this indicates that acollision has occurred, indicating multiple devices on the bus. The device decode is achieved in the thirdtransmission of the bit from the host back to the bq2024. If the bit transmitted by the host does not match the bittransmitted by the bq2024, then the device with mismatch stops transmitting. Devices that did match, continuetransmitting. This process is continued until all bits of a single device are read. The SEARCH ROM command isreissued and the process is repeated to read additional devices.
NOTE:
If the number of devices on the bus is unknown, the SEARCH ROM command shouldbe used.
A. B = bit(n):nth bit transmitted by bq2024B. C = bit(n): complement of nth bit transmitted by bq2024C. H = bit(n):nth bit transmitted by host
Figure 5. SEARCH ROM Sequence
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SKIP ROM
MEMORY/STATUS FUNCTION COMMANDS
READ DATA MEMORY COMMANDS
READ MEMORY/Page CRC
bq2024
SLUS770 – MAY 2007
This SKIP ROM command, CCh, allows the host to access the memory/status functions without issuing the64-bit ROM code sequence. The SKIP ROM command is directly followed by a memory/status functionscommand. Because this command can cause bus collisions when multiple SDQ devices are on the same bus,this command should be issued in single device applications.
Figure 6. SKIP ROM Sequence
Six memory/status function commands allow read and modification of the 1536-bit EPROM data memory or the64-bit EPROM status memory. There are two types of READ MEMORY command, plus the WRITE MEMORY,READ STATUS, and WRITE STATUS commands. Additionally, the part responds to a PROGRAM PROFILEbyte command. The bq2024 responds to memory/status function commands only after a part is selected by aROM command.
Two READ MEMORY commands are available on the bq2024. Both commands are used to read data from the1536-bit EPROM data field. They are the READ MEMORY/Page CRC and the READ MEMORY/Field CRCcommands. The READ MEMORY/Page CRC generates CRC at the end any 32-byte page boundary whereasthe READ MEMORY/Field CRC generates CRC when the end of the 1536-bit data memory is reached.
To read memory and generate the CRC at the 32-byte page boundaries of the bq2024, the ROM command isfollowed by the READ MEMORY/Generate CRC command, C3h, followed by the address low byte and then theaddress high byte.
An 8-bit CRC of the command byte and address bytes is computed by the bq2024 and read back by the host toconfirm that the correct command word and starting address were received. If the CRC read by the host isincorrect, a reset pulse must be issued and the entire sequence must be repeated. If the CRC received by thehost is correct, the host issues read time slots and receives data from the bq2024 starting at the initial addressand continuing until the end of a 32-byte page is reached. At that point, the host sends eight additional read timeslots and receive an 8-bit CRC that is the result of shifting into the CRC generator all of the data bytes from theinitial starting byte to the last byte of the current page. Once the 8-bit CRC has been received, data is againread from the 1536-bit EPROM data field starting at the next page. This sequence continues until the final pageand its accompanying CRC are read by the host. Thus each page of data can be considered to be 33 byteslong, the 32 bytes of user-programmed EPROM data and an 8-bit CRC that gets generated automatically at theend of each page.
READ EPROM Memory and CRCInitialization and ROM Read andMEMORY/Generate Address Low Byte Address High Byte ByteCommand Sequence Verify CRCCRC Command Generated at 32-Byte
PageC3h A0 A7 A8 A15
Boundaries
NOTE: Individual bytes of address and data are transmitted LSB first.
Figure 7. READ MEMORY/Page CRC
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READ MEMORY/Field CRC
WRITE MEMORY
bq2024
SLUS770 – MAY 2007
To read memory without CRC generation on 32-byte page boundaries, the ROM command is followed by theREAD MEMORY command, F0h, followed by the address low byte and then the address high byte.
NOTE:
As shown in Figure 8 , individual bytes of address and data are transmitted LSB first.
An 8-bit CRC of the command byte and address bytes is computed by the bq2024 and read back by the host toconfirm that the correct command word and starting address were received. If the CRC read by the host isincorrect, a reset pulse must be issued and the entire sequence must be repeated. If the CRC received by thehost is correct, the host issues read time slots and receives data from the bq2024 starting at the initial addressand continuing until the end of the 1536-bit data field is reached or until a reset pulse is issued. If reading occursthrough the end of memory space, the host may issue eight additional read time slots and the bq2024 respondswith an 8-bit CRC of all data bytes read from the initial starting byte through the last byte of memory. After theCRC is received by the host, any subsequent read time slots appear as logical 1s until a reset pulse is issued.Any reads ended by a reset pulse prior to reaching the end of memory does not have the 8-bit CRC available.
Read EPROMInitialization and ROM
READ MEMORY Command Address Low Address High Read and Memory Until End Read andCommand
F0h Byte Byte Verify CRC of EPROM Verify CRCSequence
MemoryA0 A7 A8 A15
Figure 8. READ MEMORY/Field CRC
The WRITE MEMORY command is used to program the 1536-bit EPROM memory field. The 1536-bit memoryfield is programmed in 8-byte segments. Data is first written into an 8-byte RAM buffer one byte at a time. Thecontents of the RAM buffer is then ANDed with the contents of the EPROM memory field when the programmingcommand is issued.
Figure 9 illustrates the sequence of events for programming the EPROM memory field. After issuing a ROMcommand, the host issues the WRITE MEMORY command, 0Fh, followed by the low byte and then the highbyte of the starting address. The bq2024 calculates and transmits an 8-bit CRC based on the WRITE commandand address.
If at any time during the WRITE MEMORY process, the CRC read by the host is incorrect, a reset pulse must beissued, and the entire sequence must be repeated.
After the bq2024 transmits the CRC, the host then transmits 8 bytes of data to the bq2024. Another 8-bit CRC iscalculated and transmitted based on the 8 bytes of data. If this CRC agrees with the CRC calculated by the host,the host transmits the program command 5Ah and then applies the programming voltage for at least 2500 µs ort
EPROG
. The contents of the RAM buffer is then logically ANDed with the contents of the 8-byte EPROM offset bythe starting address.
The starting address can be any integer multiple of eight between 0000 and 00BF (hex) such as 0000, 0008,and 0010 (hex).
The WRITE DATA MEMORY command sequence can be terminated at any point by issuing a reset pulseexcept during the program pulse period t
PROG
.
NOTE:
The bq2024 responds with the data from the selected EPROM address sent leastsignificant-bit first. This response should be checked to verify the programmed byte. Ifthe programmed byte is incorrect, then the host must reset the part and begin thewrite sequence again.
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NOTE:IndividualbytesofaddressanddataaretransmittedLSBfirst
WriteMemory
Command?
(0Fh)
Selected
State
Selected
State
BusMaster TransmitsLowByte Address
(LSBFirst) AD0to AD7
BusMaster TransmitsHighByte Address
(LSBFirst) AD8to AD15
bq2024
Loads AddressInto AddressCounter
bq2024 TransmitsCRCofWriteCommand
and Address,thenClearsCRCRegister
bq2024Receives8BytesofDataand
StoresinRAMBuffer
bq2024 Transmits
CRCofPreviousReceived8BytesofData
Code5Ah
Received
YN VoltageonData
Pin=VPP
Y
N
N
Y
ContentsofRAMbuffer AND’edwithcontentsof
datamemoryoffsetby
addresscounterandstoredindata
memoryoffsetbyaddresscounter .
programmingtimerequiredtobeat
leastt EPROG whenVPP Vdcondatapin
bq2024
Transmits1ByteofDataMemory
at AddressCounter
8thByte
Transmitted
Y
N
bq2024 WaitsforReset
(NoFurtherResponse)
bq2024
Increments Address
Counterand Transmits1
ByteofDataMemory
Indexedby AddressCounter
bq2024
SLUS770 – MAY 2007
For both of these cases, the decision to continue programming is made entirely by the host, because thebq2024 is not able to determine if the 8-bit CRC calculated by the host agrees with the 8-bit CRC calculated bythe bq2024.
Prior to programming, bits in the 1536-bit EPROM data field appear as logical 1s.
Figure 9. WRITE MEMORY Command Flow
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READ STATUS
WRITE STATUS
bq2024
SLUS770 – MAY 2007
The READ STATUS command is used to read data from the EPROM status data field. After issuing a ROMcommand, the host issues the READ STATUS command, AAh, followed by the address low byte and then theaddress high byte.
NOTE:
An 8-bit CRC of the command byte and address bytes is computed by the bq2024and read back by the host to confirm that the correct command word and startingaddress were received.
If the CRC read by the host is incorrect, a reset pulse must be issued and the entire sequence must berepeated. If the CRC received by the host is correct, the host issues read time slots and receives data from thebq2024 starting at the supplied address and continuing until the end of the EPROM Status data field is reached.At that point, the host receives an 8-bit CRC that is the result of shifting into the CRC generator all of the databytes from the initial starting byte through the final factory-programmed byte that contains the 00h value.
This feature is provided because the EPROM status information may change over time making it impossible toprogram the data once and include an accompanying CRC that is always valid. Therefore, the READ statuscommand supplies an 8-bit CRC that is based on (and always is consistent with) the current data stored in theEPROM status data field.
After the 8-bit CRC is read, the host receives logical 1s from the bq2024 until a reset pulse is issued. The READSTATUS command sequence can be ended at any point by issuing a reset pulse.
Read STATUSInitialization and ROM
READ MEMORY Command Address Low Address High Read and Memory Until End Read andCommand
AAh Byte Byte Verify CRC of STATUS Verify CRCSequence
MemoryA0 A7 A8 A15
Figure 10. READ STATUS Command
The Write Status command is used to program the EPROM Status data field after the bq2024 has been selectedby a ROM command
The flow chart in Figure 11 illustrates that the host issues the Write Status command, 55h, followed by theaddress low byte and then the address high byte the followed by the byte of data to be programmed.
NOTE:
Individual bytes of address and data are transmitted LSB first. An 8-bit CRC of thecommand byte, address bytes, and data byte is computed by the bq2024 and readback by the host to confirm that the correct command word, starting address, anddata byte were received.
If the CRC read by the host is incorrect, a reset pulse must be issued and the entire sequence must berepeated. If the CRC received by the host is correct, the program command (5Ah) is issued. After the programcommand is issued, then the programming voltage, V
PP
is applied to the DATA pin for period t
PROG
. Prior toprogramming, the first seven bytes of the EPROM STATUS data field appear as logical 1s. For each bit in thedata byte provided by the host that is set to a logical 0, the corresponding bit in the selected byte of the EPROMSTATUS data field is programmed to a logical 0 after the programming pulse has been applied at the bytelocation. The eighth byte of the EPROM STATUS byte data field is factory-programmed to contain 00h.
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WriteStatus
Command?
(55h)
Selected
State
Selected
State
bq2024ReceivesLow AddressByte
(LSBFirst) AD0to AD7
bq2024ReceivesHigh AddressByte
(LSBFirst) AD8to AD15
bq2024Loads Addressinto AddressCounter
bq2024Receives1ByteofData
andStoresinRAMBuffer
bq2024 TransmitsCRCofWriteStatus
Command, Address,andData
Code5Ah
Received
YN
Y
N
N
Y
ContentsofRAMbuffer AND’edwithcontentsof
datamemoryaspointedtobyaddresscounter .
Programmingtimerequiredtobeatleast
t
bq2024
TransmitsDataByteof
StatusMemoryPointed
toby AddressCounter
bq2024 WaitsforReset
EndofStatus
Memory?
Y
N
bq2024
Increments Address
CounterandLoads
New AddressintoCRC
Register
bq2024
ReceivesDataByte
bq2024
Calculatesand Transmits
CRCofLoaded Addressand
ShiftedData
V =V ?
DATA PP
EPROG whenVPP isappliedtothedatapin
bq2024
SLUS770 – MAY 2007
Figure 11. WRITE STATUS Command Flow
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bq2024
SLUS770 – MAY 2007
After the programming pulse is applied and the data line returns to V
PU
, the host issues eight read time slots toverify that the appropriate bits have been programmed. The bq2024 responds with the data from the selectedEPROM STATUS address sent least significant bit first. This response should be checked to verify theprogrammed byte. If the programmed byte is incorrect, then the host must reset the device and begin the writesequence again. If the bq2024 EPROM data byte programming was successful, the bq2024 automaticallyincrements its address counter to select the next byte in the STATUS MEMORY data field. The least significantbyte of the new two-byte address is also loaded into the 8-bit CRC generator as a starting value. The hostissues the next byte of data using eight write time slots.
As the bq2024 receives this byte of data into the RAM buffer, it also shifts the data into the CRC generator thathas been preloaded with the LSB of the current address and the result is an 8-bit CRC of the new data byte andthe LSB of the new address. After supplying the data byte, the host reads this 8-bit CRC from the bq2024 witheight read time slots to confirm that the address incremented properly and the data byte was received correctly.If the CRC is incorrect, a Reset Pulse must be issued and the Write Status command sequence must berestarted. If the CRC is correct, the host issues a programming pulse and the selected byte in memory isprogrammed.
NOTE:
The initial write of the WRITE STATUS command, generates an 8-bit CRC value thatis the result of shifting the command byte into the CRC generator, followed by thetwo-address bytes, and finally the data byte. Subsequent writes within this WRITESTATUS command due to the bq2024 automatically incrementing its address countergenerates an 8-bit CRC that is the result of loading (not shifting) the LSB of the new(incremented) address into the CRC generator and then shifting in the new data byte.
For both of these cases, the decision to continue programming the EPROM Status registers is made entirely bythe host, because the bq2024 is not able to determine if the 8-bit CRC calculated by the host agrees with the8-bit CRC calculated by the bq2024. If an incorrect CRC is ignored and a program pulse is applied by the host,incorrect programming could occur within the bq2024. Also note that the bq2024 always increments its internaladdress counter after the receipt of the eight read time slots used to confirm the programming of the selectedEPROM byte. The decision to continue is again made entirely by the host, therefore if the EPROM data bytedoes not match the supplied data byte but the master continues with the WRITE STATUS command, incorrectprogramming could occur within the bq2024. The WRITE STATUS command sequence can be ended at anypoint by issuing a reset pulse.
Table 3. Command Code Summary
COMMAND
DESCRIPTION CATEGORY(HEX)
Read Serialization ROM and33h
CRC55h Match Serialization ROM
ROM Commands Available in Command Level IF0h Search Serialization ROMCCh Skip Serialization ROMF0h Read Memory/Field CRCAAh Read EPROM StatusC3h Read Memory/Page CRC
Memory Function CommandsAvailable in Command Level II0Fh Write Memory99h Programming Profile55h Write EPROM Status
Program Command Available Only in WRITE5Ah Program Control
MEMORY and WRITE STATUS Modes
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PROGRAM PROFILE BYTE
Other
Command
Codes
bq2024 Transmits
MasterIssuesReset
N
Y
bq2024
isin
ResetState
FromROM
Command
Program
ProfileCommand?
99h
55h
SDQ SIGNALING
RESET AND PRESENCE PULSE
VPU
VIH
VIL
tRST
tPPD tPP
RESET
(SentbyHost)
PresencePulse
(Sentbybq2024)
tRSTREC
WRITE
bq2024
SLUS770 – MAY 2007
The PROGRAM PROFILE byte is read to determine the WRITE MEMORY programming sequence required bya specific manufacturer. After issuing a ROM command, the host issues the PROGRAM PROFILE BYTEcommand, 99h. Figure 12 shows the the bq2024 responds with 55h. This informs the host that the WRITEMEMORY programming sequence is the one described in the WRITE MEMORY command section of this datasheet.
Figure 12. PROGRAM PROFILE Command Flow
All SDQ signaling begins with initializing the device, followed by the host driving the bus low to write a 1 or 0, orto begin the start frame for a bit read. Figure 13 shows the initialization timing, whereas Figure 14 and Figure 15show that the host initiates each bit by driving the DATA bus low for the start period, t
WSTRB
/ t
RSTRB
. After the bitis initiated, either the host continues controlling the bus during a WRITE, or the bq2024 responds during aREAD.
If the DATA bus is driven low for more than 120 µs, the bq2024 may be reset. Figure 13 shows that if the DATAbus is driven low for more than 480 µs, the bq2024 resets and indicates that it is ready by responding with aPRESENCE PULSE.
Figure 13. Reset Timing Diagram
The WRITE bit timing diagram in Figure 14 shows that the host initiates the transmission by issuing the t
WSTRBportion of the bit and then either driving the DATA bus low for a WRITE 0, or releasing the DATA bus for aWRITE 1.
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tWSTRB
tWDSU tWDH
trec
VPU VIH
VIL
Write ”1”
Write ”0”
READ
tRSTRB
tODD tODHO
tREC
VPU VIH
VIL
Read ”1”
Read ”0”
PROGRAM PULSE
VPP
VPU
VSS
tPREC
tPSU tEPROG
tPRE tPFE
IDLE
CRC Generation
bq2024
SLUS770 – MAY 2007
Figure 14. Write Bit Timing Diagram
The READ bit timing diagram in Figure 15 shows that the host initiates the transmission of the bit by issuing thet
RSTRB
portion of the bit. The bq2024 then responds by either driving the DATA bus low to transmit a READ 0 orreleasing the DATA bus to transmit a READ 1.
Figure 15. Read Bit Timing Diagram
Figure 16. Program Pulse Timing Diagram
If the bus is high, the bus is in the IDLE state. Bus transactions can be suspended by leaving the DATA bus inIDLE. Bus transactions can resume at any time from the IDLE state.
The bq2024 has an 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master cancompute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within thebq2024 to determine if the ROM data has been received error-free by the bus master. The equivalent polynomialfunction of this CRC is: X
8
+ X
5
+ X
4
+1.
Under certain conditions, the bq2024 also generates an 8-bit CRC value using the same polynomial function justshown and provides this value to the bus master to validate the transfer of command, address, and data bytesfrom the bus master to the bq2024. The bq2024 computes an 8-bit CRC for the command, address, and databytes received for the WRITE MEMORY and the WRITE STATUS commands and then outputs this value to thebus master to confirm proper transfer. Similarly, the bq2024 computes an 8-bit CRC for the command andaddress bytes received from the bus master for the READ MEMORY, READ STATUS, and READ DATA/GENERATE 8-BIT CRC commands to confirm that these bytes have been received correctly. The CRCgenerator on the bq2024 is also used to provide verification of error-free data transfer as each page of data fromthe 1536-bit EPROM is sent to the bus master during a READ DATA/GENERATE 8-BIT CRC command, and forthe eight bytes of information in the status memory field.
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UDG-02065
QRD Q RD Q RD Q RD Q RD Q RD Q RD Q RD
CLK DAT
++ +
bq2024
SLUS770 – MAY 2007
In each case where a CRC is used for data transfer validation, the bus master must calculate a CRC value usingthe polynomial function previously given and compare the calculated value to either the 8-bit CRC value storedin the 64-bit ROM portion of the bq2024 (for ROM reads) or the 8-bit CRC value computed within the bq2024.The comparison of CRC values and decision to continue with an operation are determined entirely by the busmaster. No circuitry on the bq2024 prevents a command sequence from proceeding if the CRC stored in orcalculated by the bq2024 does not match the value generated by the bus master. Proper use of the CRC canresult in a communication channel with a high level of integrity.
Figure 17. 8-Bit CRC Generator Circuit (X
8
+ X
5
+ X
4
+ 1)
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
BQ2024DBZR SOT-23 DBZ 3 3000 179.0 8.4 3.15 2.95 1.22 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Jul-2010
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ2024DBZR SOT-23 DBZ 3 3000 203.0 203.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Jul-2010
Pack Materials-Page 2
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