1
FEATURES
>400.0 Mbps (200 MHz) switching rates
+340mV nominal differential signaling
3.3 V power su pply
TTL compatible inputs
Cold sparing all pins
Ultra low power CMOS technology
1.5ns maximum, propagation delay
310ps maximum, differential skew
Radiation-hardened design; total dose irradiation testing to
MIL-STD-883 Method 1019
- Total-dose: 300 krad(Si) and 1Mrad(Si)
- Latchup immune (LET > 100 MeV-cm2/mg)
Packaging options:
- 16-lead flatpack (dual in-line)
Standard Microcircuit Drawing 5962-98651
- QML Q and V compliant part
INTRODUCTION
The UT54LVDS031LV Quad Driver is a quad CMOS
differential line driver designed for applications requiring ultra
low power dissipation and high data rates. The device is
designed to support data rates in excess of 400.0 Mbps (200
MHz) utilizing Low Voltage Differential Signaling (LVDS)
technology.
The UT54LVDS031LV accepts low voltage TTL input levels
and translates them to low voltage (340mV) differential output
signals. In addition, the driver supports a three-state function
that may be used to disable the output stage, disabling the load
current, and thus dropping the device to an ultra low idle power
state.
The UT54LVDS031LV and companion quad line receiver
UT54LVDS032LV provide new alternatives to hig h power
pseudo-ECL devices for high speed point-to-point interface
applications.
All pins have Cold Spare buffers. These buffers will be high
impedance when VDD is tied to VSS.
Standard Products
UT54LVDS031LV/E Low Voltage Quad Driver
Data Sheet
October, 2004
www.aeroflex.com/lvds
Figure 1. UT54LVDS031LV Quad Driver Block Di agram
D1
D2
D3
D4
DOUT1+
DOUT1-
DOUT2+
DOUT2-
DOUT3+
DOUT3-
DOUT4+
DOUT4-
DIN1
DIN2
DIN4
DIN3
EN
EN
2
TRUTH TABLE
PIN DESCRIPTION
APPLICATIONS INFORMATION
The UT54LVDS031LV driver’ s intended use is primarily in an
uncomplicated point-to-point configuration as is shown in
Figure 3. This configuration provides a clean signaling
environment for quick edge rates of the drivers. The receiver is
connected to the driver through a balanced media such as a
standard twisted pair cable, a parallel pair cable, or simply PCB
traces. Typically, the characteristic impedance of the media is
in the range of 100Ω. A termination resistor of 100Ω should be
selected to match the media and is located as close to the receiver
input pins as possible. The termination resistor con vert s the
current sourced by the driver into voltages that are detected by
the receiver. Other configurations are possible such as a multi-
receiver configuration, but the effects of a mid-stream
connector(s), cable stub(s), and other impedance
discontinuities, as well as ground shifting, noise margin limits,
and total termination loading must be taken into account.
The UT54LVDS031LV differential line driver is a balanced
current source design. A current mode driver , has a high output
impedance and supplies a constant current for a range of loads
(a voltage mode driver on the other han d supplies a constant
voltage for a range of loads). Current is switched through the
load in one direction to produce a logic state and in the other
direction to produce the other logic state. The current mode
requires (as discussed above) that a resistive termination be
employed to terminate the signal and to complete the loop as
shown in Figure 3. AC or unterminated configurations are not
allowed. The 3.4mA loop current will develop a differential
voltage of 340mV across the 100Ω termination resistor which
the receiver detects with a 240mV minimum dif fer ential noi se
margin neglecting resistive line losses (driven signal minus
receiver threshold (340mV - 100mV = 240mV)). The signal is
centered around +1.2V (Driver Offset, VOS) with respect to
ground as shown in Figure 4. Note: The steady-state voltage
(VSS) peak-to-peak swing is twice the differential voltage (VOD)
and is typically 680mV.
Enables Input Output
EN EN DIN DOUT+ DOUT-
L H X Z Z
All other combinations
of ENABLE inputs L L H
H H L
Pin No. Name Description
1, 7, 9, 15 DIN Driver input pin, TTL/CMOS
compatible
2, 6, 10, 14 DOUT+ Non-inverting driver output pin,
LVDS levels
3, 5, 1 1, 13 DOUT- Inverting driver output pin,
LVDS levels
4 EN Active high enable pin, OR-ed
with EN
12 EN Active low enable pin, OR-ed
with EN
16 VDD Power supply pin, +3.3V + 0.3V
8V
SS Ground pin
Figure 2. UT54LVDS031LV Pinout
UT54LVDS031LV
Driver
16
15
14
13
12
11
10
9
VDD
DIN4
DOUT4+
DOUT4-
EN
DOUT3-
DOUT3+
DIN3
1
DIN1
2
DOUT1+ 3
DOUT1-
4
EN 5
DOUT2- 6
DOUT2+ 7
DIN2
8
VSS
ENABLE
DATA
INPUT
1/4 UT54LVDS031LV
1/4 UT54LVDS032LV
+
-DATA
OUTPUT
Figure 3. Point-to-Point Application
RT 100Ω
3
The current mode driver provides substantial benefits over
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and life test.
3. Test per MIL-STD-883, Method 1012.
DIN
DOUT-
DOUT+
SINGLE-ENDED
DOUT+ - DOUT-
DIFFERENTIAL OUTPUT
V0D
3V
0V
VOH
VOS
VOL
+VOD
-VOD
0V
0V (DIFF.) VSS
Figure 4. Driver Output Levels
Note: The footprint of the UT54LVDS031LV is the same as the
industry standard Quad Differential (RS-422) Driver.
SYMBOL PARAMETER LIMITS
VDD DC supply volta ge -0.3 to 4.0V
VI/O Voltage on any pin during operation -0.3 to (VDD + 0.3V)
Voltage on any pin during cold spare -.3 to 4.0V
TSTG Storage temperature -65 to +150°C
PDMaximum power dissip at ion 1.25 W
TJMaximum junction temperature2+150°C
ΘJC Thermal resistance, junction-to-case310°C/W
IIDC input current ±10mA
4
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS
VDD Positive supply voltage 3.0 to 3.6V
TCCase temperature range -55 to +125°C
VIN DC input voltage 0V to VDD
5
DC ELECTRICAL CHARACTERISTICS1, 2
(VDD = 3.3V + 0.3V; -55°C < TC < +125°C)
Notes:
1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except differential voltages.
2. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates directio n on ly.
3. Guaranteed by characterization.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIH High-level input voltage (TTL) 2.0 VDD V
VIL Low-level input voltage (TTL) VSS 0.8 V
VOL Low-level output voltage RL = 100Ω0.925 V
VOH High-level output voltage RL = 100Ω1.650 V
IIN Input leakage current VIN = VDD or GND, VDD = 3.6V -10 +10 µA
ICS Cold Spare Leakage Current VIN=3.6V, VDD=VSS -20 +20 µΑ
VOD1Differential Output Voltage RL = 100Ω(figure 5) 250 400 mV
∆VOD1Change in Magnitude of VOD for
Complementary Output States RL = 100Ω(figure 5) 35 mV
VOS Offset Voltage RL = 100Ω, 1.125 1.450 V
∆VOS Change in Magnitude of VOS for
Complementary Output States RL = 100Ω(figure 5) 25 mV
VCL3Input clamp voltage ICL = +18mA -1.5 V
IOS2, 3 Output Short Circuit Current VIN = VDD, VOUT+ = 0V or
VIN = GND, VOUT- = 0V
9.0 mA
IOZ3Output Three-State Current EN = 0.8V and EN = 2.0 V,
VOUT = 0V or VDD, VDD = 3.6V -10 +10 µΑ
ICCL3Loaded supply current, drivers
enabled RL = 100Ω all channels
VIN = VDD or VSS(all inputs) 18.0 mA
ICCZ3Loaded supply current, drivers
disabled DIN = VDD or VSS
EN = VSS, EN = VDD 3.0 mA
Vos Voh Vol+
2
---------------------------
=
⎝⎠
⎛⎞
6
Figure 5. Driver VOD and VOS Test Circuit or Equivalent Circuit
D
DIN
DOUT-
DOUT+
40pF
Driver Enabled
Generator
50Ω
RL = 100ΩVOD
40pF
7
AC SWITCHING CHARACTERISTICS1, 2, 3
(VDD = +3.3V + 0.3V, TA = -55 °C to +125 °C)
Notes:
1. Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the same chip with an event on the inputs.
2. Generator waveform for all tests un less otherwise specified: f = 1 MHz, ZO = 50, tr < 1ns, and tf < 1ns.
3. CL includes probe and jig capacitance.
4. Guaranteed by characterization
5. Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
SYMBOL PARAMETER MIN MAX MIN MAX UNIT
UT54LVDS031LV UT54LVDS031LVE
tPHLD Differential Propagation Delay High to Low
(figures 6 and 7) 0.3 3.0 0.8 1.5 ns
tPLHD Differential Propagation Delay Low to High
(figures 6 and 7) 0.3 3.0 0.8 1.5 ns
tSKD Differential Skew (tPHLD - tPLHD) (figures 6 and 7) 0 400 0 310 ps
tSK1 Channel-to-Channel Skew1 (figures 6 and 7) 0 500 0 280 ps
tSK2 Chip-to-Chip Skew5 (figure 6 and 7) 2.7 700 ps
tTLH4Rise Time (figures 6 and 7) 1.5 0.6 ns
tTHL4Fall Time (figures 6 and 7) 1.5 0.6 ns
tPHZ Disable Ti me High to Z (figures 8 and 9) 5.0 2.8 ns
tPLZ Disable Time Low to Z (figures 8 and 9) 5.0 2.8 ns
tPZH Enable Time Z to High (figures 8 and 9) 7.0 2.5 ns
tPZL Enable Time Z to Low (figures 8 and 9) 7.0 2.5 ns
8
D
DIN
DOUT-
DOUT+
Driver Enabled
Generator
50Ω
RL = 100Ω
Figure 6. Driver Propagation Delay and Transition Time Test Circuit or Equivalant Circuit
40pF
40pF
DIN
DOUT-
DOUT+
VDIFF
tPHLD
VDD
0V
VOH
VOL
0V
VDIFF = DOUT+ - DOUT-
0V (Differential)
1.5V
tTHL
20%
80%
0V
20%
80%
tTLH
tPLHD
1.5V
Figure 7. Driver Propagation Delay and Transition Time Waveforms
9
D
VDD
VSS
DIN
EN
Generator
50ΩEN
RL=100Ω
DOUT+
DOUT-
Figure 8. Driver Three-State Delay Test Circuit or Equivalant Circuit
40pF
40pF
EN when EN = VDD
EN when EN = VSS
or
DOUT+ when DIN =VDD
DOUT- when DIN = VSS
DOUT+ when DIN = VSS
DOUT- when DIN = VDD tPLZ tPZL
50% 50%
VOL
VOS
VOS
VOH
0V
VDD
0V
VDD
1.5V
1.5V
1.5V
1.5V
50%
tPZH
tPHZ
Figure 9. Driver Three-State Delay Waveform
50%
10
Notes:
1. All exposed metalized areas are gold plated over electrop lated nickel per MIL-PRF-385 35.
2. The lid is electrically connected to VSS.
3. Lead finishes are in ac cor da nce to MIL-P RF -38535.
4. Package dimensions and sym bols are similar to MIL-STD- 1835 variation F-5A.
5. Lead position and coplanarity are not measured.
6. ID mark symbol is vendor option.
7. With solder, increase maximum by 0.003.
Figure 10. 16-pin Ceramic Flatpack
PACKAGING
11
ORDERING INFORMATION
UT54LVDS031LV/E QUAD DRIVER:
UT54 *********** - * * * * *
Device Type:
LVDS031LV LVDS Driver
LVDS031LVE LVDS Driver Enhanced AC’s
Access T i me:
Not applicable
Package Type:
(U) = 16-lead Flatpack (dual-in-line)
Screening:
(C) = Military Temperature Range flow
(P) = Prototype flow
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per Aeroflex Manufacturing Flows Document. T ested at 25°C only . Lead finish is GOLD ONL Y. Radiation neither
tested nor guaranteed.
4. Military Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested at -55°C, room temp, and
125°C. Radiation neither tested nor guaranteed.
12
UT54LVDS031LV/E QUAD DRIVER: SMD
5962 - ** *
Federal Stoc k Class Designator: No Options
Total Dose
(R) = 1E5 rad(Si)
(F) = 3E5 rad(Si)
(G) = 5E5 rad(Si)
(H) = 1E6 rad(Si)
Drawing Number: 5962-98651
Device Type
02 = LVDS Driver, 300k, 500k and 1M Rad(Si)
03 = LVDS Driver, 100k Rad(Si)
04 = LVDS Driver with enhanced ACs, 300K, 500K and 1Mrad(Si)
05 = LVDS Driver with enhanced ACs, 100Krad(Si)
Class Designator:
(Q) = QML Class Q
(V) = QML Class V
Case Outline:
(Y) = 16 lead Flatpack (dual-in-line)
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)
98651 **
Notes:
1.Lead finish (A,C, or X) must be specifi ed.
2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3.Total dose radiation must be specified when ordering. QML Q and QML V not available without r adiation hardening.
13
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