A3949SLB-T - Allegro Microsystems

Description

Designed for PWM (pulse width modulated) control of DC

motors, the A3949 is capable of peak output currents to ±2.8 A

and operating voltages to 36 V.

PHASE and ENABLE input terminals are provided for use

in controlling the speed and direction of a DC motor with

externally applied PWM control signals. Internal synchronous

rectification control circuitry is provided to reduce power

dissipation during PWM operation.

Internal circuit protection includes thermal shutdown with

hysteresis, undervoltage monitoring of VBB and VCP , and

crossover current protection.

The A3949 is supplied in a power package, a 16-pin plastic SOIC

with a copper batwing tab (part number suffix LB). The packages

are lead (Pb) free, with 100% matte tin leadframes.

29319.47i

Features and Benefits

▪ Single supply operation

▪ Very small outline package

▪ Low RDS(ON) outputs

▪ Sleep function

▪ Internal UVLO

▪ Crossover current protection

▪ Thermal shutdown protection

DMOS Full-Bridge Motor Driver

Functional Block Diagram

A3949

VREG CP2

Load

Supply

Low Side

Gate Supply

CP1

Charge

Pump

0.1 μF

DMOS Full Bridge

OSC

.22 μF

25 V

0.1 μF100 μF

Control

Logic

MODE

PHASE

ENABLE

SLEEP

VCP

VBB

OUTA

OUTB

SENSE

GND

Packages:

Not to scale

Package LB, 16-pin SOIC

with internally fused pins

DMOS Full-Bridge Motor Driver

A3949

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Absolute Maximum Ratings

Characteristic Symbol Notes Rating Units

Load Supply Voltage VBB

36 V

Peak < 2 μs38V

Logic Input Voltage VIN –0.3 to 7 V

Sense Voltage VSENSE 0.5 V

Output Current, Repetitive IOUT

Output current rating may be limited by duty cycle,

ambient temperature, and heat sinking. Under any

set of conditions, DO NOT exceed the speciﬁ ed

IOUT or TJ.

±2.8 A

Operating Ambient Temperature TARange S –20 to 85 ºC

Maximum Junction Temperature TJ(max) 150 ºC

Storage Temperature Tstg –55 to 150 ºC

Selection Guide

Part Number Package Packing

A3949SLBTR-T 16-pin, SOIC 1000 per reel

Package Thermal Characteristics*

Characteristic Symbol Note Rating Units

Package Thermal Resistance RθJA Measured on 2-layer PCB with 2 in.

2 2-oz. copper each side 52 °C/W

*Additional information is available on the Allegro website.

DMOS Full-Bridge Motor Driver

A3949

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ELECTRICAL CHARACTERISTICS at TA = 25°C, VBB = 8 V to 36 V (unless otherwise noted)

Characteristics Symbol Test Conditions Min. Typ. Max. Units

Output-On Resistance RDSON

Source driver, IOUT = –2.8 A, TJ= 25°C – .4 .48 Ω

Source driver, IOUT = –2.8 A, TJ= 125°C – .68 – Ω

Sink driver, IOUT = 2.8 A, TJ= 25°C – .3 .43 Ω

Sink driver, IOUT = –2.8 A, TJ= 125°C – .576 – Ω

Body Diode Forward Voltage VF

Source diode, IF = –2.8 A – 1.1 1.3 V

Sink diode, IF = 2.8 A – 1 1.3 V

Motor Supply Current IBB

fPWM < 50 kHz – 6 8.5 mA

Charge pump turned on; outputs disabled – 3 4.5 mA

Sleep mode – – 10 μA

Logic Input Voltage

PHASE, ENABLE, MODE

VIN(1) 2.0 – – V

VIN(0) – – 0.8 V

Logic Input Voltage

SLEEP

VIN(1) 2.7 – – V

VIN(0) – – 0.8 V

Logic Input Current

PHASE, MODE pins

IIN(1) VIN = 2.0 V – < 1.0 20 μA

IIN(0) VIN = 0.8 V – < –2.0 –20 μA

Logic Input Current

ENABLE pin

IIN(1) VIN = 2.0 V – 40 100 μA

IIN(0) VIN = 0.8 V – 16 40 μA

Logic Input Current

SLEEP pin

IIN(1) VIN = 2.7 V – 27 50 μA

IIN(0) VIN = 0.8 V – < 1 10 μA

Propagation Delay Times tpd

From PWM change to source or sink turn on – 600 – ns

From PWM change to source or sink turn off – 100 – ns

Crossover Delay tCOD – 500 – ns

Protection Circuitry

UVLO Enable Threshold VBB rising – 6 – V

UVLO Hysteresis – 250 – mV

Thermal Shutdown Temp. TJ– 170 – °C

Thermal Shutdown Hysteresis ΔTJ–15– °C

DMOS Full-Bridge Motor Driver

A3949

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

PWM Control Timing Diagram

ENABLE

PHASE

MODE

OUTA

OUTB

IOUT

0 V

SLEEP

A Charge pump and VR EG pow er- up delay (approximately 200 us)

0 A

2 3 4 56 7 98

VBB

A 1

VBB VBB

OUTBOUTA

OUTA OUTB

DMOS Full-Bridge Motor Driver

A3949

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

VREG. This supply voltage is used to operate the sink-

side DMOS outputs. VREG is internally monitored and in

the case of a fault condition, the outputs of the device are

disabled. The VREG pin should be decoupled with a 0.22 F

capacitor to ground.

Charge Pump. The charge pump is used to generate a

supply above VBB to drive the source-side DMOS gates. A

0.1 uF ceramic monolithic capacitor should be connected

between CP1 and CP2 for pumping purposes. A 0.1 uF

ceramic monolithic capacitor should be connected between

VCP and VBB to act as a reservoir to run the high side

DMOS devices. The VCP voltage is internally monitored,

and in the case of a fault condition, the outputs of the device

are disabled.

Shutdown. In the event of a fault due to excessive junction

temperature, or low voltage on VCP or VREG, the outputs of

the device are disabled until the fault condition is removed.

At power-up, the UVLO circuit disables the drivers.

Sleep Mode. Control input SLEEP is used to minimize

power consumption when the A3949 is not in use. This

disables much of the internal circuitry, including the low-side

gate supply and the charge pump. A logic low on this pin

puts the device into Sleep mode. A logic high allows normal

operation. After coming out of Sleep mode, the user should

wait 1 ms before applying PWM signals, to allow the charge

pump to stabilize.

Braking. The braking function is implemented by driv-

ing the device in slow decay mode via the MODE pin, and

applying an enable chop command. Because it is possible to

drive current in both directions through the DMOS switches,

this conﬁ guration effectively shorts out the motor-generated

BEMF, as long as the enable chop mode is asserted on the

ENABLE pin. The maximum current can be approximated

by VBEMF / RL. Care should be taken to insure that the maxi-

mum ratings of the device are not exceeded in worse case

braking situations of high speed and high inertial loads.

Functional Description

PHASE ENABLE MODE SLEEP OUTA OUTB Function

1 1 X 1 H L Forward

0 1 X 1 L H Reverse

X 0 1 1 L L Brake (slow decay)

1001LH Fast decay SR*

0001HL Fast decay SR*

X X X 0 Hi-Z Hi-Z Sleep mode

Control Logic Table

* To prevent reversal of current during fast decay SR (synchronous rectiﬁ cation), the outputs

go to the high impedance state as the current approaches zero.

DMOS Full-Bridge Motor Driver

A3949

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Name Description Number

N/C Not used 1

MODE Logic input 2

PHASE Logic input for direction control 3

GND Ground 4*

SLEEP Logic input 5

ENABLE Logic input 6

OUTA Output A for full bridge 7

SENSE Power return 8

VBB Load supply voltage 9

OUTB Output B for full bridge 10

CP1 Charge pump capacitor 11

CP2 Charge pump capacitor 12

GND Ground 13*

VCP Reservoir capacitor 14

VREG Low side gate supply decoupler 15

N/C Not used 16

*These pins are internally connected.

LB Package

N/C

MODE

PHASE

GND

SLEEP

ENABLE

OUTA

SENSE

N/C

VREG

VCP

GND

CP2

CP1

OUTB

VBB

DMOS Full-Bridge Motor Driver

A3949

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

LB 16-Pin SOICW

4º

10.30

0.27

0.84

0.25

2.65 MAX

0.20

9.50

0.65

2.25

1.27

0.41

7.50

SEATING

PLANE

C0.10

16X

GAUGE PLANE

SEATING PLANE All dimensions nominal, not for tooling use

Dimensions in millimeters

(reference JEDEC MS-013 AA)

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

Pins 4 and 13 fused internally

ATerminal #1 mark area

BReference pad layout (reference IPC SOIC127P1030X265-16M)

All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary

to meet application process requirements and PCB layout tolerances

BPCB Layout Reference View

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-

mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;

nor for any in fringe ment of patents or other rights of third parties which may result from its use.

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