TC74ACT161,163P/F
2014-03-01
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TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74ACT161P, TC74ACT161F
TC74ACT163P, TC74ACT163F
Synchronous Presettable 4-Bit Binary Counter
TC74ACT161P/F/FN Asynchronous Clear
TC74ACT163P/F/FN Synchronous Clear
The TC74ACT161 and T163 are advanced high speed CMOS
SYNCHRONOUS PRESETTABLE 4 BIT BINARY COUNTERs
fabricated with silicon gate and double-layer metal wiring
C2MOS technology.
They achieve the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
These devices may be used as a level converter for interfacing
TTL or NMOS to High Speed CMOS. The inputs are compatible
with TTL, NMOS and CMOS output voltage levels.
The CK input is active on the rising edge. Both LOAD and
CLR inputs are active on low logic level.
Presetting of these IC’s is synchronous to the rising edge of CK.
The clear function of the TC74ACT163 is synchronous to CK,
while the TC74ACT161 are cleared asynchronously.
Two enable inputs (ENP and ENT) and CARRY OUTPUT are
provided to enable easy cascading of counters, which facilitates
easy implementation of n-bit counters without using external
gates.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
High speed: fmax = 110 MHz (typ.) at VCC = 5 V
Low power dissipation: ICC = 8 μA (max) at Ta = 25°C
Compatible with TTL outputs: VIL = 0.8 V (max)
V
IH = 2.0 V (min)
Symmetrical output impedance: |IOH| = IOL = 24 mA (min)
Capability of driving 50
transmission lines.
Balanced propagation delays: tpLH
tpHL
Pin and function compatible with 74F161/163
TC74ACT161P, TC74ACT163P
TC74ACT161F, TC74ACT163F
Weight
DIP16-P-300-2.54A : 1.00 g (typ.)
SOP16-P-300-1.27A : 0.18 g (typ.)
Start of commercial production
1989-11
TC74ACT161,163P/F
2014-03-01
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Pin Assignment
IEC Logic Symbol
TC74ACT161 TC74ACT163
Truth Table
Inputs Outputs
CLR
(161)
CLR
(163) LOAD ENP ENT CK
(161)
CK
(163) QA QB QC QD
Function
L L X X X X L L L L Reset to “0”
H H L X X A B C D Preset Data
H H H X L No Change No Count
H H H L X No Change No Count
H H H H H Count Up Count
H X X X X No Change No Count
X: Don’t care
A, B, C, D: Logic level of data inputs
Carry: Carry = ENTQAQBQCQD
TC74ACT161,163P/F
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Timing Chart
TC74ACT161,163P/F
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System Diagram (Note)
Note: Truth table of internal F/F
TC74ACT161 TC74ACT163
D CK R Q Q D CK R Q Q
X X H L H X H L H
L L L H L L L H
H L H L X L H L
X L No Change X L No Change
X: Don’t care
(Note)
(Note)
(Note)
(Note)
TC74ACT161,163P/F
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Absolute Maximum Ratings (Note 1)
Characteristics Symbol Rating Unit
Supply voltage range VCC 0.5 to 7.0 V
DC input voltage VIN 0.5 to VCC + 0.5 V
DC output voltage VOUT 0.5 to VCC + 0.5 V
Input diode current IIK ±20 mA
Output diode current IOK ±50 mA
DC output current IOUT ±50 mA
DC VCC/ground current ICC ±125 mA
Power dissipation PD 500 (DIP) (Note 2)/180 (SOP) mW
Storage temperature Tstg 65 to 150 °C
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: 500 mW in the range of Ta = 40 to 65°C. From Ta = 65 to 85°C a derating factor of 10 mW/°C should be
applied up to300 mW.
Operating Ranges (Note)
Characteristics Symbol Rating Unit
Supply voltage VCC 4.5 to 5.5 V
Input voltage VIN 0 to VCC V
Output voltage VOUT 0 to VCC V
Operating temperature Topr 40 to 85 °C
Input rise and fall time dt/dV 0 to 10 ns/V
Note: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
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Electrical Characteristics
DC Characteristics
Test Condition Ta = 25°C Ta =
40 to 85°C
Characteristics Symbol
VCC (V) Min Typ. Max Min Max
Unit
High-level input
voltage VIH 4.5 to 5.5 2.0 2.0 V
Low-level input
voltage VIL 4.5 to 5.5 0.8 0.8 V
High-level output
voltage VOH
VIN
= VIH or
VIL
IOH = 50 μA
IOH = 24 mA
IOH = 75 mA (Note)
4.5
4.5
5.5
4.4
3.94
4.5
4.4
3.80
3.85
V
Low-level output
voltage VOL
VIN
= VIH or
VIL
IOL = 50 μA
IOL = 24 mA
IOL = 75 mA (Note)
4.5
4.5
5.5
0.0
0.1
0.36
0.1
0.44
1.65
V
Input leakage
current IIN V
IN = VCC or GND 5.5 ±0.1 ±1.0 μA
ICC V
IN = VCC or GND 5.5 8.0 80.0 μA
Quiescent supply
current IC Per input: VIN = 3.4 V
Other input: VCC or GND 5.5 1.35 1.5 mA
Note: This spec indicates the capability of driving 50 transmission lines.
One output should be tested at a time for a 10 ms maximum duration.
Timing Requirements (input: tr = tf = 3 ns)
Test Condition Ta =
25°C
Ta =
40 to
85°C
Characteristics Symbol
V
CC (V) Limit Limit
Unit
Minimum pulse width
(CK)
tW (L)
tW (H)
Figure 1 5.0 ± 0.5 5.0 5.0 ns
Minimum pulse width
(CLR ) (Note1)
tW (L) Figure 4 5.0 ± 0.5 5.0 5.0 ns
Minimum pulse width
(LOAD , ENP, ENT) ts Figure 2, Figure 3 5.0 ± 0.5 6.0 6.0 ns
Minimum set-up time
(A, B, C, D) ts Figure 2 5.0 ± 0.5 4.0 4.0 ns
Minimum set-up time
(CLR ) (Note 2)
ts Figure 5 5.0 ± 0.5 3.0 3.0 ns
Minimum hold time
(LOAD , ENP, ENT) th Figure 2, Figure 3 5.0 ± 0.5 1.0 1.0 ns
Minimum hold time
(A, B, C, D) th Figure 2 5.0 ± 0.5 2.0 2.0 ns
Minimum hold time
(CLR ) (Note 2)
th Figure 5 5.0 ± 0.5 2.0 2.0 ns
Minimum removal time
(CLR ) (Note 1)
trem Figure 4 5.0 ± 0.5 1.0 1.0 ns
Note 1: For TC74ACT161 only
Note 2: For TC74ACT163 only
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AC Characteristics (CL = 50 pF, RL = 500 , input: tr = tf = 3 ns)
Test Condition Ta = 25°C Ta =
40 to 85°C
Characteristics Symbol
VCC (V) Min Typ. Max Min Max
Unit
Propagation delay
time
(CK-Q)
tpLH
tpHL
Figure 1 5.0 ± 0.5 7.2 10.5 1.0 12.0 ns
Propagation delay
time
(CK-CARRY, count
mode)
tpLH
tpHL
Figure 1 5.0 ± 0.5 8.5 13.0 1.0 15.0 ns
Propagation delay
time
(CK-CARRY, preset
mode)
tpLH
tpHL
Figure 2 5.0 ± 0.5 9.7 15.0 1.0 17.0 ns
Propagation delay
time
(ENT-CARRY)
tpLH
tpHL
Figure 6 5.0 ± 0.5 6.6 10.0 1.0 11.5 ns
Propagation delay
time (Note 2)
(CLR -Q)
tpHL Figure 4 5.0 ± 0.5 6.3 10.0 1.0 11.5 ns
Propagation delay
time (Note 2)
(CLR -CARRY)
tpHL Figure 4 5.0 ± 0.5 7.7 12.3 1.0 14.0 ns
Maximum clock
frequency fmax 5.0 ± 0.5 70 100 60 MHz
Input capacitance CIN 5 10 10 pF
Power dissipation
capacitance
CPD
(Note 1)
32 pF
Note 1: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPDVCCfIN + ICC
When the outputs drive a capacitive load, total current consumption is the sum of CPD, and ΔICC which is
obtained from the following formula:
)
16
C
16
C
8
C
4
C
2
C
(VfI CO
QDQCQBQA
CCCKCC ++++=Δ
CQA~CQD and CCO are the capacitances at QA~QD and CARRY OUT, respectively.
fCK is the input frequency of the CK.
Note 2: for TC74ACT161 only
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Switching Characteristics Test Waveform
Count Mode Clear Mode (TC74ACT161)
Preset Mode Clear Mode (TC74ACT163)
Count Enable Mode Cascade Mode (fix maximum count)
Figure 2 Figure 5
Figure 1 Figure 4
Figure 3 Figure 6
TC74ACT161,163P/F
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Typical Application
Parallel Carry N-Bit Counter
TC74ACT161,163P/F
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Package Dimensions
Weight: 1.00 g (typ.)
TC74ACT161,163P/F
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Package Dimensions
Weight: 0.18 g (typ.)
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2014-03-01
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