(R) DEVICE SPECIFICATION 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH FEATURES * * * * * * * * GENERAL DESCRIPTION 32 x 32 differential crosspoint switch Full broadcast switching capability Differential 10K PECL data path Configurable differential output driver enables Up to 1.5 Gbit/s NRZ data rate TTL configuration controls Reconfigurable without disturbing operation 196-pin LDCC package The S2025 is a very high-speed 32 x 32 differential crosspoint switch with full broadcast capability. Any of its 32 differential PECL input signal pairs can be connected to any or all of its 32 differential PECL output signal pairs. In addition, the S2025 includes configurable differential output driver enables that allow it to be expanded to larger differential crosspoint switch structures. The differential 10K PECL logic data path makes the part ideal for high-speed applications. The differential nature of the data path is retained throughout the crosspoint structure, to minimize data distortion and to handle NRZ data rates up to 1.5 gigabits per second. TTL configuration controls simplify interfacing to slower speed circuitry. Once a new configuration has been entered into the configuration register file, the S2025 can be completely reconfigured in only 6 ns without disturbing switch operations. APPLICATIONS * * * * * * S2025 S2025 Internet switches Digital video Digital demultiplexing Microwave or fiber-optic data distribution High-speed automatic test equipment Datacom or telecom switching Figure 1. Functional Block Diagram DIN00P DIN00N PECL Diff. Input Buffers DIN31P DIN31N 64 32 x 32 Differential Crosspoint 160 CONFIGN 64 DOUT00P DOUT00N PECL Diff. Output Buffers Output Enables DOUT31P DOUT31N 32 Active Configuration Latch OADDR RESETN OADDRO-4 LOADN 5:32 Decode 32 SELECT 5 OA Reg 32 x 6 Configuration Register File EN IADDRO-5 6 IA Register June 24, 1999 / Revision B DATA 192 OACLK IADDR IACLK 1 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025 DATA TRANSFER For each configured connection between a differential input pair and an enabled output pair, any data appearing at the input pair will be passed immediately through to the output pair. the configuration register selected, the desired input selection is provided on the bits IADDR0-4 of the IA register. Whether or not the output pair is to be enabled is provided on the bit IADDR5 (1= enable, 0 = disable) of the same register. The bits IADDR0-5 are set using the IADDR and IACLK inputs. The IACLK input, with 100 MHz maximum frequency, can load the IA shift register through the IADDR input, with the IADDR5 entering first, followed by the IADDR4 (MSB), and so on. The IADDR0-5 information will be stored into the selected configuration register by the LOADN strobe. When the differential switch is to be reconfigured, the S2025 minimizes the time required through the use of an active configuration latch. While the switch is operational, and prior to the time at which it must be reconfigured, a new configuration can be loaded into the output pair configuration registers. Once the 32 output pair configuration registers contain the desired connection and output pair driver enable information, the contents of the registers are transferred in parallel to the active configuration latch by the CONFIGN strobe. This allows multiple connections to be simultaneously changed. The configuration latch can be made transparent by tying the CONFIGN input to a logic 0. When this is done, changes strobed into the output pair configuration registers by the LOADN input pair will be passed immediately to the switch. RECONFIGURATION The S2025 can be selectively reconfigured one output pair at a time, or any number of output pairs can be reconfigured simultaneously. Configuration data is stored in 32 registers, one register for each output pair. As shown in Figure 1, the configuration data is passed in parallel from all 32 registers to a latch which holds the active switch configuration. This two-stage arrangement allows one or more output pairs to be reconfigured simultaneously. Each configuration register in the configuration Register File (CRF) holds 6 bits. Five bits are used to select which input pair will be connected to the output pair and one bit is used to enable or disable the output pair driver. To connect an output pair to a given input pair, the output pair to be reconfigured is selected using bits OADDR0-4 of the OA register. These bits are set using the OADDR and OACLK inputs. The OACLK input, with 100 MHz maximum frequency, can load the OA shift register through the OADDR input, with the OADDR4 (MSB) entering first, followed by the OADDR3, and so on. With Figure 2. Data Transfer Waveforms DIMPW DINO-31 P/N A B C D E tDIDO A DOUTO-31 P/N B C D E tCFDO CONFIGN tLDDO LOADN 2 June 24, 1999 / Revision B 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025 Figure 3. Reconfiguration Waveforms 1 2 3 4 5 6 1 2 IACLK IADDR0-5 LDMPW LOADN tSUIAC tHIAC CFMPW CONFIGN tSULC a. Input Address Register 1 2 3 4 5 1 2 OACLK OADDR0-4 LDMPW LOADN tSUOAC tHOAC CFMPW CONFIGN tSULC b. Output Address Register IACLK OACLK IADDR OADDR tSUIAD tHIAD tSUOAD tHOAD c. Clock Timing June 24, 1999 / Revision B 3 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025 Reset Behavior When the RESETN input pair is asserted, the S2025 assumes a configuration where all the differential output drivers are disabled. Individual output drivers then remain disabled until they are explicitly reconfigured to be enabled. Table 1. Data Transfer Timing1 Symbol tDIDO Description Min. Max. Units Propagation delay from DIN0-31 P/N to DOUT0-31 P/N 3 ns tCFDO Propagation delay from falling edge of CONFIGN to DOUT0-31 P/N valid 6 ns tLDDO Propagation delay from falling edge of LOADN to DOUT0-31 P/N valid (When CONFIGN is held low) 8 ns DIMPW Pulse width of DIN0-31 P/N 0.650 ns FMAX Data rate 1500 Mbit/s Table 2. Reconfiguration Timing 2 Symbol t Max. Units Setup time of IADDR before rising edge of IACLK 2 ns t HIAD Hold time of IADDR after rising edge of IACLK 1 ns t Setup time of IACLK before falling edge of LOADN 1 ns Hold time of IACLK after rising edge of LOADN 2 ns SUOAD Setup time of OADDR before rising edge of OACLK 2 ns t HOAD Hold time of OADDR after rising edge of OACLK 1 ns t Setup time of OACLK before falling edge of LOADN 2 ns Hold time of OACLK after rising edge of LOADN 2 ns Setup time of LOADN to CONFIGN so that the falling edge of CONFIGN will start reconfiguration 1 ns Pulse width low of LOADN 4.5 ns Pulse width low of CONFIGN 4.5 ns IACLK, OACLK maximum frequency 100 MHz t HIAC t SUOAC t HOAC t SULC LD MPW CF F 4 Min. SUIAD SUIAC 1. 2. Description MPW MAX All timing measured from the VCC -1.3V point on the signals. All timing measured from the 1.5V point on the signals. June 24, 1999 / Revision B 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025 Table 3. S2025 Pin Assignment and Descriptions Pin Name Level I/O Pin # DIN31P DIN31N DIN30P DIN30N DIN29P DIN29N DIN28P DIN28N DIN27P DIN27N DIN26P DIN26N DIN25P DIN25N DIN24P DIN24N DIN23P DIN23N DIN22P DIN22N DIN21P DIN21N DIN20P DIN20N DIN19P DIN19N DIN18P DIN18N DIN17P DIN17N DIN16P DIN16N DIN15P DIN15N DIN14P DIN14N DIN13P DIN13N DIN12P DIN12N DIN11P DIN11N DIN10P DIN10N DIN9P DIN9N DIN8P DIN8N DIN7P DIN7N DIN6P DIN6N Diff. PECL Input Pairs 99 100 45 48 101 103 43 44 104 107 42 41 105 110 39 37 106 111 38 33 109 115 31 36 116 112 29 32 118 117 23 30 121 119 27 21 127 125 20 19 129 128 18 15 134 130 13 14 137 131 12 11 June 24, 1999 / Revision B Description Input data. Differential. Can be used as single-ended input pairs with VBB tied to one side of each differential pair. 5 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025 Table 3. S2025 Pin Assignment and Descriptions (continued) Pin Name Level I/O Pin # DIN5P DIN5N DIN4P DIN4N DIN3P DIN3N DIN2P DIN2N DIN1P DIN1N DIN0P DIN0N Diff. PECL I 14 0 141 9 8 143 142 6 7 146 145 3 5 Differential PECL input data. Differential inputs can be used as single-ended inputs with VBB tied to one side of each differential input pair. OADDR TTL I 160 Serial data input to the Output Address Shift Register OACLK TTL I 181 Output Address Shift Register is loaded on the rising edge of OACLK. IADDR TTL I 86 Serial data input to the Input Address Shift Register. IADDR5 is the output buffer enable bit (1 = enable, 0 = disable). IACLK TTL I 65 Input Address Shift Register is loaded on the rising edge of IACLK. LOADN TTL I 135 Load strobe, active Low. When low, stores the configuration data in IA register into the configuration register file. CONFIGN TTL I 13 9 Configuration strobe, active Low. When low, parallel loads the contents of the configuration register file into the active configuration latch. RESETN TTL I 136 Reset. Active Low. Resets all the output enable bits in the configuration register file and in the active configuration latch. Diff. PECL O 96 94 92 93 89 91 87 90 85 83 82 80 Output data. Differential. DOUT31P DOUT31N DOUT30P DOUT30N DOUT29P DOUT29N DOUT28P DOUT28N DOUT27P DOUT27N DOUT26P DOUT26N 6 Description June 24, 1999 / Revision B 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025 Table 3. S2025 Pin Assignment and Descriptions (continued) Pin Name Level I/O Pin # DOUT25P DOUT25N DOUT24P DOUT24N DOUT23P DOUT23N DOUT22P DOUT22N DOUT21P DOUT21N DOUT20P DOUT20N DOUT19P DOUT19N DOUT18P DOUT18N DOUT17P DOUT17N DOUT16P DOUT16N DOUT15P DOUT15N DOUT14P DOUT14N DOUT13P DOUT13N DOUT12P DOUT12N DOUT11P DOUT11N DOUT10P DOUT10N DOUT9P DOUT9N DOUT8P DOUT8N DOUT7P DOUT7N DOUT6P DOUT6N DOUT5P DOUT5N DOUT4P DOUT4N DOUT3P DOUT3N DOUT2P DOUT2N DOUT1P DOUT1N DOUT0P DOUT0N Diff. PECL O 79 78 70 77 68 72 66 69 64 62 59 61 58 57 55 56 52 54 47 49 1 2 194 192 190 191 188 189 185 187 183 184 179 180 176 177 169 175 174 167 166 164 163 161 157 159 156 155 154 152 153 150 June 24, 1999 / Revision B Description Output data. Differential. 7 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025 Table 3. S2025 Pin Assignment and Descriptions (continued) Pin Name 8 Level I/O Pin # Description VCC +5V - 4, 10, 16, 22, 28, 34, 40, 46, 51, 53, 60, 67, 71, 74, 81, 88, 95, 97, 102, 108, 114, 120, 126, 132, 138, 144, 149, 151, 158, 165, 168, 172, 178, 186, 193, 195 Core and ECL I/O Power Supplies TTLGND GND - 50, 98, 148, 196 TTL Ground ECLGND GND - 17, 24, 25, 26, 35, 63, 73, 75, 76, 84, 113, 122, 123, 124, 133, 162, 170, 171, 173, 182 Core Ground June 24, 1999 / Revision B 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 TTLGND VCC DOUT0N VCC DOUT1N DOUT0P DOUT1P DOUT2N DOUT2P DOUT3P VCC DOUT3N OADDR DOUT4N ECLGND DOUT4P DOUT5N VCC DOUT5P DOUT6N VCC DOUT7P ECLGND ECLGND VCC ECLGND DOUT6P DOUT7N DOUT8P DOUT8N VCC DOUT9P DOUT9N OACLK ECLGND DOUT10P DOUT10N DOUT11P VCC DOUT11N DOUT12P DOUT12N DOUT13P DOUT13N DOUT14N VCC DOUT14P VCC TTLGND Figure 4. S2025 Pinout 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 S2025 Pinout Top View 196-pin LDCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 DOUT15P DOUT15N DIN0P VCC DIN0N DIN2P DIN2N DIN4N DIN4P VCC DIN6N DIN6P DIN8P DIN8N DIN10N VCC ECLGND DIN10P DIN12N DIN12P DIN14N VCC DIN16P ECLGND ECLGND ECLGND DIN14P VCC DIN18P DIN16N DIN20P DIN18N DIN22N VCC ECLGND DIN20N DIN24N DIN22P DIN24P VCC DIN26N DIN26P DIN28P DIN28N DIN30P VCC DOUT16P DIN30N DOUT16N TTLGND VCC DOUT31P VCC DOUT31N DOUT30N DOUT30P DOUT29N DOUT28N DOUT29P VCC DOUT28P IADDR DOUT27P ECLGND DOUT27N DOUT26P VCC DOUT26N DOUT25P DOUT25N DOUT24N ECLGND ECLGND VCC ECLGND DOUT23N VCC DOUT24P DOUT22N DOUT23P VCC DOUT22P IACLK DOUT21P ECLGND DOUT21N DOUT20N VCC DOUT20P DOUT19P DOUT19N DOUT18N DOUT18P DOUT17N VCC DOUT17P VCC TTLGND 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 THDIODE DIN1P DIN1N VCC DIN3P DIN3N DIN5N DIN5P CONFIGN VCC DIN7P RESETN LOADN DIN9P ECLGND VCC DIN7N DIN9N DIN11P DIN11N DIN13P VCC DIN13N ECLGND ECLGND ECLGND DIN15P VCC DIN15N DIN17P DIN17N DIN19P DIN21N VCC ECLGND DIN19N DIN23N DIN25N DIN21P VCC DIN27N DIN23P DIN25P DIN27P DIN29N VCC DIN29P DIN31N DIN31P June 24, 1999 / Revision B 9 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025 Figure 5. 196-Pin LDCC Package 148 TOP 196 147 1 .105 .010 1.350 .010 TOP VIEW 99 49 50 98 .290 min .045 .005 .008 .002 .025 .002 .055 .010 COPLANAR TO .004 1.550 .015 Non-conductive Tie-bar* All dimensions nominal in inches. * Trim non-conductive tie-bar prior to board attachment Thermal Management Symbol Description jc Thermal resistance from junction to case ja Thermal resistance from junction to ambient ja Thermal resistance from junction to ambient with heatsink Airflow Value Units 2.3 o Still air 25.6 o 800 LFPM 3.53 o C/W C/W C/W Note: S2025 requires an AMCC heatsink 45-17 with an airflow of 800 LFPM for operation over commercial temperatures. 10 June 24, 1999 / Revision B 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025 Figure 6. AMCC Heat Sink 45-17 June 24, 1999 / Revision B 11 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025 THERMAL MANAGEMENT GUIDELINES Because of the relatively high power dissipation of the S2025 device, thermal management is a key design consideration. The junction temperature (Tj) of the device must not exceed 150C for it to operate within its specifications. There are a number of ways to implement thermal management, depending upon the system requirements and applications. AMCC is offering the following two methods as guidelines to ensure proper operation of the S2025. 1. Convection--Heat Sink with Forced Air Flow AMCC offers the standard heat sink 45-17 for impingement cooling (air flow forced directly to the face of the heat sink). This method is similar to the fan/heat-sink devices used on new, high-performance, and high-power microprocessors. The dimensions of the heat sink are given in Figure 6. Considering the junction-to-case, and case-toambient thermal resistivities, one can estimate the amount of required air flow and the maximum ambient temperature (Ta) in order to keep the Tj below the critical limit of 150C. Table 4 lists these values for 45-17 and 45-24 heat sinks when Tj = 150C. 2. Conduction--Liquid Cooling Methods Passive cooling schemes, such as Aavid Engineering's Oasis technology may also be used to ensure low junction temperature. Oasis uses Flourinert, a liquid that boils around 57C, to transfer heat from the hot device to a condenser, where the vaporized Flourinert is cooled, becomes liquid again, and returns to the hot device. The S2025 case temperature would not exceed 57C, as long as the cooling system is functioning properly. In such case, using the following equation, one could calculate the maximum anticipated Tj to be around 85C. Tj = Tc + (Pd x 2) (Tc is the case temperature in C, and Pd is the dissipated power in Watts.) For more information on Oasis technology, please contact: Aavid Engineering Incorporated Oasis Products Group One Kool Path/P.O. Box 400 Laconia, NH 03247-0400 Tel: 603/528-3400 FAX: 603/528-1478 Table 4. Maximum Ambient Temperatures 12 Ta C (max) (H/S 45-17) Air Flow (LFPM) 30 200 50 400 60 600 70 800 June 24, 1999 / Revision B 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025 Table 5. Absolute Maximum Ratings Supply Voltage VCC 7.0V PECL Input Voltage VCC - 2.5V to VCC PECL Output Source Current (continuous) -50mA DC TTL Input Voltage 5.5V Operating Junction Temperature Tj +150C Storage Temperature -65C to +150C Table 6. Recommended Operating Conditions Parameter Supply Voltage VCC Ambient Temperature Min Nom Max Units 4.75 5.0 5.25 V 70 C 150 C 2600 mA 0 Junction Temperature ICC 1950 Table 7. TTL Input DC Characteristics Symbol Conditions Guaranteed Input HIGH Voltage for all input pairs Guaranteed Input LOW Voltage for all input pairs 1 Input HIGH Voltage VIL1 Input LOW Voltage VIK Input Clamp Diode Voltage VCC = MIN, IIN = -18 mA IIH Input HIGH Current II IIL VIH 1. 2. Parameter Commercial 0 to 70C Min Typ2 Max Unit V 2.0 0.8 V -1.2 V VCC = MAX, VIN = 2.7V 50 A Input HIGH Current at Max. VCC = MAX, VIN =VCC + 0.3V 1 mA Input LOW Current VCC = MAX,VIN = 0.5V -0.4 mA -0.8 Typical limits are at 25C, VCC = 5.0V. These input levels provide a zero noise immunity and should only be tested in a static, noise-free environment. June 24, 1999 / Revision B 13 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025 Figure 7. Differential Input Voltage V IN (+) V V V IN (+) - V IN IN SWING (-) (-) Note: V (+) - V (-) IN IN is the algebraic difference V ID =2XV SWING of the output signals Table 8. PECL DC Characteristics3 Symbol Min VIH2 VIL2 Max Units VCC-1145 VCC-600 mV VCC -2000 VCC-1400 mV VBIAS2 Typ VCC -1300 mV IIH2 30 A IIL2 -.5 A Max Units 2800 mV 1. Internal bias point. 2. Single ended connection. 3. DC is considered to be an input signal between 0 Hz and 1 KHz. Table 9. Differential PECL Characteristics Symbol VID1 Mi n 500 Typ 1. Differential input voltage - algebraic difference 14 June 24, 1999 / Revision B 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025 Figure 8. Differential Output Voltage V (+) OUT V SWING V (-) OUT V (+) - V (-) OUT OUT Note: V (+) - V (-) OUT OUT is the algebraic difference V =2XV OD SWING of the output signals Table 10. PECL DC Characteristics2 Symbol Min VOH1 VOL1 Typ Max Units VCC-1095 VCC-695 mV VCC -1900 VCC-1365 mV IOH 20 mA IOL 5 mA 1. All outputs are loaded with 50 to VCC - 2V. 2. DC is considered to be an output signal between 0Hz and 1KHz. Table 11. Differential PECL Characteristics Symbol Mi n VOD1 700 Typ Max Units 2330 mV 1. Differential input voltage - algebraic difference. June 24, 1999 / Revision B 15 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025 EXPANDING TO A 64 X 64 SWITCH The S2025 includes configurable differential output pair driver enables that allow it to be expanded to form a 64 x 64 differential crosspoint switch. As shown in Figure 9, four S2025 devices can be used to form a 64 x 64 differential crosspoint switch. Each of the 64 pairs of differential outputs are connected to output pairs on two different S2025 devices. Similarly, each of the 64 pairs of differential outputs are connected to output pairs on two different S2025 devices. The configuration register files of the two devices are then programmed to enable only one of the two connected output pairs at once. With the interconnection scheme shown in Figure 9, any of the 64 output pairs can be connected to any of the 64 input pairs. To avoid power-up output pair contention, the Reset condition for the S2025 assumes a configuration where all the differential output pairs are disabled. Normal high-speed PECL routing and termination practices are required for all PECL connections. For maximum data throughput, reflected signals from impedance mismatches at the package/pcb boundary, as well as those due to poor placement of terminating impedances must be minimized. Care also must be taken during board layout to position the devices for the shortest possible trace lengths when connecting differential outputs together. Larger differential crosspoint switch structures can also be built using the S2025's ability to selectively enable and disable its differential output pair drivers. Figure 9. Expanding to a 64 x 64 Switch DOUTOOP DOUTOON DINOOP DINOON DIN31P DIN31N 32 X 32 Differential Crosspoint Switch DOUT31P DOUT31N 32 X 32 Differential Crosspoint Switch 32 X 32 Differential Crosspoint Switch DOUT32P DOUT32N DOUT63P DOUT63N DIN32P DIN32N 32 X 32 Differential Crosspoint Switch DIN63P DIN63N 16 June 24, 1999 / Revision B 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025 Ordering Information Prefix Device S - Integrated Circuit Package 2025 C - 8, 800MBPS, 196 LDCC lead formed with Heatsink unattached C - 15, 1.5GBPS, 196 LDCC lead formed with Heatsink unattached XXXX X Prefix Device Package O 900 D E CE RT 1 IS X IFI Applied Micro Circuits Corporation * 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 * (800)755-2622 * Fax: (858) 450-9885 http://www.amcc.com AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 1999 Applied Micro Circuits Corporation June 24, 1999 / Revision B 17