High Performance AS7C3256 Fe Oa es aT AGn ran tel CMOS SRAM y OS low voltage 32KX8 CMOS SRAM Features * Organization: 32,768 words x 8 bits * Equal access and cycle times * Single 3.3 + 0.3V power supply * Easy memory expansion with CE and OE inputs * 5V tolerant I/O specification * TTL-compatible, three-state /O * High speed * Ideal for cache, modem, portable computing - 10/12/15/20 ns address access time ~ 78% power reduction during CPU idle mode - 3/3/4/5 ns output enable access time 28-pin JEDEC standard packages * Very low power consumption - 300 mil PDIP and SOJ - Active: 216 mW max, [0 ns cycle ~ 8X 13.4 TSOP - Standby: 3.6 mW max, CMOS [/O * ESD protection 2 2000 volts 1.1 mW max, CMOS I/O, L version * Latch-up current 2 200 mA * 2.0V data retention Logic block diagram Pin arrangement <1 N Vee . TSOP 8x 13.4 DIP, SO] GND > Input buffer oF oI 2S aw a0 A Ny E30 3B it, a! wr gee HS igs A2 & : S WE 427 165 Vos 2 al E mous YR aszes2s6 EB IR) * Ag 3 Array ry 4 Ain Cy? = VO? UL 3 @ a! 123 yor ms Ad 5 (262.144) a a6 G4 11] yoo 2 a ASS IO ao t- 700 a1 cas oS at Alt re acy 8 Poa fy Column decoder Control WE be OF virco k}- CE AAAAAAA 78.9 WIE I213 Selection guide 73256-12 703256-15 73256-20 Unit Maximum address access time 12 15 20 ns Maximum output enable access time 3 4+ 5 ns Maximum operating current 55 50 45 mA 1.0 1.0 1.0 mA Maximum CMOS standby current _ L 0.3 0.3 0.3 mA Shaded areas contain advance informauon ALLIANCE SEMICONDUCTORSRAM AS7C3256 AS7C3256L II AY Functional description The AS7C3256 is a 3.3V high performance CMOS 262, 144-bit Static Random-Access Memory (SRAM) organized as 32,768 words x 8 bits. It is designed for memory applications requiring fast data access at low voltage, including Pentium , PowerPC and portable computing. Alliances advanced circu design and process techniques permit 3.3V operation without sacrificing performance or operating margins. The device enters standby mode when CE is HIGH. CMOS standby mode consumes $3.6 mW (<i. mW for the L version). Normal operation offers 75% power reduction after initial access, resulung in significant power savings during CPU idle, suspend, and stretch mode. Both versions of the AS7C3256 offer 2.0V data retention. Equal address access and cycle times (t44. tre. two) of 10/12/15/20 ns with output enable access times (tog) of 3/3/4/5 ns are ideal for high performance applications. The chip enable (CE) input permuts easy memory expansivn with multiple-bank memory organizations. A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins 1/O0-1/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (GE) or write enable (WE). A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) HIGH. The chip drives I/ O pins with the data word referenced by the input address. When chip enable or output enable is HIGH, or write enable is LOW, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible and 5V tolerant Operation is trom a single 3.3+0.3V supply. The AS7C3256 is packaged in high volume industry standard packages. Absolute maximum ratings Parameter Symbol Min Max Unit Power supply voltage relative to GND Vee -0.5 +4.6 v Input voltage relative to GND Vin 0.5 +6.0 Vv Power dissipation Py - 1.0 Ww Storage temperature (plastic) Tay 55 +150 Temperature under bias Thias -10 +85 DC output current Tout - 20 mA Stresses greater than those hsted under Absulute Maximum Ratings ma} cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any uther conditions outside these indicated un the operational sections of this specification 1s not unphed Exposure to absolute miax - imum rating conditions for extended periods may affect reliability. Truth table CE WE OE Data Mode H x x High Z Standby (Isp, [spy ) L H H High Z Output disable L H L Dout Read L L x Din Write Key: X = Don't Care, L = LOW. H = HIGH Recommended operating conditions (T, = 0C to +70C) Parameter Symbol Min Typ Max Unit Voc 3.0 33 3.6 Vv Supply voltage GND 0.0 0.0 0.0 v Vin 2.0 - 5.5 Vv Input voltage Vin ~o st = 08 v ty min = 2 OV for pulse width less than tpe-2. IL P RE 34DC operating characteristics ! Parameter Symbol Test conditions Input leakage ; current yd Veco = Max, V,, = GND to Ve Output leakage thol CE = Vip. Voc = Max. current Lo Vou = GND to Vee Operating power , _ _ ly current lec CE=\ {L+ f= fas, Tout =OmA Isp CE= Vy. f= Standby power CES Vec-0.2, supply current Ign, Vy 5 0.2V or Vig > Vee 0.29, f=0 Io, = 8 MA, Vee = Min Output voltage OF ce Ve =-4 mA, Vere = Min Shaded areas contain advance information Capacitance ? AS7C3256 AS7C3256L (Vec = 3.30.3V, GND = OV, T, = 0C to +70C) -10 -12 -15 -20 Max i Max | Min Max | Unit l 1 1 | pa pA mA mA mA mA Vv Vv (f = ! MHz, T, = Room temperature, Voc =3.3V) Parameter Symbol Signals Test conditions Max Unit Input capacitance Cw A, CE, WE, OE Vin = OV 5 pF 1/O capacitance Cro 1/0 Vin = Your = OV 7 pF 35 SRAMa waaay AS7C3256 AS7C3256L | ___] Key to switching waveforms : Rising input __! Falling input Undefined output/dont care Read cycle * (Voc = 3.340.3V, GND = OV, T, = 0C we +70C) -10 -12 -15 -20 Min = Max 15 - - (5 - 15 Min Max 20 - - 20 - 20 5 Min = Max 12 - ~ 12 = 12 Parameter Symbol Unit Notes Read cycle time ns ws Address access time ns ns 3 Chip enable (CE) access time lice Output enable (OE) access time ns ns 5 Output hold from address change toes CE LOW to output in Low Z lerz CE HIGH to ourput in High Z touz OE LOW to output in Low Z lorz OF HIGH to output in High Z lon? Power up time ley ns ns ns ns Ibs. wtaAtatatutu Apel eye ey Power down time ns Shaded areas contain advance information Read waveform | +79 Address controlled lec | Address K tya oH Dout Data valid Read waveform 2 4649 CE controlled I CE OE Dou Data valid lec Supply SK 50% is current 36AS7C3256 Hl AS7C3256L (Vcc = 3.340.3V, GND = OV, T, = 0 to +70C) Write cycle -10 -12 -15 -20 Parumeter Symbol i xX | Min Max + Min Max | Unit Notes Write cycle time tw - 20 - ns Chip enable to write end tow - 12 ns Address setup t write end taw - 12 ns Address setup time tas ns Write pulse width tw ns Address hold from end of write tau hs Data valid to write end low ns Data hold ume 'pH ns 4,5 Write enable to output in High Z tw ns 4.5 Output active from write end low ns 4,5 Shaded areas contain advance informahon Write waveform | '1! WE controlled twe law TAH Address \ __ twe V WE i 7 >1 fas |< tpw >->>| tpn Din x Data valid __ wz | owe Dout | Write waveform 2 7?! CE controlled Address CE WE 'pw Dn Data valid D, 37SRAM AS7C3256 AS7C3256L a: Data retention characteristics Parameter Symbol Test conditions Min Max Unit Voc for data retention Vor V0 = 20 2.0 - Vv cc = Data retention current I CE 200 HA : CE 2 Vec0.2V CCDR cc-0 150 (L) WA Chip enable to data retention time tcpr Vin 2 Vec0.2V 0 ~ ns Operation recovery time tp or {ac - ns Vin 0.2V Input leakage current {Ir n l HA Data retention waveform Data retention mode K Vor 2 2.0V /\ 3.0V cpr + Vv CE A Vin DR AC test conditions : Output load: see Figure B, except for tcp z and tcp see Figure C. Vin X ; Thevenin equivalent 68Q Input pulse level: GND to 3.0V. See Figure A. DoueY~#\Yr + 1-729 Input rise and fall times: 5 ns. See Figure A. wo +3.3V +3.3V Input and output timing reference levels: 1.5V. 320Q 320Q +3.3V Dout Dout 350Q 30 pF* 3502 5 pF* *including scope and jig capacitance GND GND GND Figure A: Input wavetorm Figure B: Output toad Figure C: Output load for teyz- toyz Notes During Vec power-up, a pull-up resistor to Vee on CE ts required to meet Isp specification. This parameter is sampled and not 100%c tested. For test conditions, see AC Test Conditions. Figures A. B, C. This parameter 1s guaranteed but not tested. WE 1s HIGH tor read cycle. CE and OE are LOW for read cycle. Address valid prior to or comncident with CE transinon LOW. All read cycle umings are referenced from the last valid address to the first transitioning address. 0 CE or WE must be HIGH during address transitions. 1 = SO wmW~rN DH EwWe 38 All write cycle timings are referenced from the Last valid address to the first transitioning address. tepz and t-yyz are specified with CL = SpF as in Figure C Transition is measured +500mV from steady-state voltageAS7C3256 AS7C3256L Typical DC and AC characteristics Normalized supply current I>, Isg vs. supply voltage Voc lee Is Normalized Tec, 3.0 33 3.6 Supply voltage () Normalized access time ty 4 vs. supply voltage Ve. Normalized access time 30 3.3 3.6 Supply voltage (V} Output source current Loy vs. output voltage Voy Output source current (mA) 0.0 L 65 3.3 Ourput voltage (V)} Normalized lee. lyg Normalized access ime Output sink Current (mA) Normalized supply current Ino. Igg vs. ambient temperature T, lee -i5 10 35 60 85 Ambient temperature ( C7} Normalized access time ty vs, ambient temperature T, Veo = 3.3 15 10 35 80S Ambient temperature (C) Output sink current fy. vs. output voltage Vi yp v rou = T, = 25C 00 1.65 33 Output valtage (V1 wy scale) a S hore woe A Normalized kan co S - Lt {.2 1.0 0.8 06 Normalized log Change uly, (ns) Normalized supply current Ky, vs. ambient temperature Ty Vee = 3.30 55 -10 35 80 125 Ambient temperature (C) Norinalized supply current [.-,- vs. cycle frequency I tap. 1, Wi Veo = 3.3 T,=25C ) 20 +0 6G RO Cycle Frequency (MHz) Typical access time change Ata. vs output capaciuve loading 0 250 500 750 iaoo Capacitance (pF) 39 SS weeAS7C3256 AS7C3256L AS7C3256 ordering information Package Access time 10 ns Plastic DIP, 300 mil Plastic SOJ, 300 mul TSOP 8x13.4 Shaded areas contain ads ance information AS7C3256 part numbering system 12 ns AS7C3256-12PC AS7C3256L-1 2PC [5 ns AS7C3256-15PC AS7C3256L-15PC 20 ns AS7C3256-20PC AS7C3256L-20PC AS7C3256-12JC AS7C3256L-12JC AS7C3256-15JC AS7C3256L-15JC AS7C3256-20JC AS7C3256L-20JC AS7C3256-12TC AS7C3256L-12TC AS7C32$6-15TC AS7C3256L-15TC AS7C3256-20TC AS7C3256L-20TC ASC 3 156 -XX x Cc - Blank = 5V supply Access Package P= PDIP 300 mil Commercial temperature range, SRAM prefix } = 33 supply Device number rime J = SO} 306 mil 0C 10 70C T = TSOP 8xt3.+ 40