ADC11C170LFEBC - Texas Instruments

ADC11C170

www.ti.com

SNAS412B –JULY 2007–REVISED APRIL 2013

ADC11C170 11-Bit, 170 MSPS, 1.1 GHz Bandwidth A/D Converter with CMOS Outputs

Check for Samples: ADC11C170

1FEATURES DESCRIPTION

The ADC11C170 is a high-performance CMOS

2• 1.1 GHz Full Power Bandwidth analog-to-digital converter capable of converting

• Internal Sample-and-Hold Circuit analog input signals into 11-Bit digital words at rates

• Low Power Consumption up to 170 Mega Samples Per Second (MSPS). This

converter uses a differential, pipelined architecture

• Internal Precision 1.0V Reference with digital error correction and an on-chip sample-

• Single-Ended or Differential Clock Modes and-hold circuit to minimize power consumption and

• Clock Duty Cycle Stabilizer the external component count, while providing

excellent dynamic performance. A unique sample-

• Dual +3.3V and +1.8V Supply Operation (+/- and-hold stage yields a full-power bandwidth of 1.1

10%) GHz. The ADC11C170 operates from dual +3.3V and

• Power-Down and Sleep Modes +1.8V power supplies and consumes 747 mW of

• Offset Binary or 2's Complement Output Data power at 170 MSPS.

Format The separate +1.8V supply for the digital output

• Pin-Compatible: ADC14155, ADC12C170, interface allows lower power operation with reduced

ADC11C125 noise. A power-down feature reduces the power

consumption to 5 mW while still allowing fast wake-up

• 48-pin WQFN Package, (7x7x0.8mm, 0.5mm time to full operation. In addition there is a sleep

Pin-Pitch) feature which consumes 50 mW of power and has a

faster wake-up time.

APPLICATIONS The differential inputs provide a full scale differential

• High IF Sampling Receivers input swing equal to 2 times the reference voltage. A

• Wireless Base Station Receivers stable 1.0V internal voltage reference is provided, or

• Power Amplifier Linearization the ADC11C170 can be operated with an external

reference.

• Multi-carrier, Multi-mode Receivers

• Test and Measurement Equipment Clock mode (differential versus single-ended) and

output data format (offset binary versus 2's

• Communications Instrumentation complement) are pin-selectable. A duty cycle

• Radar Systems stabilizer maintains performance over a wide range of

input clock duty cycles.

KEY SPECIFICATIONS The ADC11C170 is pin compatible with the

• Resolution 11 Bits ADC11C125, ADC12C170, and ADC14155.

• Conversion Rate 170 MSPS It is available in a 48-lead WQFN package and

• SNR (fIN = 70 MHz) 65.1 dBFS (typ) operates over the industrial temperature range of

−40°C to +85°C.

• SFDR (fIN = 70 MHz) 85.4 dBFS (typ)

• ENOB (fIN = 70 MHz) 10.5 bits (typ)

• Full Power Bandwidth 1.1 GHz (typ)

• Power Consumption 715 mW (typ)

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADC11C170

(Top View)

48 VA

AGND

VREF

VRM

VRN

VRP

AGND

36 VDR

25 VDR

DRGND

D10 (MSB)

OVR

DRDY

DRGND

CLK_SEL/DF

(LSB) D0

OGND

DRGND

VDR

DGND

VD47

CLK-

CLK+

AGND

PD/Sleep

AGND

VIN+

VIN-

AGND

* Exposed pad must be soldered to ground

plane to ensure rated performance.

INTERNAL

REFERENCE

SHA 11BIT HIGH SPEED

PIPELINE ADC

CLOCK/DUTY CYCLE

STABILIZER

DRDY

DIGITAL

CORRECTION

VIN+

VIN-

CLK+

CLK-

OVR

D0 - D10

VREF

VRP

VRM

VRN

ADC11C170

SNAS412B –JULY 2007–REVISED APRIL 2013

www.ti.com

Block Diagram

Connection Diagram

Product Folder Links: ADC11C170

AGND

IDC

VREF

AGND

VRM

VRN

VRP

AGND

ADC11C170

www.ti.com

SNAS412B –JULY 2007–REVISED APRIL 2013

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Equivalent Circuit Description

ANALOG I/O

3 VIN−Differential analog input pins. The differential full-scale input

signal level is two times the reference voltage with each input

pin signal centered on a common mode voltage, VCM.

4 VIN+

43 VRP

45 VRM

These pins should each be bypassed to AGND with a low ESL

(equivalent series inductance) 0.1 µF capacitor placed very

close to the pin to minimize stray inductance. A 0.1 µF

capacitor should be placed between VRP and VRN as close to

the pins as possible, and a 10 µF capacitor should be placed

in parallel.

44 VRN VRP and VRN should not be loaded. VRM may be loaded to

1mA for use as a temperature stable 1.5V reference.

It is recommended to use VRM to provide the common mode

voltage, VCM, for the differential analog inputs, VIN+ and VIN−.

This pin can be used as either the +1.0V internal reference

voltage output (internal reference operation) or as the external

reference voltage input (external reference operation).

To use the internal reference, VREF should be decoupled to

AGND with a 0.1 µF, low equivalent series inductance (ESL)

capacitor. In this mode, VREF defaults as the output for the

internal 1.0V reference.

46 VREF To use an external reference, overdrive this pin with a low

noise external reference voltage. The input impedance looking

into this pin is 9kΩ. Therefore, to overdrive this pin, the output

impedance of the external reference source should be <<

9kΩ.

This pin should not be used to source or sink current.

The full scale differential input voltage range is 2 * VREF.

Product Folder Links: ADC11C170

AGND

ADC11C170

SNAS412B –JULY 2007–REVISED APRIL 2013

www.ti.com

Pin Descriptions and Equivalent Circuits (continued)

Pin No. Symbol Equivalent Circuit Description

This is a four-state pin controlling the input clock mode and

output data format.

CLK_SEL/DF = VA, CLK+ and CLK−are configured as a

differential clock input. The output data format is 2's

complement.

CLK_SEL/DF = (2/3)*VA, CLK+ and CLK−are configured as a

8 CLK_SEL/DF differential clock input. The output data format is offset binary.

CLK_SEL/DF = (1/3)*VA, CLK+ is configured as a single-

ended clock input and CLK−should be tied to AGND. The

output data format is 2's complement.

CLK_SEL/DF = AGND, CLK+ is configured as a single-ended

clock input and CLK−should be tied to AGND. The output

data format is offset binary.

This is a three-state input controlling Power Down and Sleep

modes.

PD/Sleep = VA, Power Down is enabled. In the Power Down

state only the reference voltage circuitry remains active and

7 PD/Sleep power dissipation is reduced.

PD/Sleep = VA/2, Sleep mode is enabled. Sleep mode

consumes more power than Power Down mode but has a

faster recovery time.

PD/Sleep = AGND, Normal operation.

11 CLK+ The clock input pins can be configured to accept either a

single-ended or a differential clock input signal.

When the single-ended clock mode is selected through

CLK_SEL/DF (pin 8), connect the clock input signal to the

CLK+ pin and connect the CLK−pin to AGND.

When the differential clock mode is selected through

CLK_SEL/DF (pin 8), connect the positive and negative clock

inputs to the CLK+ and CLK−pins, respectively.

12 CLK−The analog input is sampled on the falling edge of the clock

input.

Product Folder Links: ADC11C170

DRGND

VDR

DGND

40Ö

ADC11C170

www.ti.com

SNAS412B –JULY 2007–REVISED APRIL 2013

Pin Descriptions and Equivalent Circuits (continued)

Pin No. Symbol Equivalent Circuit Description

DIGITAL I/O

Digital data output pins that make up the 11-Bit conversion

20-24, D0–D10 result. D0 (pin 20) is the LSB, while D10 (pin 32) is the MSB

27-32 of the output word. Output levels are CMOS compatible.

Over-Range Indicator. This output is set HIGH when the input

33 OVR amplitude exceeds the 11-Bit conversion range (0 to 2047).

Data Ready Strobe. This pin is used to clock the output data.

It has the same frequency as the sampling clock. One word of

data is output in each cycle of this signal. The rising edge of

this signal should be used to capture the output data.

34 DRDY

Output GND, internally tied to GND through 5k ohm resistor to

17-19 OGND provide pin compatibility with 12 or 14 bit ADCs.

ANALOG POWER

Positive analog supply pins. These pins should be connected

1, 6, 9, 37, VAto a quiet +3.3V source and be bypassed to AGND with 0.01

40, 41, 48 µF and 0.1 µF capacitors located close to the power pins.

2, 5, 10, 38, The ground return for the analog supply.

39, 42, 47, AGND Note: Exposed pad on bottom of package must be soldered to

Exposed Pad ground plane to ensure rated performance.

DIGITAL POWER

Positive digital supply pin. This pin should be connected to a

13 VDquiet +3.3V source and be bypassed to DGND with a 0.01 µF

and 0.1 µF capacitor located close to the power pin.

14 DGND The ground return for the digital supply.

Positive driver supply pin for the output drivers. This pin

should be connected to a quiet voltage source of +1.8V and

15, 25, 36 VDR be bypassed to DRGND with 0.01 µF and 0.1 µF capacitors

located close to the power pins.

The ground return for the digital output driver supply. These

pins should be connected to the system digital ground, but not

16, 26, 35 DRGND be connected in close proximity to the ADC's DGND or AGND

pins. See Layout and Grounding for more details.

Product Folder Links: ADC11C170

ADC11C170

SNAS412B –JULY 2007–REVISED APRIL 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings(1)(2)(3)

Supply Voltage (VA, VD)−0.3V to 4.2V

Supply Voltage (VDR)−0.3V to 2.35V

|VA–VD|≤100 mV

Voltage on Any Input Pin −0.3V to (VA+0.3V)

(Not to exceed 4.2V)

Voltage on Any Output Pin −0.3V to (VDR +0.2V)

(Not to exceed 2.35V)

Input Current at Any Pin other than Supply Pins(4) ±5 mA

Package Input Current(4) ±50 mA

Max Junction Temp (TJ) +150°C

Thermal Resistance (θJA) 24°C/W

Package Dissipation at TA= 25°C(5) 5.2W

ESD Rating Human Body Model(6) 2000 V

Machine Model(6) 200 V

Charge Device Model 1000 V

Storage Temperature −65°C to +150°C

Soldering process must comply with TI's Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.(7)

(1) All voltages are measured with respect to GND = AGND = DGND = DRGND = 0V, unless otherwise specified.

(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is specified to be functional, but do not ensure specific performance limits. For ensured specifications and test

conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance

characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the

maximum Operating Ratings is not recommended.

(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.

(4) When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be

limited to ±5 mA. The ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power

supplies with an input current of ±5 mA to 10.

(5) The maximum allowable power dissipation is dictated by TJ,max, the junction-to-ambient thermal resistance, (θJA), and the ambient

temperature, (TA), and can be calculated using the formula PD,max = (TJ,max - TA)/θJA. The values for maximum power dissipation listed

above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the

power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided.

(6) Human Body Model is 100 pF discharged through a 1.5 kΩresistor. Machine Model is 220 pF discharged through 0 Ω

(7) Reflow temperature profiles are different for lead-free and non-lead-free packages.

Operating Ratings(1)(2)

Operating Temperature −40°C ≤TA≤+85°C

Supply Voltage (VA, VD) +3.0V to +3.6V

Output Driver Supply (VDR) +1.6V to +2.0V

CLK −0.05V to (VA+ 0.05V)

Clock Duty Cycle 30/70 %

Analog Input Pins 0V to 2.6V

VCM 1.4V to 1.6V

|AGND-DGND| ≤100mV

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is specified to be functional, but do not ensure specific performance limits. For ensured specifications and test

conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance

characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the

maximum Operating Ratings is not recommended.

(2) All voltages are measured with respect to GND = AGND = DGND = DRGND = 0V, unless otherwise specified.

Product Folder Links: ADC11C170

AGND

To Internal Circuitry

I/O

ADC11C170

www.ti.com

SNAS412B –JULY 2007–REVISED APRIL 2013

Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply: VIN = -1dBFS, AGND = DGND = DRGND = 0V, VA= VD=

+3.3V, VDR = +1.8V, Internal VREF = +1.0V, fCLK = 170 MHz, VCM = VRM, CL= 5 pF/pin, Single-Ended Clock Mode, Offset

Binary Format. Typical values are for TA= 25°C. Boldface limits apply for TMIN ≤TA≤TMAX.All other limits apply for TA=

25°C(1)(2)(3)

Typical Units

Symbol Parameter Conditions Limits

(4) (Limits)

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 11 Bits (min)

2LSB (max)

INL Integral Non Linearity (5) Full Scale Input ±0.62 -2 LSB (min)

0.96 LSB (max)

DNL Differential Non Linearity Full Scale Input ±0.38 -0.94 LSB (min)

3.7 %FS (max)

PGE Positive Gain Error +1.57 -1.8 %FS (min)

1.8 %FS (max)

NGE Negative Gain Error -1.23 -3.7 %FS (min)

TC GE Gain Error Tempco −40°C ≤TA≤+85°C +8.0 ppm/°C

0.89 %FS (max)

VOFF Offset Error (VIN+=VIN−)−0.12 -1.3 %FS (min)

TC VOFF Offset Error Tempco −40°C ≤TA≤+85°C +0.5 ppm/°C

Under Range Output Code 0 0

Over Range Output Code 2047 2047

REFERENCE AND ANALOG INPUT CHARACTERISTICS

VCM Common Mode Input Voltage 1.5 V

VRM Reference Ladder Midpoint Output Voltage Output load = 1 mA 1.5 V

(CLK HIGH) 9 pF

VIN = 1.5 Vdc ±

CIN VIN Input Capacitance (each pin to GND)(6) 0.5 V (CLK LOW) 6 pF

VREF Reference Voltage(7) 1.00 V

Reference Input Resistance 9 kΩ

(1) The inputs are protected as shown below. Input voltage magnitudes above VAor below GND will not damage this device, provided

current is limited per Note 4 under Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes above

2.6V or below GND as described in the Operating Ratings section.

(2) To ensure accuracy, it is required that |VA–VD|≤100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for VREF = +1.0V (2VP-P differential input), the 11-Bit LSB is 976.6 µV.

(4) Typical figures are at TA= 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

(5) Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through

positive and negative full-scale.

(6) The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.

(7) Optimum performance will be obtained by keeping the reference input in the 0.9V to 1.1V range. The LM4051CIM3-ADJ (SOT-23

package) is recommended for external reference applications.

Product Folder Links: ADC11C170

AGND

To Internal Circuitry

I/O

ADC11C170

SNAS412B –JULY 2007–REVISED APRIL 2013

www.ti.com

Dynamic Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply: VIN = -1dBFS, AGND = DGND = DRGND = 0V, VA= VD=

+3.3V, VDR = +1.8V, Internal VREF = +1.0V, fCLK = 170 MHz, VCM = VRM, CL= 5 pF/pin, Single-Ended Clock Mode, Offset

Binary Format. Typical values are for TA= 25°C. Boldface limits apply for TMIN ≤TA≤TMAX.All other limits apply for TA=

25°C(1)(2)(3)

Typical Units

Symbol Parameter Conditions Limits

(4) (Limits)

DYNAMIC CONVERTER CHARACTERISTICS, AIN= -1dBFS

FPBW Full Power Bandwidth -1 dBFS Input, −3 dB Corner 1.1 GHz

fIN = 10 MHz 65.2 dBFS

fIN = 70 MHz 65.1 64.0 dBFS

SNR Signal-to-Noise Ratio fIN = 150 MHz 64.9 dBFS

fIN = 250 MHz 64.6 dBFS

fIN = 400 MHz 63.8 dBFS

fIN = 10 MHz 86.4 dBFS

fIN = 70 MHz 85.4 74.0 dBFS

SFDR Spurious Free Dynamic Range fIN = 150 MHz 82.4 dBFS

fIN = 250 MHz 83.4 dBFS

fIN = 400 MHz 69.8 dBFS

fIN = 10 MHz 10.5 Bits

fIN = 70 MHz 10.5 10.2 Bits

ENOB Effective Number of Bits fIN = 150 MHz 10.5 Bits

fIN = 250 MHz 10.4 Bits

fIN = 400 MHz 10.1 Bits

fIN = 10 MHz -83.1 dBFS

fIN = 70 MHz -83.2 -72.0 dBFS

THD Total Harmonic Disortion fIN = 150 MHz -78.9 dBFS

fIN = 250 MHz -78.5 dBFS

fIN = 400 MHz -67.2 dBFS

fIN = 10 MHz -93.5 dBFS

fIN = 70 MHz -93.4 -80.0 dBFS

H2 Second Harmonic Distortion fIN = 150 MHz -82.4 dBFS

fIN = 250 MHz -83.4 dBFS

fIN = 400 MHz -74.0 dBFS

fIN = 10 MHz -93.2 dBFS

fIN = 70 MHz -87.9 -74 dBFS

H3 Third Harmonic Distortion fIN = 150 MHz -88.8 dBFS

fIN = 250 MHz -83.5 dBFS

fIN = 400 MHz -69.8 dBFS

(1) The inputs are protected as shown below. Input voltage magnitudes above VAor below GND will not damage this device, provided

current is limited per Note 4 under Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes above

2.6V or below GND as described in the Operating Ratings section.

(2) To ensure accuracy, it is required that |VA–VD|≤100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for VREF = +1.0V (2VP-P differential input), the 11-Bit LSB is 976.6 µV.

(4) Typical figures are at TA= 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

Product Folder Links: ADC11C170

AGND

To Internal Circuitry

I/O

ADC11C170

www.ti.com

SNAS412B –JULY 2007–REVISED APRIL 2013

Dynamic Converter Electrical Characteristics (continued)

Unless otherwise specified, the following specifications apply: VIN = -1dBFS, AGND = DGND = DRGND = 0V, VA= VD=

+3.3V, VDR = +1.8V, Internal VREF = +1.0V, fCLK = 170 MHz, VCM = VRM, CL= 5 pF/pin, Single-Ended Clock Mode, Offset

Binary Format. Typical values are for TA= 25°C. Boldface limits apply for TMIN ≤TA≤TMAX.All other limits apply for TA=

25°C(1)(2)(3)

Typical Units

Symbol Parameter Conditions Limits

(4) (Limits)

fIN = 10 MHz 65.2 dBFS

fIN = 70 MHz 65.0 63.3 dBFS

SINAD Signal-to-Noise and Distortion Ratio fIN = 150 MHz 64.7 dBFS

fIN = 250 MHz 64.4 dBFS

fIN = 400 MHz 62.4 dBFS

Logic and Power Supply Electrical Characteristics

Unless otherwise specified, the following specifications apply: VIN = -1 dBFS, AGND = DGND = DRGND = 0V, VA= VD=

+3.3V, VDR = +1.8V, Internal VREF = +1.0V, fCLK = 170 MHz, VCM = VRM, CL= 5 pF/pin, Single-Ended Clock Mode, Offset

Binary Format. Typical values are for TA= 25°C. Boldface limits apply for TMIN ≤TA≤TMAX.All other limits apply for TA=

25°C(1)(2)(3)

Typical Units

Symbol Parameter Conditions Limits

(4) (Limits)

CLK INPUT CHARACTERISTICS

VIN(1) Logical “1” Input Voltage VD= 3.6V 2.0 V (min)

VIN(0) Logical “0” Input Voltage VD= 3.0V 0.8 V (max)

IIN(1) Logical “1” Input Current VIN = 3.3V 10 µA

IIN(0) Logical “0” Input Current VIN = 0V −10 µA

CIN Input Capacitance 5 pF

DIGITAL OUTPUT CHARACTERISTICS (D0–D11, DRDY, OVR)

VOUT(1) Logical “1” Output Voltage IOUT =−0.5 mA , VDR = 1.8V 1.2 V (min)

VOUT(0) Logical “0” Output Voltage IOUT = 1.6 mA, VDR = 1.8V 0.4 V (max)

+ISC Output Short Circuit Source Current VOUT = 0V −10 mA

−ISC Output Short Circuit Sink Current VOUT = VDR 10 mA

COUT Digital Output Capacitance 5 pF

POWER SUPPLY CHARACTERISTICS

IAAnalog Supply Current Full Operation 207 252 mA (max)

IDDigital Supply Current Full Operation 9.9 10.5 mA (max)

IDR Digital Output Supply Current Full Operation(5) 13 mA

(1) The inputs are protected as shown below. Input voltage magnitudes above VAor below GND will not damage this device, provided

current is limited per Note 4 under Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes above

2.6V or below GND as described in the Operating Ratings section.

(2) To ensure accuracy, it is required that |VA–VD|≤100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for VREF = +1.0V (2VP-P differential input), the 11-Bit LSB is 976.6 µV.

(4) Typical figures are at TA= 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

(5) IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,

the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0x f0+ C1x f1+....C11 x

f11) where VDR is the output driver power supply voltage, Cnis total capacitance on the output pin, and fnis the average frequency at

which that pin is toggling.

Product Folder Links: ADC11C170

AGND

To Internal Circuitry

I/O

ADC11C170

SNAS412B –JULY 2007–REVISED APRIL 2013

www.ti.com

Logic and Power Supply Electrical Characteristics (continued)

Unless otherwise specified, the following specifications apply: VIN = -1 dBFS, AGND = DGND = DRGND = 0V, VA= VD=

+3.3V, VDR = +1.8V, Internal VREF = +1.0V, fCLK = 170 MHz, VCM = VRM, CL= 5 pF/pin, Single-Ended Clock Mode, Offset

Binary Format. Typical values are for TA= 25°C. Boldface limits apply for TMIN ≤TA≤TMAX.All other limits apply for TA=

25°C(1)(2)(3)

Typical Units

Symbol Parameter Conditions Limits

(4) (Limits)

Power Consumption Excludes IDR(6) 715 mW

Power Down Power Consumption 5 mW

Sleep Power Consumption 50 mW

(6) IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,

the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0x f0+ C1x f1+....C11 x

f11) where VDR is the output driver power supply voltage, Cnis total capacitance on the output pin, and fnis the average frequency at

which that pin is toggling.

Timing and AC Characteristics

Unless otherwise specified, the following specifications apply: VIN = -1dBFS, AGND = DGND = DRGND = 0V, VA= VD=

+3.3V, VDR = +1.8V, Internal VREF = +1.0V, fCLK = 170 MHz, VCM = VRM, CL= 5 pF/pin, Single-Ended Clock Mode, Offset

Binary Format. Typical values are for TA= 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface

limits apply for TMIN ≤TA≤TMAX.All other limits apply for TA= 25°C(1)(2)(3)

Typical Units

Symbol Parameter Conditions Limits

(4) (Limits)

Maximum Clock Frequency 170 MHz (max)

Minimum Clock Frequency 5MHz (min)

tCH Clock High Time 2.7 ns

tCL Clock Low Time 2.7 ns

Clock

Conversion Latency Cycles

Output Delay of CLK to Relative to falling edge of

tOD 2.0 ns

DATA CLK

Time output data is valid

tDV Data Output Setup Time before the output edge of 1.9 1.35 ns (min)

DRDY(5)

Time till output data is not

tDNV Data Output Hold Time valid after the output edge of 1.9 1.35 ns (min)

DRDY(5)

tAD Aperture Delay 0.5 ns

Aperture Jitter 0.08 ps rms

0.1 µF on pins 43, 44; 10 µF

and 0.1 µF between pins 43,

Power Down Recovery Time 3.0 ms

44; 0.1 µF and 10 µF on pins

45, 46

(1) The inputs are protected as shown below. Input voltage magnitudes above VAor below GND will not damage this device, provided

current is limited per Note 4 under Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes above

2.6V or below GND as described in the Operating Ratings section.

(2) To ensure accuracy, it is required that |VA–VD|≤100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for VREF = +1.0V (2VP-P differential input), the 11-Bit LSB is 976.6 µV.

(4) Typical figures are at TA= 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

(5) This test parameter is specified by design and characterization.

Product Folder Links: ADC11C170

ADC11C170

www.ti.com

SNAS412B –JULY 2007–REVISED APRIL 2013

Timing and AC Characteristics (continued)

Unless otherwise specified, the following specifications apply: VIN = -1dBFS, AGND = DGND = DRGND = 0V, VA= VD=

+3.3V, VDR = +1.8V, Internal VREF = +1.0V, fCLK = 170 MHz, VCM = VRM, CL= 5 pF/pin, Single-Ended Clock Mode, Offset

Binary Format. Typical values are for TA= 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface

limits apply for TMIN ≤TA≤TMAX.All other limits apply for TA= 25°C(1)(2)(3)

Typical Units

Symbol Parameter Conditions Limits

(4) (Limits)

0.1 µF on pins 43, 44; 10 µF

and 0.1 µF between pins 43,

Sleep Recovery Time 100 µs

44; 0.1 µF and 10 µF on pins

45, 46

Product Folder Links: ADC11C170

ADC11C170

SNAS412B –JULY 2007–REVISED APRIL 2013

www.ti.com

Specification Definitions

APERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for

conversion.

APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.

Aperture jitter manifests itself as noise in the output.

CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the

total time of one period. The specification here refers to the ADC clock input signal.

COMMON MODE VOLTAGE (VCM)is the common DC voltage applied to both input terminals of the ADC.

CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is

presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay

plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the

conversion by the pipeline delay.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion Ratio or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is

equivalent to a perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input.

GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as:

Gain Error = Positive Full Scale Error −Negative Full Scale Error (1)

It can also be expressed as Positive Gain Error and Negative Gain Error, which are calculated as:

PGE = Positive Full Scale Error - Offset Error NGE = Offset Error - Negative Full Scale Error (2)

INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from

negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code

transition). The deviation of any given code from this straight line is measured from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two

sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in

the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS.

LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is VFS/2n,

where “VFS” is the full scale input voltage and “n” is the ADC resolution in bits.

MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC11C170 is

ensured not to have any missing codes.

MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.

NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of

½ LSB above negative full scale.

OFFSET ERROR is the difference between the two input voltages [(VIN+) – (VIN-)] required to cause a transition

from code 2047 to 2048.

OUTPUT DELAY is the time delay after the falling edge of the clock before the data update is presented at the

output pins.

PIPELINE DELAY (LATENCY) See CONVERSION LATENCY.

POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of

1½ LSB below positive full scale.

POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power

supply voltage. PSRR is the ratio of the Full-Scale output of the ADC with the supply at the minimum DC supply

limit to the Full-Scale output of the ADC with the supply at the maximum DC supply limit, expressed in dB.

Product Folder Links: ADC11C170

tOD

Clock N Clock N + 7

Sample N + 7

tAD

Sample N + 6

Sample N

Sample N + 8 Sample N + 9 Sample N + 10

CLK

VIN

D0 - D10

tCH

tCL

Data N + 2

| |

Data N - 1

90%

10%

90%

10%

fCLK

Data N

Latency

Data N + 1

DRDY

tDNV

tDV

ADC11C170

www.ti.com

SNAS412B –JULY 2007–REVISED APRIL 2013

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms

value of the sum of all other spectral components below one-half the sampling frequency, not including

harmonics or DC.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral components below half the clock frequency, including

harmonics but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the

input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum

that is not present at the input.

TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first nine harmonic

levels at the output to the level of the fundamental at the output. THD is calculated as

(3)

where f1is the RMS power of the fundamental (output) frequency and f2through f10 are the RMS power of the

first 9 harmonic frequencies in the output spectrum.

SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in

the input frequency at the output and the power in its 2nd harmonic level at the output.

THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in

the input frequency at the output and the power in its 3rd harmonic level at the output.

Timing Diagram

Figure 1. Output Timing

Product Folder Links: ADC11C170

ADC11C170

SNAS412B –JULY 2007–REVISED APRIL 2013

www.ti.com

Transfer Characteristic

Figure 2. Transfer Characteristic (Offset Binary Format)

Product Folder Links: ADC11C170

AGND

To Internal Circuitry

I/O

ADC11C170

www.ti.com

SNAS412B –JULY 2007–REVISED APRIL 2013

Typical Performance Characteristics, DNL, INL

Unless otherwise specified, the following specifications apply: VIN = -1dBFS, AGND = DGND = DRGND = 0V, VA= VD=

+3.3V, VDR = +1.8V, Internal VREF = +1.0V, fCLK = 170 MHz, VCM = VRM, CL= 5 pF/pin, Single-Ended Clock Mode, Offset

Binary Format. Typical values are for TA= 25°C. (1) (2) (3)

DNL INL

Figure 3. Figure 4.

(1) The inputs are protected as shown below. Input voltage magnitudes above VAor below GND will not damage this device, provided

current is limited per Note 4 under Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes above

2.6V or below GND as described in the Operating Ratings section.

(2) To ensure accuracy, it is required that |VA–VD|≤100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for VREF = +1.0V (2VP-P differential input), the 11-Bit LSB is 976.6 µV.

Product Folder Links: ADC11C170

ADC11C170

SNAS412B –JULY 2007–REVISED APRIL 2013

www.ti.com

Typical Performance Characteristics, Dynamic Performance

Unless otherwise specified, the following specifications apply: VIN = -1dBFS, AGND = DGND = DRGND = 0V, VA= VD=

+3.3V, VDR = +1.8V, Internal VREF = +1.0V, fCLK = 170 MHz, fIN = 70 MHz, VCM = VRM, CL= 5 pF/pin, Single-Ended Clock

Mode, Offset Binary Format. Typical values are for TA= 25°C.

SNR, SINAD, SFDR DISTORTION

vs. vs.

fIN fIN

Figure 5. Figure 6.

SNR, SINAD, SFDR DISTORTION

vs. vs.

VAVA

Figure 7. Figure 8.

SNR, SINAD, SFDR DISTORTION

vs. vs.

VDR VDR

Figure 9. Figure 10.

Product Folder Links: ADC11C170

ADC11C170

www.ti.com

SNAS412B –JULY 2007–REVISED APRIL 2013

Typical Performance Characteristics, Dynamic Performance

Unless otherwise specified, the following specifications apply: VIN = -1dBFS, AGND = DGND = DRGND = 0V, VA= VD=

+3.3V, VDR = +1.8V, Internal VREF = +1.0V, fCLK = 170 MHz, fIN = 70 MHz, VCM = VRM, CL= 5 pF/pin, Single-Ended Clock

Mode, Offset Binary Format. Typical values are for TA= 25°C.

SNR, SINAD, SFDR DISTORTION

vs. vs.

VREF VREF

Figure 11. Figure 12.

SNR, SINAD, SFDR DISTORTION

vs. vs.

Temperature Temperature

Figure 13. Figure 14.

Product Folder Links: ADC11C170

ADC11C170

SNAS412B –JULY 2007–REVISED APRIL 2013

www.ti.com

Typical Performance Characteristics, Dynamic Performance

Unless otherwise specified, the following specifications apply: VIN = -1dBFS, AGND = DGND = DRGND = 0V, VA= VD=

+3.3V, VDR = +1.8V, Internal VREF = +1.0V, fCLK = 170 MHz, fIN = 70 MHz, VCM = VRM, CL= 5 pF/pin, Single-Ended Clock

Mode, Offset Binary Format. Typical values are for TA= 25°C.

Spectral Response @ 70 MHz Input Spectral Response @ 150 MHz Input

Figure 15. Figure 16.

Spectral Response @ 250 MHz Input Spectral Response @ 411 MHz Input

Figure 17. Figure 18.

Product Folder Links: ADC11C170

ADC11C170

www.ti.com

SNAS412B –JULY 2007–REVISED APRIL 2013

FUNCTIONAL DESCRIPTION

Operating on dual +3.3V and +1.8V supplies, the ADC11C170 digitizes a differential analog input signal to 11

bits, using a differential pipelined architecture with error correction circuitry and an on-chip sample-and-hold

circuit to ensure maximum performance.

The user has the choice of using an internal 1.0V stable reference, or using an external reference. The

ADC11C170 will accept an external reference between 0.9V and 1.1V (1.0V recommended) which is buffered

on-chip to ease the task of driving that pin. The +1.8V output driver supply reduces power consumption and

decreases the noise at the output of the converter.

The quad state function pin CLK_SEL/DF (pin 8) allows the user to choose between using a single-ended or a

differential clock input and between offset binary or 2's complement output data format. The digital outputs are

CMOS compatible signals that are clocked by a synchronous data ready output signal (DRDY, pin 34) at the

same rate as the clock input. For the ADC11C170 the clock frequency can be between 5 MSPS and 170 MSPS

(typical) with fully specified performance at 170 MSPS. The analog input is acquired at the falling edge of the

clock and the digital data for a given sample is output on the falling edge of the DRDY signal and is delayed by

the pipeline for 7 clock cycles. The data should be captured on the rising edge of the DRDY signal.

Power-down is selectable using the PD/Sleep pin (pin 7). A logic high on the PD/Sleep pin disables everything

except the voltage reference circuitry and reduces the converter power consumption to 5 mW. When PD/Sleep is

biased to VA/2 the the chip enters sleep mode. In sleep mode everything except the voltage reference circuitry

and its accompanying on chip buffer is disabled; power consumption is reduced to 50 mW. For normal operation,

the PD/Sleep pin should be connected to the analog ground (AGND). A duty cycle stabilizer maintains

performance over a wide range of clock duty cycles.

APPLICATIONS INFORMATION

OPERATING CONDITIONS

We recommend that the following conditions be observed for operation of the ADC11C170:

3.0V ≤VA≤3.6V

VD= VA

VDR = 1.8V

5 MHz ≤fCLK ≤170 MHz

1.0V internal reference

0.9V ≤VREF ≤1.1V (for an external reference)

VCM = 1.5V (from VRM)

Single Ended Clock Mode

ANALOG INPUTS

Signal Inputs

Differential Analog Input Pins

The ADC11C170 has one pair of analog signal input pins, VIN+ and VIN−, which form a differential input pair. The

input signal, VIN, is defined as

VIN = (VIN+) – (VIN−) (4)

Figure 19 shows the expected input signal range. Note that the common mode input voltage, VCM, should be

1.5V. Using VRM (pin 45) for VCM will ensure the proper input common mode level for the analog input signal. The

peaks of the individual input signals should each never exceed 2.6V. Each analog input pin of the differential pair

should have a peak-to-peak voltage equal to the reference voltage, VREF, be 180° out of phase with each other

and be centered around VCM.The peak-to-peak voltage swing at each analog input pin should not exceed the

value of the reference voltage or the output data will be clipped.

Product Folder Links: ADC11C170

ADC11C170

SNAS412B –JULY 2007–REVISED APRIL 2013

www.ti.com

Figure 19. Expected Input Signal Range

For single frequency sine waves the full scale error in LSB can be described as approximately

EFS = 2048 ( 1 - sin (90° + dev)) (5)

Where dev is the angular difference in degrees between the two signals having a 180° relative phase relationship

to each other (see Figure 20). For single frequency inputs, angular errors result in a reduction of the effective full

scale input. For complex waveforms, however, angular errors will result in distortion.

Figure 20. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause

Distortion

It is recommended to drive the analog inputs with a source impedance less than 100Ω. Matching the source

impedance for the differential inputs will improve even ordered harmonic performance (particularly second

harmonic).

Table 1 indicates the input to output relationship of the ADC11C170.

Table 1. Input to Output Relationship

VIN+VIN−Binary Output 2’s Complement Output

VCM −VREF/2 VCM + VREF/2 000 0000 0000 100 0000 0000 Negative Full-Scale

VCM −VREF/4 VCM + VREF/4 010 0000 0000 110 0000 0000

VCM VCM 100 0000 0000 000 0000 0000 Mid-Scale

VCM + VREF/4 VCM −VREF/4 110 0000 0000 010 0000 0000

VCM + VREF/2 VCM −VREF/2 111 1111 1111 011 1111 1111 Positive Full-Scale

Driving the Analog Inputs

The VIN+ and the VIN−inputs of the ADC11C170 have an internal sample-and-hold circuit which consists of an

analog switch followed by a switched-capacitor amplifier. The analog inputs are connected to the sampling

capacitors through NMOS switches, and each analog input has parasitic capacitances associated with it.

When the clock is high, the converter is in the sample phase. The analog inputs are connected to the sampling

capacitor through the NMOS switches, which causes the capacitance at the analog input pins to appear as the

pin capacitance plus the internal sample and hold circuit capacitance (approximately 9 pF). While the clock level

remains high, the sampling capacitor will track the changing analog input voltage. When the clock transitions

from high to low, the converter enters the hold phase, during which the analog inputs are disconnected from the

sampling capacitor. The last voltage that appeared at the analog input before the clock transition will be held on

the sampling capacitor and will be sent to the ADC core. The capacitance seen at the analog input during the

hold phase appears as the sum of the pin capacitance and the parasitic capacitances associated with the sample

and hold circuit of each analog input (approximately 6 pF). Once the clock signal transitions from low to high, the

analog inputs will be reconnected to the sampling capacitor to capture the next sample. Usually, there will be a

difference between the held voltage on the sampling capacitor and the new voltage at the analog input. This will

cause a charging glitch that is proportional to the voltage difference between the two samples to appear at the

analog input pin. The input circuitry must be fast enough to allow the sampling capacitor to settle before the clock

signal goes low again, as incomplete settling can degrade the SFDR performance.

Product Folder Links: ADC11C170

ADC11C170

www.ti.com

SNAS412B –JULY 2007–REVISED APRIL 2013

A single-ended to differential conversion circuit is shown in Figure 21. A transformer is preferred for high

frequency input signals. Terminating the transformer on the secondary side provides two advantages. First, it

presents a real broadband impedance to the ADC inputs and second, it provides a common path for the charging

glitches from each side of the differential sample-and-hold circuit.

One short-coming of using a transformer to achieve the single-ended to differential conversion is that most RF

transformers have poor low frequency performance. A differential amplifier can be used to drive the analog inputs

for low frequency applications. The amplifier must be fast enough to settle from the charging glitches on the

analog input resulting from the sample-and-hold operation before the clock goes high and the sample is passed

to the ADC core.

The SFDR performance of the converter depends on the external signal conditioning circuity used, as this affects

how quickly the sample-and-hold charging glitch will settle. An external resistor and capacitor network as shown

in Figure 21 should be used to isolate the charging glitches at the ADC input from the external driving circuit and

to filter the wideband noise at the converter input. These components should be placed close to the ADC inputs

because the analog input of the ADC is the most sensitive part of the system, and this is the last opportunity to

filter that input. For Nyquist applications the RC pole should be at the ADC sample rate. The ADC input

capacitance in the sample mode should be considered when setting the RC pole. For wideband undersampling

applications, the RC pole should be set at about 1.5 to 2 times the maximum input frequency to maintain a linear

delay response.

Input Common Mode Voltage

The input common mode voltage, VCM, should be in the range of 1.4V to 1.6V and be a value such that the peak

excursions of the analog signal do not go more negative than ground or more positive than 2.6V. It is

recommended to use VRM (pin 45) as the input common mode voltage.

Reference Pins

The ADC11C170 is designed to operate with an internal 1.0V reference, or an external 1.0V reference, but

performs well with external reference voltages in the range of 0.9V to 1.1V. The internal 1.0 Volt reference is the

default condition when no external reference input is applied to the VREF pin. If a voltage in the range of 0.9V to

1.1V is applied to the VREF pin, then that voltage is used for the reference. The VREF pin should always be

bypassed to ground with a 0.1 µF capacitor close to the reference input pin. Lower reference voltages will

decrease the signal-to-noise ratio (SNR) of the ADC11C170. Increasing the reference voltage (and the input

signal swing) beyond 1.1V may degrade THD for a full-scale input, especially at higher input frequencies.

It is important that all grounds associated with the reference voltage and the analog input signal make connection

to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path.

The Reference Bypass Pins (VRP, VRM, and VRN) are made available for bypass purposes. All these pins should

each be bypassed to ground with a 0.1 µF capacitor. A 0.1 µF and a 10 µF capacitor should be placed between

the VRP and VRN pins, as shown in Figure 21. This configuration is necessary to avoid reference oscillation,

which could result in reduced SFDR and/or SNR. VRM may be loaded to 1mA for use as a temperature stable

1.5V reference. The remaining pins should not be loaded.

Smaller capacitor values than those specified will allow faster recovery from the power down and sleep modes,

but may result in degraded noise performance. Loading any of these pins, other than VRM, may result in

performance degradation.

The nominal voltages for the reference bypass pins are as follows:

VRM = 1.5 V

VRP = VRM + VREF / 2

VRN = VRM −VREF / 2

Control Inputs

Power-Down & Sleep (PD/Sleep)

The power-down and sleep modes can be enabled through this three-state input pin. Table 2 shows how to

utilize these options.

Product Folder Links: ADC11C170

ADC11C170

SNAS412B –JULY 2007–REVISED APRIL 2013

www.ti.com

Table 2. Power Down/Sleep Selection Table

PD Input Voltage Power State

VAPower-down

VA/2 Sleep

AGND On

The power-down and sleep modes allows the user to conserve power when the converter is not being used. In

the power-down state all bias currents of the analog circuitry, excluding the reference are shut down which

reduces the power consumption to 5 mW with no clock running. In sleep mode some additional buffer circuitry is

left on to allow an even faster wake time; power consumption in the sleep mode is 50 mW with no clock running.

In both of these modes the output data pins are undefined and the data in the pipeline is corrupted.

The Exit Cycle time for both the sleep and power-down mode is determined by the value of the capacitors on the

VRP, VRM and VRN reference bypass pins (pins 43, 44 and 45). These capacitors lose their charge when the ADC

is not operating and must be recharged by on-chip circuitry before conversions can be accurate. For power-down

mode the Exit Cycle time is about 3 ms with the recommended component values. The Exit Cycle time is faster

for sleep mode. Smaller capacitor values allow slightly faster recovery from the power down and sleep mode, but

can result in a reduction in SNR, SINAD and ENOB performance.

Clock Mode Select/Data Format (CLK_SEL/DF)

Single-ended versus differential clock mode and output data format are selectable using this quad-state function

pin. Table 3 shows how to select between the clock modes and the output data formats.

Table 3. Clock Mode and Data Format Selection Table

CLK_SEL/DF Input Voltage Clock Mode Output Data Format

VADifferential 2's Complement

(2/3) * VADifferential Offset Binary

(1/3) * VASingle-Ended 2's Complement

AGND Single-Ended Offset Binary

CLOCK INPUTS

The CLK+ and CLK−signals control the timing of the sampling process. The CLK_SEL/DF pin (pin 8) allows the

user to configure the ADC for either differential or single-ended clock mode. In differential clock mode, the two

clock signals should be exactly 180° out of phase from each other and of the same amplitude. In the single-

ended clock mode, the clock signal should be routed to the CLK+ input and the CLK−input should be tied to

AGND in combination with the correct setting from Table 3.

To achieve the optimum noise performance, the clock inputs should be driven with a stable, low jitter clock signal

in the range indicated in the Electrical Table. The clock input signal should also have a short transition region.

This can be achieved by passing a low-jitter sinusoidal clock source through a high speed buffer gate. This

configuration is shown in Figure 21. The trace carrying the clock signal should be as short as possible and

should not cross any other signal line, analog or digital, not even at 90°. Figure 21 shows the recommended

clock input circuit.

The clock signal also drives an internal state machine. If the clock is interrupted, or its frequency is too low, the

charge on the internal capacitors can dissipate to the point where the accuracy of the output data will degrade.

This is what limits the minimum sample rate.

The clock line should be terminated at its source in the characteristic impedance of that line. Take care to

maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905

(SNLA035) for information on setting characteristic impedance.

It is highly desirable that the the source driving the ADC clock pins only drive that pin. However, if that source is

used to drive other devices, then each driven pin should be AC terminated with a series RC to ground, such that

the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is

(6)

Product Folder Links: ADC11C170

ADC11C170

www.ti.com

SNAS412B –JULY 2007–REVISED APRIL 2013

where tPD is the signal propagation rate down the clock line, "L" is the line length and ZOis the characteristic

impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it

as seen from the clock source. Typical tPD is about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of

"L" and tPD should be the same (inches or centimeters).

The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise

duty cycle is difficult, the ADC11C170 has a Duty Cycle Stabilizer. It is designed to maintain performance over a

clock duty cycle range of 30% to 70%.

DIGITAL OUTPUTS

Digital outputs consist of the 1.8V CMOS signals D0-D10, DRDY, OVR and OGND.

The ADC11C170 has 16 CMOS compatible data output pins: 11 data output bits corresponding to the converted

input value, a data ready (DRDY) signal that should be used to capture the output data, an over-range indicator

(OVR) which is set high when the sample amplitude exceeds the 11-Bit conversion range and three output

ground pins (OGND) which should be ignored except when used for compatibility with a 12 or 14 bit part. Valid

data is present at these outputs while the PD/Sleep pin is low.

Data should be captured and latched with the rising edge of the DRDY signal. Depending on the setup and hold

time requirements of the receiving circuit (ASIC), either the rising edge or the falling edge of the DRDY signal

can be used to latch the data. Generally, rising-edge capture would maximize setup time with minimal hold time;

while falling-edge-capture would maximize hold time with minimal setup time. However, actual timing for the

falling-edge case depends greatly on the CLK frequency and both cases also depend on the delays inside the

ASIC. Refer to the AC Electrical Characteristics table.

Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for

each conversion, the more instantaneous digital current flows through VDR and DRGND. These large charging

current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic

performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will

reduce this problem. Additionally, bus capacitance beyond the specified 5 pF/pin will cause tOD to increase,

reducing the setup and hold time of the ADC output data. The result could be an apparent reduction in dynamic

performance.

To minimize noise due to output switching, the load currents at the digital outputs should be minimized. This can

be done by using a programmable logic device (PLD) such as the LC4032V-25TN48C to level translate the ADC

output data from 1.8V to 3.3V for use by any other circuitry. Only one load should be connected to each output

pin. The outputs of the ADC11C170 have 40Ωon-chip series resistors to limit the output currents at the digital

outputs. Additionally, inserting series resistors of about 22Ωat the digital outputs, close to the ADC pins, will

isolate the outputs from trace and other circuit capacitances and limit the output currents, which could otherwise

result in performance degradation. See Figure 21.

Product Folder Links: ADC11C170

AGND

ADC11C170

0.01 PF

(LSB) D0

OGND

46 VREF

0.1 PF

+3.3V from

Regulator

49.9

VRM

VRN

VRP

Flux XFMR: ADT1-1WT or ETC1-1T

Balun XFMR: ADT1-12 or ETC1-1-13

(See ADC11C125 8VHU¶V*XLGHIRU

other Input Network Configurations)

0.1 PF

33.2

0.1 PF

VIN-

VIN+

CLK_SEL/DF

CLK+

CLK_SEL/DF PD/Sleep

PD/Sleep

15 pF

0.1 PF

10 PF

0.1 PFD9

(MSB) D10

0.1 PF

AGND

DGND

VIN LC4032V-25TN48C

PLD 11-bit

Digital

Output

Word

0.1 PF

OVR

DRDY

0.1 PF10 PF

10 PF

24.9

0.01 PF

AGND

DRGND

VDR

+3.3V from

Regulator +1.8V from

Regulator

24.9

0.1 PF

CLK-

0.1 PF

CLKIN

NC7WV125K8X

High Speed Buffer

0.01 PF

0.1 PF

+1.8V from

Regulator

0.01 PF

0.1 PF

+3.3V from

Regulator

0.1 PF

OGND

0.1 PF

15 pF

ADC11C170

SNAS412B –JULY 2007–REVISED APRIL 2013

www.ti.com

If 14-bit compatibility is not required do not connect pins 17 - 19. If 12-bit compatibility if not required do not connect

pin 19.

Figure 21. Application Circuit using Transformer Drive Circuit.

POWER SUPPLY CONSIDERATIONS

The power supply pins should be bypassed with a 0.1 µF capacitor and with a 0.01 µF ceramic chip capacitor

close to each power pin. Leadless chip capacitors are preferred because they have low series inductance.

As is the case with all high-speed converters, the ADC11C170 is sensitive to power supply noise. Accordingly,

the noise on the analog supply pin should be kept below 100 mVP-P.

No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be

especially careful of this during power turn on and turn off.

The VDR pin provides power for the output drivers and may be operated from a supply in the range of 1.6V to

2.0V. This enables lower power operation, reduces the noise coupling effects from the digital outputs to the

analog circuitry and simplifies interfacing to lower voltage devices and systems. Note, however, that tOD

increases with reduced VDR. A level translator may be required to interface the digital output signals of the

ADC11C170 to non-1.8V CMOS devices.

LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining

separate analog and digital areas of the board, with the ADC11C170 between these areas, is required to achieve

specified performance.

The ground return for the data outputs (DRGND) carries the ground current for the output drivers. The output

current can exhibit high transients that could add noise to the conversion process. To prevent this from

happening, the DRGND pins should NOT be connected to system ground in close proximity to any of the

ADC11C170's other ground pins.

Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor

performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the

clock line as short as possible.

Product Folder Links: ADC11C170

ADC11C170

www.ti.com

SNAS412B –JULY 2007–REVISED APRIL 2013

The effects of the noise generated from the ADC output switching can be minimized through the use of 22Ω

resistors in series with each data output line. Locate these resistors as close to the ADC output pins as possible.

Since digital switching transients are composed largely of high frequency components, total ground plane copper

weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area

is more important than is total ground plane area.

Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in

high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to

keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the

generally accepted 90° crossing should be avoided with the clock line as even a little coupling can cause

problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to

degradation of SNR. Also, the high speed clock can introduce noise into the analog chain.

Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the

signal path through all components should form a straight line wherever possible.

Be especially careful with the layout of inductors and transformers. Mutual inductance can change the

characteristics of the circuit in which they are used. Inductors and transformers should not be placed side by

side, even with just a small part of their bodies beside each other. For instance, place transformers for the analog

input and the clock input at 90° to one another to avoid magnetic coupling.

The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.

Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to

the reference input pin and ground should be connected to a very clean point in the ground plane.

All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed in the analog area of

the board. All digital circuitry and dynamic I/O lines should be placed in the digital area of the board. The

ADC11C170 should be between these two areas. Furthermore, all components in the reference circuitry and the

input signal chain that are connected to ground should be connected together with short traces and enter the

ground plane at a single, quiet point. All ground connections should have a low inductance path to ground.

DYNAMIC PERFORMANCE

To achieve the best dynamic performance, the clock source driving the CLK input must have a sharp transition

region and be free of jitter. Isolate the ADC clock from any digital circuitry with buffers, as with the clock tree

shown in Figure 22 . The gates used in the clock tree must be capable of operating at frequencies much higher

than those used if added jitter is to be prevented. Best performance will be obtained with a single-ended drive

input drive, compared with a differential clock.

As mentioned in Layout and Grounding, it is good practice to keep the ADC clock line as short as possible and to

keep it well away from any other signals. Other signals can introduce jitter into the clock signal, which can lead to

reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90° crossings

have capacitive coupling, so try to avoid even these 90° crossings of the clock line.

Figure 22. Isolating the ADC Clock from other Circuitry with a Clock Tree

Product Folder Links: ADC11C170

ADC11C170

SNAS412B –JULY 2007–REVISED APRIL 2013

www.ti.com

REVISION HISTORY

Changes from Revision A (April 2013) to Revision B Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 25

Product Folder Links: ADC11C170

PACKAGE OPTION ADDENDUM

www.ti.com 16-Aug-2014

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

ADC11C170CISQ/NOPB ACTIVE WQFN RHS 48 TBD Call TI Call TI -40 to 85 ADC11C170

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 16-Aug-2014

Addendum-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products Applications

Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive

Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications

Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers

DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps

DSP dsp.ti.com Energy and Lighting www.ti.com/energy

Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial

Interface interface.ti.com Medical www.ti.com/medical

Logic logic.ti.com Security www.ti.com/security

Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com

Wireless Connectivity www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265