W536030T/060T/090T/120T
VOICE/MELODY/LCD CONTROLLER
(ViewTalk TM Series)
Publication Release Date: April 15, 2005
- 1 - Revision
A9
Table of Contents-
1. GENERAL DESCRIPTION ...........................................................................................2
2. FEATURES.....................................................................................................................3
3. BLOCK DIAGRAM.......................................................................................................5
4. PAD DESCRIPTION ......................................................................................................6
5. ELECTRICAL CHARACTERISTICS.........................................................................12
5.1 Absolute Maximum Ratings .............................................................................12
5.2 DC Characteristics ............................................................................................12
5.3 AC Characteristics ............................................................................................16
6. TYPICAL APPLICATION CIRCUITS ........................................................................20
6.1 Sub Clock with RC Mode.................................................................................20
6.2 Sub Clock with Crystal Mode...........................................................................21
7. REVISION HISTORY..................................................................................................22
W536030T/060T/090T/120T
- 2 -
1. GENERAL DESCRIPTION
The W536XXXT, a member of ViewTalkTM family, is a high-performance 4-bit micro-
controller (uC) with built-in speech unit, melody unit and 64seg * 32 com LCD driver unit
which includes internal regulator,pump circuit and dedicated two pages LCD RAM. The 4-bit
uC core contains dual clock source, 4-bit ALU, two 8-bit timers, one 14 bits divider,
maximum 24 pads for input or output, 8 interrupt sources and 8-level nesting for
subroutine/interrupt applications. Speech unit, integrated as a single chip with maximum 128
seconds (based on 6.4K sample rate with 5 bits MDPCM), is capable of expanding to 512
seconds speech addressed by external memory W55XXX with serial bus interface.
It can be implemented with Winbond Power Speech using MDPCM algorithm. Melody unit
provides dual tone output and can store up to 1k notes. Power reduction mode is also built in
to minimize power dissipation. It is ideal for games, educational toys, remote controllers,
watches, clocks and other application products which incorporate both LCD display and
speech.
BODY W536030T W536060T W536090T W536120T
Voice 30 sec 60 sec 90 sec 120 sec
I/O pad 4I/O, 4I
(RA/RD)
4I/O, 8I
(RA/RC/RD)
8I/O, 8I, 8O
(RA/RB/RC/RD/RE/RF)
8I/O, 8I, 8O
(RA/RB/RC/RD/RE/RF)
WDT disable/Enable
(Mask Option) Y Y Y Y
Sub-clock
RC/XTAL mode
(Mask Option)
Y Y Y Y
RD port shared as
serial bus
(Mask Option)
Y(1) Y(1) N N (2)
Tri-state serial bus
(Mask Option) ( 3) Y Y Y Y
Cascaded Voice ROM
through serial bus (2) Y(1) Y(1) N Y
Notes:
(1). Share 3 pads of RD port (RD1/CLK, RD2/DATA and RD3/ADDR)
(2). Dedicate serial bus 3 pads (CLK, DATA and ADDR) to interface with W55XXX. Cascaded Voice ROM can help user to expand voice
up to 512 sec by W55XXX chip.
(3). Tri-state serial bus mask option can float serial bus while voice playing is no active. Let this mask option is disabled to get minimum
power consumption in general.
W536030T/060T/090T/120T
Publication Release Date: April 15, 2005
- 3 - Revision A9
2. FEATURES
• Operating voltage: 2.4 volt ~ 5.5 volt
• Watch dog disabled/enabled by mask option
• Dual clock operating system
− Main clock with Ring/Crystal (400 KHz to 4 MHz)
− Sub-clock with 32.768 KHz RC/Crystal by mask option
• Memory
− Program ROM (P-ROM): 64K × 20 (ROM Bank0, 1, 2, 3, 4, 5, 6)
− Data RAM (W-RAM): 1.4K × 4 bit
(RAM Bank 0 is 896 nibbles from 0: 000~0:37F and 0: 380~0:3FF are mapped to special register.
RAM Bank F is 512 nibbles from F: 200~F: 3FF either data RAM or dedicated to script kernel)
− LCD RAM (L-RAM): 512 × 4 bit × 2 pages (RAM Bank1, 2 from 200~3FF)
• Maximum 24 input/output pads
− Ports for input only: 8 pads (RC, RD port; RD1~3 can share as serial bus for external memory
W55XXX interface @W536030T/060T)
− Ports for output only: 8 pads (RE & RF port; W536090T/120T available only)
− Ports for Input/output: 8 pads (RA and RB port; RB port is available for W536090T /W536120T
only)
• Power-down mode
− Hold mode (except for 32KHz oscillator)
− Stop mode (including 32KHz oscillator and release by RD or RC port)
• Eight types of interrupts
− Five internal interrupts (Divider, Timer 0, Timer 1, Speech, Melody)
− Three external interrupts (Port RC, RD, RA)
• One built-in 14-bit clock frequency divider circuit
• Two built-in 8-bit programmable countdown timers
− Timer 0: one of two clock sources (FOSC/4 or FOSC/1024) can be selected
− Timer 1: built-in auto-reload function includes internal timer, external event counter from RC.0
• Built-in 18/14-bit watchdog timer for system reset.
• Powerful instruction sets
• 8-level subroutine (including interrupt) nesting
• LCD driver unit capability
− VLCD higher than (VDD -0.5V)
− Built-in voltage regulator to V2 pad
− 64 seg × 32 com
− 1/32 or 1/16 duty, 1/5 or 1/4 bias, internal pump circuit option by special register
− COM24~ 31 and SEG40~63 can be shared as general input/output by special register
− Either uC ROM or voice ROM used as LCD picture
• Speech function
− Provided 1M / 2M/ 3M/ 4M bits Voice ROM for W536030T/060T/090T/120T based on 5 bits
MDPCM algorithm
− Voice ROM (V-ROM) available for uC data or LCD picture data.
− Maximum 8*256 Label/Interrupt vector (voice section number) available
− Provide two types of speech busy flag to either each GO or each trigger
− Maximum up to 16M bits speech address capability interface with external memory W55XXX
W536030T/060T/090T/120T
- 4 -
through serial bus.
• Melody function
− Provide 1K notes (22bits/note) dedicated melody ROM
− Provide two types of melody busy flag to uC either each note or each song
− Provide 6 kinds of beat, 16 kinds of tempo, and pitch range from G3# to C7
− Tremolo, triple frequency and 3 kinds of percussion available
− Maximum 31 songs available
• Can mix speech with melody
• Multi-engine controller
• Direct driving speaker/buzzer or DAC output
• Chip On Board available
W536030T/060T/090T/120T
Publication Release Date: April 15, 2005
- 5 - Revision A9
3. BLOCK DIAGRAM
XIN XOUT X32I X32O
LCD DRIVER
PC
STACK
(8 Levels)
Timer 0
Timing
Generator
SEG0~63 V3,V4,V5,V6
Timer 1
Watch Dog
ALU
ACC
Divide
ROM
64K*20Bit
DH1,DH2
COM0~31
LCD RAM
512*4*2 bit
Data RAM
1.4K*4 bit
Special Register
HCF
HEFIEF EVF
FLAG1 PSR0MR0
PEF
FLAG0
LPX3
PM0
LPX2LPX0 LPX1
PORT RA
VLCD PUMP &
REGULATOR
TONE
RA0~3
RES
LPX4
PORT RC
PORT RD
RC0~3
RD0~3
LPX5 LPY0 LPY1
SPC MLD
Dual
Tone
melody
(1K notes)
MLD_play
MLD_busy
Speech
MDPCM
core
SPC_play
SPC_busy
PWM1/DAC
ROSC
Parallel
to Serial
Interrupt ,Hold & Stop
Control
RE0~3
RF0~3
PORT RB RB0~3
PORT RE
PORT RF
ADDR
CLK
DATA
V2
VDDA
VDD
VSS
VSSP
TEST
Voice ROM
(1M /2M/3M/4M bits) PWM/DAC
Mix
Block
PWM2
VDDP
LPXY
VSSA
Shared_ROM Data
W536030T/060T/090T/120T
- 6 -
4. PAD DESCRIPTION
SYMBOL I/O FUNCTION
XIN/RXIN I
Input pad for main clock oscillator. It can be connected to crystal
when crystal mode is selected (SCR0.2 = 1), otherwise connect a
resistor to VDD to generate main system clock while Ring mode is
selected (SCR0.2 = 0 and default). Oscillator can be enabled or
stopped by set SCR0.1 to 1 or clear to 0 separately. External
capacitor connects to start oscillation and get more accurate clock
when crystal mode
XOUT O
Output pad for oscillator which is connected to another crystal
pad when in crystal mode. External capacitor connects to start
oscillation when in crystal mode.
X32I/RSUB1 I
32.768 KHz crystal input pad or external resistor node 1 by
mask option. External 15~20pF capacitor connects to start
oscillation and get more accurate clock when in crystal mode.
X32O/RSUB2 O
32.768 KHz crystal output pad or external resistor node 2 by
mask option. External 15~20pF capacitor connects to start
oscillation when in crystal mode.
RA0 ~
RA3/TONE
(8)
I/O
General Input/Output port specified by PM1 register. If output
mode is selected, PM0 register bit 0 can be used to specify
CMOS/NMOS driving capability option. Initial state is input
mode. RA3 may be uses as TONE if bit 0 of MR0 special register
is set to logic 1. An interrupt source.
RB0 ~ RB3
(8) I/O
General Input/Output port specified by PM2 register. If output
mode is selected, PM0 register bit 1 can be used to specify
CMOS/NMOS driving capability option. Initial state is input
mode (W536090T /W536120T only.)
RC0 ~ RC3
I
4-bit schmitter input with internal pull high option specified by
PM3 register bit 2. Each pad has an independent interrupt
capability specified by PEFL special register. Interrupt and STOP
mode wake up source. RC0 is also the external event counter
source of Timer1. (W536060T/090T/120T only.)
RD0
RD1/CLK
RD2/DATA
RD3/ADDR
(4)
I
4-bit schmitter input port with internal pull high option specified
by PM3 register bit 3. Each pad has an independent interrupt
capability specified by PEFH special register. Interrupt and STOP
mode wake up source. RD1~3 will be shared as the external
memory W55XXX interface pads while RD port shared as serial
bus mask option is enabled @W536030T/060T.
W536030T/060T/090T/120T
Publication Release Date: April 15, 2005
- 7 - Revision A9
RE0~RE3
(8) O Output port only. PM3 register bit 0 can be used to specify
CMOS/NMOS driving capability option. (W536090T/120T only)
RF0~RF3
(8)
O Output port only. PM3 register bit 1 can be used to specify
CMOS/NMOS driving capability option. (W536090T/120T only)
RES I System reset pad, active low with internal pull-high resistor.
W536030T/060T/090T/120T
- 8 -
PAD Description, continued
SYMBOL I/O FUNCTION
TEST I Test pad. Active high with internal pull low resistor.
ROSC I
Connect resistor to VDD pad to generate speech or melody
playing clock source.
PWM1/DAC O
While speech or melody is active, PWM1/DAC is speaker direct
driving output or DAC output controlled by voice output file.
PWM2 O
While speech or melody is active, PWM2 is another speaker
direct driving output.
ADDR (5) O
External serial memory address write clock for voice extension
(W536120T only). The “Tri-sate serial bus” mask option can use
tri-sate WRP pad while external voice ROM is not available.
Default that mask option is disabled and fixes WRP pad state
while external voice is not enabled to get chip low power
consumption.
CLK (5) O
External serial memory address read clock for voice extension.
(W536120T only). The pad state is same as WRP pad depended
on “Tri-sate serial bus” mask option.
DATA (5) I/O
External serial memory data in/out for voice extension
(W536120T only). The pad state is same as WRP pad depended
on “Tri-sate serial bus” mask option.
SEG0−SEG39 O Dedicated LCD segment output pads.
SEG40/PORTN.
0
SEG43/PORTN.
3
O/O LCD segment output pads, and can be shared as general output
by register LCDM3 bit 1. Default function is segment pad.
SEG44/PORTM
.0
SEG47/PORTM
.3
O/I
LCD segment output pads, and can be shared as general input by
register LCDM3 bit 0. Default function is segment pad and
PM5.1=0 to inhibit LCD waveform abnormal.
SEG48/PORTL.
0
SEG51/PORTL.
3
O/O LCD segment output pads, and can be shared as general output
by register LCDM2 bit 3. Default function is segment pad.
W536030T/060T/090T/120T
Publication Release Date: April 15, 2005
- 9 - Revision A9
SEG52/PORTK.
0
SEG55/PORTK.
3
O/I
LCD segment output pads, and can be shared as general input by
register LCDM2 bit 2. Default function is segment pad and
PM5.0 = 0 to inhibit LCD waveform abnormal.
SEG56/PORTJ.
0
SEG59/PORTJ.
3
O/I
O
LCD segment output pads, and can be shared as general
input/output by register LCDM2 bit 1. PM4 register is used
to select input or output while shared I/O function is active.
Default function is segment pad and PM4.3 = 0 to inhibit
LCD waveform abnormal.
SEG60/PORTI.0
SEG63/PORTI.3
O/I
O
LCD segment output pads, and can be shared as general
input/output by register LCDM2 bit 0. PM4 register is used to
select input or output while shared I/O function is active. Default
function is segment pad and PM4.2 = 0 to inhibit LCD waveform
abnormal.
W536030T/060T/090T/120T
- 10 -
PAD Description, continued
SYMBOL I/O FUNCTION
COM0−COM15 O
LCD common signal output pads either 1/32 duty or 1/16 duty.
The LCD frame rate is controlled by LCDM1 register, and default
value LCDM1 = 0111b with 64Hz frame rate.
COM16−COM2
3 O
LCD common signal output pads while 1/32 duty is active. The
LCD frame rate is controlled by LCDM1 register, and default
value LCDM1 = 0111b with 64Hz frame rate.
COM24/PORTP.
0
COM27/PORTP.
3
O/O
LCD common signal output pads, or shared as general output by
register LCDM3.2 when in 1/16 duty mode. Default function is
common function.
COM28/PORTO
.0
COM31/PORTO
.3
O/I
LCD common signal output pads, or shared as general input by
register LCDM3.2 when in 1/16 duty mode. Default function is
common function and PM5.2 = 0 to inhibit LCD waveform
abnormal.
DH1, DH2 (6) O
Connection terminal for voltage double capacitor with 0.1uF. The
DH2 connects to capacitor positive node and DH1 negative node
if polar capacitor is used.
V3 ~ V6 (6) O LCD COM/SEG output driving voltage. Need an external 0.1uF
capacitor to every pad terminal.
V2 (6) I/O
Voltage regulator output pad. An external capacitor is a must.
Output level can be controlled from 0~Fh by LCDM4 register. If
internal pump is enabled (LCDM3.3 = 0 and default value), LCD
operating voltage (VLCD) will be 4*V2 or 5*V2 depending on
1/4 bias or 1/5 bias. A limitation should be noted that VLCD
must be higher than (VDD -0.5v) to avoid chip leakage current.
While external reference voltage is selected (LCDM3.3 = 1), V2
pad input voltage can not be over 1.5 Volt to inhibit chip damage.
VSSP I Power ground for PWM or DAC playing output.
VSSA (7) I Power ground. (For w536090/120T only)
VSS I Power ground
VDDP I Power source for PWM or DAC playing output.
VDDA (7) I Power source. (For w536090/120T only)
W536030T/060T/090T/120T
Publication Release Date: April 15, 2005
- 11 - Revision A9
VDD I Power source.
Notes:
(4). RD1~3 are shared as CLK/DATA/ADDR to interface with W55XXX @W536030T/060T
(5). @W536120T only
(6). 0.1uF is default value, and capacitor value should be larger than 0.1uF if LCD dot size over 0.5mm*0.5mm.
(7). External application circuit should connect together, please refer to APPLICATION CIRCUIT. To sure chip operation properly, please
bond all VDDP, VDDA, VDD, VSSP, VSS and VSSA pads and connect VSSP, VSS from chip outside PCB circuit. VSSA and VDDA are for
W536090/120T only
(8). When working at NMOS open drain mode, external pull high voltage can't higher than VDD to avoid leakage current.
W536030T/060T/090T/120T
- 12 -
5. ELECTRICAL CHARACTERISTICS
5.1 Absolute Maximum Ratings
PARAMETER RATING UNIT
Supply Voltage to Ground Potential -0.3 to +7.0 V
Applied Input/Output Voltage -0.3 to +7.0 V
Power Dissipation 120 mW
Ambient Operating Temperature 0 to +70 °C
Storage Temperature -55 to +150 °C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
5.2 DC Characteristics
(VDD−VSS = 3.0V, No load, FM = 4 MHz with Ring mode, Fs = 32.768 KHz, with Xtal mode, TA = 25° C, STN LCD panel on with dot size
0.5mm*0.5mm; unless otherwise specified)
PARAMETER SY
M. CONDITIONS MI
N. TYP. MA
X.
UNI
T
Op. Voltage VDD 2.4 5.5 V
Op. Current IOP1 Dual clock with
crystal - 600 700
µA
(No Load, no Voice, Dual clock with Ring
type 600 700
No Melody) Sub-clock only, LCD
off 40 50
Sub-clock only, LCD
on 70 90
Hold Mode Current
(No Load, LCD OFF) IOP2 Sub-clock active only 6 10 µA
Hold Mode Current
(No load, LCD ON) IOP3 Sub-clock active only 70 µA
Stop Mode Current IOP4 LCD auto off 1 µA
CLK/ADDR Output High
Current IoH1 Vout = 2.7V -0.8 mA
CLK/ADDR Output low
Current IoL1 Vout = 0.4V 0.8 mA
W536030T/060T/090T/120T
Publication Release Date: April 15, 2005
- 13 - Revision A9
Input Low Voltage VIL - VSS - 0.3 VDD
Input High Voltage VIH - 0.7 - 1 VDD
Port RA, RB, RE, RF
Output Low Voltage VABL I
OL = 2.0 mA - - 0.4 V
Port RA, RB, RE, RF
Output High Voltage VABH I
OH = -2.0 mA 2.4 - - V
W536030T/060T/090T/120T
- 14 -
DC Characteristics, continued
PARAMETER SYM
. CONDITIONS MI
N TYP MA
X
UNI
T
Pull-up Resistor RCD Port RC, RD 200 300 400 KΩ
Share Output RI, RJ, RL,
RN, RP Sink Current IOL3 VOL = 0.4V -300 uA
RES Pull-up Resistor RRES - 50 100 200
KΩ
PWM1/2 Source Current
(9) ISPH Volume Option = 00 -20 mA
(RLOAD = 8Ω between
PWM1 Volume Option = 01 -70
And PWM2) Volume Option = 10 -110
Volume Option = 11 -135
PWM1/2 Sink Current (9) ISPL Volume Option = 00 20 mA
(RLOAD = 8Ω between
PWM1 Volume Option = 01 70
And PWM2) Volume Option = 10 110
Volume Option = 11 135
DAC output Current IDAC V
DD = 3v, RL=100ohm -4 -5 -6 mA
LCD Supply Current ILCD No Load, All Seg. ON - 50 - µA
COM/SEG On Resistor RON IOH = ±50 µA 5K 10K Ω
V2 Pad Output Voltage VRR Depended on LCDM4 0.7 1.45 V
V2 Pad Output Deviation
(10) VD1 No Load ±5 %
V2 Pad Voltage Step VR2 LCDM4 increased 1 50 mV
V6 Pad Output Voltage
(LCD's VLCD depended
on
VLCD 1/4 Bias & no load
3.8
*
V2
3.85
* V2
3.9
* V2 V
LCDM4 register) (10) 1/5 Bias & no load
4.75
*
V2
4.8
* V2
4.85
* V2
V2 Input Voltage VEXT LCDM3.3 = 1 1.5 V
W536030T/060T/090T/120T
Publication Release Date: April 15, 2005
- 15 - Revision A9
Notes:
(9) PWM current deviation will be ±20%.
(10) VLCD deviation is governed by LCD dot size. More larger LCD dot will get larger deviation.
W536030T/060T/090T/120T
- 16 -
5.3 AC Characteristics
(VDD−VSS = 3.0V, No load, FM = 4 MHz with Ring mode, Fs = 32.768 KHz, with Xtal mode, TA = 25° C, STN LCD on with dot size
0.5mm*0.5mm; unless otherwise specified)
PARAMETER SYM. CONDITIONS MIN
. TYP. MA
X.
UNI
T
Sub-clock Frequency FSUB
Crystal type and X32IN
and X32O with 17pF
external cap.
32768 Hz
Main-clock Frequency FM Ring type/Crystal type 400
K - 4M Hz
Chip Operation
Frequency FOSC SCR0.0 = 1, FSYS =
FSUB 32768 Hz
SCR0.0 = 0; FSYS =
FMAIN
400
K - 4M
Instruction Cycle Time TCYC One machine cycle - 4/FOSC - S
Reset Active Width TRAW FOSC = 32.768 KHz 1 - - µS
Interrupt Active Width TIAW FOSC = 32.768 KHz 1 - - µS
Main clock Ring
frequency FRXIN RXIN = 680KΩ 1M Hz
(11) RXIN = 330K Ω 2M
RXIN = 200KΩ 3M
RXIN = 130KΩ 4M
Sub-Clock RC Oscillator FRSUB RSUB = 680KΩ 32 KHz
Sub-Clock Oscillation
Stable Time @ Cold
Start
FSTOP RSUB = 680KΩ
0.8 1 S
Frequency Deviation of
main-clock FRXIN ≤
2MHz
∆f
f
f(3V) f(2.4V)
f(3V)
− 10 %
Frequency Deviation of
main-clock FRXIN =
3MHz
∆f
f
f(3V) f(2.4V)
f(3V)
− 15 %
Frequency Deviation of
main-clock FRXIN = 4
∆f
f
f(3V) f(2.4V)
f(3V)
− 20 %
W536030T/060T/090T/120T
Publication Release Date: April 15, 2005
- 17 - Revision A9
MHz
ROSC Frequency FROSC ROSC = 680KΩ 3 MHz
Frequency Deviation of
FROSC = 3MHz
∆f
f
f(3V) f(2.4V)
f(3V)
− 7.5 %
Frame frequency FLCD LCDM1 = 0111 b (default) 64 Hz
Notes:
(11). The deviation will be +20% while VDD drops from 5.5V to 2.4V based on same resistor
W536030T/060T/090T/120T
- 18 -
Iop Vs. Main clock RC mode
0
200
400
600
800
1000
1234
Freq (MhZ)
Iop (uA)
3V
4.5V
Oscillation Freq Vs. Sub-Clock
20
24
28
32
36
40
44
560 620 680 750 820 1K
Rsub (Kohm)
Fsub (KhZ)
3V
4.5V
W536030T/060T/090T/120T
Publication Release Date: April 15, 2005
- 19 - Revision A9
Main Freq Vs. Rxin
0
1
2
3
4
5
6
130 150 160 200 330 680 2K 3K
RXIN (Kohm)
Fmain
(MhZ)
2.4V
3v
4.5V
5.5V
Voice Operating Freq. Vs. ROSC
2
2.5
3
3.5
4
4.5
470 560 680 910
ROSC (Kohm)
Freq (MhZ)
3V
4.5V
W536030T/060T/090T/120T
- 20 -
6. TYPICAL APPLICATION CIRCUITS
6.1 Sub Clock with RC Mode
1/5 Bias 1/32 Duty
VDDP
VDDP
DH1
SEG0~63
RES
VDD
PWM2
ADDR/RD3
V6
V2
___
DATA/RD2
V3
X32IN
Rosc
DH2
W536XXXT
VSS
PWM1/DAC
XIN
COM0~31
V5
VSSP
X32IO
VDDP
CLK/RD1
V4
C1
C11
C2
Battery
SPEAKER
C13
C5
R5
C4
470
SWITCH
C12
R3
Q1
8050
R1
C10
C3
R4
SPEAKER
C6
C14
C9
R2
(*1)
(*2)
(*3)
(*4)
64SEG*32COM
LCD Panel
VLCD>VDD-0.5V
(*4)
(*5)
VDDP
W55MXX
VSSA
VDDA
COMPONENT C1 C2~C4 C5~C6 C7~C8 C9~C14 R1 R2 R3 R4
Value 4.7uF 0.1uF 100pF - 0.1~1uF 680KΩ 680KΩ
650KΩ/1MHz
350KΩ/2MHz
225KΩ/3MHz
160KΩ/4MHz
100Ω
Notes:
1. C9~C14 depends on LCD panel dot size.
2. Option R5 equals to 100Ω if high noise immunity is needed.
3. For DAC option application.
4. To ensure that three batteries function well in W536F20 demo board. C6 should stay close to pad PWM/PWM2 at its best. Under the
mask ROM version, C5 and C6 can be skipped.
5. Sure chip operation properly, please bond all VDDP, VDD, VDDA, VSSA, VSSP and VSS; and connect VSSP pad to VSS from external PCB
circuit. VSSA and VDDA are for W536090T/120T only.
W536030T/060T/090T/120T
Publication Release Date: April 15, 2005
- 21 - Revision A9
6.2 Sub Clock with Crystal Mode
1/5 Bias 1/16 Duty
VDDP
VDDP
VDD
XIN
X32IO
X32IN
___
RES
PWM1/DAC
CLK/RD1
DATA/RD2
ADDR/RD3
VSS
VSSP
W536XXXT
Rosc
COM0~15
SEG0~39
PWM2
V6
DH2
DH1
SPEAKER
SPEAKER
R1
R4
C3
R5
Q1
8050
SWITCH
470
C4
R3
C5
C6
Battery
C2
C1
C14
C13
32K
C7
C8
(*3)
(*1)
(*2)
(*4)
(*5)
(*4)
64SEG*16COM
LCD Panel
VLCD>VDD-0.5V
VDD
VDDP
W55MXX
V2
C9
V3
C10
V4
C11
V5
C12
VSSA
VDDA
COMPONENT C1 C2~C4 C5~C6 C7~C8 C9~C14 R1 R2 R3 R4
Value 4.7uF 0.1uF 100pF 15-30PF 0.1~1uF 680KΩ -
650KΩ/1MHz
350KΩ/2MHz
225KΩ/3MHz
160KΩ/4MHz
100Ω
Notes:
1. C9~C14 depends on LCD panel dot size.
2. Option R5 equals to 100Ω if high noise immunity is needed.
3. For DAC option application.
4. To ensure that three batteries function well in W536F20 demo board. C6 should stay close to pad PWM/PWM2 at its best. Under the
mask ROM version, C5 and C6 can be skipped.
5. Sure chip operation properly, please bond all VDDP, VDD, VDDA, VSSA, VSSP and VSS; and connect VSSP pad to VSS from external PCB
circuit. VSSA and VDDA are for W536090T/120T only.
W536030T/060T/090T/120T
- 22 -
7. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
A2 Aug. 10, 1999 - • MASK option
A3 Aug. 23,1999 - • W536060A to 12io only, and external
speech shared RD port except
W536120X Part No
A4 April 13, 2000 - • Modify some errors and add "Tri-state
serial bus" mask option and cascaded
voice ROM function
A5 Sep. 10, 2000 - • Add Application Circuit
A6 Dec. 15, 2000 - • Add AC Picture
A7 May 22, 2001 - • Application circuit modify
A8 May 21, 2003 - • Application circuit modify
• Melody Function
A9 APRIL 15, 2005 23 ADD IMPORTANT NOTICE
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Further more, Winbond products are not intended for applications wherein failure of Winbond
products could result or lead to a situation wherein personal injury, death or severe property or
environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
W536030T/060T/090T/120T
Publication Release Date: April 15, 2005
- 23 - Revision A9
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
Winbond Electronics Corporation America
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
Winbond Electronics (H.K.) Ltd.
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
FAX: 852-27552064
Unit 9-15, 22F, Millennium City,
TEL: 852-27513100
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Winbond Electronics (Shanghai) Ltd.
200336 China
FAX: 86-21-62365998
27F, 2299 Yan An W. Rd. Shanghai,
TEL: 86-21-62365999
Winbond Electronics Corporation Japan
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
FAX: 81-45-4781800
7F Daini-ueno BLDG, 3-7-18
TEL: 81-45-4781881
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
