AS1526, AS1527 1 0 - B i t , S i n g l e S u p p l y, L o w - P o w e r, 7 3 k s p s A / D C o n v e r t e r s 1 General Description 2 Key Features The AS1526/AS1527 are low-power, 10-bit, 73ksps analog-to-digital (A/D) converters specifically designed for single-supply A/D applications. Superior AC characteristics, very low power consumption, and robust packaging make these ultra-small devices perfect for battery-powered analog-data collection devices. 10-Bit Resolution with 7.5s Conversion Time The integrated successive-approximation register (SAR) and a fast (1.5s) sampling track/hold time provide an economic and highlyreliable A/D conversion solution. Internal 2.5V Reference (AS1526) Sampling Rate: 73ksps Straight Binary (Unipolar) Data Format Single-Supply Operation:+2.7V to +3.6V Low Power-Consumption: - The AS1526/AS1527 operate from a single 2.7 to 3.6V supply. The AS1527 requires an external reference, using less power than the AS1526, however, the AS1526 features an internal 2.5V reference. As with the AS1527, the AS1526 can also be used with an external reference, which uses the input range 0V to VREF, including the positive supply range. Integrated Track/Hold Amplifier Internal Clock The AS1527 consumes only 3mW (VDD = 3V) at the 73ksps maximum sampling speed. Both devices feature a low-current (0.3A) shutdown mode, which reduces power consumption at slower throughput rates. Data accesses are made via the standard, high-speed 3-wire serial interface, which is SPI-, QSPI-, and Microwire-compatible. Both devices contain an internal clock, however, both devices also support an external clock for increased flexibility. The AS1526/AS1527 are available in an 8-pin SOIC-150 package. 4mW (73ksps, AS1526) 3mW (73ksps, AS1527) 66W (1ksps, AS1527) 1W (Shutdown Mode) SPI/QSPI/Microwire 3-Wire Serial Interface Operating Temperature Range: -40 to +85C 8-pin SOIC-150 Package 3 Applications The devices are ideal for remote sensors, data-acquisition, data logging devices, lab instruments, or for any other space-limited A/D devices with low power consumption and single-supply requirements. Figure 1. Block Diagram and Pin Assignments 1 AS1526/AS1527 VDD 7 Output Shift Register CSN 8 VDD 1 DOUT AIN 2 SCLK 3 SHDNN 2 AIN 4 REF www.ams.com Control Logic Internal Clock SHDNN 3 Track/Hold 10-Bit SAR REF 4 2.5V Ref 8 SCLK 6 AS1526/ AS1527 7 CSN 6 DOUT 5 GND 5 GND Revision 1.4 AS1526 only 1 - 20 AS1526/AS1527 Datasheet 4 Pin Assignments Figure 2. Pin Assignments (Top View) VDD 1 AIN 2 8 SCLK AS1526/ AS1527 SHDNN 3 7 CSN 6 DOUT REF 4 5 GND 4.1 Pin Descriptions Table 1. Pin Descriptions Pin Number Pin Name Description 1 VDD Positive Supply Voltage. +2.7 to +3.6V 2 AIN Sampling Analog Input. 0V to VREF range. SHDNN Three-Level Shutdown Input. Pulling this pin low puts the AS1526/AS1527 in shutdown mode, down to 4A (max) supply current. The devices are fully operational with this pin high or floating. Note: For the AS1526, pulling this pin high enables the internal reference; letting this pin float disables the internal reference allowing for the use of an external reference. See also pin 4. 4 REF A/D Conversion Reference Voltage. This pin serves as the internal 2.5V reference output for the AS1526; bypass this pin with a 4.7F capacitor. This pin also serves as the external reference voltage input for the AS1527, or for AS1526 if the internal reference is disabled. Bypass this pin with a minimum of 0.1F when using an external reference. See also pin 3. 5 GND Analog and Digital Ground 6 DOUT Serial Data Output. Data changes state at SCLK's falling edge. Note: This pin is high-impedance when pin CSN is high. 7 CSN Active-Low Chip Select. The falling edge of this pin initiates a conversion. Note: When this pin is high, DOUT is high-impedance. 8 SCLK Serial Clock Input. This pin clocks data out at rates up to 2.1MHz. 3 www.ams.com Revision 1.4 2 - 20 AS1526/AS1527 Datasheet - A b s o l u t e Maximum Ratings 5 Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 4 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter Min Max Units VDD to GND 0.3 +5 V AIN to GND -0.3 VDD + 0.3V V REF to GND -0.3 VDD + 0.3V V Digital Inputs to GND -0.3 VDD + 0.3V V DOUT to GND -0.3 VDD + 0.3V V DOUT Current -25 +25 mA 471 mW Continuous Power Dissipation (TAMB = +70C) Operating Temperature Range -40 +85 C Storage Temperature Range -60 +150 C Package-Body Peak Temperature Moisture Sensitivity Level www.ams.com 260 C 3 Comments Derate 5.88mW/C above +70C The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020C "Moisture/Reflow Sensitivity Classification for non-hermetic Solid State Surface Mount Devices". Represents a max floor lifetime of 168h Revision 1.4 3 - 20 AS1526/AS1527 Datasheet - E l e c t r i c a l Characteristics 6 Electrical Characteristics VDD = +2.7 to +3.6V, 73ksps, fSCLK = 2.1MHz (50% duty cycle); AS1526:4.7F capacitor at REF, AS1527: external reference; VREF = 2.5V applied to REF; TAMB = TMIN to TMAX (unless otherwise specified). Table 3. Electrical Characteristics Symbol DC Accuracy Parameter Conditions Min Typ Max Units 1 Resolution 10 0.5 LSB 1 LSB Offset Error 2 LSB 3 2 LSB Relative Accuracy DNL Bits 2 Differential Non-Linearity Gain Error No missing codes over temperature Gain Temperature Coefficient 1 ppm/C 61 dB -70 dB 70 dB 2.5 MHz 2.5 MHz Dynamic Specifications (10kHz sine-wave input, 0V to 2.5Vp-p, 73ksps, fSCLK =2.1MHz) SINAD Signal-to-Noise + Distortion Ratio THD Total Harmonic Distortion SFDR Spurious-Free Dynamic Range Small-Signal Bandwidth Up to the 5th harmonic -3dB rolloff Full-Power Bandwidth Conversion Rate tCONV Conversion Time tACQ Track/Hold Acquisition Time Throughput Rate tAP 4 Aperture Delay 5.5 fSCLK = 2.1MHz refer to Figure 27 Aperture Jitter 7.5 s 1.5 s 73 ksps 7 ns <50 ps Analog Input Input Voltage Range 0 Input Capacitance VREF 21 V pF Internal Reference (AS1526 only) REF Output Voltage TAMB = +25C 5 2.47 2.50 REF Short-Circuit Current REF Temperature Coefficient Load Regulation CREFBYP 6 2.53 V 45 mA AS1526 30 ppm/C 0 to 0.2mA output load 0.35 mV Capacitive Bypass at REF 4.7 F External Reference (VREF = 2.5V) Input Voltage Range 1.00 Input Current 100 Input Resistance REF Input Current in Shutdown CREFBYP www.ams.com 18 SHDNN = 0V Capacitive Bypass at REF Revision 1.4 V 150 A 25 0.01 0.1 VDD + 50mV k 10 A F 4 - 20 AS1526/AS1527 Datasheet - E l e c t r i c a l Characteristics Table 3. Electrical Characteristics (Continued) Symbol Parameter Conditions Min Typ Max Units Digital Inputs: SCLK, SHDNN, CSN VIH SCLK, CSN Input High Voltage VIL SCLK, CSN Input Low Voltage VHYST SCLK, CSN Input Hysteresis IIN SCLK, CSN Input Leakage CIN SCLK, CSN Input Capacitance VSH SHDNN Input High Voltage VSL SHDNN Input Low Voltage 0.7x VDD V 0.3x VDD 0.2 VIN = 0V or VDD 0.01 7 SHDNN Input Current V V 1 A 15 pF VDD 0.4 V SHDNN = 0V or VDD 1.1 0.4 V 4.0 A VDD 1.1 V VSM SHDNN Input Mid Voltage VFLT SHDNN Voltage, Floating SHDNN = float SHDNN Max Allowed Leakage, Mid Input SHDNN = float 50 ISINK = 5mA 0.4 ISINK = 16mA 0.8 VDD/2 V nA Digital Output: DOUT VOL Output Voltage Low VOH Output Voltage High ISOURCE = 0.5mA IL Tri-State Leakage Current CSN = VDD COUT Tri-State Output Capacitance CSN = VDD VDD 0.5 V V 0.01 7 10 A 15 pF 3.6 V Power Requirements VDD Supply Voltage IDD Supply Current PSR Power-Supply Rejection 2.7 8 Int. Reference (AS1526), VDD = 3.6V 1.4 2.0 External Reference, VDD = 3.6V 1.0 1.4 Shutdown mode, VDD = 3.6V 0.3 2 VDD = VDDMIN to VDDMAX, full-scale input 1 mA A mV 1. Tested at VDD = +2.7V. 2. Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offset have been calibrated. 3. Offset nulled. 4. Achievable with standard timing (see Figure 25 on page 12). 5. Sample tested at 0.1% AQL. 6. External load should not change during conversion for specified accuracy. 7. Guaranteed by design; not subject to production testing. 8. Measured as [VFS(VDDMIN) - VFS(VDDMAX)] with external reference. www.ams.com Revision 1.4 5 - 20 AS1526/AS1527 Datasheet - E l e c t r i c a l Characteristics 6.1 Timing Characteristics VDD = +2.7 to +3.6V, TAMB = TMIN to TMAX (unless otherwise specified). Table 4. Timing Characteristics Parameter Symbol Acquisition Time 1 Conditions Min Typ Max 1.5 tACQ Units s SCLK Falling-to-DOUT Valid tDO Figure 3, CLOAD = 50pF CSN Falling-to-Output Enable tDV CSN Rising-to-Output Disable tTR SCLK Clock Frequency fSCLK 0 SCLK Pulse Width High tCH 200 ns SCLK Pulse Width Low tCL 200 ns SCLK Low-to-CSN Falling Setup Time tCS0 50 ns tSTR 0 ns tCS 240 ns DOUT Rising-to-SCLK Rising 2 CSN Pulse Width 20 200 ns Figure 3, CLOAD = 50pF 240 ns Figure 4, CLOAD = 50pF 240 ns 2.1 MHz 1. To guarantee acquisition time, tACQ is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired 2. Guaranteed by design; not subject to production testing. Figure 3. DOUT Enable-Time Load Circuits +2.7V DOUT 6k CLOAD 50pF 6k DOUT CLOAD 50pF GND DGND High-impedance to VOH and VOL to VOH DGND High-impedance to VOL and VOH to VOL Figure 4. DOUT Disable-Time Load Circuits +2.7V DOUT CLOAD 50pF 6k 6k DOUT DGND GND CLOAD 50pF VOH to high-impedance DGND VOL to high-impedance www.ams.com Revision 1.4 6 - 20 AS1526/AS1527 Datasheet - Ty p i c a l Operating Characteristics 7 Typical Operating Characteristics 1 1 0.8 0.8 0.6 0.6 0.4 0.4 DNL (LSB) . INL (LSB) . VDD = 3.0V, VREF = 2.5V, fSCLK = 2.1MHz, CLOAD = 50pF, TAMB = +25C (unless otherwise specified). Figure 5. Integral Nonlinearity vs. Digital Output Code Figure 6. Differential Nonlinearity vs. Digital Output Code 0.2 0 -0.2 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1 -1 0 256 512 768 1024 0 Digital Output Code 768 1024 Figure 8. FFT @ 10kHz 0 0 Fsample = 80.8ksps NFFT = 16384 -20 Fsample = 80.8ksps NFFT = 16384 -20 -40 FFT (dBC) . -40 FFT (dBC) . 512 Digital Output Code Figure 7. FFT @ 1kHz -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 -160 0 10 20 30 40 0 Input Signal Frequency (kHz) 9.92 9.94 9.89 9.93 ENOB (Bit) . 9.95 9.86 9.83 9.77 9.89 2 2.4 2.8 3.2 3.6 0 Reference Voltage (V) www.ams.com 40 9.91 9.9 1.6 30 9.92 9.8 1.2 20 Figure 10. ENOB vs. Input Signal Frequency 9.95 0.8 10 Input Signal Frequency (kHz) Figure 9. ENOB vs. VREF ENOB (Bit) . 256 10 20 30 40 Frequency (kHz) Revision 1.4 7 - 20 AS1526/AS1527 Datasheet - Ty p i c a l Operating Characteristics Figure 11. Supply Current vs. Supply Voltage Figure 12. Supply Current vs. Temperature 2 1.5 Supply Current (mA) . Supply Current (mA) . 2 Internal Reference 1 External Reference 0.5 0 2.7 3 3.3 1.5 Internal Reference 1 External Reference 0.5 0 3.6 -40 -15 60 85 2 0.75 0.5 0.25 0 2.7 3 3.3 1.5 1 0.5 0 3.6 -40 -15 10 35 60 85 60 85 Temperature (C) Supply Voltage (V) Figure 15. Offset Error vs. Supply Voltage Figure 16. Offset Voltage vs. Temperature 0.3 0.5 0.2 0.4 Offset Error (LSB) . . 35 Figure 14. Shutdown Supply Current vs. Temperature 1 Supply Current (A) . Shutdown Supply Current (A) . Figure 13. Shutdown Supply Current vs. Supply Voltage Offset Error (LSB) 10 Temperature (C) Supply Voltage (V) 0.1 0 -0.1 0.3 0.2 0.1 -0.2 2.7 3 3.3 3.6 0 -40 www.ams.com -15 10 35 Temperature (C) Supply Voltage (V) Revision 1.4 8 - 20 AS1526/AS1527 Datasheet - Ty p i c a l Operating Characteristics Figure 18. Gain Error vs. Temperature 0.2 0.2 0.1 0.1 Gain Error (LSB) . Gain Error (LSB) . Figure 17. Gain Error vs. Supply Voltage 0 -0.1 -0.2 2.7 3 3.3 0 -0.1 -0.2 3.6 -40 -15 35 60 85 Figure 20. Internal Reference Voltage vs. Temperature 2.52 2.51 Internal Reference Voltage (V). Internal Reference Voltage (V) . Figure 19. Internal Reference Voltage vs. Supply Voltage 2.505 2.5 2.495 2.49 2.51 2.5 2.49 2.48 2.7 3 3.3 3.6 -40 -15 10 35 60 85 60 85 Temperature (C) Supply Voltage (V) Figure 21. Integral Nonlinearity vs. Supply Voltage Figure 22. Integral Nonlinearity vs. Temperature 0.5 0.5 0.4 0.4 INL (LSB) . INL (LSB) . 10 Temperature (C) Supply Voltage (V) 0.3 0.2 0.1 0.3 0.2 0.1 0 2.7 3 3.3 3.6 0 -40 www.ams.com -15 10 35 Temperature (C) Supply Voltage (V) Revision 1.4 9 - 20 AS1526/AS1527 Datasheet - D e t a i l e d Description 8 Detailed Description The AS1526/AS1527 analog-to-digital converters have two modes of operation: Normal A/D Conversion Mode - Pulling pin SHDNN high or leaving it open puts the device into normal A/D conversion mode. Shutdown Mode - Pulling pin SHDNN low shuts the device down and reduces supply current below 2A (VDD 3.6V). Note: Pulling pin CSN low starts a conversion. The conversion result is available at pin DOUT in unipolar serial format (see Timing and Control on page 11). Figure 23 shows a basic configuration for the AS1526/AS1527. The integrated input track/hold circuitry and a successive-approximation register (SAR) circuitry convert analog input signals to a digital 10-bit output. No external-hold capacitor is needed for the track/hold circuit. The devices convert analog input signals in the 0V to VREF range in 13s (includes track/hold acquisition time). The AS1526 internal reference is trimmed to 2.5V; the AS1527 requires an external reference. Both devices can accept external reference voltages from 1.0V to VDD. The serial interface requires only three digital lines (at pins SCLK, CSN, and DOUT) and provides a simple microprocessor interface. Figure 23. Operational Diagram 1 +2.7 to +3.6V 4.7F + 8 SCLK VDD 0.1F 2 AIN 3 7 AS1526/ AS1527 SHDNN Reference Input Required for AS1527, Optional for AS1526 CSN 6 DOUT 4 5 REF GND AS1526 - 4.7F AS1527 - 0.1F 8.1 Analog Input Figure 24 illustrates the integrated comparator sampling architecture. The full scale input voltage is set by the voltage at pin REF. Figure 24. Equivalent Input Circuit REF CHOLD 13pF AIN CSWITCH 14pF + - + Sample Switch CHOLD 13pF GND - Comparator RIN - + S&H and DAC CSWITCH includes all parasitics The devices' input tracking circuitry has a 2.5MHz small-signal bandwidth, thus it is possible to under-sample (digitize high-speed transient events) and measure periodic signals with bandwidths exceeding the devices' sampling rate. Note: Anti-aliasing filtering should be used to avoid aliasing of unwanted high-frequency signals into the bandwidth of interest. www.ams.com Revision 1.4 10 - 20 AS1526/AS1527 Datasheet - D e t a i l e d 8.1.1 Description Input Protection Internal protection diodes clamp the analog input to VDD and GND, allowing the input to swing from (GND - 0.3V) to (VDD + 0.3V) without damage. However, for accurate conversions near full scale, the input must not exceed VDD by more than 50mV, or be lower than GND by 50mV. Note: If the analog input exceeds the supply by 50mV, limit the input current to 2mA. 8.2 Track/Hold In track mode, the analog signal is acquired and stored in the internal hold capacitors. During acquisition, the analog input at pin AIN charges capacitor CHOLD (see Figure 24 on page 10). Bringing CSN low ends the acquisition interval and the charge on CHOLD represent the sampled input voltage. In hold mode, the T/H switches are opened thus the input is disconnected from the capacitor CHOLD. During this mode the successive approximation is performed which in turn forms a digital representation of the analog input signal. At the end of the conversion, the input side of the in meantime discharged CHOLD switches back to AIN, and CHOLD charges to the input signal again. The maximum time for the T/H to acquire a signal (tACQ) is a function of how quickly its input capacitance is charged. tACQ increases proportionally to the input signal's impedance, and at higher impedances more time must be allowed between conversions. tACQ is also the minimum time needed for the signal to be acquired, and is calculated by: tACQ = 7(RS + RIN) x 21pF Where: RIN = 4.5k RS = the input signal's source impedance. tACQ is never less than 1.5s. Source impedances < 1k do not significantly affect the AC performance of the devices. (EQ 1) Note: Higher source impedances can be used if a 0.01F capacitor is connected to the analog input. Note that the input capacitor forms an RC filter with the input source impedance, limiting the devices' input signal bandwidth. 8.3 External Clock The AS1526/AS1527 do not require an external clock for analog-to-digital data conversion. This allows the microprocessor to read back the conversion results at any clock rate from up to 2.1MHz at any time. The clock duty cycle is unrestricted if each clock phase is at least 200ns. Note: The external clock must not be run while a conversion is in progress. 8.4 Timing and Control Conversion-start and data-read operations are controlled by digital inputs CSN and SCLK. Refer to Figures 25 - 27 (see page 12) for graphical timing and control information. The falling edge on pin CSN initiates a conversion sequence: 1. 2. 3. 4. 5. 6. 7. 8. The T/H stage holds the voltage at pin AIN, and the A/D conversion begins. Pin DOUT changes from high-impedance to logic-low. SCLK must be kept low during the conversion. The internal SAR stores the data during the conversion process. Pin DOUT going high indicates the conversion process has completed. The rising edge of pin DOUT can be used as a framing signal. SCLK shifts the data out of this register any time after the conversion is complete. DOUT transitions on the falling edge of pin SCLK. The next falling clock edge produces the MSB of the conversion at DOUT, followed by the remaining bits. Since there are 10 data bits and one leading high-bit or 10 data bits, two sub bits, and one leading high-bit, at least 11 or 13 falling clock edges are needed to shift out these bits, respectively. 9. Extra clock pulses occurring after the conversion result has been clocked out, and prior to a rising edge of CSN, produce trailing zeros at DOUT and have no effect on the conversion process. 10. For minimum cycle time, clock out the data with 10.5 clock cycles at full speed using the rising edge of DOUT as the EOC signal. Pull CSN high after reading the conversion's LSB. After the specified minimum time (tCS) CSN can be pulled low to initiate the next conversion. www.ams.com Revision 1.4 11 - 20 AS1526/AS1527 Datasheet - D e t a i l e d Description Figure 25. Serial Interface Standard Cycle Timing Diagram CSN SCLK B9 DOUT Interface Track/Hold Stage Conversion In Progress Idle Track B8 B7 EOC B6 B5 B4 B3 B2 B0 S1 S0 Clock Out Serial Data Hold Trailing 0s Sub Bits Idle Hold Track tCONV 7.5s Cycle Time B1 12.5 x 0.476s = 5.95s 0s 0s tCS 0.24s Total = 13.7s Figure 26. Serial Interface Minimum Cycle Timing Diagram CSN SCLK B9 DOUT Interface Track/Hold Stage Conversion In Progress Idle Track B8 B7 EOC B6 B4 B3 B2 B1 B0 Clock Out Serial Data Hold Idle Hold Track tCONV 7.5s Cycle Time B5 10.5 x 0.476s = 5s 0s tCS 0.24s Total = 12.74s Figure 27. Detailed Serial Interface Timing Diagram tCS CSN tCSO tCH SCLK tDO DOUT tTR tCL tCONV tDV B0 S1 S0 tSTR Internal Track/Hold Track/Acquire Hold Track/Acquire tAP 8.5 Transfer Function The data output from the AS1526/AS1527 is binary (unipolar), and Figure 28 depicts the nominal transfer function. Code transitions occur midway between successive integer LSB values. Note: If VREF = +2.50V, then 1 LSB = 2.44mV (2.50V/1024). www.ams.com Revision 1.4 12 - 20 AS1526/AS1527 Datasheet - D e t a i l e d Description Figure 28. Unipolar Transfer Function 11...111 Full Scale (FS) Transition 11...1110 Full Scale = VREF Zero Scale = 0 1LSB = VREF/1024 Output Code 11....101 00...011 00...010 00...001 00...000 0 1 2 3 FS - 3/2LSB Input Voltage AIN 8.6 Reducing Supply Current Power consumption can be reduced significantly by powering down the devices between conversions. Figure 30 shows a plot of an average supply current versus sampling rate. Wake-up time (tWAKE) can also factor into reduced power consumption. tWAKE is defined as the time from when pin SHDNN is deasserted to the time when a conversion may be initiated (see Figure 29). Figure 29. Shutdown Sequence Timing Diagram Complete Conversion Sequence CSN tWAKE SHDNN DOUT Conversion 0 Power-Up Conversion 1 Shutdown Power-Up For the AS1526 using the internal reference, tWAKE depends on the time in shutdown mode (see Figure 31) since the external 4.7F reference bypass capacitor slowly loses charge during shutdown. The wakeup time for AS1526 and AS1527 using an internal reference are largely dependent on the external reference's power-up time. The wakeup time for the ADC itself from shutdown mode is approximately 4s. www.ams.com Revision 1.4 13 - 20 AS1526/AS1527 Datasheet - D e t a i l e d Description Figure 30. Supply Current vs. Sampling Rate Figure 31. Powerup Time vs. Time in Shutdown 800 10000 Internal Reference . 1000 Internal Reference 100 10 External Reference 3V 1 3V Power-Up delay (s) Supply Current (A) . 700 600 500 400 300 200 100 0.1 0.1 10 1000 0 0.001 100000 0.01 0.1 1 10 Tim e in Shutdown (s ) Sam pling Rate (s ps ) 8.7 Internal 2.5V Reference (AS1526) The AS1526 internal 2.5V reference output is connected to pin REF and also drives the internal DAC (see Figure 24 on page 10). REF output can be used as a reference voltage source for other components and can source up to 400A. The internal reference is enabled by pulling pin SHDNN high. Letting SHDNN float disables the internal reference, which allows the use of an external reference (see External Reference on page 14). Pin REF should be bypassed with a 4.7F capacitor as shown in Figure 23 on page 10. Larger capacitors increase wake-up time when the devices exit shutdown mode (see Layout Considerations on page 17) 8.8 External Reference Both devices can operate with an external reference at pin REF. The external reference should be within the +1.0V to VDD voltage range to achieve specified accuracy. The minimum input impedance is 18k for DC currents. Note: To use an external reference with the AS1526, disable the internal reference by letting pin SHDNN float. During conversion, the external reference should be capable of delivering up to 250A of DC load current and have an output impedance 10. The recommended minimum value for the bypass capacitor is 0.1F. If the reference has higher output impedance or is noisy, bypass it close to pin REF with a 4.7F capacitor. www.ams.com Revision 1.4 14 - 20 AS1526/AS1527 Datasheet - A p p l i c a t i o n Information 9 Application Information 9.1 Initialization When power is first applied, and if SHDNN is not pulled low, it takes the fully discharged 4.7F reference bypass capacitor up to 20ms to provide adequate charge for specified accuracy. With an external reference, the initialization time is 10s after the power supplies have stabilized. Note: A/D conversions must not be started during initialization of the AS1526/AS1527. 9.2 Serial Interface The AS1526/AS1527 fully support SPI, QSPI, and Microwire interfaces. For SPI, select the correct clock polarity and sampling edge in the SPI control registers (set CPOL = 0 and CPHA = 0). Microwire, SPI, and QSPI all transmit a byte and receive a byte at the same time. 9.2.1 Serial Interface Configuration The AS1526/AS1527 serial interface can be configured with the following procedure: 1. 2. 3. 4. 5. Put the microprocessor's serial interface into master mode (so that it generates the serial clock). Select a clock frequency up to 2.1MHz. Keeping SCLK low, pull CSN low via one of the microprocessor's general-purpose I/O lines. Monitor DOUT for its rising edge to determine the EOC, or wait the maximum conversion time specified before activating SCLK. Activate SCLK for a minimum of 11 clock cycles. The first falling clock edge produces the MSB of the conversion. Output data transitions on the falling edge of SCLK, and is available in MSB-first format at pin DOUT. Observe the SCLK to DOUT valid timing characteristic. Data can be clocked into the microprocessor on the rising edge of SCLK. 6. CSN should be pulled high at or after the 13th falling clock edge. If CSN remains low, trailing zeros are clocked out after the LSB. 7. With CSN = high, wait the minimum specified time, tCS, before initiating a new conversion by pulling CSN low. If a conversion is aborted by pulling CSN high before the conversion's end, wait for the minimum acquisition time, tACQ, before starting a new conversion. Note: CSN must be held low until all data bits are clocked out. 8. Data can be output in two bytes or continuously (see Figure 34 on page 16). The bytes contain the result of the conversion padded with one leading 1, two sub-bits, and trailing 0s. 9.2.2 SPI and Microwire Interfaces When interfacing the AS1526/AS1527 to a microprocessor's SPI or Microwire interface (see Figure 32 and Figure 33), set SPI control registers CPOL = 0 and CPHA = 0. Figure 32. SPI Serial Interface Connections 8 SCK SSM CPU SCLK 7 I/O CSN MISO DOUT AS1526/ AS1527 6 www.ams.com Revision 1.4 15 - 20 AS1526/AS1527 Datasheet - A p p l i c a t i o n Information Figure 33. Microwire Serial Interface Connections 8 SK SCLK I/O CSN 7 CPU AS1526/ AS1527 6 SI DOUT A conversion process begins on the falling edge of CSN (see Figure 34). DOUT goes low, indicating a conversion is in progress. Wait until DOUT goes high or until the maximum specified conversion time elapses before starting another conversion. Two consecutive 1-byte reads are required to retrieve the full 10+2 bits from the devices. Output data transitions occurs on the falling edge of SCLK, and is clocked into the microprocessor on the rising edge of SCLK. The first byte contains a leading 1, and seven bits of conversion result data. The second byte contains the remaining three bits of conversion result data, two sub-bits, and three trailing zeros. Figure 34. SPI/Microwire Serial Interface Timing (CPOL = CPHA = 0) 2nd Byte Read 1st Byte Read SCLK CSN tCONV DOUT EOC D9 D8 D7 D6 D5 D4 D3 D2 D1 MSB 9.2.3 D0 S1 S0 LSB High-Z when CSN is High QSPI When interfacing the AS1526/AS1527 to a microprocessor's QSPI interface (see Figure 35), set QSPI control register CPOL = CPHA = 0. Figure 35. QSPI Serial Interface Connections 8 SCK SSM CPU SCLK 7 CSM CSN MISO DOUT AS1526/ AS1527 6 www.ams.com Revision 1.4 16 - 20 AS1526/AS1527 Datasheet - A p p l i c a t i o n Information Unlike the SPI interface, which requires two 1-byte reads to acquire the 10 data bits from the AS1526/AS1527, QSPI allows the minimum number of clock cycles necessary to clock in the data. The devices require 11 clock cycles from the microprocessor to clock out the 10 data bits with no trailing zeros or 13 clock cycles from the microprocessor to clock out the 10 data bits and two sub-bits with no trailing zeros (see Figure 36). Note: The maximum clock frequency to ensure compatibility with QSPI is 2.097MHz. Figure 36. QSPI Serial Interface Timing (CPOL = CPHA = 0) SCLK CSN tCONV EOC DOUT D9 D8 D7 D6 D5 D4 D3 D2 D1 MSB D0 LSB S1 S0 High-Z when CSN is High 9.3 Layout Considerations The AS1526/AS1527 require proper layout and design procedures for optimum performance. Use printed circuit boards; wirewrap boards should not be used. Separate analog and digital traces from each other. Analog and digital traces should not run parallel to each other (especially clock traces). Digital traces should not run beneath the AS1526/AS1527. Use a single-point analog ground at GND, separate from the digital ground (see Figure 37). Connect all other analog grounds and DGND to this star ground point for further noise reduction. No other digital system ground should be connected to this single-point analog ground. The ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. High-frequency noise in the VDD power supply may affect the AS1526/AS1527 high-speed comparator. Bypass this supply to the single- point analog ground with 0.1F and 4.7F bypass capacitors (see Figure 37). The bypass capacitors should be placed as close to the device as possible for optimum power supply noise-rejection. If the power supply is very noisy, a 10 resistor can be connected as a lowpass filter to attenuate supply noise. Figure 37. Recommended Ground Design +3V Power Supplies +3V GND DGND GND GND 5 10 (Optional) 4.7F + +3V www.ams.com Digital Circuitry 0.1F AS1526/ AS1527 1 VDD Revision 1.4 17 - 20 AS1526/AS1527 Datasheet - A p p l i c a t i o n Information 9.4 Package Drawings and Markings Figure 38. 8-pin SOIC-150 Package Notes: 1. Lead coplanarity should be 0 to 0.10mm (.004") max. 2. Package surface finishing: (2.1) Top: matte (charmilles #18-30). (2.2) All sides: matte (charmilles #18-30). (2.3) Bottom: smooth or matte (charmilles #18-30). 3. All dimensions exclusive of mold flash, and end flash from the package body shall not exceed 0.24mm (0.10") per side (D). 4. Details of pin #1 identifier are optional but must be located within the zone indicated. Symbol Min Max A1 B C D E e H h L A 0.10 0.36 0.19 4.80 3.81 0.25 0.46 0.25 4.98 3.99 ZD A2 www.ams.com Revision 1.4 1.27BSC 5.80 0.25 .041 1.52 0 6.20 0.50 1.27 1.72 8 0.53REF 1.37 1.57 18 - 20 AS1526/AS1527 Datasheet - O r d e r i n g Information 10 Ordering Information The devices are available as the standard products shown in Table 5. Table 5. Ordering Information Type Description Delivery Form Package AS1526-BSOU Single-Supply, Low-Power, 73ksps A/D Converter with Internal +2.5V Reference Tubes 8-pin SOIC-150 AS1526-BSOT Single-Supply, Low-Power, 73ksps A/D Converter with Internal +2.5V Reference Tape and Reel 8-pin SOIC-150 AS1527-BSOU Single-Supply, Low-Power, 73ksps A/D Converter Tubes 8-pin SOIC-150 AS1527-BSOT Single-Supply, Low-Power, 73ksps A/D Converter Tape and Reel 8-pin SOIC-150 Note: All products are RoHS compliant and Pb-free. Buy our products or get free samples online at www.ams.com/ICdirect Technical Support is available at www.ams.com/Technical-Support For further information and requests, email us at sales@ams.com (or) find your local distributor at www.ams.com/distributor www.ams.com Revision 1.4 19 - 20 AS1526/AS1527 Datasheet - O r d e r i n g Information Copyrights Copyright (c) 1997-2012, ams AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by ams AG is believed to be correct and accurate. However, ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services. Contact Information Headquarters ams AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel Fax : +43 (0) 3136 500 0 : +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.ams.com/contact www.ams.com Revision 1.4 20 - 20