2.35 V to 5.25 V, 1 MSPS,
12-/10-/8-Bit ADCs in 6-Lead SC70
AD7476A/AD7477A/AD7478A
Rev. F
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FEATURES
Fast throughput rate: 1 MSPS
Specified for VDD of 2.35 V to 5.25 V
Low power
3.6 mW at 1 MSPS with 3 V supplies
12.5 mW at 1 MSPS with 5 V supplies
Wide input bandwidth
71 dB SNR at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
Standby mode: 1 μA maximum
6-lead SC70 package
8-lead MSOP package
Qualified for automotive applications
APPLICATIONS
Battery-powered systems
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
High speed modems
Optical sensors
FUNCTIONAL BLOCK DIAGRAM
12-/10-/8-BIT
SUCCESSIVE-
APPROXIMATION
ADC
CONTROL
LOGIC
AD7476A/AD7477A/AD7478A
GND
V
DD
V
IN
SCLK
SDATA
CS
T/H
02930-001
Figure 1.
GENERAL DESCRIPTION
The AD7476A/AD7477A/AD7478A are 12-bit, 10-bit, and 8-bit
high speed, low power, successive-approximation analog-to-
digital converters (ADCs), respectively. The parts operate from
a single 2.35 V to 5.25 V power supply and feature throughput
rates up to 1 MSPS. The parts contain a low noise, wide
bandwidth track-and-hold amplifier that can handle input
frequencies in excess of 13 MHz. The conversion process and
data acquisition are controlled using CS and the serial clock,
allowing the devices to interface with microprocessors or DSPs.
The input signal is sampled on the falling edge of CS, and the
conversion is also initiated at this point. There are no pipeline
delays associated with the parts. The AD7476A/AD7477A/
AD7478A use advanced design techniques to achieve low power
dissipation at high throughput rates. The reference for the part
is taken internally from VDD to allow the widest dynamic input
range to the ADC. Thus, the analog input range for the part is
0 V to VDD. The conversion rate is determined by the SCLK.
PRODUCT HIGHLIGHTS
1. First 12-/10-/8-bit ADCs in a SC70 package.
2. High throughput with low power consumption.
3. Flexible power/serial clock speed management. The
conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption
to be reduced when a power-down mode is used while not
converting. The parts also feature a power-down mode to
maximize power efficiency at lower throughput rates.
Current consumption is 1 μA maximum and 50 nA
typically when in power-down mode.
4. Reference derived from the power supply.
5. No pipeline delay. The parts feature a standard successive
approximation ADC with accurate control of the sampling
instant via a CS input and once-off conversion control.
AD7476A/AD7477A/AD7478A
Rev. F | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AD7476A Specifications .............................................................. 3
AD7477A Specifications .............................................................. 5
AD7478A Specifications .............................................................. 6
Timing Specifications .................................................................. 8
Absolute Maximum Ratings .......................................................... 10
ESD Caution ................................................................................ 10
Pin Configurations and Function Descriptions ......................... 11
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
Circuit Information .................................................................... 15
The Converter Operation .......................................................... 15
ADC Transfer Function ............................................................. 15
Typical Connection Diagram ....................................................... 16
Analog Input ............................................................................... 16
Digital Inputs .............................................................................. 17
Modes of Operation ....................................................................... 18
Normal Mode .............................................................................. 18
Power-Down Mode .................................................................... 18
Power-Up Time .......................................................................... 18
Power vs. Throughput Rate ........................................................... 20
Serial Interface ................................................................................ 21
AD7478A in a 12 SCLK Cycle Serial Interface ....................... 22
Microprocessor Interfacing ........................................................... 23
AD7476A/AD7477A/AD7478A to TMS320C541 Interface 23
AD7476A/AD7477A/AD7478A to ADSP-218x Interface .... 23
AD7476A/AD7477A/AD7478A to DSP563xx Interface ...... 24
Application Hints ........................................................................... 25
Grounding and Layout .............................................................. 25
Evaluating the AD7476A/AD7477A Performance ............... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
Automotive Products ................................................................. 27
REVISION HISTORY
1/11—Rev. E to Rev. F
Changes to Features Section............................................................ 1
Changes to Ordering Guide .......................................................... 26
Added Automotive Products Section .......................................... 27
2/09—Rev. D to Rev. E
Changes to Features .......................................................................... 1
Changes to Ordering Guide .......................................................... 26
4/06—Rev. C to Rev. D
Updated Format .................................................................. Universal
Changes to Ordering Guide .......................................................... 26
AD7476A/AD7477A/AD7478A
Rev. F | Page 3 of 28
SPECIFICATIONS
AD7476A SPECIFICATIONS
VDD = 2.35 V to 5.25 V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS, TA = TMIN to TMAX, unless otherwise noted.1
Table 1.
Parameter A Grade2 B Grade2 Y Grade2 Unit Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 100 kHz sine wave
Signal-to-Noise + Distortion (SINAD)3 70 70 70 dB min VDD = 2.35 V to 3.6 V, TA = 25°C
69 69 69 dB min VDD = 2.4 V to 3.6 V
71.5 71.5 71.5 dB typ VDD = 2.35 V to 3.6 V
69 69 69 dB min VDD = 4.75 V to 5.25 V, TA = 25°C
68 68 68 dB min VDD = 4.75 V to 5.25 V
Signal-to-Noise Ratio (SNR)3 71 71 71 dB min VDD = 2.35 V to 3.6 V, TA = 25°C
70 70 70 dB min VDD = 2.4 V to 3.6 V
70 70 70 dB min VDD = 4.75 V to 5.25 V, TA = 25°C
69 69 69 dB min VDD = 4.75 V to 5.25 V
Total Harmonic Distortion (THD)3 –80 –80 –80 dB typ
Peak Harmonic or Spurious Noise (SFDR)3 –82 –82 –82 dB typ
Intermodulation Distortion (IMD)3
Second-Order Terms –84 –84 –84 dB typ fa = 100.73 kHz, fb = 90.72 kHz
Third-Order Terms –84 –84 –84 dB typ fa = 100.73 kHz, fb = 90.72 kHz
Aperture Delay 10 10 10 ns typ
Aperture Jitter 30 30 30 ps typ
Full Power Bandwidth 13.5 13.5 13.5 MHz typ @ 3 dB
2 2 2 MHz typ @ 0.1 dB
DC ACCURACY B and Y grades4
Resolution 12 12 12 Bits
Integral Nonlinearity3 ±1.5 ±1.5 LSB max
±0.75 LSB typ
Differential Nonlinearity –0.9/+1.5 –0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits
±0.75 LSB typ
Offset Error3, 5 ±1.5 ±1.5 LSB max
±1.5 ±0.2 ±0.2 LSB typ
Gain Error3, 5 ±1.5 ±1.5 LSB max
±1.5 ±0.5 ±0.5 LSB typ
Total Unadjusted Error (TUE)3, 5 ±2 ±2 LSB max
ANALOG INPUT
Input Voltage Range 0 to VDD 0 to VDD 0 to VDD V
DC Leakage Current ±0.5 ±0.5 ±0.5 μA max
Input Capacitance 20 20 20 pF typ Track-and-hold in track; 6 pF typ when in hold
LOGIC INPUTS
Input High Voltage, VINH 2.4 2.4 2.4 V min
1.8 1.8 1.8 V min VDD = 2.35 V
Input Low Voltage, VINL 0.8 0.8 0.8 V max VDD = 5 V
0.4 0.4 0.4 V max VDD = 3 V
Input Current, IIN, SCLK Pin ±0.5 ±0.5 ±0.5 μA max Typically 10 nA, VIN = 0 V or VDD
Input Current, IIN, CS Pin ±10 ±10 ±10 nA typ
Input Capacitance, CIN6 5 5 5 pF max
AD7476A/AD7477A/AD7478A
Rev. F | Page 4 of 28
Parameter A Grade2 B Grade2 Y Grade2 Unit Test Conditions/Comments
LOGIC OUTPUTS
Output High Voltage, VOH VDD – 0.2 VDD – 0.2 VDD – 0.2 V min ISOURCE = 200 μA; VDD = 2.35 V to 5.25 V
Output Low Voltage, VOL 0.4 0.4 0.4 V max ISINK = 200 μA
Floating-State Leakage Current ±1 ±1 ±1 μA max
Floating-State Output Capacitance6 5 5 5 pF max
Output Coding Straight (Natural) Binary
CONVERSION RATE
Conversion Time 800 800 800 ns max 16 SCLK cycles
Track-and-Hold Acquisition Time3 250 250 250 ns max
Throughput Rate 1 1 1 MSPS max See Serial Interface section
POWER REQUIREMENTS
VDD 2.35/5.25 2.35/5.25 2.35/5.25 V min/max
IDD Digital I/Ps = 0 V or VDD
Normal Mode (Static) 2.5 2.5 2.5 mA typ VDD = 4.75 V to 5.25 V, SCLK on or off
1.2 1.2 1.2 mA typ VDD = 2.35 V to 3.6 V, SCLK on or off
Normal Mode (Operational) 3.5 3.5 3.5 mA max VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS
1.7 1.7 1.7 mA max VDD = 2.35 V to 3.6 V, fSAMPLE = 1 MSPS
Full Power-Down Mode (Static) 1 1 1 μA max Typically 50 nA
Full Power-Down Mode (Dynamic) 0.6 0.6 0.6 mA typ VDD = 5 V, fSAMPLE = 100 kSPS
Power Dissipation7 0.3 0.3 0.3 mA typ VDD = 3 V, fSAMPLE = 100 kSPS
Normal Mode (Operational) 17.5 17.5 17.5 mW max VDD = 5 V, fSAMPLE = 1 MSPS
5.1 5.1 5.1 mW max VDD = 3 V, fSAMPLE = 1 MSPS
Full Power-Down Mode 5 5 5 μW max VDD = 5 V
3 3 3 μW max VDD = 3 V
1 Temperature ranges are as follows: A, B grades from –40°C to +85°C, Y grade from –40°C to +125°C.
2 Operational from VDD = 2.0 V, with input low voltage (VINL) 0.35 V maximum.
3 See the Terminology section.
4 B and Y grades, maximum specifications apply as typical figures when VDD = 4.75 V to 5.25 V.
5 SC70 values guaranteed by characterization.
6 Guaranteed by characterization.
7 See the Power vs. Throughput Rate section.
AD7476A/AD7477A/AD7478A
Rev. F | Page 5 of 28
AD7477A SPECIFICATIONS
VDD = 2.35 V to 5.25 V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS, TA = TMIN to TMAX, unless otherwise noted.1
Table 2.
Parameter A Grade2 Unit Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 100 kHz sine wave
Signal-to-Noise + Distortion (SINAD)3 61 dB min
Total Harmonic Distortion (THD)3 –72 dB max
Peak Harmonic or Spurious Noise (SFDR)3 –73 dB max
Intermodulation Distortion (IMD)3
Second-Order Terms –82 dB typ fa = 100.73 kHz, fb = 90.7 kHz
Third-Order Terms –82 dB typ fa = 100.73 kHz, fb = 90.7 kHz
Aperture Delay 10 ns typ
Aperture Jitter 30 ps typ
Full Power Bandwidth 13.5 MHz typ @ 3 dB
2 MHz typ @ 0.1 dB
DC ACCURACY
Resolution 10 Bits
Integral Nonlinearity ±0.5 LSB max
Differential Nonlinearity ±0.5 LSB max Guaranteed no missed codes to 10 bits
Offset Error3, 4 ±1 LSB max
Gain Error3, 4 ±1 LSB max
Total Unadjusted Error (TUE)3, 4 ±1.2 LSB max
ANALOG INPUT
Input Voltage Range 0 to VDD V
DC Leakage Current ±0.5 µA max
Input Capacitance 20 pF typ Track-and-hold in track; 6 pF typ when in hold
LOGIC INPUTS
Input High Voltage, VINH 2.4 V min
1.8 V min VDD = 2.35 V
Input Low Voltage, VINL 0.8 V max VDD = 5 V
0.4 V max VDD = 3 V
Input Current, IIN, SCLK Pin ±0.5 μA max Typically 10 nA, VIN = 0 V or VDD
Input Current, IIN, CS Pin ±10 nA typ
Input Capacitance, CIN5 5 pF max
LOGIC OUTPUTS
Output High Voltage VOH VDD – 0.2 V min ISOURCE = 200 μA, VDD = 2.35 V to 5.25 V
Output Low Voltage, VOL 0.4 V max ISINK = 200 μA
Floating-State Leakage Current ±1 μA max
Floating-State Output Capacitance5 5 pF max
Output Coding Straight (Natural) Binary
CONVERSION RATE
Conversion Time 700 ns max 14 SCLK cycles with SCLK at 20 MHz
Track-and-Hold Acquisition Time3 250 ns max
Throughput Rate 1 MSPS max
AD7476A/AD7477A/AD7478A
Rev. F | Page 6 of 28
Parameter A Grade2 Unit Test Conditions/Comments
POWER REQUIREMENTS
VDD 2.35/5.25 V min/max
IDD Digital I/Ps = 0 V or VDD
Normal Mode (Static) 2.5 mA typ VDD = 4.75 V to 5.25 V, SCLK on or off
1.2 mA typ VDD = 2.35 V to 3.6 V, SCLK on or off
Normal Mode (Operational) 3.5 mA max VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS
1.7 mA max VDD = 2.35 V to 3.6 V, fSAMPLE = 1 MSPS
Full Power-Down Mode (Static) 1 μA max Typically 50 nA
Full Power-Down Mode (Dynamic) 0.6 mA typ VDD = 5 V, fSAMPLE = 100 kSPS
Power Dissipation6 0.3 mA typ VDD = 3 V, fSAMPLE = 100 kSPS
Normal Mode (Operational) 17.5 mW max VDD = 5 V, fSAMPLE = 1 MSPS
5.1 mW max VDD = 3 V, fSAMPLE = 1 MSPS
Full Power-Down Mode 5 μW max VDD = 5 V
1 Temperature range is from –40°C to +85°C.
2 Operational from VDD = 2.0 V, with input high voltage (VINH) 1.8 V minimum.
3 See the Terminology section.
4 SC70 values guaranteed by characterization.
5 Guaranteed by characterization.
6 See the Power vs. Throughput Rate section.
AD7478A SPECIFICATIONS
VDD = 2.35 V to 5.25 V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS, TA = TMIN to TMAX, unless otherwise noted.1
Table 3.
Parameter A Grade2 Unit Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 100 kHz sine wave
Signal-to-Noise + Distortion (SINAD)3 49 dB min
Total Harmonic Distortion (THD)3 –65 dB max
Peak Harmonic or Spurious Noise (SFDR)3 –65 dB max
Intermodulation Distortion (IMD)3
Second-Order Terms –76 dB typ fa = 100.73 kHz, fb = 90.7 kHz
Third-Order Terms –76 dB typ fa = 100.73 kHz, fb = 90.7 kHz
Aperture Delay 10 ns typ
Aperture Jitter 30 ps typ
Full Power Bandwidth 13.5 MHz typ @ 3 dB
2 MHz typ @ 0.1 dB
DC ACCURACY
Resolution 8 Bits
Integral Nonlinearity3 ±0.3 LSB max
Differential Nonlinearity3 ±0.3 LSB max Guaranteed no missed codes to eight bits
Offset Error3, 4 ±0.3 LSB max
Gain Error3, 4 ±0.3 LSB max
Total Unadjusted Error (TUE)3, 4 ±0.5 LSB max
ANALOG INPUT
Input Voltage Range 0 to VDD V
DC Leakage Current ±0.5 μA max
Input Capacitance 20 pF typ Track-and-hold in track; 6 pF typ when in hold
AD7476A/AD7477A/AD7478A
Rev. F | Page 7 of 28
Parameter A Grade2 Unit Test Conditions/Comments
LOGIC INPUTS
Input High Voltage, VINH 2.4 V min
1.8 V min VDD = 2.35 V
Input Low Voltage, VINL 0.8 V max VDD = 5 V
0.4 V max VDD = 3 V
Input Current, IIN, SCLK Pin ±0.5 μA max Typically 10 nA, VIN = 0 V or VDD
Input Current, IIN, CS Pin ±10 nA typ
Input Capacitance, CIN5 5 pF max
LOGIC OUTPUTS
Output High Voltage, VOH VDD – 0.2 V min ISOURCE = 200 μA, VDD = 2.35 V to 5.25 V
Output Low Voltage, VOL 0.4 V max ISINK = 200 μA
Floating-State Leakage Current ±1 μA max
Floating-State Output Capacitance5 5 pF max
Output Coding Straight (Natural) Binary
CONVERSION RATE
Conversion Time 600 ns max 12 SCLK cycles with SCLK at 20 MHz
Track-and-Hold Acquisition Time3 225 ns max
Throughput Rate 1.2 MSPS max
POWER REQUIREMENTS
VDD 2.35/5.25 V min/max
IDD Digital I/Ps = 0 V or VDD
Normal Mode (Static) 2.5 mA typ VDD = 4.75 V to 5.25 V, SCLK on or off
1.2 mA typ VDD = 2.35 V to 3.6 V, SCLK on or off
Normal Mode (Operational) 3.5 mA max VDD = 4.75 V to 5.25 V
1.7 mA max VDD = 2.35 V to 3.6 V
Full Power-Down Mode (Static) 1 μA max Typically 50 nA
Full Power-Down Mode (Dynamic) 0.6 mA typ VDD = 5 V, fSAMPLE = 100 kSPS
Power Dissipation6 0.3 mA typ VDD = 3 V, fSAMPLE = 100 kSPS
Normal Mode (Operational) 17.5 mW max VDD = 5 V
5.1 mW max VDD = 3 V
Full Power-Down Mode 5 μW max VDD = 5 V
1 Temperature range is from –40°C to +85°C.
2 Operational from VDD = 2.0 V, with input high voltage (VINH) 1.8 V minimum.
3 See the Terminology section.
4 SC70 values guaranteed by characterization.
5 Guaranteed by characterization.
6 See the Power vs. Throughput Rate section.
AD7476A/AD7477A/AD7478A
Rev. F | Page 8 of 28
TIMING SPECIFICATIONS
VDD = 2.35 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted.1
Table 4.
Parameter Limit at TMIN, TMAX Unit Description
fSCLK2 10 kHz min3 A, B grades
20 kHz min3 Y grade
20 MHz max
tCONVERT 16 × tSCLK AD7476A
14 × tSCLK AD7477A
12 × tSCLK AD7478A
tQUIET 50 ns min Minimum quiet time required between bus relinquish
and start of next conversion
t1 10 ns min Minimum CS pulse width
t2 10 ns min CS to SCLK setup time
t34 22 ns max Delay from CS until SDATA three-state disabled
t44 40 ns max Data access time after SCLK falling edge
t5 0.4 tSCLK ns min SCLK low pulse width
t6 0.4 tSCLK ns min SCLK high pulse width
t75 SCLK to data valid hold time
10 ns min VDD ≤ 3.3 V
9.5 ns min 3.3 V < VDD ≤ 3.6 V
7 ns min VDD > 3.6 V
t86 36 ns max SCLK falling edge to SDATA high impedance
t7 values also apply to t8 minimum values ns min SCLK falling edge to SDATA high impedance
tPOWER-UP7 1 μs max Power-up time from full power-down
1 Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Minimum fSCLK at which specifications are guaranteed.
4 Measured with the load circuit shown in Figure 2, and defined as the time required for the output to cross 0.8 V or 1.8 V when VDD = 2.35 V, and
0.8 V or 2.0 V for VDD > 2.35 V.
5 Measured with a 50 pF load capacitor.
6 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. Therefore, the time, t8, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
7 See the Power-Up Time section.
AD7476A/AD7477A/AD7478A
Rev. F | Page 9 of 28
Timing Diagrams
TO OUTPUT
PIN CL
50pF
200
µ
AIOH
200
µ
AIOL
1.6V
02930-002
Figure 2. Load Circuit for Digital Output Timing Specifications
Timing Example 1
Having fSCLK = 20 MHz and a throughput of 1 MSPS, a cycle
time of
t2 + 12.5 (1/fSCLK) + tACQ = 1 µs
where:
t2 = 10 ns min, leaving tACQ to be 365 ns. This 365 ns satisfies the
requirement of 250 ns for tACQ.
From Figure 4, tACQ is comprised of
2.5 (1/fSCLK) + t8 + tQUIET
where:
t8 = 36 ns maximum. This allows a value of 204 ns for tQUIET,
satisfying the minimum requirement of 50 ns.
Timing Example 2
Having fSCLK = 5 MHz and a throughput is 315 kSPS yields a
cycle time of
t2 + 12.5 (1/fSCLK) + tACQ = 3.174 µs
where:
t2 = 10 ns min, this leaves tACQ to be 664 ns. This 664 ns satisfies
the requirement of 250 ns for tACQ.
From Figure 4, tACQ is comprised of
2.5 (1/fSCLK) + t8 + tQUIET, t8 = 36 ns maximum
This allows a value of 128 ns for tQUIET, satisfying the minimum
requirement of 50 ns.
In this example and with other, slower clock values, the signal
may already be acquired before the conversion is complete, but
it is still necessary to leave 50 ns minimum tQUIET between
conversions. In Example 2, acquire the signal fully at
approximately Point C in Figure 4.
CS
SCLK
SDATA
t
2
t
6
t
3
t
4
t
7
t
5
t
8
t
CONVERT
t
QUIET
ZERO ZERO ZERO DB11 DB10 DB2 DB1 DB0
B
THREE-STATETHREE-
STATE
Z
4 LEADING ZEROS
1 3 13 14 15 16
t
1
4 52
02930-003
Figure 3. AD7476A Serial Interface Timing Diagram
CS
SCLK
t2
tCONVERT
B
1 2 5 13 14 15 16
C
t
8
t
QUIET
t
ACQ
12.5(1/fSCLK)1/THROUGHPUT
3 4
02930-004
Figure 4. Serial Interface Timing Example
AD7476A/AD7477A/AD7478A
Rev. F | Page 10 of 28
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.1
Table 5.
Parameter Ratings
VDD to GND –0.3 V to +7 V
Analog Input Voltage to GND –0.3 V to VDD + 0.3 V
Digital Input Voltage to GND –0.3 V to +7 V
Digital Output Voltage to GND –0.3 V to VDD + 0.3 V
Input Current to Any Pin Except Supplies 10 mA
Operating Temperature Range
Commercial (A and B Grades) –40°C to +85°C
Industrial (Y Grade) –40°C to +125°C
Storage Temperature Range –65°C to +150°C
Junction Temperature 150°C
MSOP Package
θJA Thermal Impedance 205.9°C/W
θJC Thermal Impedance 43.74°C/W
SC70 Package
θJA Thermal Impedance 340.2°C/W
θJC Thermal Impedance 228.9°C/W
Lead Temperature, Soldering
Reflow (10 sec to 30 sec) 235 (0/+5)°C
Pb-Free Temperature Soldering
Reflow 255 (0/+5)°C
ESD 3.5 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1 Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electro
static discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD7476A/AD7477A/AD7478A
Rev. F | Page 11 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
TOP VIEW
(Not to Scale)
6
5
4
1
2
3
V
DD
GND
V
IN
CS
SDATA
SCLK
AD7476A/
AD7477A/
AD7478A
02930-005
Figure 5. 6-Lead SC70 Pin Configuration
8
7
6
5
1
2
3
4
NC = NO CONNECT
VDD
SDATA
VIN
GND
SCLK
NCNC TOP VIEW
(Not to Scale)
AD7476A/
AD7477A/
AD7478A
CS
02930-006
Figure 6. 8-Lead MSOP Pin Configuration
Table 6. Pin Function Descriptions
Mnemonic Description
CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the
AD7476A/AD7477A/AD7478A and also frames the serial data transfer.
VDD Power Supply Input. The VDD range for AD7476A/AD7477A/AD7478A is from 2.35 V to 5.25 V.
GND Analog Ground. Ground reference point for all circuitry on AD7476A/AD7477A/AD7478A. Refer all analog input signals to this
GND voltage.
VIN Analog Input. Single-ended analog input channel. The input range is 0 V to VDD.
SDATA Data Out. Logic output. The conversion result from AD7476A/AD7477A/AD7478A is provided on this output as a serial data
stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7476A consists of four
leading zeros followed by 12 bits of conversion data that are provided MSB first. The data stream from the AD7477A consists
of four leading zeros followed by 10 bits of conversion data followed by two trailing zeros, provided MSB first. The data stream
from the AD7478A consists of four leading zeros followed by 8 bits of conversion data followed by four trailing zeros that are
provided MSB first.
SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the
clock source for the conversion process of AD7476A/AD7477A/AD7478A.
NC No Connect.
AD7476A/AD7477A/AD7478A
Rev. F | Page 12 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 7, Figure 8, and Figure 9 each show a typical FFT plot for
the AD7476A, AD7477A, and AD7478A, respectively, at a
1 MSPS sample rate and 100 kHz input frequency. Figure 10
shows the signal-to-(noise + distortion) ratio performance vs.
the input frequency for various supply voltages while sampling
at 1 MSPS with an SCLK frequency of 20 MHz for the
AD7476A.
Figure 11 and Figure 12 show INL and DNL performance for
the AD7476A. Figure 13 shows a graph of the total harmonic
distortion vs. the analog input frequency for different source
impedances when using a supply voltage of 3.6 V and sampling
at a rate of 1 MSPS (see the Analog Input section). Figure 14
shows a graph of the total harmonic distortion vs. the analog
input signal frequency for various supply voltages while
sampling at 1 MSPS with an SCLK frequency of 20 MHz.
FREQUENCY (kHz)
5
–55
–115 0 50050
SNR (dB)
100 150 200 250 300 350 400 450
–15
–35
–75
–95
8192 POINT FFT
V
DD
= 2.7V
f
SAMPLE
= 1MSPS
f
IN
= 100kHz
SINAD = 72.05dB
THD = –82.87dB
SFDR = –87.24dB
02930-007
Figure 7. AD7476A Dynamic Performance at 1 MSPS
FREQUENCY (kHz)
–45
–105
SNR (dB)
–5
–25
–65
–85
8192 POINT FFT
V
DD
= 2.35V
f
SAMPLE
= 1MSPS
f
IN
= 100kHz
SINAD = 61.67dB
THD = –79.59dB
SFDR = –82.93dB
0 50050 100 150 200 250 300 350 400 450
02930-008
Figure 8. AD7477A Dynamic Performance at 1 MSPS
FREQUENCY (kHz)
5
–25
–55
SNR (dB)
–5
–15
–35
–45
8192 POINT FFT
V
DD
= 2.35V
f
SAMPLE
= 1MSPS
f
IN
= 100kHz
SINAD = 49.77dB
THD = –75.51dB
SFDR = –70.71dB
0 50050 100 150 200 250 300 350 400 450
–75
–65
–85
–95
02930-009
Figure 9. AD7478A Dynamic Performance at 1 MSPS
FREQUENCY (kHz)
–66
–69
–72
10 1000
SINAD (dB)
100
–67
–68
–70
–71
–73
–74
V
DD
= 5.25V
V
DD
= 2.35V
V
DD
= 2.7V
V
DD
= 4.75V
V
DD
= 3.6V
02930-010
Figure 10. AD7476A SINAD vs. Input Frequency at 1 MSPS
AD7476A/AD7477A/AD7478A
Rev. F | Page 13 of 28
CODE
1.0
0.4
–0.2
0 1024
INL ERROR (LSB)
512
0.8
0.6
0.2
0
–0.4
–0.6
–0.8
–1.0 1536 2048 2560 3072 3584 4096
V
DD
= 2.35V
TEMP = 25°C
fSAMPLE
= 1MSPS
02930-011
Figure 11. AD7476A INL Performance
CODE
1.0
0.4
–0.2
0 1024
DNL ERROR (LSB)
512
0.8
0.6
0.2
0
–0.4
–0.6
–0.8
–1.0 1536 2048 2560 3072 3584 4096
VDD = 2.35V
TEMP = 25°C
fSAMPLE = 1MSPS
02930-012
Figure 12. AD7476A DNL Performance
INPUT FREQUENCY (kHz)
0
–30
–60
10 1000
THD (dB)
100
–10
–20
–40
–50
–70
–80
–90
V
DD
= 3.6V
R
IN
= 10kΩ
R
IN
= 1kΩ
R
IN
= 130Ω
R
IN
= 13Ω
R
IN
= 0Ω
02930-013
Figure 13. THD vs. Analog Input Frequency for Various Source Impedances
INPUT FREQUENCY (kHz)
–60
–75
–9010 1000
THD (dB)
100
–65
–70
–80
–85 V
DD
= 5.25V
V
DD
= 2.35V
V
DD
= 2.7V
V
DD
= 4.75V
V
DD
= 3.6V
02930-014
Figure 14. THD vs. Analog Input Frequency for Various Supply Voltages
AD7476A/AD7477A/AD7478A
Rev. F | Page 14 of 28
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. For the
AD7476A/AD7477A/AD7478A, the endpoints of the transfer
function are zero scale (1 LSB below the first code transition),
and full scale (1 LSB above the last code transition).
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, that is, AGND + 1 LSB.
Gain Error
This is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal, that is, VREF – 1 LSB after the offset
error has been adjusted out.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode at the end
of a conversion. The track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within 0.5 LSB, after the end of conversion. See
the Serial Interface section for more details.
Signal-to-(Noise + Distortion) Ratio (SINAD)
This is the measured ratio of signal-to-(noise + distortion) at
the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitiza-
tion process; the more levels, the smaller the quantization noise.
The theoretical signal-to-(noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by signal-to-
(noise + distortion) = (6.02 N + 1.76) dB. Thus, it is 74 dB for a
12-bit converter, 62 dB for a 10-bit converter, and 50 dB for an
8-bit converter.
Total Unadjusted Error (TUE)
This is a comprehensive specification that includes the gain,
linearity, and offset errors.
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of
harmonics to the fundamental. It is defined as
1
2
6
2
5
2
4
2
3
2
2
V
VVVVV
THD ++++
=log20)dB(
where V1 is the rms amplitude of the fundamental, and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise (SFDR)
Peak harmonic or spurious noise is defined as the ratio of the rms
value of the next largest component in the ADC output spectrum
(up to fS/2 and excluding dc) to the rms value of the fundamental.
Normally, the value of this specification is determined by the largest
harmonic in the spectrum. For ADCs where the harmonics are
buried in the noise floor, it is a noise peak.
Intermodulation Distortion (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities create distortion
products at sum and difference frequencies of mfa, nfb, where
m and n = 0, 1, 2, 3, and so on. Intermodulation distortion
terms are those for which neither m nor n are equal to zero. For
example, the second-order terms include (fa + fb) and (fa – fb),
and the third-order terms include (2fa + fb), (2fa – fb), (fa + 2fb),
and (fa – 2fb).
The AD7476A/AD7477A/AD7478A are tested using the CCIF
standard where two input frequencies are used (see fa and fb in
the Specifications section). In this case, the second-order terms
are usually distanced in frequency from the original sine waves,
while the third-order terms are usually at a frequency close to the
input frequencies. As a result, the second- and third-order terms
are specified separately. The calculation of the intermodulation
distortion is per the THD specification, where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in decibels.
AD7476A/AD7477A/AD7478A
Rev. F | Page 15 of 28
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7476A/AD7477A/AD7478A are fast, micropower,
12-/10-/8-bit, single-supply analog-to-digital converters (ADCs),
respectively. The parts can be operated from a 2.35 V to 5.25 V
supply. When operated from either a 5 V supply or a 3 V supply,
the AD7476A/AD7477A/AD7478A are capable of throughput
rates of 1 MSPS when provided with a 20 MHz clock. The
AD7476A/AD7477A/AD7478A provide the user with an on-
chip, track-and-hold ADC and a serial interface housed in a
tiny 6-lead SC70 or 8-lead MSOP package, offering the user
considerable space-saving advantages over alternative solutions.
The serial clock input accesses data from the part but also pro-
vides the clock source for the successive-approximation ADC.
The analog input range is 0 V to VDD. The ADC does not require
an external reference or an on-chip reference. The reference for
the AD7476A/AD7477A/AD7478A is derived from the power
supply and, thus, gives the widest dynamic input range. The
AD7476A/AD7477A/AD7478A also feature a power-down
option to allow power saving between conversions. The power-
down feature is implemented across the standard serial interface,
as described in the Modes of Operation section.
THE CONVERTER OPERATION
AD7476A/AD7477A/AD7478A are successive approximation,
analog-to-digital converters based around a charge redistribu-
tion DAC. Figure 15 and Figure 16 show simplified schematics
of the ADC. Figure 15 shows the ADC during its acquisition
phase. SW2 is closed and SW1 is in Position A, the comparator
is held in a balanced condition, and the sampling capacitor
acquires the signal on VIN.
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
COMPARATOR
SW2
SAMPLING
CAPACITOR
ACQUISITION
PHASE
SW1
A
B
AGND V
DD
/2
V
IN
02930-015
Figure 15. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 16), SW2 opens
and SW1 moves to Position B, causing the comparator to become
unbalanced. The control logic and the charge redistribution
DAC are used to add and subtract fixed amounts of charge from
the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. Figure 17 shows the ADC transfer function.
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
COMPARATOR
SW2
SAMPLING
CAPACITOR
CONVERSION
PHASE
SW1
A
B
AGND VDD/2
VIN
02930-016
Figure 16. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7476A/AD7477A/AD7478A is
straight binary. The designed code transitions occur at the
successive integer LSB values, that is, 1 LSB, 2 LSB, and so on.
The LSB size is VDD/4096 for the AD7476A, VDD/1024 for the
AD7477A, and VDD/256 for the AD7478A. The ideal transfer
characteristic for the AD7476A/AD7477A/AD7478A is shown
in Figure 17.
000...000
0V
ADC CODE
ANALOG INPUT
111...111
000...001
000...010
111...110
111...000
011...111 1LSB =V
DD
/256 (AD7478A)
1LSB +V
DD
– 1LSB
1LSB =V
DD
/1024 (AD7477A)
1LSB =V
DD
/4096 (AD7476A)
02930-017
Figure 17. AD7476A/AD7477A/AD7478A
Transfer Characteristic
AD7476A/AD7477A/AD7478A
Rev. F | Page 16 of 28
TYPICAL CONNECTION DIAGRAM
Figure 18 shows a typical connection diagram for the AD7476A/
AD7477A/AD7478A. VREF is taken internally from VDD and, as
such, VDD should be well decoupled. This provides an analog
input range of 0 V to VDD. The conversion result is output in a
16-bit word with four leading zeros followed by the MSB of the
12-bit, 10-bit, or 8-bit result. The 10-bit result from the AD7477A
is followed by two trailing zeros, and the 8-bit result from the
AD7478A is followed by four trailing zeros. Alternatively, because
the supply current required by the AD7476A/AD7477A/AD7478A
is so low, a precision reference can be used as the supply source
to the AD7476A/AD7477A/AD7478A. A REF19x voltage refer-
ence (REF195 for 5 V or REF193 for 3 V) can be used to supply
the required voltage to the ADC (see Figure 18). This configuration
is especially useful if the power supply is quite noisy, or if the
system supply voltages are at some value other than 5 V or 3 V
(for example, 15 V).
The REF19x outputs a steady voltage to the AD7476A/
AD7477A/AD7478A. If the low dropout REF193 is used, the
current it needs to supply to the AD7476A/AD7477A/ AD7478A is
typically 1.2 mA. When the ADC is converting at a rate of 1
MSPS, the REF193 needs to supply a maximum of 1.7 mA to the
AD7476A/AD7477A/AD7478A. The load regulation of the
REF193 is typically 10 ppm/mA (VS = 5 V), resulting in an error
of 17 ppm (51 µV) for the 1.7 mA drawn from it. This corresponds
to a 0.069 LSB error for the AD7476A with VDD = 3 V from the
REF193, a 0.017 LSB error for the AD7477A, and a 0.0043 LSB
error for the AD7478A.
For applications where power consumption is a concern, use the
power-down mode of the ADC and the sleep mode of the
REF19x reference to improve power performance. See the
Modes of Operation section.
AD7476A/
AD7477A/
AD7478A
SCLK
SDATA
CS
V
IN
GND
0VTOV
DD
INPUT
V
DD
µC/µP
SERIAL
INTERFACE
0.1µF1µF
TANT
REF193
1.2mA
680nF
10µF0.1µF
3V 5V
SUPPLY
02930-018
Figure 18. REF193 as Power Supply to AD7476A/
AD7477A/AD7478A
Table 7 provides typical performance data with various
references used as a VDD source for a 100 kHz input tone at
room temperature under the same setup conditions.
Table 7. AD7476A Typical Performance for Various Voltage
References
Reference Tied to VDD AD7476A SNR Performance (dB)
AD780 @ 3 V 72.65
REF193 72.35
AD780 @ 2.5 V 72.5
REF192 72.2
REF43 72.6
ANALOG INPUT
Figure 19 shows an equivalent circuit of the analog input
structure of the AD7476A/AD7477A/AD7478A. The two
diodes, D1 and D2, provide ESD protection for the analog
input. Care must be taken to ensure that the analog input signal
never exceeds the supply rails by more than 300 mV. This
causes the diodes to become forward-biased and start
conducting current into the substrate. The maximum current
these diodes can conduct without causing irreversible damage
to the part is 10 mA. The Capacitor C1 in Figure 19 is typically
about 6 pF and can primarily be attributed to pin capacitance.
The Resistor R1 is a lumped component made up of the on
resistance of a switch. This resistor is typically about 100 Ω. The
Capacitor C2 is the ADC sampling capacitor and has a
capacitance of 20 pF typically.
For ac applications, removing high frequency components from
the analog input signal is recommended by use of a band-pass
filter on the relevant analog input pin. In applications where
harmonic distortion and signal-to-noise ratio are critical, drive
the analog input from a low impedance source. Large source
impedances significantly affect the ac performance of the ADC,
necessitating the use of an input buffer amplifier. The choice of
the op amp is a function of the particular application.
D1
D2
R1
C2
20pF
V
DD
V
IN
C1
6pF
CONVERSION PHASE – SWITCH OPEN
TRACK PHASE – SWITCH CLOSED
02930-019
Figure 19. Equivalent Analog Input Circuit
AD7476A/AD7477A/AD7478A
Rev. F | Page 17 of 28
Table 8 provides typical performance data with various op amps
used as the input buffer for a 100 kHz input tone at room
temperature under the same setup conditions.
Table 8. AD7476A Typical Performance with Various Input
Buffers, VDD = 3 V
Op Amp in the Input Buffer AD7476A SNR Performance (dB)
AD711 72.3
AD797 72.5
AD845 71.4
When no amplifier is used to drive the analog input, limit the
source impedance to low values. The maximum source imped-
ance depends on the amount of total harmonic distortion (THD)
that can be tolerated. The THD increases as the source impedance
increases, degrading the performance (see Figure 13).
DIGITAL INPUTS
The digital inputs applied to the AD7476A/AD7477A/AD7478A
are not limited by the maximum ratings that limit the analog
input. Instead, the digital inputs applied can reach 7 V and are
not restricted by the VDD + 0.3 V limit as on the analog input.
For example, if operating the AD7476A/AD7477A/AD7478A
with a VDD of 3 V, u s e 5 V logic levels on the digital inputs.
However, note that the data output on SDATA still has 3 V logic
levels when VDD = 3 V. Another advantage of SCLK and CS not
being restricted by the VDD + 0.3 V limit is that power supply
sequencing issues are avoided. If CS or SCLK are applied before
VDD, there is no risk of latch-up as there would be on the analog
input if a signal greater than 0.3 V were applied prior to VDD.
AD7476A/AD7477A/AD7478A
Rev. F | Page 18 of 28
MODES OF OPERATION
The modes of operation for the AD7476A/AD7477A/AD7478A
are selected by controlling the (logic) state of the CS signal during
a conversion. There are two possible modes of operation: normal
and power-down. The point at which CS is pulled high after the
conversion has been initiated determines whether the AD7476A/
AD7477A/AD7478A enters power-down mode. Similarly, if
already in power-down, CS can control whether the device returns
to normal operation or remains in power-down. These modes of
operation are designed to provide flexible power management
options. These options can be chosen to optimize the power
dissipation/throughput rate ratio for different application
requirements.
NORMAL MODE
This mode is intended for the fastest throughput rate performance.
In normal mode, the user does not have to worry about any
power-up times because AD7476A/AD7477A/AD7478A
remain fully powered at all times. Figure 20 shows the general
diagram of the operation of the AD7476A/AD7477A/AD7478A
in this mode. The conversion is initiated on the falling edge of
CS as described in the Serial Interface section. To ensure that
the part remains fully powered up at all times, CS must remain
low until at least 10 SCLK falling edges have elapsed after the
falling edge of CS. If CS is brought high any time after the 10th
SCLK falling edge but before the end of the tCONVERT, the part
remains powered up, but the conversion is terminated and
SDATA goes back into three-state. For the AD7476A, 16 serial
clock cycles are required to complete the conversion and access
the complete conversion results. For the AD7477A and AD7478A,
a minimum of 14 and 12 serial clock cycles are required to com-
plete the conversion and access the complete conversion results,
respectively. CS can idle high until the next conversion or idle
low until CS returns high sometime prior to the next conversion
(effectively idling CS low). Once a data transfer is complete
(SDATA has returned to three-state), another conversion can be
initiated after the quiet time, tQUIET, has elapsed by bringing CS
low again.
POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required; either the ADC is powered down
between each conversion, or a series of conversions is performed
at a high throughput rate and the ADC is then powered down
for a relatively long duration between these bursts of several
conversions. When the AD7476A/AD7477A/AD7478A are in
power-down, all analog circuitry is powered down. To enter
power-down, the conversion process must be interrupted by
bringing CS high anywhere after the second falling edge of SCLK
and before the 10th falling edge of SCLK, as shown in Figure 22.
Once CS has been brought high in this window of SCLKs, the
part enters power-down, the conversion that was initiated by
the falling edge of CS is terminated, and SDATA goes back into
three-state. If CS is brought high before the second SCLK falling
edge, the part remains in normal mode and does not power
down. This avoids accidental power-down due to glitches on the
CS line. In order to exit this mode of operation and power up
the AD7476A/AD7477A/AD7478A again, a dummy conversion
is performed. On the falling edge of CS, the device begins to
power up and continues to power up as long as CS is held low
until after the falling edge of the 10th SCLK. The device is fully
powered up once 16 SCLKs have elapsed, and valid data results
from the next conversion, as shown in Figure 24. If CS is
brought high before the 10th falling edge of SCLK, then the
AD7476A/AD7477A/AD7478A go back into power-down. This
avoids accidental power-up due to glitches on the CS line or an
inadvertent burst of eight SCLK cycles while CS is low.
Although the device can begin to power up on the falling edge
of CS, it powers down again on the rising edge of CS as long as it
occurs before the 10th SCLK falling edge.
POWER-UP TIME
The power-up time of the AD7476A/AD7477A/AD7478A is
1 µs, meaning that with any frequency of SCLK up to 20 MHz,
one dummy cycle is always sufficient to allow the device to
power up. Once the dummy cycle is complete, the ADC is fully
powered up and the input signal is acquired properly. The quiet
time, tQUIET, must still be allowed from the point where the bus
goes back into three-state after the dummy conversion to the
next falling edge of CS. When running at a 1 MSPS throughput
rate, the AD7476A/AD7477A/AD7478A power up and acquire
a signal within 0.5 LSB in one dummy cycle, that is, 1 µs.
When powering up from the power-down mode with a dummy
cycle, as in Figure 22, the track-and-hold that was in hold mode
while the part was powered down returns to track mode after
the first SCLK edge the part receives after the falling edge of CS.
This is shown as Point A in Figure 22. Although at any SCLK
frequency, one dummy cycle is sufficient to power up the device
and acquire VIN, it does not necessarily mean that a full dummy
cycle of 16 SCLKs must always elapse to power up the device
and acquire VIN fully; 1 µs is sufficient to power up the device
and acquire the input signal. If, for example, a 5 MHz SCLK
frequency is applied to the ADC, the cycle time becomes 3.2 µs.
In one dummy cycle, 3.2 µs, the part powers up and VIN
acquires fully. However, after 1 µs with a 5 MHz SCLK, only five
SCLK cycles would have elapsed. At this stage, the ADC would
fully power up and acquire the signal. In this case, the CS can be
brought high after the 10th SCLK falling edge and brought low
again after a time, tQUIET, to initiate the conversion.
AD7476A/AD7477A/AD7478A
Rev. F | Page 19 of 28
SDATA
SCLK
CS
1 10 12 14 16
AD7476A/AD7477A/AD7478A
02930-020
VALID DATA
Figure 20. Normal Mode Operation
THREE-STATE
SDATA
SCLK
CS
1 10 12 14 16
2
02930-021
Figure 21. Entering Power-Down Mode
INVALID DATA
SDATA
SCLK
CS
1 10 12 14 16
A1 16
VALID DATA
THE PART IS FULLY
POWERED UPWITH
VIN FULLY ACQUIRED
THE PART
BEGINSTO
POWER UP
02930-022
Figure 22. Exiting Power-Down Mode
When power supplies are first applied to the AD7476A/AD7477A/
AD7478A, the ADC can power up in either the power-down or
normal modes. Because of this, it is best to allow a dummy cycle
to elapse to ensure that the part is fully powered up before
attempting a valid conversion. Likewise, if it is intended to keep
the part in the power-down mode while not in use and the user
wishes the part to power up in power-down mode, the dummy
cycle can be used to ensure that the device is in power-down by
executing a cycle such as that shown in Figure 22. Once supplies
are applied to the AD7476A/AD7477A/AD7478A, the power-up
time is the same as that when powering up from the power-down
mode. It takes approximately 1 μs to power up fully if the part
powers up in normal mode. It is not necessary to wait 1 μs before
executing a dummy cycle to ensure the desired mode of operation.
Instead, a dummy cycle can occur directly after power is
supplied to the ADC. If the first valid conversion is performed
directly after the dummy conversion, care must be taken to
ensure that an adequate acquisition time has been allowed. As
mentioned earlier, when powering up from the power-down
mode, the part returns to track upon the first SCLK edge
applied after the falling edge of CS. However, when the ADC
initially powers up after supplies are applied, the track-and-hold
is already in track. This means, assuming one has the facility to
monitor the ADC supply current, if the ADC powers up in the
desired mode of operation and thus a dummy cycle is not
required to change the mode, a dummy cycle is not required to
place the track-and-hold into track.
AD7476A/AD7477A/AD7478A
Rev. F | Page 20 of 28
POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7476A/AD7477A/
AD7478A when not converting, the average power consump-
tion of the ADC decreases at lower throughput rates. Figure 23
shows that as the throughput rate is reduced, the device remains
in its power-down state longer and the average power consumption
over time drops accordingly.
For example, if the AD7476A/AD7477A/AD7478A operate in a
continuous sampling mode with a throughput rate of 100 kSPS
and an SCLK of 20 MHz (VDD = 5 V) and the devices are placed
in the power-down mode between conversions, the power
consumption is calculated as follows:
The power dissipation during normal operation is 17.5 mW
(VDD = 5 V). If the power-up time is one dummy cycle, that is,
1 μs, and the remaining conversion time is another cycle, that is,
1 μs, then the AD7476A/AD7477A/AD7478A dissipate 17.5 mW
for 2 μs during each conversion cycle.
If the throughput rate is 100 kSPS, the cycle time is 10 μs, then
the average power dissipated during each cycle is (2/10) ×
(17.5 mW) = 3.5 mW.
If VDD = 3 V, SCLK = 20 MHz, and the devices are again in
power-down mode between conversions, then the power
dissipation during normal operation is 5.1 mW. Thus, the
AD7576A/AD7477A/AD8478A dissipate 5.1 mW for 2 μs
during each conversion cycle. With a throughput rate of
100 kSPS, the average power dissipated during each cycle is
(2/10) × (5.1 mW) = 1.02 m W.
Figure 23 shows the power vs. the throughput rate when using
the power-down mode between conversions with both 5 V and
3 V supplies. The power-down mode is intended for use with
throughput rates of approximately 333 kSPS or less, because at
higher sampling rates, the power-down mode produces no
power savings.
THROUGHPUT (kSPS)
100
0.1
0
POWER (mW)
10
1
0.01 50 100 150 200 250 300 350
V
DD
= 5V, SCLK = 20MHz
V
DD
= 3V, SCLK = 20MHz
02930-023
Figure 23. Power vs. Throughput
AD7476A/AD7477A/AD7478A
Rev. F | Page 21 of 28
SERIAL INTERFACE
Figure 24, Figure 25, and Figure 26 show the detailed timing
diagrams for serial interfacing to the AD7476A, AD7477A, and
AD7478A, respectively. The serial clock provides the conversion
clock and also controls the transfer of information from the
AD7476A/AD7477A/AD7478A during conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
and takes the bus out of three-state; the analog input is sampled
at this point. Also, the conversion is initiated at this point.
For the AD7476A, the conversion requires 16 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-
and-hold goes back into track on the next SCLK rising edge, as
shown in Figure 24 at Point B. On the 16th SCLK falling edge,
the SDATA line goes back into three-state. If the rising edge of
CS occurs before 16 SCLKs have elapsed, the conversion is
terminated and the SDATA line goes back into three-state;
otherwise, SDATA returns to three-state on the 16th SCLK
falling edge, as shown in Figure 24. Sixteen serial clock cycles
are required to perform the conversion process and to access
data from the AD7476A.
For the AD7477A, the conversion requires 14 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-
and-hold goes back into track on the next rising edge as shown
at Point B in Figure 25. If the rising edge of CS occurs before
14 SCLKs have elapsed, the conversion is terminated and the
SDATA line goes back into three-state. If 16 SCLKs are
considered in the cycle, SDATA returns to three-state on the
16th SCLK falling edge, as shown in Figure 25.
For the AD7478A, the conversion requires 12 SCLK cycles to
complete. The track-and-hold goes back into track on the rising
edge after the 11th falling edge, as shown in Figure 26 at Point B. If
the rising edge of CS occurs before 12 SCLKs have elapsed, the
conversion is terminated and the SDATA line goes back into three-
state. If 16 SCLKs are considered in the cycle, SDATA returns to
three-state on the 16th SCLK falling edge, as shown in Figure 26.
CS
SCLK
S
DATA
t
2
t
6
t
3
t
4
t
7
t
5
t
8
t
CONVERT
t
QUIET
ZERO ZERO ZERO DB11 DB10 DB2 DB1 DB0
B
THREE-STATETHREE-
STATE
Z
4 LEADING ZEROS
1 3 13 14 15 16
t
1
1/THROUGHPUT
245
02930-024
Figure 24. AD7476A Serial Interface Timing Diagram
SCLK 1 5 13 15
THREE-STATE
t
4
2 16
t
5
t
3
t
2
DB9 DB8 DB0 ZERO
t
6
t
7
t
8
14
4 LEADING ZEROS
ZERO ZERO ZERO Z
t
1
1/THROUGHPUT
ZERO
2 TRAILING ZEROS
SDATA
t
CONVERT
t
QUIET
B
THREE-STATE
CS
4
02930-025
3
Figure 25. AD7477A Serial Interface Timing Diagram
CS
SCLK 113 15
SDATA
4 LEADING ZEROS
THREE-STATE
t
4
2316
t
5
t
3
t
2
THREE-STATE
DB7
t
6
t
7
t
8
14
ZERO ZERO ZERO Z
t
1
1/ THROUGHPUT
ZERO ZERO ZERO ZERO
11 12
4 TRAILING ZEROS
t
CONVERT
t
QUIET
B
4
02930-026
Figure 26. AD7478A Serial Interface Timing Diagram
AD7476A/AD7477A/AD7478A
Rev. F | Page 22 of 28
CS going low clocks out the first leading zero to be read in by
the microcontroller or DSP. The remaining data is then clocked
out by subsequent SCLK falling edges beginning with the
second leading zero. Thus, the first falling clock edge on the
serial clock has the first leading zero provided and also clocks
out the second leading zero. For the AD7476A, the final bit in
the data transfer is valid on the 16th falling edge, having been
clocked out on the previous (15th) falling edge.
In applications with a slower SCLK, it is possible to read in data
on each SCLK rising edge. In this case, the first falling edge of
SCLK clocks out the second leading zero, which can be read in
the first rising edge. However, the first leading zero that was
clocked out when CS went low will be missed, unless it was not
read in the first falling edge. The 15th falling edge of SCLK clocks
out the last bit and it can be read in the 15th rising SCLK edge.
If CS goes low just after one SCLK falling edge has elapsed, CS
clocks out the first leading zero as it did before, and it can be
read in the SCLK rising edge. The next SCLK falling edge clocks
out the second leading zero, and it can be read in the following
rising edge.
AD7478A IN A 12 SCLK CYCLE SERIAL INTERFACE
For the AD7478A, if CS is brought high in the 12th rising edge
after four leading zeros and eight bits of the conversion have
been provided, the part can achieve a 1.2 MSPS throughput
rate. For the AD7478A, the track-and-hold goes back into track
in the 11th rising edge. In this case, a fSCLK = 20 MHz and a
throughput of 1.2 MSPS give a cycle time of
t2 + 10.5(1/fSCLK)+ tACQ = 833 ns
With t2 = 10 ns min, this leaves tACQ to be 298 ns. This 298 ns
satisfies the requirement of 225 ns for tACQ.
From Figure 27, tACQ is comprised of
0.5 (1/fSCLK) + t8 + tQUIET
where t8 = 36 ns maximum.
This allows a value of 237 ns for tQUIET, satisfying the minimum
requirement of 50 ns.
SCLK
t
1
1
5
11
SDATA
THREE-STATE DB7 DB6 DB0
ZERO
ZERO
ZERO
4 LEADING ZEROS
2 3
t
2
t
8
12
1/THROUGHPUT
t
ACQ
10.5(1/
f
SCLK
)
t
CONVERT
t
QUIET
B
THREE-STATE
CS
4
02930-027
Z
Figure 27. AD7478A in a 12 SCLK Cycle Serial Interface
AD7476A/AD7477A/AD7478A
Rev. F | Page 23 of 28
MICROPROCESSOR INTERFACING
The serial interface on the AD7476A/AD7477A/AD7478A
allows the part to be directly connected to a range of different
microprocessors. This section explains how to interface the
AD7476A/AD7477A/AD7478A with some of the more
common microcontroller and DSP serial interface protocols.
AD7476A/AD7477A/AD7478A TO TMS320C541
INTERFACE
The serial interface on the TMS320C541 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices, such as
the AD7476A/AD7477A/AD7478A. The CS input allows easy
interfacing between the TMS320C541 and the AD7476A/
AD7477A/AD7478A without any glue logic required. The serial
port of the TMS320C541 is set up to operate in burst mode
(FSM = 1 in the serial port control register, SPC) with Internal
Serial Clock CLKX (MCM = 1 in the SPC register) and internal
frame signal (TXM = 1 in the SPC register), so both pins are
configured as outputs. For the AD7476A, set the word length to
16 bits (FO = 0 in the SPC register). This DSP only allows
frames with a word length of 16 bits or 8 bits. Therefore, in the
case of the AD7477A and AD7478A where 14 bits and 12 bits
are required, the FO bit is set up to 16 bits. This means that to
obtain the conversion result, 16 SCLKs are needed. In both
situations, the remaining SCLKs clock out trailing zeros. For the
AD7477A, two trailing zeros are clocked out in the last two clock
cycles; for the AD7478A, four trailing zeros are clocked out.
To summarize, the values in the SPC register are
FO = 0
FSM = 1
MCM = 1
TXM = 1
The format bit, FO, can be set to 1 to set the word length to
eight bits in order to implement the power-down mode on the
AD7476A/AD7477A/AD7478A.
The connection diagram is shown in Figure 28. For signal
processing applications, it is imperative that the frame
synchronization signal from the TMS320C541 provide
equidistant sampling.
AD7476A/
AD7477A/
AD7478A
1
SCLK
SDATA
CS
CLKX
CLKR
FSX
FSR
TMS320C541
1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
DR
02930-028
Figure 28. Interfacing to the TMS320C541
AD7476A/AD7477A/AD7478A TO ADSP-218x
INTERFACE
The ADSP-218x family of DSPs are interfaced directly to the
AD7476A/AD7477A/AD7478A without any glue logic
required. Set up the SPORT control register as follows:
TFSW = RFSW = 1, alternate framing
INVRFS = INVTFS = 1, active low frame signal
DTYPE = 00, right justify data
ISCLK = 1, internal serial clock
TFSR = RFSR = 1, frame every word
IRFS = 0, sets up RFS as an input
ITFS = 1, sets up TFS as an output
SLEN = 1111, 16 bits for the AD7476A
SLEN = 1101, 14 bits for the AD7477A
SLEN = 1011, 12 bits for the AD7478A
AD7476A/AD7477A/AD7478A
Rev. F | Page 24 of 28
To implement the power-down mode, set SLEN to 0111 to issue
an 8-bit SCLK burst. The connection diagram is shown in
Figure 29. The ADSP-218x has the TFS and RFS of the SPORT
tied together, with TFS set as an output and RFS set as an input.
The DSP operates in alternate framing mode, and the SPORT
control register is set up as described. The frame synchronization
signal generated on the TFS is tied to CS, and, as with all signal
processing applications, equidistant sampling is necessary.
However, in this example, the timer interrupt is used to control
the sampling rate of the ADC and, under certain conditions,
equidistant sampling may not be achieved.
AD7476A/
AD7477A/
AD7478A
1
SCLK
SDATA
CS
SCLK
DR
RFS
TFS
ADSP-218x
1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
02930-029
Figure 29. Interfacing to the ADSP-218x
The timer registers, for example, are loaded with a value that
provides an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS controls the RFS and, thus, the reading
of data. The frequency of the serial clock is set in the SCLKDIV
register. When the instruction to transmit with TFS is given,
that is, TX0 = AX0, the state of the SCLK is checked. The DSP
waits until the SCLK has gone high, low, and high before
transmission starts. If the timer and SCLK values are chosen
such that the instruction to transmit occurs on or near the
rising edge of SCLK, the data can be transmitted or it can wait
until the next clock edge. For example, the ADSP-2111 has a
master clock frequency of 16 MHz. If the SCLKDIV register is
loaded with the Value 3, an SCLK of 2 MHz is obtained and
eight master clock periods will elapse for every one SCLK
period. If the timer registers are loaded with the Value 803,
100.5 SCLKs occur between interrupts and, subsequently,
between transmit instructions. This situation results in
nonequidistant sampling as the transmit instruction is
occurring on an SCLK edge. If the number of SCLKs between
interrupts is a whole integer figure of N, equidistant sampling is
implemented by the D S P.
AD7476A/AD7477A/AD7478A TO DSP563xx
INTERFACE
The connection diagram in Figure 30 shows how the
AD7476A/AD7477A/AD7478A can be connected to the SSI
(synchronous serial interface) of the DSP563xx family of DSPs
from Motorola. The SSI is operated in synchronous and normal
mode (SYN 1 = and MOD = 0 in Control Register B, CRB) with
internally generated word length frame sync for both Tx and Rx
(Bit FSL1 = 0 and Bit FSL0 = 0 in CRB). Set the word length in
Control Register A (CRA) to 16 by setting Bit WL2 = 0, Bit
WL1 = 1, and Bit WL0 = 0 for the AD7476A. The word length
for the AD7478A can be set to 12 bits (WL2 = 0, WL1 = 0, and
WL0 = 1). This DSP does not offer the option for a 14-bit word
length, so the AD7477A word length is set up to 16 bits, the
same as the AD7476A. For the AD7477A, the conversion process
uses 16 SCLK cycles, with the last two clock periods clocking out
two trailing zeros to fill the 16-bit word.
To implement the power-down mode on the AD7476A/AD7477A/
AD7478A, the word length can be changed to eight bits by setting
Bit WL2 = 0, Bit WL1 = 0, and Bit WL0 = 0 in CRA. The FSP
bit in the CRB register can be set to 1, meaning the frame goes
low and a conversion starts. Likewise, by means of the Bit SCD2,
Bit SCKD, and Bit SHFD in the CRB register, it establishes that
Pin SC2 (the frame sync signal) and Pin SCK in the serial port
are configured as outputs and the MSB is shifted first.
In summary:
MOD = 0
SYN = 1
WL2, WL1, and WL0 depend on the word length
FSL1 = 0 and FSL0 = 0
FSP = 1, negative frame sync
SCD2 = 1
SCKD = 1
SHFD = 0
Note that for signal processing applications, it is imperative that
the frame synchronization signal from the DSP563xx provide
equidistant sampling.
AD7476A/
AD7477A
AD7478A
1
SDATA
SCLK
CS
DSP563xx
1
SCK
SRD
SC2
1
ADDITIONAL PINS OMITTED FOR CLARITY.
02930-030
Figure 30. Interfacing to the DSP563xx
AD7476A/AD7477A/AD7478A
Rev. F | Page 25 of 28
APPLICATION HINTS
GROUNDING AND LAYOUT
Design the printed circuit board that houses the AD7476A/
AD7477A/AD7478A such that the analog and digital sections
are separated and confined to certain areas of the board. This
facilitates the use of ground planes that can be separated easily.
A minimum etch technique is generally best for ground planes
because it gives the best shielding. Join digital and analog
ground planes at only one place. If the AD7476A/AD7477A/
AD7478A is in a system where multiple devices require an
AGND to DGND connection, make the connection at one
point only, a star ground point that is established as close as
possible to the AD7476A/AD7477A/AD7478A.
Avoid running digital lines under the device as these couple
noise onto the die. Allow the analog ground plane to run under
the AD7476A/AD7477A/AD7478A in order to avoid noise
coupling. Use as large a trace as possible on the power supply
lines to the AD7476A/AD7477A/AD7478A to provide low
impedance paths and reduce the effects of glitches on the power
supply line. Shield fast switching signals like clocks with digital
grounds to avoid radiating noise to other sections of the board,
and never run clock signals near the analog inputs. Avoid crossover
of digital and analog signals. Run traces on opposite sides of the
board at right angles to each other. This reduces the effects of
feedthrough through the board. A microstrip technique is by far
the best but is not always possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground planes while signals are placed on the solder side.
Good decoupling is also very important. Decouple the supply
with, for instance, a 680 nF 0805 capacitor to GND. When using
the SC70 package in applications where the size of the components
is of concern, a 220 nF 0603 capacitor, for example, can be used
instead. However, in that case, the decoupling may not be as
effective, resulting in an approximate SINAD degradation of
0.3 dB. To achieve the best performance from these decoupling
components, the user should endeavor to keep the distance
between the decoupling capacitor and the VDD and GND pins to
a minimum with short track lengths connecting the respective
pins. Figure 31 and Figure 32 and show the recommended
positions of the decoupling capacitor for the SC70 and MSOP
packages, respectively.
02930-032
Figure 31. Recommended Supply Decoupling Scheme for the SC70 Package
As can be seen in Figure 32, for the MSOP package, the
decoupling capacitor has been placed as close as possible to the
IC with short track lengths to VDD and GND pins. The
decoupling capacitor can also be placed on the underside of the
PCB directly underneath the IC, between the VDD and GND
pins attached by vias. This method is not recommended on
PCBs above a standard 1.6 mm thickness. The best performance
is realized with the decoupling capacitor on the top of the PCB
next to the IC.
Similarly, for the SC70 package, locate the decoupling capacitor
as close as possible to the VDD and the GND pins. Because of its
pinout, that is, VDD being next to GND, the decoupling capacitor
can be placed extremely close to the IC. The decoupling capacitor
can be placed on the underside of the PCB directly under the
VDD and GND pins, but the best performance is achieved with
the decoupling capacitor on the same side as the IC.
02930-031
Figure 32. Recommended Supply Decoupling Scheme for the
AD7476A/AD7477A/AD7478A MSOP Package
EVALUATING THE AD7476A/AD7477A
PERFORMANCE
The evaluation board package includes a fully assembled and
tested evaluation board, documentation, and software for
controlling the board from the PC via the EVAL-BOARD
CONTROLLER. The EVAL-BOARD CONTROLLER can be
used in conjunction with the AD7476ACB/AD7477ACB
evaluation board, as well as many other Analog Devices
evaluation boards ending in the CB designator, to
demonstrate/evaluate the ac and dc performance of the
AD7476A/AD7477A. The software allows the user to perform
ac (fast Fourier transform) and dc (histogram of codes) tests on
the AD7476A/AD7477A. See the evaluation board application
note for more information.
AD7476A/AD7477A/AD7478A
Rev. F | Page 26 of 28
OUTLINE DIMENSIONS
1.30 BSC
COMPLIANT TO JEDEC STANDARDS MO-203-AB
1.00
0.90
0.70
0.46
0.36
0.26
2.20
2.00
1.80
2.40
2.10
1.80
1.35
1.25
1.15
072809-A
0.10 MAX
1.10
0.80
0.40
0.10
0.22
0.08
3
1 2
46 5
0.65 BSC
COPLANARITY
0.10
SEATING
PLANE
0.30
0.15
Figure 33. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
COMP
LIANT TO JEDEC STANDARDS MO-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 34. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2, 3, 4 Temperature Range Linearity Error (LSB)5 Package Description Package Option6 Branding
AD7476AAKSZ-500RL7 –40°C to +85°C ±0.75 typical 6-Lead SC70 KS-6 C3V
AD7476AAKSZ-REEL –40°C to +85°C ±0.75 typical 6-Lead SC70 KS-6 C3V
AD7476AAKSZ-REEL7 –40°C to +85°C ±0.75 typical 6-Lead SC70 KS-6 C3V
AD7476ABKSZ-500RL7 –40°C to +85°C ±1.5 maximum 6-Lead SC70 KS-6 C3W
AD7476ABKSZ-REEL –40°C to +85°C ±1.5 maximum 6-Lead SC70 KS-6 C3W
AD7476ABKSZ-REEL7 –40°C to +85°C ±1.5 maximum 6-Lead SC70 KS-6 C3W
AD7476ABRM –40°C to +85°C ±1.5 maximum 8-Lead MSOP RM-8 CEY
AD7476ABRM-REEL –40°C to +85°C ±1.5 maximum 8-Lead MSOP RM-8 CEY
AD7476ABRM-REEL7 –40°C to +85°C ±1.5 maximum 8-Lead MSOP RM-8 CEY
AD7476ABRMZ –40°C to +85°C ±1.5 maximum 8-Lead MSOP RM-8 C3W
AD7476ABRMZ-REEL –40°C to +85°C ±1.5 maximum 8-Lead MSOP RM-8 C3W
AD7476ABRMZ-REEL7 –40°C to +85°C ±1.5 maximum 8-Lead MSOP RM-8 C3W
AD7476AWYRMZ –40°C to +125°C ±1.5 maximum 8-Lead MSOP RM-8 C45
AD7476AWYRMZ-RL7 –40°C to +125°C ±1.5 maximum 8-Lead MSOP RM-8 C45
AD7476AYKSZ-500RL7 –40°C to +125°C ±1.5 maximum 6-Lead SC70 KS-6 C45
AD7476AYKSZ-REEL7 –40°C to +125°C ±1.5 maximum 6-Lead SC70 KS-6 C45
AD7476AYRMZ –40°C to +125°C ±1.5 maximum 8-Lead MSOP RM-8 C45
AD7476AYRMZ-REEL7 –40°C to +125°C ±1.5 maximum 8-Lead MSOP RM-8 C45
AD7477AAKSZ-500RL7 –40°C to +85°C ±0.5 maximum 6-Lead SC70 KS-6 C3X
AD7477AAKSZ-REEL –40°C to +85°C ±0.5 maximum 6-Lead SC70 KS-6 C3X
AD7477AARM-REEL –40°C to +85°C ±0.5 maximum 8-Lead MSOP RM-8 CFZ
AD7477AARMZ –40°C to +85°C ±0.5 maximum 8-Lead MSOP RM-8 C3X
AD7477AARMZ-REEL –40°C to +85°C ±0.5 maximum 8-Lead MSOP RM-8 C3X
AD7477AARMZ-REEL7 –40°C to +85°C ±0.5 maximum 8-Lead MSOP RM-8 C3X
AD7477AWARMZ –40°C to +85°C ±0.5 maximum 8-Lead MSOP RM-8 C3X
AD7477AWARMZ-RL –40°C to +85°C ±0.5 maximum 8-Lead MSOP RM-8 C3X
AD7478AAKSZ-500RL7 –40°C to +85°C ±0.3 maximum 6-Lead SC70 KS-6 C48
AD7478AAKSZ-REEL –40°C to +85°C ±0.3 maximum 6-Lead SC70 KS-6 C48
AD7478AAKSZ-REEL7 –40°C to +85°C ±0.3 maximum 6-Lead SC70 KS-6 C48
AD7478AARM –40°C to +85°C ±0.3 maximum 8-Lead MSOP RM-8 CJZ
AD7478AARMZ –40°C to +85°C ±0.3 maximum 8-Lead MSOP RM-8 C48
AD7476A/AD7477A/AD7478A
Rev. F | Page 27 of 28
Model1, 2, 3, 4 Temperature Range Linearity Error (LSB)5 Package Description Package Option6 Branding
AD7478AARMZ-REEL –40°C to +85°C ±0.3 maximum 8-Lead MSOP RM-8 C48
AD7478AARMZ-REEL7 –40°C to +85°C ±0.3 maximum 8-Lead MSOP RM-8 C48
AD7478AWARMZ –40°C to +85°C ±0.3 maximum 8-Lead MSOP RM-8 C48
AD7478AWARMZ-RL –40°C to +85°C ±0.3 maximum 8-Lead MSOP RM-8 C48
EVAL-AD7476ACBZ Evaluation Board
EVAL-CONTROL BRD2 Evaluation Control
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 EVAL-AD7476ACBZ can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.
4 EVAL-CONTROL BRD2 is a complete unit, allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. To order a
complete evaluation kit, you will need to order the particular ADC evaluation board, for example, EVAL-AD7476ACB, the EVAL-CONTROLBRD2, and a 12 V ac
transformer. See relevant evaluation board application note for more information.
5 Linearity error here refers to integral nonlinearity.
6 KS = SC70; RM = MSOP.
AUTOMOTIVE PRODUCTS
The AD7476AWYRMZ, AD7476AWYRMZ-RL7, AD7477AWARMZ, AD7477AWARMZ-RL, AD7478AWARMZ, and
AD7478AWARMZ-RL models are available with controlled manufacturing to support the quality and reliability requirements of
automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for these models.
AD7476A/AD7477A/AD7478A
Rev. F | Page 28 of 28
NOTES
©2002–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02930-0-1/11(F)
