Fast, Voltage-Out, DC to 440 MHz,
95 dB Logarithmic Amplifier
AD8310
Rev. F
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FEATURES
Multistage demodulating logarithmic amplifier
Voltage output, rise time <15 ns
High current capacity: 25 mA into grounded RL
95 dB dynamic range: −91 dBV to +4 dBV
Single supply of 2.7 V min at 8 mA typ
DC to 440 MHz operation, ±0.4 dB linearity
Slope of +24 mV/dB, intercept of −108 dBV
Highly stable scaling over temperature
Fully differential dc-coupled signal path
100 ns power-up time, 1 mA sleep current
APPLICATIONS
Conversion of signal level to decibel form
Transmitter antenna power measurement
Receiver signal strength indication (RSSI)
Low cost radar and sonar signal processing
Network and spectrum analyzers
Signal-level determination down to 20 Hz
True-decibel ac mode for multimeters
FUNCTIONAL BLOCK DIAGRAM
+
–
VPOS
INHI
INLO
COMM
3
8mA
1.0kΩ
BAND GAP REFERENCE
AND BIASING
SIX 14.3dB 900MHz
AMPLIFIER STAGES
NINE DETECTOR CELLS
SPACED 14.3dB
INPUT-OFFSET
COMPENSATION LOOP
2
2μA
/
dB
MIRROR
3kΩ3kΩ
1kΩ
COMM
COMM
COMM
ENBL
BFIN
VOUT
OFLT
ENABLE
BUFFER
INPUT
OUTPUT
OFFSET
FILTER
AD8310
SUPPLY
+INPUT
–INPUT
COMMON
33pF
8
7
6
5
1
2
3
4
01084-001
Figure 1.
GENERAL DESCRIPTION
The AD8310 is a complete, dc to 440 MHz demodulating
logarithmic amplifier (log amp) with a very fast voltage mode
output, capable of driving up to 25 mA into a grounded load in
under 15 ns. It uses the progressive compression (successive
detection) technique to provide a dynamic range of up to 95 dB
to ±3 dB law conformance or 90 dB to a ±1 dB error bound up
to 100 MHz. It is extremely stable and easy to use, requiring no
significant external components. A single-supply voltage of
2.7 V to 5.5 V at 8 mA is needed, corresponding to a power
consumption of only 24 mW at 3 V. A fast-acting CMOS-
compatible enable pin is provided.
Each of the six cascaded amplifier/limiter cells has a small-
signal gain of 14.3 dB, with a −3 dB bandwidth of 900 MHz.
A total of nine detector cells are used to provide a dynamic
range that extends from −91 dBV (where 0 dBV is defined as
the amplitude of a 1 V rms sine wave), an amplitude of about
±40 μV, up to +4 dBV (or ±2.2 V). The demodulated output
is accurately scaled, with a log slope of 24 mV/dB and an
intercept of −108 dBV. The scaling parameters are supply-
and temperature-independent.
The fully differential input offers a moderately high impedance
(1 kΩ in parallel with about 1 pF). A simple network can match
the input to 50 Ω and provide a power sensitivity of −78 dBm to
+17 dBm. The logarithmic linearity is typically within ±0.4 dB
up to 100 MHz over the central portion of the range, but it is
somewhat greater at 440 MHz. There is no minimum frequency
limit; the AD8310 can be used down to low audio frequencies.
Special filtering features are provided to support this wide range.
The output voltage runs from a noise-limited lower boundary of
400 mV to an upper limit within 200 mV of the supply voltage
for light loads. The slope and intercept can be readily altered
using external resistors. The output is tolerant of a wide variety
of load conditions and is stable with capacitive loads of 100 pF.
The AD8310 provides a unique combination of low cost, small
size, low power consumption, high accuracy and stability, high
dynamic range, a frequency range encompassing audio to UHF,
fast response time, and good load-driving capabilities, making
this product useful in numerous applications that require the
reduction of a signal to its decibel equivalent.
The AD8310 is available in the industrial temperature range of
−40°C to +85°C in an 8-lead MSOP package.
AD8310
Rev. F | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ........................................................................ 9
Progressive Compression ............................................................ 9
Slope and Intercept Calibration ................................................ 10
Offset Control ............................................................................. 10
Product Overview ........................................................................... 11
Enable Interface .......................................................................... 11
Input Interface ............................................................................ 11
Offset Interface ........................................................................... 12
Output Interface ......................................................................... 12
Using the AD8310 .......................................................................... 14
Basic Connections ...................................................................... 14
Transfer Function in Terms of Slope and Intercept ............... 15
dBV vs. dBm ............................................................................... 15
Input Matching ........................................................................... 15
Narrow-Band Matching ............................................................ 16
General Matching Procedure .................................................... 16
Slope and Intercept Adjustments ............................................. 17
Increasing the Slope to a Fixed Value ...................................... 17
Output Filtering .......................................................................... 18
Lowering the High-Pass Corner Frequency of the Offset
Compensation Loop .................................................................. 18
Applications Information .............................................................. 19
Cable-Driving ............................................................................. 19
DC-Coupled Input ..................................................................... 19
Evaluation Board ............................................................................ 20
Die Information .............................................................................. 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
6/10—Rev. E to Rev. F
Added Die Information Section ................................................... 22
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23
6/05—Rev. D to Rev. E
Changes to Figure 6 .......................................................................... 6
Change to Basic Connections Section ......................................... 14
Changes to Equation 10 ................................................................. 17
Changes to Ordering Guide .......................................................... 22
10/04—Rev. C to Rev. D
Format Updated .................................................................. Universal
Typical Performance Characteristics Reordered .......................... 6
Changes to Figure 41 and Figure 42 ............................................. 20
7/03—Rev. B to Rev. C
Replaced TPC 12 ............................................................................... 5
Change to DC-Coupled Input Section ........................................ 14
Replaced Figure 20 ......................................................................... 15
Updated Outline Dimensions ....................................................... 16
2/03—Rev. A to Rev. B
Change to Evaluation Board Section ........................................... 15
Change to Table III ......................................................................... 16
Updated Outline Dimensions ....................................................... 16
1/00—Rev. 0 to Rev. A
10/99—Revision 0: Initial Version
AD8310
Rev. F | Page 3 of 24
SPECIFICATIONS
TA = 25°C, VS = 5 V, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
INPUT STAGE Inputs INHI, INLO
Maximum Input1
Single-ended, p-p ±2.0 ±2.2 V
4 dBV
Equivalent Power in 50 Ω Termination resistor of 52.3 Ω 17 dBm
Differential drive, p-p 20 dBm
Noise Floor Terminated 50 Ω source 1.28 nV/√Hz
Equivalent Power in 50 Ω 440 MHz bandwidth −78 dBm
Input Resistance From INHI to INLO 800 1000 1200 Ω
Input Capacitance From INHI to INLO 1.4 pF
DC Bias Voltage Either input 3.2 V
LOGARITHMIC AMPLIFIER Output VOUT
±3 dB Error Dynamic Range From noise floor to maximum input 95 dB
Transfer Slope 10 MHz ≤ f ≤ 200 MHz 22 24 26 mV/dB
Overtemperature, −40°C < TA < +85°C 20 26 mV/dB
Intercept (Log Offset)2
10 MHz ≤ f ≤ 200 MHz −115 −108 −99 dBV
Equivalent dBm (re 50 Ω) −102 −95 −86 dBm
Overtemperature, −40°C ≤ TA ≤ +85°C −120 −96 dBV
Equivalent dBm (re 50 Ω) −107 −83 dBm
Temperature sensitivity −0.04 dB/°C
Linearity Error (Ripple) Input from −88 dBV (−75 dBm) to +2 dBV (+15 dBm) ±0.4 dB
Output Voltage Input = −91 dBV (−78 dBm) 0.4 V
Input = 9 dBV (22 dBm) 2.6 V
Minimum Load Resistance, RL 100 Ω
Maximum Sink Current 0.5 mA
Output Resistance 0.05 Ω
Video Bandwidth 25 MHz
Rise Time (10% to 90%) Input level = −43 dBV (−30 dBm), RL ≥ 402 Ω, CL ≤ 68 pF 15 ns
Input level = −3 dBV (+10 dBm), RL ≥ 402 Ω, CL ≤ 68 pF 20 ns
Fall Time (90% to 10%) Input level = −43 dBV (−30 dBm), RL ≥ 402 Ω, CL ≤ 68 pF 30 ns
Input level = −3 dBV (+10 dBm), RL ≥ 402 Ω, CL ≤ 68 pF 40 ns
Output Settling Time to 1% Input level = −13 dBV (0 dBm), RL ≥ 402 Ω, CL ≤ 68 pF 40 ns
POWER INTERFACES
Supply Voltage, VPOS 2.7 5.5 V
Quiescent Current Zero signal 6.5 8.0 9.5 mA
Overtemperature −40°C < TA < +85°C 5.5 8.5 10 mA
Disable Current 0.05 μA
Logic Level to Enable Power High condition, −40°C < TA < +85°C 2.3 V
Input Current When High 3 V at ENBL 35 μA
Logic Level to Disable Power Low condition, −40°C < TA < +85°C 0.8 V
1 The input level is specified in dBV, because logarithmic amplifiers respond strictly to voltage, not power. 0 dBV corresponds to a sinusoidal single-frequency input of
1 V rms. A power level of 0 dBm (1 mW) in a 50 Ω termination corresponds to an input of 0.2236 V rms. Therefore, the relationship between dBV and dBm is a fixed
offset of 13 dBm in the special case of a 50 Ω termination.
2 Guaranteed but not tested; limits are specified at six sigma levels.
AD8310
Rev. F | Page 4 of 24
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage, VS 7.5 V
Input Power (re 50 Ω), Single-Ended 18 dBm
Differential Drive 22 dBm
Internal Power Dissipation 200 mW
θJA 200°C/W
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD8310
Rev. F | Page 5 of 24
01084-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
INLO
1
INHI
8
COMM
2
ENBL
7
OFLT
3
BFIN
6
VPOS
5
AD8310
TOP VIEW
(Not to Scale)
VOUT
4
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 INLO One of Two Balanced Inputs. Biased roughly to VPOS/2.
2 COMM Common Pin. Usually grounded.
3 OFLT Offset Filter Access. Nominally at about 1.75 V.
4 VOUT Low Impedance Output Voltage. Carries a 25 mA maximum load.
5 VPOS Positive Supply. 2.7 V to 5.5 V at 8 mA quiescent current.
6 BFIN Buffer Input. Used to lower postdetection bandwidth.
7 ENBL CMOS Compatible Chip Enable. Active when high.
8 INHI Second of Two Balanced Inputs. Biased roughly to VPOS/2.
AD8310
Rev. F | Page 6 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT LEVEL (dBV)
–120 20–100
(–87dBm) –80 –60 –40 –20 0
(+13dBm)
3.0
0
RSSI OUTPUT (V)
2.5
2.0
1.5
1.0
0.5
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
01084-011
Figure 3. RSSI Output vs. Input Level, 100 MHz Sine Input
at TA = −40°C, +25°C, and +85°C, Single-Ended Input
INPUT LEVEL (dBV)
–120 –100
(–87dBm) –80 –60 –40 –20 0
(+13dBm) 20
3.0
RSSI OUTPUT (V)
2.5
2.0
1.5
1.0
0.5
0
10MHz 50MHz
100MHz
01084-012
Figure 4. RSSI Output vs. Input Level at TA = 25°C
for Frequencies of 10 MHz, 50 MHz, and 100 MHz
INPUT LEVEL (dBV)
–120 20–100
(–87dBm) –80 –60 –40 –20 0
(+13dBm)
3.0
0
RSSI OUTPUT (V)
2.5
2.0
1.5
1.0
0.5
200MHz
300MHz
440MHz
01084-013
01084-043
P
IN
(dBm)
RSSI OUTPUT (V)
ERROR (dB)
3.0
2.5
2.0
1.5
1.0
0.5
0
3
2
1
0
–1
–2
–3
–90 –80 –70 –60 –50 –40 –30 –20 –10 0 10 20
Figure 5. RSSI Output vs. Input Level at TA = 25°C
for Frequencies of 200 MHz, 300 MHz, and 440 MHz
–40°C
25°C
85°C
–40°C 25°C
85°C
Figure 6. Log Linearity of RSSI Output vs. Input Level,
100 MHz Sine Input at TA = −40°C, +25°C, and +85°C
INPUT LEVEL (dBV)
5
–5
–120 20–100
(–87dBm)
ERROR (dB)
–80 –60 –40 –20 0
(+13dBm)
4
–1
–2
–3
–4
2
0
3
110MHz
50MHz
100MHz
01084-015
Figure 7. Log Linearity of RSSI Output vs. Input Level at TA = 25°C
for Frequencies of 10 MHz, 50 MHz, and 100 MHz
INPUT LEVEL (dBV)
5
–5
–120 20–100
(–87dBm)
ERROR (dB)
–80 –60 –40 –20 0
(+13dBm)
4
–1
–2
–3
–4
2
0
3
1200MHz
300MHz
440MHz
01084-016
Figure 8. Log Linearity of RSSI Output vs. Input Level at TA = 25°C
for Frequencies of 200 MHz, 300 MHz, and 440 MHz
AD8310
Rev. F | Page 7 of 24
50μs PER
HORIZONTAL
DIVISION
500mV PER
VERTICAL
DIVISION
V
OUT
100pF
3300pF
GROUND REFERENCE
0.01μF
V
OUT
500mV PER
VERTICAL
DIVISION 25ns PER
HORIZONTAL
DIVISION
GROUND REFERENCE
10mV PER
VERTICAL
DIVISION
INPUT
01084-009
Figure 9. Small-Signal AC Response of RSSI Output with External BFIN
Capacitance of 100 pF, 3300 pF, and 0.01 μF
01084-010
100ns PER
HORIZONTAL
DIVISION
GND REFERENCE
INPUT
500mV PER
VERTICAL
DIVISION
500mV PER
VERTICAL
DIVISION
V
OUT
154Ω
100Ω
200Ω
01084-005
Figure 10. Large-Signal RSSI Pulse Response with CL = 100 pF
and RL = 100 Ω, 154 Ω, and 200 Ω
100ns PER
HORIZONTAL
DIVISION
GND REFERENCE
INPUT
500mV PER
VERTICAL
DIVISION
V
OUT
500mV PER
VERTICAL
DIVISION
–3dBV INPUT
LEVEL SHOWN
HERE
Figure 12. Small-Signal RSSI Pulse Response
with RL = 402 Ω and CL = 68 pF
V
OUT
CURVES
OVERLAP
500mV PER
VERTICAL
DIVISION
GND REFERENCE
INPUT
100ns PER
HORIZONTAL
DIVISION
500mV PER
VERTICAL
DIVISION
01084-007
Figure 13. Large-Signal RSSI Pulse Response with RL = 100 Ω
and CL = 33 pF, 68 pF, and 100 pF
V
OUT
100ns PER
HORIZONTAL
DIVISION
01084-006
Figure 11. RSSI Pulse Response with RL = 402 Ω and CL = 68 pF,
for Inputs Stepped from 0 dBV to −33 dBV, −23 dBV, −13 dBV, and −3 dBV
20mV PER
VERTICAL
DIVISION
INPUT
200mV PER
VERTICAL
DIVISION
GND REFERENCE
01084-008
Figure 14. Small-Signal RSSI Pulse Response with RL = 50 Ω
and Back Termination of 50 Ω (Total Load = 100 Ω)
AD8310
Rev. F | Page 8 of 24
ENABLE VOLTAGE (V)
0.000010.5 2.50.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3
T
A
= –40°C
100
SUPPLY CURRENT (mA)
10
1
0.1
0.01
0.001
0.0001
T
A
= +85°C
T
A
= +25°C
V
OUT
–3dBV
500mV PER
VERTICAL
DIVISION
–23dBV
–43dBV
–63dBV
–83dBV
5V PER
VERTICAL
DIVISION
ENABLE
200ns PER HORIZONTAL DIVISION
01084-004
Figure 18. Power-On/Off Response Time
with RF Input of −83 dBV to −3 dBV
01084-003
Figure 15. Supply Current vs. Enable Voltage
at TA = −40°C, +25°C, and +85°C
FREQUENCY (MHz)
20 1 100010 100
21
30
29
RSSI SLOPE (mV/dB)
24
23
22
26
25
28
27
FREQUENCY (MHz)
–99
–101
–119 1 100010
RSSI INTERCEPT (dBV)
100
–111
–113
–115
–117
–107
–109
–103
–105
01084-018
01084-017
Figure 16. RSSI Slope vs. Frequency
Figure 19. RSSI Intercept vs. Frequency
INTERCEPT (dBV)
0
–115 –113
SLOPE (mV/dB)
0
21.5 22.0
5
30
10
COUNT
25
20
15
22.5 23.0 23.5 24.0 24.5
35
40 NORMAL
(23.6584,
0.308728)
NORMAL
(–107.6338,
2.36064)
12
4
COUNT
2
10
8
6
14
16
01084-019
Figure 17. Transfer Slope Distribution, VS = 5 V, Frequency = 100 MHz, 25°C
–111 –109 –107 –105 –103 –101 –99 –97
18
20
22
24
01084-020
Figure 20. Intercept Distribution, VS = 5 V, Frequency = 100 MHz, 25°C
AD8310
Rev. F | Page 9 of 24
THEORY OF OPERATION
(
)
O
IN
SLOPE
OUT PPVV −
=
Logarithmic amplifiers perform a more complex operation than
classical linear amplifiers, and their circuitry is significantly
different. A good grasp of what log amps do and how they do it
can help users avoid many pitfalls in their applications. For a
complete discussion of the theory, see the AD8307 data sheet.
The essential purpose of a log amp is not to amplify (though
amplification is needed internally), but to compress a signal of
wide dynamic range to its decibel equivalent. It is, therefore, a
measurement device. An even better term might be logarithmic
converter, because the function is to convert a signal from one
domain of representation to another via a precise nonlinear
transformation:
⎟
⎟
⎠
⎜
⎜
⎝
=
X
Y
OUT V
VV log ⎞⎛ IN
V (1)
where:
VOUT is the output voltage.
VY is the slope voltage. The logarithm is usually taken to
base ten, in which case VY is also the volts-per-decade.
VIN is the input voltage.
VX is the intercept voltage.
Log amps implicitly require two references (here VX and VY)
that determine the scaling of the circuit. The accuracy of a log
amp cannot be any better than the accuracy of its scaling
references. In the AD8310, these are provided by a band gap
reference.
V
OUT
5V
Y
4V
Y
3V
Y
2V
Y
V
Y
–2V
Y
V
OUT
=0
LOG V
IN
V
SHIFT
LOWER INTERCEPT
V
IN
=10
–2
V
X
–40dBc V
IN
=10
2
V
X
+40dBc V
IN
=10
4
V
X
+80dBc
V
IN
=V
X
0dBc
01084-021
Figure 21. General Form of the Logarithmic Function
While Equation 1, plotted in Figure 21, is fundamentally
correct, a different formula is appropriate for specifying the
calibration attributes or demodulating log amps like the
AD8310, operating in RF applications with a sine wave input.
(2)
where:
VOUT is the demodulated and filtered baseband (video or RSSI)
output.
VSLOPE is the logarithmic slope, now expressed in V/dB
(25 mV/dB for the AD8310).
PIN is the input power, expressed in dB relative to some
reference power level.
PO is the logarithmic intercept, expressed in dB relative to the
same reference level.
A widely used reference in RF systems is dB above 1 mW in
50 Ω, a level of 0 dBm. Note that the quantity (PIN − PO) is dB.
The logarithmic function disappears from the formula, because
the conversion has already been implicitly performed in stating
the input in decibels. This is strictly a concession to popular
convention. Log amps manifestly do not respond to power
(tacitly, power absorbed at the input), but rather to input
voltage. The input is specified in dBV (decibels with respect to
1 V rms) throughout this data sheet. This is more precise,
although still incomplete, because the signal waveform is also
involved. Many users specify RF signals in terms of power
(usually in dBm/50 Ω), and this convention is used in this data
sheet when specifying the performance of the AD8310.
PROGRESSIVE COMPRESSION
High speed, high dynamic-range log amps use a cascade of
nonlinear amplifier cells to generate the logarithmic function
as a series of contiguous segments, a type of piecewise linear
technique. The AD8310 employs six cells in its main signal
path, each having a small-signal gain of 14.3 dB (×5.2) and a
−3 dB bandwidth of about 900 MHz. The overall gain is about
20,000 (86 dB), and the overall bandwidth of the chain is
approximately 500 MHz, resulting in a gain-bandwidth product
(GBW) of 10,000 GHz, about a million times that of a typical
op amp. This very high GBW is essential to accurate operation
under small-signal conditions and at high frequencies. The
AD8310 exhibits a logarithmic response down to inputs as
small as 40 μV at 440 MHz.
Progressive compression log amps either provide a baseband
video response or accept an RF input and demodulate this
signal to develop an output that is essentially the envelope of the
input represented on a logarithmic or decibel scale. The
AD8310 is the latter kind. Demodulation is performed in a total
of nine detector cells. Six are associated with the amplifier
stages, and three are passive detectors that receive a progres-
sively attenuated fraction of the full input. The maximum signal
frequency can be 440 MHz, but, because all the gain stages are
dc-coupled, operation at very low frequencies is possible.
AD8310
Rev. F | Page 10 of 24
SLOPE AND INTERCEPT CALIBRATION
All monolithic log amps from Analog Devices use precision
design techniques to control the logarithmic slope and
intercept. The primary source of this calibration is a pair of
accurate voltage references that provide supply- and
temperature-independent scaling. The slope is set to 24 mV/dB
by the bias chosen for the detector cells and the subsequent gain
of the postdetector output interface. With this slope, the full
95 dB dynamic range can be easily accommodated within the
output swing capacity, when operating from a 2.7 V supply.
Intercept positioning at −108 dBV (−95 dBm re 50 Ω) has
likewise been chosen to provide an output centered in the
available voltage range.
Precise control of the slope and intercept results in a log amp
with stable scaling parameters, making it a true measurement
device as, for example, a calibrated received signal strength
indicator (RSSI). In this application, the input waveform is
invariably sinusoidal. The input level is correctly specified in
dBV. It can alternatively be stated as an equivalent power, in
dBm, but in this case, it is necessary to specify the impedance in
which this power is presumed to be measured. In RF practice, it
is common to assume a reference impedance of 50 Ω, in which
0 dBm (1 mW) corresponds to a sinusoidal amplitude of
316.2 mV (223.6 mV rms). However, the power metric is
correct only when the input impedance is lowered to 50 Ω,
either by a termination resistor added across INHI and INLO,
or by the use of a narrow-band matching network.
Note that log amps do not inherently respond to power, but to
the voltage applied to their input. The AD8310 presents a
nominal input impedance much higher than 50 Ω (typically
1 kΩ at low frequencies). A simple input matching network
can considerably improve the power sensitivity of this type of
log amp. This increases the voltage applied to the input and,
therefore, alters the intercept. For a 50 Ω reactive match, the
voltage gain is about 4.8, and the whole dynamic range moves
down by 13.6 dB. The effective intercept is a function of wave-
form. For example, a square-wave input reads 6 dB higher than
a sine wave of the same amplitude, and a Gaussian noise input
reads 0.5 dB higher than a sine wave of the same rms value.
OFFSET CONTROL
In a monolithic log amp, direct coupling is used between the
stages for several reasons. First, it avoids the need for coupling
capacitors, which typically have a chip area at least as large as
that of a basic gain cell, considerably increasing die size. Second,
the capacitor values predetermine the lowest frequency at which
the log amp can operate. For moderate values, this can be as
high as 30 MHz, limiting the application range. Third, the
parasitic back-plate capacitance lowers the bandwidth of the
cell, further limiting the scope of applications.
However, the very high dc gain of a direct-coupled amplifier
raises a practical issue. An offset voltage in the early stages of
the chain is indistinguishable from a real signal. If it were as
high as 400 μV, it would be 18 dB larger than the smallest ac
signal (50 μV), potentially reducing the dynamic range by this
amount. This problem can be averted by using a global feedback
path from the last stage to the first, which corrects this offset in
a similar fashion to the dc negative feedback applied around an
op amp. The high frequency components of the feedback signal
must, of course, be removed to prevent a reduction of the HF
gain in the forward path.
An on-chip filter capacitor of 33 pF provides sufficient suppres-
sion of HF feedback to allow operation above 1 MHz. The −3 dB
point in the high-pass response is at 2 MHz, but the usable range
extends well below this frequency. To further lower the frequency
range, an external capacitor can be added at OFLT (Pin 3). For
example, 300 pF lowers it by a factor of 10.
Operation at low audio frequencies requires a capacitor of about
1 μF. Note that this filter has no effect for input levels well above
the offset voltage, where the frequency range would extend
down to dc (for a signal applied directly to the input pins). The
dc offset can optionally be nulled by adjusting the voltage on
the OFLT pin (see the Applications Information section).
AD8310
Rev. F | Page 11 of 24
PRODUCT OVERVIEW
The AD8310 has six main amplifier/limiter stages. These six
cells and their and associated gm styled full-wave detectors
handle the lower two-thirds of the dynamic range. Three top-
end detectors, placed at 14.3 dB taps on a passive attenuator,
handle the upper third of the 95 dB range. The first amplifier
stage provides a low noise spectral density (1.28 nV/√Hz).
Biasing for these cells is provided by two references: one
determines their gain, and the other is a band gap circuit that
determines the logarithmic slope and stabilizes it against supply
and temperature variations. The AD8310 can be enabled or
disabled by a CMOS-compatible level at ENBL (Pin 7).
The differential current-mode outputs of the nine detectors are
summed and then converted to single-sided form, nominally
scaled 2 μA/dB. The output voltage is developed by applying
this current to a 3 kΩ load resistor followed by a high speed
gain-of-four buffer amplifier, resulting in a logarithmic slope of
24 mV/dB (480 mV/decade) at VOUT (Pin 4). The unbuffered
voltage can be accessed at BFIN (Pin 6), allowing certain
functional modifications such as the addition of an external
postdemodulation filter capacitor and the alteration or
adjustment of slope and intercept.
+
–
VPOS
INHI
INLO
COMM
3
8mA
1.0kΩ
BAND GAP REFERENCE
AND BIASING
SIX 14.3dB 900MHz
AMPLIFIER STAGES
NINE DETECTOR CELLS
SPACED 14.3dB
INPUT-OFFSET
COMPENSATION LOOP
2
2μA
/dB
MIRROR
3kΩ3kΩ
1kΩ
COMM
COMM
ENBL
BFIN
VOUT
OFLT
ENABLE
BUFFER
INPUT
OUTPUT
OFFSET
FILTER
AD8310
SUPPLY
+INPUT
–INPUT
COMMON
COMM
33pF
01084-022
Figure 22. Main Features of the AD8310
The last gain stage also includes an offset-sensing cell. This
generates a bipolarity output current, if the main signal path
exhibits an imbalance due to accumulated dc offsets. This
current is integrated by an on-chip capacitor that can be
increased in value by an off-chip component at OFLT (Pin 3).
The resulting voltage is used to null the offset at the output of
the first stage. Because it does not involve the signal input
connections, whose ac-coupling capacitors otherwise introduce
a second pole into the feedback path, the stability of the offset
correction loop is assured.
The AD8310 is built on an advanced, dielectrically isolated,
complementary bipolar process. In the following interface
diagrams shown in Figure 23 to Figure 26, resistors labeled as
R are thin-film resistors that have a low temperature coefficient
of resistance (TCR) and high linearity under large-signal
conditions. Their absolute tolerance is typically within ±20%.
Similarly, capacitors labeled as C have a typical tolerance of
±15% and essentially zero temperature or voltage sensitivity.
Most interfaces have additional small junction capacitances
associated with them, due to active devices or ESD protection,
which might not be accurate or stable. Component numbering
in these interface diagrams is local.
ENABLE INTERFACE
The chip-enable interface is shown in Figure 23. The currents in
the diode-connected transistors control the turn-on and turn-off
states of the band gap reference and the bias generator. They are
a maximum of 100 μA when ENBL is taken to 5 V under worst-
case conditions. For voltages below 1 V, the AD8310 is disabled
and consumes a sleep current of less than 1 μA. When tied to the
supply or a voltage above 2 V, it is fully enabled. The internal
bias circuitry is very fast (typically <100 ns for either off or on).
In practice, however, the latency period before the log amp
exhibits its full dynamic range is more likely to be limited by
factors relating to the use of ac coupling at the input or the
settling of the offset-control loop (see the following sections).
COMM
ENBL 40kΩ
TO BIAS
STAGES
AD8310
01084-023
2
7
Figure 23. Enable Interface
INPUT INTERFACE
Figure 24 shows the essentials of the input interface. CP and CM
are parasitic capacitances, and CD is the differential input
capacitance, largely due to Q1 and Q2. In most applications,
both input pins are ac-coupled. The S switches close when
enable is asserted. When disabled, bias current IE is shut off and
the inputs float; therefore, the coupling capacitors remain
charged. If the log amp is disabled for long periods, small
leakage currents discharge these capacitors. Then, if they are
poorly matched, charging currents at power-up can generate a
transient input voltage that can block the lower reaches of the
dynamic range until it becomes much less than the signal.
A single-sided signal can be applied via a blocking capacitor to
either Pin 1 or Pin 8, with the other pin ac-coupled to ground.
Under these conditions, the largest input signal that can be
handled is 0 dBV (a sine amplitude of 1.4 V) when using a 3 V
supply; a 5 dBV input (2.5 V amplitude) can be handled with a
5 V supply. When using a fully balanced drive, this maximum
input level is permissible for supply voltages as low as 2.7 V.
Above 10 MHz, this is easily achieved using an LC matching
network. Such a network, having an inductor at the input,
usefully eliminates the input transient noted above.
AD8310
Rev. F | Page 12 of 24
TOP-END
DETECTORS
COM
INHI
INLO
C
P
C
D
C
M
COM
4kΩ~3kΩ
125Ω
6kΩ
6kΩ
2kΩ
TYP 2.2V FOR
3V SUPPLY,
3.2V AT 5V
S
VPOS
I
E
2.4mA
Q1
Q2
S
COMM
01084-024
2
5
8
1
Figure 24. Signal Input Interface
Occasionally, it might be desirable to use the dc-coupled
potential of the AD8310 in baseband applications. The main
challenge here is to present the signal at the elevated common-
mode input level, which might require the use of low noise, low
offset buffer amplifiers. In some cases, it might be possible to
use dual supplies of ±3 V, which allow the input pins to operate
at ground potential. The output, which is internally referenced
to the COMM pin (now at −3 V), can be positioned back to
ground level, with essentially no sensitivity to the particular
value of the negative supply.
OFFSET INTERFACE
The input-referred dc offsets in the signal path are nulled via
the interface associated with Pin 3, shown in Figure 25. Q1
and Q2 are the first-stage input transistors, having slightly
unbalanced load resistors, resulting in a deliberate offset voltage
of about 1.5 mV referred to the input pins. Q3 generates a small
current to null this error, dependent on the voltage at the
OFLT pin. When Q1 and Q2 are perfectly matched, this voltage
is about 1.75 V. In practice, it can range from approximately
1 V to 2.5 V for an input-referred offset of ±1.5 mV.
48kΩ
125Ω
MAIN GAIN
STAGES
Q2
Q1
Q3
16μA AT
BALANCE
Q4
g
m
S
AVERAGE
ERROR
CURRENT
OFLT
TO LAST
DETECTOR
C
OFLT
33pF
COMM
VPOS
36kΩ
INPUT
STAGE
BIAS,
01084-025
2
3
5
1.2V
Figure 25. Offset Interface and Offset-Nulling Path
In normal operation using an ac-coupled input signal, the
OFLT pin should be left unconnected. The gm cell, which is
gated off when the chip is disabled, converts a residual offset
(sensed at a point near the end of the cascade of amplifiers) to
a current. This is integrated by the on-chip capacitor, CHP, plus
any added external capacitance, COFLT, to generate the voltage
that is applied back to the input stage in the polarity needed to
null the output offset. From a small-signal perspective, this
feedback alters the response of the amplifier, which exhibits a
zero in its ac transfer function, resulting in a closed-loop, high-
pass −3 dB corner at about 2 MHz. An external capacitor lowers
the high-pass corner to arbitrarily low frequencies; using 1 μF,
the 3 dB corner is at 60 Hz.
OUTPUT INTERFACE
The nine detectors generate differential currents, having an
average value that is dependent on the signal input level, plus a
fluctuation at twice the input frequency. These are summed at
nodes LGP and LGN in Figure 26. Further currents are added at
these nodes to position the intercept by slightly raising the
output for zero input and to provide temperature compensation.
0.2pF 3kΩ
BIAS 1kΩ
4kΩ4kΩ
R1
3kΩ
2μA/dB
0.4pF1.25kΩ1.25kΩ
1.25kΩ1.25kΩ
BFIN
0.4pF
60μA
VPOS
COMM
BIAS
LGP
LGN
FROM ALL
DETECTORS
01084-026
2
6
5
VOUT
4
Figure 26. Simplified Output Interface
AD8310
Rev. F | Page 13 of 24
For zero-signal conditions, all the detector output currents are
equal. For a finite input of either polarity, their difference is
converted by the output interface to a single-sided unipolar
current, nominally scaled 2 μA/dB (40 μA/decade), at the
output pin BFIN. An on-chip resistor of ~3 kΩ, R1, converts
this current to a voltage of 6 mV/dB. This is then amplified by a
factor of 4 in the output buffer, which can drive a current of up
to 25 mA in a grounded load resistor. The overall rise time of
the AD8310 is less than 15 ns. There is also a delay time of
about 6 ns when the log amp is driven by an RF burst, starting
at zero amplitude.
When driving capacitive loads, it is desirable to add a low value
of load resistor to speed up the return to the baseline; the buffer
is stable for loads of a least 100 pF. The output bandwidth can
be lowered by adding a grounded capacitor at BFIN. The time-
constant of the resulting single-pole filter is formed with the
3 kΩ internal load resistor (with a tolerance of 20%). Therefore,
to set the −3 dB frequency to 20 kHz, use a capacitor of 2.7 nF.
Using 2.7 μF, the filter corner is at 20 Hz.
AD8310
Rev. F | Page 14 of 24
USING THE AD8310
The AD8310 has very high gain and bandwidth. Consequently,
it is susceptible to all signals that appear at the input terminals
within a very broad frequency range. Without the benefit of
filtering, these are indistinguishable from the desired signal and
have the effect of raising the apparent noise floor (that is,
lowering the useful dynamic range). For example, while the
signal of interest has an IF of 50 MHz, any of the following can
easily be larger than the IF signal at the lower extremities of its
dynamic range: a few hundred mV of 60 Hz hum picked up due
to poor grounding techniques, spurious coupling from a digital
clock source on the same PC board, local radio stations, and so
on. Careful shielding and supply decoupling is, therefore,
essential. A ground plane should be used to provide a low
impedance connection to the common pin COMM, for the
decoupling capacitor(s) used at VPOS, and for the output
ground.
BASIC CONNECTIONS
Figure 27 shows the connections needed for most applications.
A supply voltage between 2.7 V and 5.5 V is applied to VPOS
and is decoupled using a 0.01 μF capacitor close to the pin.
Optionally, a small series resistor can be placed in the power
line to give additional filtering of power-supply noise. The
ENBL input, which has a threshold of approximately 1.3 V
(see Figure 15), should be tied to VPOS when this feature is not
needed.
V
S
(2.7V–5.5V)
C2
0.01μF
52.3Ω
NC = NO CONNECT
C1
0.01μF
C4
0.01μF
NC
NC
INHI ENBL BFIN VPOS
INLO COMM OFLT VOUT
AD8310
4.7Ω
OPTIONAL
V
OUT
(RSSI)
SIGNAL
INPUT
8765
1234
01084-027
Figure 27. Basic Connections
While the AD8310’s input can be driven differentially, the input
signal is, in general, single-ended. C1 is tied to ground, and the
input signal is coupled in through C2. Capacitor C1 and
Capacitor C2 should have the same value to minimize start-up
transients when the enable feature is used; otherwise, their
values need not be equal.
The 52.3 Ω resistor combines with the 1.1 kΩ input impedance
of the AD8310 to yield a simple broadband 50 Ω input match.
An input matching network can also be used (see the Input
Matching section).
The coupling time constant, 50 × CC/2, forms a high-pass corner
with a 3 dB attenuation at fHP = 1/(π × 50 × CC), where C1 =
C2 = CC. In high frequency applications, fHP should be as large
as possible to minimize the coupling of unwanted low frequency
signals. In low frequency applications, a simple RC network
forming a low-pass filter should be added at the input for similar
reasons. This should generally be placed at the generator side of
the coupling capacitors, thereby lowering the required capacitance
value for a given high-pass corner frequency.
For applications in which the ground plane might not be an equi-
potential (possibly due to noise in the ground plane), the low
input of an unbalanced source should generally be ac-coupled
through a separate connection of the low associated with the
source. Furthermore, it is good practice in such situations to
break the ground loop by inserting a small resistance to ground
in the low side of the input connector (see Figure 28).
V
S
(2.7V–5.5V)
C2
0.01μF
52.3Ω
NC = NO CONNECT
C1
0.01μF
C4
0.01μF
NC
NC
4.7Ω
OPTIONAL
INHI ENBL BFIN VPOS
INLO COMM OFLT VOUT
AD8310
V
OUT
(RSSI)
SIGNAL
INPUT
4.7Ω
GENERATO
R
COMMON BOARD-LEVEL
GROUND
01084-028
8765
1234
Figure 28. Connections for Isolation of Source Ground from Device Ground
Figure 29 shows the output vs. the input level for sine inputs at
10 MHz, 50 MHz, and 100 MHz. Figure 30 shows the logarith-
mic conformance under the same conditions.
INPUT LEVEL (dBV)
3.0
–120 –100
OUTPUT (V)
–80 –60 –40 –20 0
(+13dBm) 20
2.5
2.0
1.5
1.0
0.5
0
10MHz 50MHz
100MHz
INTERCEPT
(–87dBm)
01084-029
Figure 29. Output vs. Input Level at 10 MHz, 50 MHz, and 100 MHz
AD8310
Rev. F | Page 15 of 24
INPUT LEVEL (dBV)
–5
–120 20–100
(–87dBm) –80 –60 –40 –20 0
(+13dBm)
5
ERROR (dB)
4
–1
–2
–3
–4
2
0
3
110MHz
50MHz
100MHz
±3dB DYNAMIC RANGE
±1dB DYNAMIC RANGE
01084-030
Figure 30. Log Conformance Error vs. Input Level at 10 MHz,
50 MHz, and 100 MHz
TRANSFER FUNCTION IN TERMS OF SLOPE AND
INTERCEPT
The transfer function of the AD8310 is characterized in terms
of its slope and intercept. The logarithmic slope is defined as the
change in the RSSI output voltage for a 1 dB change at the input.
For the AD8310, slope is nominally 24 mV/dB. Therefore, a
10 dB change at the input results in a change at the output of
approximately 240 mV. The plot of log conformance shows the
range over which the device maintains its constant slope. The
dynamic range of the log amp is defined as the range over
which the slope remains within a certain error band, usually
±1 dB or ±3 dB. In Figure 30, for example, the ±1 dB dynamic
range is approximately 95 dB (from +4 dBV to −91 dBV).
The intercept is the point at which the extrapolated linear
response would intersect the horizontal axis (see Figure 29).
For the AD8310, the intercept is calibrated to be −108 dBV
(−95 dBm). Using the slope and intercept, the output voltage
can be calculated for any input level within the specified input
range using the following equation:
VOUT = VSLOPE × (PIN − PO) (3)
where:
VOUT is the demodulated and filtered RSSI output.
VSLOPE is the logarithmic slope expressed in V/dB.
PIN is the input signal expressed in dB relative to some reference
level (either dBm or dBV in this case).
PO is the logarithmic intercept expressed in dB relative to the
same reference level.
For example, for an input level of −33 dBV (−20 dBm), the
output voltage is
VOUT = 0.024 V/dB × (−33 dBV − (−108 dBV)) = 1.8 V (4)
dBV vs. dBm
The most widely used convention in RF systems is to specify
power in dBm, decibels above 1 mW in 50 Ω. Specification of
the log amp input level in terms of power is strictly a concession
to popular convention. As mentioned previously, log amps do
not respond to power (power absorbed at the input), but to the
input voltage. The use of dBV, defined as decibels with respect
to a 1 V rms sine wave, is more precise. However, this is still
ambiguous, because waveform is also involved in the response
of a log amp, which, for a complex input such as a CDMA
signal, does not follow the rms value exactly. Because most
users specify RF signals in terms of power (more specifically, in
dBm/50 Ω) both dBV and dBm are used to specify the perform-
ance of the AD8310, showing equivalent dBm levels for the
special case of a 50 Ω environment. Values in dBV are
converted to dBm re 50 Ω by adding 13 dB.
Table 4. Correction for Signals with Differing Crest Factors
Signal Type Correction Factor1 (dB)
Sine wave 0
Square wave or dc −3.01
Triangular wave 0.9
GSM channel (all time slots on) 0.55
CDMA channel (forward link, nine
channels on)
3.55
CDMA channel (reverse link) 0.5
PDC channel (all time slots on) 0.58
1 Add to the measured input level.
INPUT MATCHING
Where higher sensitivity is required, an input matching network
is useful. Using a transformer to achieve the impedance trans-
formation also eliminates the need for coupling capacitors,
lowers the offset voltage generated directly at the input, and
balances the drive amplitude to INLO and INHI.
The choice of turns ratio depends somewhat on the frequency.
At frequencies below 50 MHz, the reactance of the input
capacitance is much higher than the real part of the input
impedance. In this frequency range, a turns ratio of about 1:4.8
lowers the input impedance to 50 Ω, while raising the input
voltage lowers the effect of the short-circuit noise voltage by the
same factor. The intercept is also lowered by the turns ratio; for
a 50 Ω match, it is reduced by 20 log10 (4.8) or 13.6 dB. The total
noise is reduced by a somewhat smaller factor, because there is a
small contribution from the input noise current.
AD8310
Rev. F | Page 16 of 24
FREQUENCY (MHz)
14
4
–160 15080
DECIBELS
100 110 130
3
2
1
0
70 90 120 140
NARROW-BAND MATCHING
Transformer coupling is useful in broadband applications.
However, a magnetically coupled transformer might not be
convenient in some situations. Table 5 lists narrow-band
matching values.
GAIN
Table 5. Narrow-Band Matching Values
fC
(MHz)
ZIN
(Ω)
C1
(pF)
C2
(pF)
LM
(nH)
Voltage Gain
(dB)
10 45 160 150 3300 13.3
20 44 82 75 1600 13.4
50 46 30 27 680 13.4
100 50 15 13 270 13.4
150 57 10 8.2 220 13.2
200 57 7.5 6.8 150 12.8
250 50 6.2 5.6 100 12.3
500 54 3.9 3.3 39 10.9
10 103 100 91 5600 10.4
20 102 51 43 2700 10.4
50 99 22 18 1000 10.6
100 98 11 9.1 430 10.5
150 101 7.5 6.2 260 10.3
200 95 5.6 4.7 180 10.3
250 92 4.3 3.9 130 9.9
500 114 2.2 2.0 47 6.8
INPUT
9
8
7
6
5
13
12
11
10
01084-032
At high frequencies, it is often preferable to use a narrow-band
matching network, as shown in Figure 31. This has several advan-
tages. The same voltage gain is achieved, providing increased
sensitivity, but a measure of selectivity is also introduced. The
component count is low: two capacitors and an inexpensive chip
inductor. Additionally, by making these capacitors unequal, the
amplitudes at INP and INM can be equalized when driving from
a single-sided source; that is, the network also serves as a balun.
Figure 32 shows the response for a center frequency of 100 MHz;
note the very high attenuation at low frequencies. The high fre-
quency attenuation is due to the input capacitance of the log amp.
C1
C2
INLO
INHI
AD8310
SIGNAL
INPUT
L
M
8
01084-031
1
Figure 31. Reactive Matching Network
Figure 32. Response of 100 MHz Matching Network
GENERAL MATCHING PROCEDURE
For other center frequencies and source impedances, the
following steps can be used to calculate the basic matching
parameters.
Step 1: Tune Out CIN
At a center frequency, fC, the shunt impedance of the input
capacitance, CIN, can be made to disappear by resonating with
a temporary inductor, LIN, whose value is given by
IN
IN C
L2
1
ω
= (5)
where CIN = 1.4 pF. For example, at fC = 100 MHz, LIN = 1.8 μH.
Step 2: Calculate CO and LO
Now, having a purely resistive input impedance, calculate the
nominal coupling elements, CO and LO, using
()
C
MIN
O
MIN
C
Of
RR
L
RRf
Cπ
=
π
=2
;
2
1 (6)
For the AD8310, RIN is 1 kΩ. Therefore, if a match to 50 Ω is
needed, at fC = 100 MHz, CO must be 7.12 pF and LO must be
356 nH.
Step 3: Split CO into Two Parts
To provide the desired fully balanced form of the network
shown in Figure 31, two capacitors C1 and C2, each of
nominally twice CO, can be used. This requires a value of
14.24 pF in this example. Under these conditions, the voltage
amplitudes at INHI and INLO are similar. A somewhat better
balance in the two drives can be achieved when C1 is made
slightly larger than C2, which also allows a wider range of
choices in selecting from standard values.
For example, capacitors of C1 = 15 pF and C2 = 13 pF can be
used, making CO = 6.96 pF.
AD8310
Rev. F | Page 17 of 24
()
+V
S
(2.7V–5.5V)
Step 4: Calculate LM
The matching inductor required to provide both LIN and LO is
the parallel combination of these.
O
IN
O
IN
MLL
LL
L+
= (7)
With LIN = 1.8 μH and LO = 356 nH, the value of LM to complete
this example of a match of 50 Ω at 100 MHz is 297.2 nH.
The nearest standard value of 270 nH can be used with only a
slight loss of matching accuracy. The voltage gain at resonance
depends only on the ratio of impedances, as given by
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
=
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
=
S
IN
S
IN
R
R
R
R
GAIN log10log20 (8)
SLOPE AND INTERCEPT ADJUSTMENTS
Where system (that is, software) calibration is not available, the
adjustments shown in Figure 33 can be used, either singly or in
combination, to trim the absolute accuracy of the AD8310.
The log slope can be raised or lowered by VR1; the values
shown provide a calibration range of ±10% (22.6 mV/dB to
27.4 mV/dB), which includes full allowance for the variability in
the value of the internal resistances. The adjustment can be
made by alternately applying two fixed input levels, provided by
an accurate signal generator, spaced over the central portion of
the dynamic range, for example, −60 dBV and −20 dBV.
Alternatively, an AM-modulated signal at about the center of
the dynamic range can be used. For a modulation depth M,
expressed as a fraction, the decibel range between the peaks and
troughs over one cycle of the modulation period is given by
M
M
+
+
=Δ 1
1
log20dB 10 (9)
For example, using a generator output of −40 dBm with a 70%
modulation depth (M = 0.7), the decibel range is 15 dB, because
the signal varies from −47.5 dBm to −32.5 dBm.
The log intercept is adjustable by VR2 over a −3 dB range with
the component values shown. VR2 is adjusted while applying
an accurately known CW signal, preferably near the lower end
of the dynamic range, to minimize the effect of any residual
uncertainty in the slope. For example, to position the intercept
to −80 dBm, a test level of −65 dBm can be applied, and VR2
can be adjusted to produce a dc output of 15 dB above 0 at
24 mV/dB, which is 360 mV.
0.01μF4.7Ω
52.3Ω
NC = NO CONNECT
C1
0.01μFNC
INHI ENBL BFIN VPOS
INLO COMM OFLT VOUT
AD8310
V
OUT
(RSSI)
SIGNAL
INPUT
10kΩ
C2
0.01μF
25kΩ
VR1
10kΩ
R
S
VR2
100kΩ
FOR V
POS
= 3V, R
S
= 500kΩ
FOR V
POS
= 5V, R
S
= 850kΩ
24mV/dB ±10%
1234
8765
01084-033
Figure 33. Slope and Intercept Adjustments
INCREASING THE SLOPE TO A FIXED VALUE
It is also possible to increase the slope to a new fixed value and,
therefore, to increase the change in output for each decibel of
input change. A common example of this is the need to map the
output swing of the AD8310 into the input range of an analog-
to-digital converter (ADC) with a rail-to-rail input swing.
Alternatively, a situation might arise when only a part of the
total dynamic range is required (for example, just 20 dB) in an
application where the nominal input level is more tightly
constrained, and a higher sensitivity to a change in this level is
required. Of course, the maximum output is limited by either
the load resistance and the maximum output current rating of
25 mA or by the supply voltage (see the Specifications section).
The slope can easily be raised by adding a resistor from VOUT
to BFIN, as shown in Figure 34. This alters the gain of the
output buffer, by means of stable positive feedback, from its
normal value of 4 to an effective value that can be as high as 16,
corresponding to a slope of 100 mV/dB.
V
S
(2.7V–5.5V)
0.01μF4.7Ω
52.3Ω
NC = NO CONNECT
C1
0.01μFNC
INHI ENBL BFIN VPOS
INLO COMM OFLT VOUT
AD8310
V
OUT
100mV/dB
SIGNAL
INPUT
C2
0.01μF
8765
R
SLOPE
12.1kΩ
1234
01084-034
Figure 34. Raising the Slope to 100 mV/dB
The resistor, RSLOPE, is set according to the equation
Slope
RSLOPE mV/dB24
1−
k22.9 Ω
= (10)
AD8310
Rev. F | Page 18 of 24
OUTPUT FILTERING LOWERING THE HIGH-PASS CORNER FREQUENCY
OF THE OFFSET COMPENSATION LOOP
For applications in which maximum video bandwidth and,
consequently, fast rise time are desired, it is essential that the
BFIN pin be left unconnected and free of any stray capacitance.
In normal operation using an ac-coupled input signal, the
OFLT pin should be left unconnected. Input-referred dc offsets
of about 1.5 mV in the signal path are nulled via an internal
offset control loop. This loop has a high-pass −3 dB corner at
about 2 MHz. In low frequency ac-coupled applications, it is
necessary to lower this corner frequency to prevent input
signals from being misinterpreted as offsets. An external
capacitor on OFLT lowers the high-pass corner to arbitrarily
low frequencies (Figure 36). For example, by using a 1 μF
capacitor, the 3 dB corner is reduced to 60 Hz.
The nominal output video bandwidth of 25 MHz can be reduced
by connecting a ground-referenced capacitor (CFILT) to the BFIN
pin, as shown in Figure 35. This is generally done to reduce out-
put ripple (at twice the input frequency for a symmetric input
waveform such as sinusoidal signals).
+4
2μA/dB
3kΩ
V
OUT
BFIN
C
FILT
AD8310
C
FILT
= 1/(2π× 3kΩ× VIDEO BANDWIDTH) – 2.1pF
01084-035
()
C
OFLT
(SEE TEXT)
AD8310
OFLT
01084-036
()
Figure 35. Lowering the Postdemodulation Video Bandwidth
CFILT is selected using the following equation: Figure 36. Lowering the High-Pass Corner Frequency
of the Offset Control Loop
pF1.2
k32
1−
×Ω×π
=idthVideoBandw
CFILT (11) The corner frequency is set by the following equation:
The video bandwidth should typically be set at a frequency
equal to about one-tenth the minimum input frequency. This
ensures that the output ripple of the demodulated log output,
which is at twice the input frequency, is well filtered.
In many log amp applications, it might be necessary to lower
the corner frequency of the postdemodulation filtering to
achieve low output ripple while maintaining a rapid response
time to changes in signal level. An example of a 4-pole active
filter is shown in the AD8307 data sheet.
OFLT
CORNER C
f××π
=26252
1 (12)
where COFLT is the capacitor connected to OFLT.
AD8310
Rev. F | Page 19 of 24
APPLICATIONS INFORMATION
The AD8310 is highly versatile and easy to use. It needs only a
few external components, most of which can be immediately
accommodated using the simple connections shown in the
Using the AD8310 section.
A few examples of more specialized applications are provided
in the following sections. See the AD8307 data sheet for more
applications (note the slightly different pin configuration).
CABLE-DRIVING
For a supply voltage of 3 V or greater, the AD8310 can drive a
grounded 100 Ω load to 2.5 V. If reverse-termination is required
when driving a 50 Ω cable, it should be included in series with
the output, as shown in Figure 37. The slope at the load is then
12 mV/dB. In some cases, it might be permissible to operate the
cable without a termination at the far end, in which case the
slope is not lowered. Where a further increase in slope is
desirable, the scheme shown in Figure 34 can be used.
AD8310
VOUT 50Ω
50Ω
01084-037
Figure 37. Output Response of Cable-Driver Application
DC-COUPLED INPUT
It might occasionally be necessary to provide response to dc
inputs. Because the AD8310 is internally dc-coupled, there is no
reason why this cannot be done. However, its differential inputs
must be positioned at least 2 V above the COM potential for
proper biasing of the first stage. Usually, the source is a single-
sided ground-referenced signal, so level-shifting and a single-
ended-to-differential conversion must be provided to correctly
drive the AD8310’s inputs.
Figure 38 shows how a level-shift to midsupply (2.5 V in this
example) and a single-ended-to-differential conversion can be
accomplished using the AD8138 differential amplifier. The four
499 Ω resistors set up a gain of unity. An output common-mode
(or bias) voltage of 2.5 is achieved by applying 2.5 V from a supply-
referenced resistive divider to the VOCM pin of the AD8138. The
differential outputs of the AD8138 directly drive the 1.1 kΩ
input impedance of the AD8310.
5V
0.01 F
μ
SIGNAL
INPUT AD8138
0.1μF
5V
499Ω
499Ω
499Ω
499Ω
10kΩ0.1μF
5V
10kΩ
NC
INHI ENBL BFIN VPOS
INLO COMM OFLT VOUT
AD8310
1234
8765
V
OUT
5V
3.01kΩ1.87kΩ
50Ω
2.5V
NC = NO CONNECT
01084-038
Figure 38. DC-Coupled Log Amp
In this application the offset voltage of the AD8138 must be
trimmed. The internal offset compensation circuitry of the
AD8310 is disabled by applying a nominal voltage of ~1.9 V to
the OFLT pin, so the trim on the AD8138 is effectively trimming
the offsets of both devices. The trim is done by grounding the
circuit’s input and slightly varying the gain resistors on the
inverting input of the AD8138 (a 50 Ω potentiometer is used in
this example) until the voltage on the AD8310’s output reaches
a minimum.
After trimming, the lower end of the dynamic range is limited
by the broadband noise at the output of the AD8138, which is
approximately 425 μV p-p. A differential low-pass filter can be
added between the AD8138 and the AD8310 when the very fast
pulse response of the circuit is not required.
INPUT LEVEL (mV)
0.1
RSSI OUTPUT (V)
1
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
10 100 1000
2.3
2.5
2.7
01084-039
Figure 39. Transfer Function of DC-Coupled Log Amp Application
AD8310
Rev. F | Page 20 of 24
EVALUATION BOARD
An evaluation board is available that has been carefully laid out
and tested to demonstrate the specified high speed performance
of the AD8310. Figure 40 shows the schematic of the evaluation
board, which follows the basic connections schematic shown in
Figure 27.
Connectors INHI, INLO, and VOUT are of the SMA type.
Supply and ground are connected to the TP1 and TP2 vector
pins. The layout and silkscreen for the component side of the
board are shown in Figure 41 and Figure 42. Switches and
component settings for different setups are described in Table 6.
For ordering information, see the Ordering Guide.
01084-041
C2
0.01μF
INHI ENBL BFIN VPOS
INLO COMM OFLT VOUT
AD8310
1234
8765
C4
0.01μF
C1
0.01μF
R3
52.3Ω
SW1
A
B
R4
0
Ω
R1
0
Ω
INHI
INLO
TP2
C7
OPEN W1 W2
R6
0Ω
C6
OPEN R7
OPEN
V
OUT
C5
OPEN
C3
OPEN
R5
0Ω
TP1
VPOS
R2
0Ω
01084-040
Figure 40. Evaluation Board Schematic
Figure 41. Layout of the Component Side of the Evaluation Board
01084-042
Figure 42. Component Side Silkscreen of the Evaluation Board
AD8310
Rev. F | Page 21 of 24
Table 6. Evaluation Board Setup Options
Component Function Default Condition
TP1, TP2 Supply and Ground Vector Pins. Not applicable
SW1 Device Enable. When in Position A, the ENBL pin is connected to +VS, and the AD8310 is in normal
operating mode. When in Position B, the ENBL pin is connected to ground, putting the device into
sleep mode.
SW1 = A
R1/R4 SMA Connector Grounds. Connects common of INHI and INLO SMA connectors to ground. They
can be used to isolate the generator ground from the evaluation board ground. See Figure 28.
R1 = R4 = 0 Ω
C1, C2, R3 Input Interface. R3 (52.3 Ω) combines with the AD8310’s 1 kΩ input impedance to give an overall
broadband input impedance of 50 Ω. C1, C2, and the AD8310’s input impedance combine to set a
high-pass input corner of 32 kHz. Alternatively, R3, C1, and C2 can be replaced by an inductor and
matching capacitors to form an input matching network. See the Input Matching section for details.
R3 = 52.3 Ω,
C1 = C2 = 0.01 μF
C3 RSSI (Video) Bandwidth Adjust. The addition of C3 (farads) lowers the RSSI bandwidth of the
AD8310’s output according to the following equation:
CFILT = 1/(2π × 3 kΩ Video Bandwidth) − 2.1 pF
C3 = open
C4, C5, R5 Supply Decoupling. The normal supply decoupling of 0.01 μF (C4) can be augmented by a larger
capacitor in C5. An inductor or small resistor can be placed in R5 for additional decoupling.
C4 = 0.01 μF,
C5 = open, R5 = 0 Ω
R6 Output Source Impedance. In cable-driving applications, a resistor (typically 50 Ω or 75 Ω) can be
placed in R6 to give the circuit a back-terminated output impedance.
R6 = 0 Ω
W1, W2, C6, R7 Output Loading. Resistors and capacitors can be placed in C6 and R7 to load-test VOUT. Jumper W1
and Jumper W2 are used to connect or disconnect the loads.
C6 = R7 = open,
W1 = W2 = installed
C7 Offset Compensation Loop. A capacitor in C7 reduces the corner frequency of the offset control
loop in low frequency applications.
C7 = open
AD8310
Rev. F | Page 22 of 24
DIE INFORMATION
3
2
18
7
6
5B
5A
4
X
Y
BOND PAD STATIST ICS
ALL ME AS UREM E NTS I N M ICRONS
MI NIMUM PASSIVAT ION OPE NING : 92 × 92, MINIMUM PAD PI TCH: 150
DIE SIZE CALCULATIO N
ALL ME AS UREM E NTS I N M ICRONS
DIE X (W IDT H OF DIE I N X DIRECT ION) = 745
DIE Y (W IDT H OF DIE I N Y DIRECTION) = 13 90
DIE THICKNESS = 305
COORDIN ATES OF BO ND PAD CENTERS:
(1) – 233, +540 ( 2) –250, +310 (3) –250, –273
(4) – 250, –519 (5B) +250, –366 (5A) +2 50, –516
(6) +250, –218 ( 7) + 249, +310 (8) +233, +540
01084-044
Figure 43. Die Outline Dimensions
Table 7. Die Pad Function Descriptions
Pin No. Mnemonic Description
1 INLO One of Two Balanced Inputs. Biased roughly to VPOS/2.
2 COMM Common Pin. Usually grounded.
3 OFLT Offset Filter Access. Nominally at about 1.75 V.
4 VOUT Low Impedance Output Voltage. Carries a 25 mA maximum load.
5A, 5B VPOS Positive Supply. 2.7 V to 5.5 V at 8 mA quiescent current.
6 BFIN Buffer Input. Used to lower postdetection bandwidth.
7 ENBL CMOS Compatible Chip Enable. Active when high.
8 INHI Second of Two Balanced Inputs. Biased roughly to VPOS/2.
AD8310
Rev. F | Page 23 of 24
COMPLIANT TO JEDEC STANDARDS MO-187-AA
100709-B
6°
0°
0.80
0.55
0.40
OUTLINE DIMENSIONS
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.95
0.85
0.75
15° MAX
0.15
0.05
Figure 44. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1Temperature Range Package Description Package Option Branding
AD8310ARM −40°C to +85°C 8-Lead MSOP, Tube RM-8 J6A
AD8310ARM-REEL7 −40°C to +85°C 8-Lead MSOP, 7” Tape and Reel RM-8 J6A
AD8310ARMZ −40°C to +85°C 8-Lead MSOP, Tube RM-8 J6A
AD8310ARMZ-REEL7 −40°C to +85°C 8-Lead MSOP, 7” Tape and Reel RM-8 J6A
AD8310ACHIPS −40°C to +85°C Die
AD8310-EVAL Evaluation Board
1 Z = RoHS Compliant Part.
AD8310
Rev. F | Page 24 of 24
NOTES
© 2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01084–0–6/10(F)
