Supertex inc.
Supertex inc.
www.supertex.com
Doc.# DSFP-HV7802
A062813
HV7802
Features
►Supply voltage 8V to 450V
►Congurable as a current or voltage output device
►Maximum sense amplier offset of 15mV
►Max VSENSE of 500mV
►Fast rise and fall time, from 700ns to 2.0µs
►Maximum quiescent current of 50µA
Applications
►SMPS current monitor
►Battery current monitor
►Motor control
General Description
The HV7802 high side current monitor IC contains a
transconductance amplier which translates a high side
current measurement voltage into an output current with
resistor programmable transconductance gain. An optional
second resistor transforms this output current into an output
voltage with an overall voltage gain set by the ratio of the two
resistors.
The measurement voltage typically originates at a current
sense resistor, which is located in a “high side” circuit, for
example a circuit not directly associated with ground.
This monitor IC features a very wide input voltage range,
congurable gain, small size, low component count, low power
consumption, ease of use, and low cost. Ofine, battery, and
portable applications can be served equally well due to the
wide input voltage range and the low quiescent current.
Typical Application Circuit
High Side Current Monitor
8V to 450V
Congurable Output
I
SENSE
V
SENSE
VOUT
RA
RB
IOUT
HV7802
IN LOAD
GND OUT
RP (optional)
RA
RSENSE
R
8V to 450V Input
IOUT = VSENSE/RA
VOUT = RB •IOUT
GV = RB/RA
V
2
Supertex inc.
www.supertex.com
Doc.# DSFP-HV7802
A062813
HV7802
Absolute Maximum Ratings
LOAD
IN
GNDOUT
1
8 6
23
RA
NC
7
NC
5
NC
4
Pin Conguration
Sym Parameter Min Typ Max Units Conditions
Supply
VIN Supply voltage 8.0 - 450 V * ---
IQQuiescent supply current - - 50 µA - VIN = 8V to 450V, VSENSE = 0mV
Input and Output
IOUT Ouput current - - 200 µA - ---
VOUT
Output voltage,
RA = RB = 5.000kΩ
0 - 15
mV -
VSENSE = 0mV
79 -121 VSENSE = 100mV
177 -223 VSENSE = 200mV
470 -530 VSENSE = 500mV
Dynamic Characteristics
tRISE Output rise time, 10% to 90% -0.7 -µs -VSENSE step 5.0mV to 500mV
- - 2.0 VSENSE step 0mV to 500mV
tFALL Output fall time, 90% to 10% -0.7 2.0 µs - VSENSE step 500mV to 0mV
Electrical Characteristics (TA = 25°C unless otherwise specied, VSENSE = VIN - VLOAD, VIN = 8V to 450V)
* Values apply over the full temperature range.
Parameter Value
VIN, VLOAD -0.5V to +460V
VOUT -0.5V to +10V
VSENSE -0.5V to +5.0V
ILOAD ±10mA
Operating ambient temperature -40°C to +85°C
Operating junction temperature -40°C to +125°C
Storage temperature -65°C to +150°C
Absolute maximum ratings are those values beyond which damage to
the device may occur. Functional operation under these conditions is not
implied. Continuous operation of the device at the absolute rating level
may affect device reliability. All voltages are referenced to device ground.
Product Marking
L = Lot Number
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
7802
LLLL
Top Marking
Bottom Marking
YYWW
8-Lead MSOP
8-Lead MSOP
(top view)
Package may or may not include the following marks: Si or
Notes:
1. Referenced to GND
2. VSENSE = VIN - VLOAD
Ordering Information
Part Number Package Option Packing
HV7802MG-G 8-Lead MSOP 2500/Reel
Typical Thermal Resistance
Package θja
8-Lead MSOP 216OC/W
-G denotes a lead (Pb)-free / RoHS compliant package
Note:
Thermal testboard per JEDEC JESD51-7
3
Supertex inc.
www.supertex.com
Doc.# DSFP-HV7802
A062813
HV7802
Block Diagram
Application Information
General
The HV7802 high side current monitor IC features accurate
current sensing, small size, low component count, low power
consumption, exceptional input voltage range, ease of use
and low cost.
Typical use is measurement of line and load current for
purpose of overcurrent protection, metering and current
regulation.
High side current sensing, as opposed to ground referenced
or low side current sensing, is desirable or required when:
►The current to be measured does not ow in a circuit
associated with ground.
►The measurement at ground level can lead to ambiguity
due to changes in the grounding arrangement during
eld use.
►The introduction of a sense resistor in the system ground
is undesirable due to issues with safety, EMI, or signal
degradation caused by common impedance coupling.
Principle of Operation
The operational amplier forces the voltage across RA to
track VSENSE, therefore, VRA = VSENSE. Transconductance gain
is equal to (1/RA).
IRA ows from the OUT pin to low side circuitry. Current to
voltage conversion can be accomplished by a resistor, RB,
as shown in the block diagram, with a transimpedance gain
equal to RB.
Typically we would like to exploit the full current capability of
the transimpedance amplier. A RA of 5kΩ will provide this
current, assuming a full scale sense voltage of 500mV and a
full scale sense current of 100µA.
In a voltage output application, the output resistor RB is
determined by the desired overall voltage gain of (RB / RA).
For example, a RB of 10kΩ results in a voltage gain of two.
OUT Pin Loading Effects
Note that the output is not buffered having an output
impedance equal to RB. Loading of the output causes voltage
gain to drop and rise and fall time to increase.
For example, assume a gain of one, using RA = RB = 5kΩ. In
this case the load resistance should exceed 5MΩ in order to
limit the gain drop to 1 part in 1000.
Assuming an output resistance of 5kΩ, a capacitive load of
20pF results in a load pole with a time constant of 100ns,
not enough to materially affect the output rise and fall time
(about 700ns).
Sense Resistor Considerations
Limit the sense resistor voltage to 500mV during normal
operating conditions. Limit the power dissipation in the sense
resistor to suit the application; a high sense voltage benets
accuracy, but may result in high power dissipation as well.
Consider the use of Kelvin connections for applications where
considerable voltage drops may occur in the PCB traces.
A layout pattern, which minimizes voltage drops across the
sense lines is shown below.
RP
(Optional,
see text)
ISENSE
VSENSE
RSENSE
Bias
Circuits
HV7802
IN LOAD
GND OUT VOUT
RA
RB
RA
+ V
SENSE
-
IN LOAD RSENSE
4
Supertex inc.
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Doc.# DSFP-HV7802
A062813
HV7802
Pin Description
Pin # Pin Name Description
1 IN Sense amplier input and supply.
2 RA Provides gain setting of the transconductance amplier. Connect gain setting resistor
(RA) between Pin 1 and Pin 2.
3 LOAD
Sense amplier input. High impedance input with Zener diode protection. Add an
external protection resistor in series with LOAD if VSENSE exceeds the range of -600mV
to +5.0V.
4 NC No Connect. This pin must be left oating for proper operation
5 NC No Connect. This pin must be left oating for proper operation.
6 OUT
Output of the transconductance amplier. Output current to output voltage conversion
can be accomplished through addition of an external resistor (RB) at this pin. Overall
voltage gain is determined by the ratio of RB to RA.
7NC No Connect. This pin must be left oating for proper operation.
8GND Supply return.
Choose a low inductance type sense resistor if preservation
of bandwidth is important. Kelvin connections help by
minimizing the inductive voltage drops as well. The inductive
voltage drop may be substantial when operating at high
frequency. A trace or component inductance of just 10nH
contributes an impedance of 6.2mΩ at 100kHz, which
constitutes a 6% error when using a 100mΩ sense resistor.
Transient Protection
Add a protection resistor (RP) in series with the LOAD
pin if VSENSE can exceed 5.0V in positive sense or 600mV
in negative sense, whether in steady state or in transient
conditions.
A large VSENSE may occur during system startup or shutdown
when charging and discharging large capacitors. VSENSE may
be large due to fault conditions, such as short circuit or a
broken or missing sense resistor.
An internal 5.0V Zener diode with a current rating of 10mA
protects the sense amplier inputs. The block diagram
shows the orientation of this diode. The Zener diode provides
clamping at 5.0V for a positive VSENSE and at 600mV for a
negative VSENSE.
Limit the Zener current to 10mA under worst case conditions.
A 100kΩ resistor limits the maximum Zener diode current to
4.5mA when VSENSE is 450V, whether positive or negative.
Note that the protection resistor may affect bandwidth.
The resistor forms a RC network with the trace and pin
capacitance at the LOAD pin. For example, capacitance of
5.0pF results in a time constant of 500ns.
The protection resistor may cause an offset voltage due to
bias current at the LOAD input. A 100kΩ protection resistor
could cause an offset of 100µV, or 0.2% of full scale, under
worst case bias current. Note that bias current is nominally
zero since LOAD is a high impedance CMOS input, resulting
in zero bias current induced offset voltage.
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
5
HV7802
(The package drawing(s) in this data sheet may not reect the most current specications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV7802
A062813
8-Lead MSOP Package Outline (MG)
3.00x3.00mm body, 1.10mm height (max), 0.65mm pitch
View B
View A-A
Seating
Plane
Gauge
Plane
L
L1
L2
View B
θ1
θ
1
8
EE1
D
eb
AA2
A1
Seating
Plane
A
A
Top View
Side View
Note 1
(Index Area
D/2 x E1/2)
Symbol A A1 A2 bD E E1 e L L1 L2 θ θ1
Dimension
(mm)
MIN 0.75* 0.00 0.75 0.22 2.80* 4.65* 2.80*
0.65
BSC
0.40
0.95
REF
0.25
BSC
0O5O
NOM - - 0.85 -3.00 4.90 3.00 0.60 - -
MAX 1.10 0.15 0.95 0.38 3.20* 5.15* 3.20* 0.80 8O15O
JEDEC Registration MO-187, Variation AA, Issue E, Dec. 2004.
* This dimension is not specied in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-8MSOPMG, Version H041309.
Note:
1. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier; an embedded metal marker; or
a printed indicator.