EMP116MEAW Series
1Mx16 Pseudo Static RAM
Preliminary
Rev 0.0
Document Title
1M x 16 bit Pseudo SRAM ( EMP116MEAW Series ) Specification
Revision History
Revision No. History Draft Date Remark
0.0 Initial Draft Oct. 24 , 2005 Preliminary
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-717
Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to
your questions about device. If you have any questions, please contact the EMLSI office.
EMP116MEAW Series
1Mx16 Pseudo Static RAM
Preliminary
Rev 0.0
1Mb x16 Pseudo Static RAM Specification
GENERAL DESCRIPTION
The EMP116MEAW series is 16,777,216 bits of Pseudo SRAM which uses DRAM type memory cells, but
this device has refresh-free operation and extreme low power consumption technology. Furthermore the
interface is compatible to a low power Asynchronous type SRAM. The EMP116MEAW is organized as
1,048,576 Words x 16 bit.
FEATURES
- Organization :1M x16
- Power Supply Voltage : 2.7 ~ 3.3V
- Separated I/O power(VccQ) & Core power(Vcc)
- Three state outputs
- Byte read/write control by UB# / LB#
- Support Page Read/Write operation with 16 words
- Support PASR, RMS, DPD and Auto-TCSR for power saving
PRODUCT FAMILY
Part Number Operating Temp. Power Supply Speed
(t
RC
)
Power Dissipation
Standby
(I
SB1
, Max.)
Operating
(I
CC2
, Max.)
EMP116MEAW-70E
-25
o
C to 85
o
C
2.7V to 3.3V 70ns 100uA 25mA
FUNCTION BLOCK DIAGRAM
COLUMN SELECT
I/O CIRCUIT
Memory Array
1M X 16
ROW SELECT
Self-Refresh
CONTROL
CONTROL
LOGIC
ADDRESS
DECODER
Din/Dout BUFFER
DQ0~
DQ15
A0~A19
ZZ#
CS#
UB#
LB#
WE#
OE#
EMP116MEAW Series
1Mx16 Pseudo Static RAM
Preliminary
Rev 0.0
GENERAL WAFER SPECIFICATIONS
- Process Technology : 0.125um CMOS Deep trench process
- 3 Metal layers including local inter-connection
- Wafer thickness : 725 +/- 25um
- Wafer Diameter : 8-inch
1Mb x16 Pseudo Static RAM
PAD DESCRIPTION
Name Function Name Function
CS# Chip select inputs LB# Lower byte (DQ
0~7
)
OE# Output enable input UB# Upper byte (DQ
8~15
)
WE# Write enable input VCC Power supply
ZZ# Low Power Control VCCQ I/O Power supply
DQ
0-15
Data In-out VSS(Q) Ground
A
0-19
Address inputs NC No connection
EMP116MEAW Series
1Mx16 Pseudo Static RAM
Preliminary
Rev 0.0
ABSOLUTE MAXIMUM RATINGS 1)
1.
Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. Undershoot at power-off : -1.0V in case of pulse width < 20ns
Parameter Symbol Ratings Unit
Voltage on Any Pin Relative to Vss V
IN
, V
OUT
-0.2 to V
CCQ
+0.3V V
Voltage on Vcc supply relative to Vss V
CC
, V
CCQ
-0.2
2)
to 3.6V V
Power Dissipation P
D
1.0 W
Storage Temperature T
STG
-65 to 150
o
C
Operating Temperature T
A
-25 to 85
o
C
FUNCTIONAL DESCRIPTION
Note: X means don’t care. (Must be low or high state)
CS# ZZ# OE# WE# LB# UB# DQ
0~7
DQ
8~15
Mode Power
H H X X X X High-Z High-Z Deselected Stand by
H L X X X X High-Z High-Z Deselected Low Power Mode
X H X X H H High-Z High-Z Deselected Stand by
L H H H L X High-Z High-Z Output Disabled Active
L H H H X L High-Z High-Z Output Disabled Active
L H L H L H Data Out High-Z Lower Byte Read Active
L H L H H L High-Z Data Out Upper Byte Read Active
L H L H L L Data Out Data Out Word Read Active
L H X L L H Data In High-Z Lower Byte Write Active
L H X L H L High-Z Data In Upper Byte Write Active
L H X L L L Data In Data In Word Write Active
EMP116MEAW Series
1Mx16 Pseudo Static RAM
Preliminary
Rev 0.0
DC AND OPERATING CHARACTERISTICS
1. Maximum Icc specifications are tested with V
CC
= V
CCmax.
Parameter Symbol Test Conditions Min Typ Max Unit
Input leakage current I
LI
V
IN
=V
SS
to V
CCQ
, V
CC=
V
CCmax
-1 - 1 uA
Output leakage current I
LO
CS#=V
IH
, ZZ#=V
IH
, OE#=V
IH
or WE#=V
IL
,
V
IO
=V
SS
to V
CCQ
, V
CC=
V
CCmax
-1 - 1 uA
Average operating current
I
CC1
Cycle time=1µs, 100% duty, I
IO
=0mA,
CS#<0.2V, ZZ#=V
IH
, V
IN
<0.2V or V
IN
>V
CCQ
-0.2V
- - 3 mA
I
CC2
Cycle time = Min, I
IO
=0mA, 100% duty,
CS#=V
IL
, ZZ#=V
IH
, V
IN
=V
IL
or V
IH
- - 25 mA
Output low voltage V
OL
I
OL
= 0.5mA, V
CC=
V
CCmin
- -
0.2*V
CCQ
V
Output high voltage V
OH
I
OH
= -0.5mA, V
CC=
V
CCmin
0.8*V
CCQ
- - V
Standby Current (CMOS) I
SB
CS#,ZZ#>V
CCQ
-0.2V, Other inputs = 0 ~ V
CCQ
(Typ. condition : V
CC
=3.0V @ 25
o
C)
(Max. condition : V
CC
=3.3V @ 85
o
C)
Standard
Reduced
Low Power
150
120
100
uA
RECOMMENDED DC OPERATING CONDITIONS 1)
1. T
A
= -25 to 85
o
C, otherwise specified
2. Overshoot: V
CC
+1.0 V in case of pulse width < 20ns
3. Undershoot: -1.0 V in case of pulse width < 20ns
4. Overshoot and undershoot are sampled, not 100% tested
.
Parameter Symbol Min Typ Max Unit
Supply voltage
V
CC
2.7 3.0 3.3 V
V
CCQ
2.7 3.0 3.3 V
Ground V
SS
, V
SSQ
0 0 0 V
Input high voltage V
IH
0.8 * V
CCQ
- V
CCQ
+ 0.2
2)
V
Input low voltage V
IL
-0.2
3)
- 0.2 * V
CCQ
V
CAPACITANCE1) (f =1MHz, TA=25oC)
1. Capacitance is sampled, not 100% tested
Item Symbol Test Condition Min Max Unit
Input capacitance C
IN
V
IN
=0V - 8 pF
Input/Ouput capacitance C
IO
V
IO
=0V - 8 pF
EMP116MEAW Series
1Mx16 Pseudo Static RAM
Preliminary
Rev 0.0
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
Input Pulse Level : 0.2V to V
CCQ
-0.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : V
CCQ
/2
Output Load (See right) : CL
1)
= 30pF
1. Including scope and Jig capacitance
CL
1)
AC CHARACTERISTICS (Vcc = 2.7 to 3.3V, Gnd = 0V, TA = -25C to +85oC)
Dout
Parameter List Symbol
Speed
Unit
Min Max
Read
Read Cycle Time t
RC
70 1k ns
Address access time t
AA
- 70 ns
Chip enable to data output t
CO
- 70 ns
Output enable to valid output t
OE
- 25 ns
UB#, LB# enable to data output t
BA
- 70 ns
Chip enable to low-Z output t
LZ
10 - ns
UB#, LB# enable to low-Z output t
BLZ
10 - ns
Output enable to low-Z output t
OLZ
5 - ns
Chip disable to high-Z output t
HZ
0 15 ns
UB#, LB# disable to high-Z output t
BHZ
0 15 ns
Output disable to high-Z output t
OHZ
0 15 ns
Output hold from Address change t
OH
5 - ns
Write
Write Cycle Time t
WC
70 1k ns
Chip enable to end of write t
CW
60 - ns
Address setup time t
AS
0 - ns
Address valid to end of write t
AW
60 - ns
UB#, LB# valid to end of write t
BW
60 - ns
Write pulse width t
WP
50 - ns
Write recovery time t
WR
0 - ns
Write to output high-Z t
WHZ
0 15 ns
Data to write time overlap t
DW
20 - ns
Data hold from write time t
DH
0 - ns
End write to output low-Z t
OW
5 - ns
Page
Maximum cycle time t
MRC
- 1k ns
Page mode cycle time t
PC
25 - ns
Page mode address access time t
PAA
- 25 ns
EMP116MEAW Series
1Mx16 Pseudo Static RAM
Preliminary
Rev 0.0
TIMING DIAGRAMS
Address
CS#
LB#, UB#
OE#
Data Out
t
CO
t
OH
t
BA
t
OE
t
BHZ
t
OHZ
Data Vaild
t
OLZ
t
BLZ
t
LZ
t
AA
t
HZ
READ CYCLE (2) (ZZ#=WE#=V
IH
)
NOTES (READ CYCLE)
1. t
HZ
, t
BHZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels.
2. Do not Access device with cycle timing shorter than t
RC
for continuous periods > 1us.
READ CYCLE (1) (Address controlled, CS#=OE#=V
IL
, ZZ#=WE#=V
IH
, UB# or/and LB#=V
IL
)
t
RC
Address
t
AA
Data Out
Data Valid
t
OH
Previous Data Valid
High-Z
t
RC
EMP116MEAW Series
1Mx16 Pseudo Static RAM
Preliminary
Rev 0.0
PAGE READ CYCLE (ZZ#=WE#=V
IH
, 16 Words access)
t
MRC
Address
t
RC
High-Z
Data Valid Data Valid Data Valid Data Valid Data Valid
(A19~A4)
Address
(A3~A0)
t
PC
t
PC
t
PC
t
PC
CS#
LB#,UB#
OE#
Data
Out
t
AA
t
CO
t
BA
t
OE
t
OLZ
t
BLZ
t
LZ
t
PAA
t
PAA
t
PAA
t
PAA
t
OHZ
t
BHZ
t
HZ
t
OH
NOTES (READ CYCLE)
1. t
HZ
, t
BHZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels.
2. Do not Access device with cycle timing shorter than t
RC
for continuous periods > 1us.
EMP116MEAW Series
1Mx16 Pseudo Static RAM
Preliminary
Rev 0.0
t
WR
t
WC
Address
CS#
LB#,UB#
WE#
Data In
t
CW
t
AW
t
BW
t
WP
t
AS
t
DW
t
DH
WRITE CYCLE (1) (WE# controlled, ZZ#=V
IH
)
Data Valid
High-Z
Data Undefined
Data Out
t
OW
t
WHZ
t
WR
t
WC
Address
CS#
LB#,UB#
WE#
Data In
t
CW
t
AW
t
BW
t
WP
t
AS
t
DW
t
DH
WRITE CYCLE (2) (CS# controlled, ZZ#=V
IH
)
Data Valid
High-ZData Out
t
WR
t
WC
Address
CS#
LB#,UB#
WE#
Data In
t
CW
t
AW
t
BW
t
WP
t
AS
t
DW
t
DH
WRITE CYCLE (3) (UB#/LB# controlled, ZZ#=V
IH
)
Data Valid
High-ZData Out
EMP116MEAW Series
1Mx16 Pseudo Static RAM
Preliminary
Rev 0.0
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(t
WP
) of low CS#, low WE# and low UB# or LB#. A write begins at the last
transition among low CS# and low WE# with asserting UB# or LB# low for single byte operation or simultaneously
asserting UB# and LB# low for word operation. A write ends at the earliest transition among high CS# and high WE#.
The t
WP
is measured from the beginning of write to the end of write.
2. t
CW
is measured from CS# going low to end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CS# or WE# going high.
5. Do not Access device with cycle timing shorter than t
WC
for continuous periods > 1us.
PAGE WRITE CYCLE (ZZ#=V
IH
, 16 Words access)
t
MRC
Address
t
WC
High-Z
Data Valid Data Valid Data Valid Data Valid Data Valid
(A19~A4)
Address
(A3~A0)
t
PC
t
PC
t
PC
t
PC
CS#
LB#,UB#
WE#
Data In
Data Out
t
OW
t
WHZ
t
AS
t
DW
t
DH
t
DW
t
DH
t
DW
t
DH
t
DW
t
DH
t
DW
t
DH
EMP116MEAW Series
1Mx16 Pseudo Static RAM
Preliminary
Rev 0.0
LOW POWER MODES
Mode Register Set
DPD Enable / Disable Array Mode Selection
Array Half Selection (Top/Down) Array Refresh Area Selection
A19 ~ A5 A4 A3 A2 A1 A0
All 0
(Reserved for
future)
DPD
Enable/Disable
Array Mode
Selection
Array Half
Selection Array Refresh Area Selection
A4 Type A3 Type
0 Deep Power Down Enable 0 Partial Array Refresh Mode (Default)
1 DPD Disable (Default) 1 Reduced Memory Size Mode
A2 Type A1 A0 Type
0 Bottom (Default) 0 0 Full Array (Default)
1 Top 0 1 RFU (Reserved for future)
1 0 1/2 Array
1 1 1/4 Array
NOTES
1. The Partial Array Refresh and Deep Power Down mode is issued only during ZZ# low state.
2. The RMS (Reduced Memory Size) mode is enabled after ZZ# goes high and remains enabled after ZZ# goes high. To
change to a different mode, the mode register will have to be re-written.
3. If register is written to enable the Deep Power Down, the part will go into Deep Power Down during the following time that
ZZ# is driven low and there is no MRS update. When ZZ# is driven high, all of the register settings will return to dafault state
for the part (i.e. full array refresh, Deep Power Down disabled.)
t
WR
t
WC
Address
CS#
LB#,UB#
WE#
ZZ#
t
CW
t
AW
t
BW
t
WP
t
AS
Mode Register Set UpdateTiming Diagram
NOTES
The register update takes place after over the
t
ZZWE maximum time of 1us. Once the register is updated the next time ZZ#
goes low, without any updates to the register starting within the
t
ZZWE maximum time of 1us, the part will refresh the array
selected. The data bus is a don’t care when ZZ# is low during the register updates.
t
ZZWE
Register write start Register write complete Register update complete
EMP116MEAW Series
1Mx16 Pseudo Static RAM
Preliminary
Rev 0.0
UB#,LB#
~
~
~
~
LOW POWER MODES
Deep Power Down Mode Entry & Exit
WE#
ZZ#
t
ZZWE
t
R
Deep Power Down Exit
Normal
operation
~
~
t
ZZmin
Parameter Description Min Max Unit
t
ZZWE
ZZ# low to Write Enable Low 0 1
us
t
R
(Deep Power Down mode only) Operation Recovery Time 200 -
us
t
ZZmin
Low Power Mode Time 10 -
us
~
~
~
~
CS#
~
~
t
WC
A4
t
CW
t
AS
t
WR
t
AW
t
BW
t
WP
~
~
~
~
Register Write Start
EMP116MEAW Series
1Mx16 Pseudo Static RAM
Preliminary
Rev 0.0
Address Information for PASR mode and RMS mode
Partial Array Self Refresh Mode (A3=0, A4=1)
Reduced Memory Size Mode (A3=1, A4=1)
Low Power Mode Characteristics
A2 A1 A0 Refresh Section Address Size Density
0 1 1 1/4 000000h~07FFFFh 512Kb x 16 8Mb
0 1 0 1/2 000000h~0FFFFFh 1Mb x 16 16Mb
X 0 0 Full 000000h~1FFFFFh 2Mb x 16 32Mb
1 1 1 1/4 180000h~1FFFFFh 512Kb x 16 8Mb
1 1 0 1/2 100000h~1FFFFFh 1Mb x 16 16Mb
A2 A1 A0 Refresh Section Address Size Density
0 1 1 1/4 000000h~07FFFFh 512Kb x 16 8Mb
0 1 0 1/2 000000h~0FFFFFh 1Mb x 16 16Mb
1 1 1 1/4 180000h~1FFFFFh 512Kb x 16 8Mb
1 1 0 1/2 100000h~1FFFFFh 1Mb x 16 16Mb
Parameter Symbol Test Conditions Array Min Typ Max Unit
Deep Power Down Current I
ZZ
ZZ# < 0.2V, Other inputs = 0 ~ V
CCQ
(Max. condition : V
CC
=3.3V @ 85
o
C)
No Refresh - - 10 uA
Partial Array Refresh Mode
Standby Current
I
ZZa
1/4 Array - - 65 uA
I
ZZb
1/2 Array - - 75 uA
Reduced Memory Size
Mode Standby Current
I
SB1a
RMS mode. Other inputs = 0 ~ V
CCQ
(Max. condition : V
CC
=3.3V @ 85
o
C)
1/4 Array - - 65 uA
I
SB1b
1/2 Array - - 75 uA
EMP116MEAW Series
1Mx16 Pseudo Static RAM
Preliminary
Rev 0.0
TIMING WAVEFORM OF POWER UP
Power Up Mode
V
CC
CS#
200us
V
CC
(Min.)
Normal Operation
NOTE ( POWER UP )
1. After Vcc reaches Vcc(Min.) , wait 200us with CS# high. Then you get into the normal operation.
