W83194BG-803 - Winbond Electronics Corporation America

W83194BR-803/W83194BG-803

STEPLESS SiS K8

CLOCK GENERATOR

Date: Jan./23/2006 Revision: 0.51

W83194BR-803/W83194BG-803

Publication Release Date: Jan. 2006

- I - Revision 0.51

W83194BR-803/ W83194BG-803

Data Sheet Revision History

PAGES DATES VERSION WEB

VERSION MAIN CONTENTS

1 n.a. 0.5

All of the versions before 0.50 are for

internal use.

2 Jan./2006 0.51 Add lead free part

Please note that all data and specifications are subject to change without notice. All

the trademarks of products and companies mentioned in this data sheet belong to

their respective owners.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where

malfunction of these products can reasonably be expected to result in personal injury. Winbond

customers using or selling these products for use in such applications do so at their own risk and

agree to fully indemnify Winbond for any damages resulting from such improper use or sales.

W83194BR-803/W83194BG-803

-II-

Table of Content-

1. GENERAL DESCRIPTION ......................................................................................................... 1

2. PRODUCT FEATURES .............................................................................................................. 1

3. PIN CONFIGURATION............................................................................................................... 2

4. BLOCK DIAGRAM ...................................................................................................................... 3

5. PIN DESCRIPTION..................................................................................................................... 4

5.1 Crystal I/O.................................................................................................................................4

5.2 CPU, SRC, ZCLK, and AGP, PCI, Clock Outputs ..................................................................4

5.3 Fixed Frequency Outputs.........................................................................................................5

5.4 I2C Control Interface ................................................................................................................5

5.5 Power Management Pins.........................................................................................................5

5.6 Power Pins................................................................................................................................6

6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 7

7. I2C CONTROL AND STATUS REGISTERS .............................................................................. 8

7.1 Register 0: Frequency Select Register (Default = 10h) ..........................................................8

7.2 Register 1: CPU Clock Control (1 = Enable, 0 = Stopped) (Default: E2h) .............................8

7.3 Register 2: PCI Clock Control (1 = Enable, 0 = Stopped) (Default: FFh)...............................9

7.4 Register 3: PCI, AGP Clock (1 = Enable, 0 = Stopped) (Default: FFh)..................................9

7.5 Register 4: 24_48MHz, 12_48MHz, REF Control (1 = Enable, 0 = Stopped) (Default: FFh)9

7.6 Register 5: Watchdog Control (Default: 00h) ........................................................................10

7.7 Register 6: Reserved (Default: 24h) ......................................................................................10

7.8 Register 7: Winbond Chip ID (Default: 01h) (Read Only).....................................................10

7.9 Register 8: M/N Program (Default: 90h)................................................................................11

7.10 Register 9: M/N Program (Default: BBh) ...............................................................................11

7.11 Register 10: Reserved (Default: 3Bh)....................................................................................11

7.12 Register 11: Spread Spectrum Programming (Default: 0Eh) ...............................................11

7.13 Register 12: Divisor Control (Default: 01h)............................................................................12

7.14 Register 13: Step-less Enable Control (Default: 0Ah)...........................................................12

7.15 Register 14: SST Time Control (Default: 10h) ......................................................................13

7.16 Register 15: SST Control (Default: 2Ch) ...............................................................................13

7.17 Register 16: Skew Control (Default: 24h)..............................................................................13

7.18 Register 17: Slew rate Control (Default: 08h)........................................................................14

7.19 Register 18: Slew rate Control (Default: 00h)........................................................................14

7.20 Register 19: Control (Default: DBh) .......................................................................................14

7.21 Register 20: Watch dog timer (Default: 88h) .........................................................................15

7.22 Register21: Control (Default: 00h) .........................................................................................15

W83194BR-803/W83194BG-803

Publication Release Date: Jan. 2006

- III - Revision 0.51

7.23 Register 80: Winbond Test (Default: 00h) .............................................................................15

8. ACCESS INTERFACE .............................................................................................................. 16

8.1 Block Write protocol ...............................................................................................................16

8.2 Block Read protocol ...............................................................................................................16

8.3 Byte Write protocol .................................................................................................................16

8.4 Byte Read protocol.................................................................................................................16

9. SPECIFICATIONS .................................................................................................................... 17

9.1 ABSOLUTE MAXIMUM RATINGS .......................................................................................17

9.2 General Operating Characteristics ........................................................................................17

9.3 Skew Group timing clock........................................................................................................18

9.4 CPU Electrical Characteristics ...............................................................................................18

9.5 ZCLK Electrical Characteristics .............................................................................................18

9.6 AGP Electrical Characteristics ...............................................................................................19

9.7 PCI Electrical Characteristics.................................................................................................19

9.8 12M, 24M, 48M Electrical Characteristics .............................................................................19

9.9 REF Electrical Characteristics ...............................................................................................20

10. ORDERING INFORMATION..................................................................................................... 21

11. HOW TO READ THE TOP MARKING...................................................................................... 21

12. PACKAGE DRAWING AND DIMENSIONS.............................................................................. 22

W83194BR-803/W83194BG-803

Publication Release Date: Jan. 2006

- 1 - Revision 0.51

1. GENERAL DESCRIPTION

The W83194BR-803 is a Clock Synthesizer for SIS K8 chipset. W83194BR-803 provides all clocks

required for high-speed microprocessor and provides step-less frequency programming and 32

different frequencies of CPU, PCI, and AGP clocks setting, support two ZCLK clock outputs; all clocks

are externally selectable with smooth transitions.

The W83194BR-803 provides I2C serial bus interface to program the registers to enable or disable

each clock outputs and provides -0.5% and +/-0.25% center type spread spectrum or programmable

S.S.T. scale to reduce EMI.

The W83194BR-803 also has watchdog timer and reset output pin to support auto-reset when

systems hanging caused by improper frequency setting.

The W83194BR-803 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.

2. PRODUCT FEATURES

• 2 push-pull Differential pairs clock outputs for CPU

• 1 pair current mode Differential clock outputs for SRC, Fix at 100MHz.

• 2 3.3V ZCLK clock outputs for Chipset

• 2 AGP clock outputs

• 9 PCI synchronous clocks include 2 PCI clock free running

• 1 24_48Mhz clock output for super I/O.

• 1 12_48 MHz clock output for USB.

• 3 14.318MHz REF clock outputs.

• ZCLK/AGP/PCI clock out supports synchronous and asynchronous mode

• Smooth frequency switch with selections from 100 to 279MHz

• Step-less frequency programming

• I

2C 2-Wire serial interface and support byte read/write and block read/write.

• -0.5% and +/- 0.25% center type spread spectrum

• Programmable S.S.T. scale to reduce EMI

• Programmable registers to enable/stop each output and select modes

• Programmable clock outputs Slew rate control and Skew control

• Watch Dog Timer and RESET# output pins

• 48-pin SSOP package

W83194BR-803/W83194BG-803

3. PIN CONFIGURATION

-2-

#: Active low

*: Internal pull up resistor 120K to VDD

&: Internal Pull-down resistor 120K to GND

W83194BR-803/W83194BG-803

Publication Release Date: Jan. 2006

- 3 - Revision 0.51

4. BLOCK DIAGRAM

PLL2

XTAL

OSC

PLL1

Spread

Spectrum

M/N/Ratio

ROM

Latch

&POR

Control

Logic

&Config

I2C

Interface

Divider

VCOCLK

12_48MHz

REF 0:2

CPUCLKT 0:1

CPUCLKC 0:1

PCI_F 0:1

PCI 0:6

RESET#

Rref

XIN

XOUT

FS(0:3)

PCI_STOP#*

SEL24_48#&

SDATA*

SCLK*

MODE&

Divider

24_48M Hz

IREF

AGP 0:1

PCI_STOP#*

CLK_STOP#*

ZCLKT/C 0:1

SRCCLKT

SRCCLKC

SEL12_48#*

W83194BR-803/W83194BG-803

-4-

5. PIN DESCRIPTION

BUFFER TYPE SYMBOL DESCRIPTION

IN Input

INtp120k Latched input at power up, internal 120kΩ pull up.

INtd120k Latched input at power up, internal 120kΩ pull down.

OUT Output

OD Open Drain

I/OD Bi-directional Pin, Open Drain.

# Active Low

* Internal 120kΩ pull-up

& Internal 120 kΩ pull-down

5.1 Crystal I/O

PIN PIN NAME TYPE DESCRIPTION

6 XIN IN

Crystal input with internal loading capacitors (18pF) and

feedback resistors.

7 XOUT OUT

Crystal output at 14.318MHz nominally with internal loading

capacitors (18pF).

5.2 CPU, SRC, ZCLK, and AGP, PCI, Clock Outputs

PIN PIN NAME TYPE DESCRIPTION

42,41,38,37

CPUCLKT [0:1]

CPUCLKC

[0:1]

OUT Low skew (< 150ps) 3.3V push-pull differential clock outputs

for host frequencies of CPU

46,45 SRCCLKT

SRCCLKC OUT Low skew (< 150ps) 0.7V current mode 100MHz differential

clock outputs for SRC

9,10 ZCLK [0:1] OUT 3.3V ZCLK clock outputs for Hyperzip

31,30 AGP [0: 1] OUT Low skew (< 250ps) 3.3V AGP clock outputs.

PCI3 OUT 3.3V PCI clock output.

21 PCI_STOP#* INtp120k

Active low, Stop all PCI clock output besides the free running

clocks This is internal 120K pull up.

PCI4 OUT 3.3V PCI clock output.

22 CPU_STOP#* INtp120k

Active low, Stop all CPU clock output; This is internal 120K pull

up.

PCI5 OUT 3.3V PCI clock output.

23 CLK_STOP#* INtp120k

Active low, Stop CPU and ZCLK output clocks, and or Stop

AGP clocks output depending on register byte 2 bit 3, 4, This is

internal 120K pull up

PCI_F0 OUT 3.3V free running PCI clock output

14 FS2&INtd120k

Latched input for FS2 at initial power up for H/W selecting the

output frequency. This is internal 120K pull down.

PCI_F1 OUT 3.3V free running PCI clock output

13 FS3&INtd120k

Latched input for FS3 at initial power up for H/W selecting the

output frequency. This is internal 120K pull down.

13,16,17,20 PCI [6,2:0] OUT Low skew (< 250ps) 3.3V PCI clock outputs.

W83194BR-803/W83194BG-803

Publication Release Date: Jan. 2006

- 5 - Revision 0.51

5.3 Fixed Frequency Outputs

PIN PIN NAME TYPE DESCRIPTION

REF0 OUT 3.3V REF 14.318Mhz clock output.

2 FS0&INtd120k

Latched input for FS0 at initial power up for H/W selecting the

output frequency. This is internal 120K pull down.

REF1 OUT 3.3V REF 14.318Mhz clock output.

3 FS1* INtp120k

Latched input for FS1 at initial power up for H/W selecting the

output frequency, This is internal 120K pull up.

REF2 OUT 3.3V REF 14.318Mhz clock output.

4 MODE&INtd120k

Latched input at initial power up selecting the default=0 is

Desktop mode, MODE=1 is Mobile mode. This is internal

120KΩ pull down.

24_48MHz OUT

24MHz or 48MHz (default) clock output, In power on reset

period, it is a hardware-latched pin, and it can be R/W by I2C

control after power on reset period. Select by register 5 bit 7.

SEL24_48#&INtd120k

Latched input for 24MHz or 48MHz select pin. This is internal

120K pull down default 48MHz. In power on reset period, it is a

hardware-latched pin, and it can be R/W by I2C control after

power on reset period. Select by register 5 bit 7.

12_48MHz OUT

12MHz (default) or 48MHz clock output, In power on reset

period, it is a hardware-latched pin, and it can be R/W by I2C

control after power on reset period. Select by register 21 bit 4.

SEL12_48#* INtp120k

Latched input for 12MHz or 48MHz select pin. This is internal

120K pull up default 12MHz. In power on reset period, it is a

hardware-latched pin, and it can be R/W by I2C control after

power on reset period. Select by register 21 bit 4.

5.4 I2C Control Interface

PIN PIN NAME TYPE DESCRIPTION

33 SDATA* I/OD

Serial data of I2C 2-wire control interface with internal pull-up

resistor.

34 SCLK* IN

Serial clock of I2C 2-wire control interface with internal pull-up

resistor.

5.5 Power Management Pins

PIN PIN NAME TYPE DESCRIPTION

43 IREF OUT

Deciding the reference current for the SRC pairs. The pin was

connected to the precision resistor tied to ground to decide the

appropriate current.

48 RESET# OD

System reset signal when the watchdog is time out. This pin

will generate 250ms low phase when the watchdog timer is

timeout.

W83194BR-803/W83194BG-803

-6-

5.6 Power Pins

PIN PIN NAME TYPE DESCRIPTION

1 VDDREF PWR 3.3V power supply for REF.

12,19 VDDPCI PWR 3.3V power supply for PCI.

29 VDDAGP PWR 3.3V power supply for AGP.

11 VDDZCLK PWR 3.3V power supply for ZCLK.

39 VDDCPU PWR 3.3V power supply for CPU.

28 VDD48 PWR 3.3V power supply for 48MHz.

47 VDDSRC PWR 3.3V power supply for SRC.

36 AVDD PWR 3.3V power for Analog power.

5,8,18,24,25,

32,35,40,44

GND PWR Ground pin

W83194BR-803/W83194BG-803

Publication Release Date: Jan. 2006

- 7 - Revision 0.51

6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE

This frequency table is used at power on latched FS [4:0] value or software programming at SSEL

[4:0] (Register 0 bit 7 ~ 3).

FS4 FS3 FS2 FS1 FS0 CPU (MHZ) SRC (MHZ) ZCLK (MHZ) AGP (MHZ) PCI (MHZ)

0 0 0 0 0 100.00 100.00 133.33 66.67 33.33

0 0 0 0 1 100.99 100.00 134.65 67.33 33.66

0 0 0 1 0 200.00 100.00 133.33 66.67 33.33

0 0 0 1 1 201.98 100.00 134.65 67.33 33.66

0 0 1 0 0 133.33 100.00 133.33 66.67 33.33

0 0 1 0 1 133.99 100.00 133.99 67.00 33.50

0 0 1 1 0 233.33 100.00 140.00 70.00 35.00

0 0 1 1 1 235.74 100.00 141.44 70.72 35.36

0 1 0 0 0 160.00 100.00 128.00 64.00 32.00

0 1 0 0 1 166.66 100.00 133.33 66.67 33.33

0 1 0 1 0 266.66 100.00 133.33 66.67 33.33

0 1 0 1 1 269.30 100.00 134.65 67.33 33.66

0 1 1 0 0 200.00 100.00 133.33 66.67 33.33

0 1 1 0 1 201.98 100.00 134.65 67.33 33.66

0 1 1 1 0 166.66 100.00 125.00 62.50 31.25

0 1 1 1 1 166.66 100.00 133.32 66.66 33.33

1 0 0 0 0 103.00 100.00 137.33 68.67 34.33

1 0 0 0 1 105.00 100.00 140.00 70.00 35.00

1 0 0 1 0 206.00 100.00 137.33 68.67 34.33

1 0 0 1 1 210.00 100.00 140.00 70.00 35.00

1 0 1 0 0 137.33 100.00 137.33 68.66 34.33

1 0 1 0 1 140.00 100.00 140.00 70.00 35.00

1 0 1 1 0 240.33 100.00 144.20 72.10 36.05

1 0 1 1 1 245.00 100.00 147.00 73.50 36.75

1 1 0 0 0 164.80 100.00 131.20 65.60 32.80

1 1 0 0 1 168.00 100.00 134.40 67.20 33.60

1 1 0 1 0 274.66 100.00 137.33 68.66 34.33

1 1 0 1 1 279.99 100.00 140.00 70.00 35.00

1 1 1 0 0 206.00 100.00 137.33 68.67 34.33

1 1 1 0 1 210.00 100.00 140.00 70.00 35.00

1 1 1 1 0 171.66 100.00 128.74 64.37 32.19

1 1 1 1 1 174.99 100.00 131.24 65.60 32.80

W83194BR-803/W83194BG-803

-8-

7. I2C CONTROL AND STATUS REGISTERS

7.1 Register 0: Frequency Select Register (Default = 10h)

BIT NAME PWD DESCRIPTION

7 SSEL [4] 0

6 SSEL [3] 0

5 SSEL [2] 0

4 SSEL [1] 1

3 SSEL [0] 0

Frequency selection by software via I2C

2 EN_SSEL 0

Enable software program FS [4:0].

0 = Select frequency by hardware.

1= Select frequency by software I2C - Bit 7~ 3.

1 EN_SPSP 0

Enable Spread Spectrum in the frequency table.

0 = Normal

1 = Spread Spectrum enabled

0 EN_SAFE_FREQ

Enable reload safe frequency when the watchdog is timeout.

0 = reload the FS [4:0] latched pins when watchdog time out.

1 = reload the safe frequency bit defined at Register 5 bit 4~0.

7.2 Register 1: CPU Clock Control (1 = Enable, 0 = Stopped) (Default: E2h)

BIT PIN NO PWD DESCRIPTION

7 Reserve 1 Reserved

6 42,41 1

CPUT1 / C1 output control

5 38,37 1

CPUT0 / C0 output control

4 Reserved 0

Reserved (Read only)

3 - X

Power on latched value of FS3 pin, Default: 0 (Read only).

2 - X

Power on latched value of FS2 pin, Default: 0 (Read only).

1 - X

Power on latched value of FS1 pin, Default: 1 (Read only).

0 - X

Power on latched value of FS0 pin, Default: 0 (Read only).

W83194BR-803/W83194BG-803

Publication Release Date: Jan. 2006

- 9 - Revision 0.51

7.3 Register 2: PCI Clock Control (1 = Enable, 0 = Stopped) (Default: FFh)

BIT PIN NO PWD DESCRIPTION

7 Reserved 1 Reserved

6 15 1

PCI_F1 output control

5 13 1

PCI6 output control

4 AGP1S_EN 1

CLK_STOP# pin control, 1: Enable AGP1 stop feature, 0: Disable stop

feature.

3 AGP0S_EN 1

CLK_STOP# pin control, 1: Enable AGP0 stop feature, 0: Disable stop

feature.

2 23 1

PCI5 output control

1 22 1

PCI4 output control

0 21 1

PCI3 output control

7.4 Register 3: PCI, AGP Clock (1 = Enable, 0 = Stopped) (Default: FFh)

BIT PIN NO PWD DESCRIPTION

7 20 1 PCI2 output control

6 17 1

PCI1 output control

5 16 1

PCI0 output control

4 14 1

PCI_F0 output control

3 Reserved 1 Reserved

2 Reserved 1 Reserved

1 30 1

AGP_1 output control

0 31 1

AGP_0 output control

7.5 Register 4: 24_48MHz, 12_48MHz, REF Control (1 = Enable, 0 = Stopped)

(Default: FFh)

BIT PIN NO PWD DESCRIPTION

7 26 1 24_48MHz output control

6 Reserved 1 Reserved

5 27 1 12_48MHz output control

4 4 1 REF2 output control

3 3 1 REF1 output control

2 2 1 REF0 output control

1 10 1 ZCLK1 output control

0 9 1 ZCLK1 output control

W83194BR-803/W83194BG-803

-10-

7.6 Register 5: Watchdog Control (Default: 00h)

BIT NAME PWD DESCRIPTION

7 SEL24_48 X

24 / 48 MHz output selection, 1: 24 MHz, 0: 48 MHz (Default).

Default value follow hardware trapping data on SEL24_48# pin.

6 EN_WD 0

Program this bit =>

1: Enable Watchdog Timer feature.

0: Disable Watchdog Timer feature.

Read-back this bit =>

During timer count down the bit read back to 1.

If count to zero, this bit read back to 0.

5 WD_TIMEOUT 0

Read Back only. Timeout Flag. This bit is Read Only.

1: Watchdog has ever started and counts to zero.

0: Watchdog is restarted and counting.

4 SAF_FREQ [4] 0

3 SAF_FREQ [3] 0

2 SAF_FREQ [2] 0

1 SAF_FREQ [1] 0

0 SAF_FREQ [0] 0

These bits will be reloaded in Reg-0 to select frequency table. As the

watchdog is timeout and EN_SAFE_FREQ=1.

7.7 Register 6: Reserved (Default: 24h)

BIT NAME PWD DESCRIPTION

7 Reserved 0

Reserved for Winbond test uses only don’t modify it.

6 Reserved 0 Reserved

5 Reserved 1

4 Reserved 0

3 Reserved 0

Reserved

2 Reserved 1 Reserved

1 Reserved 0 Reserved

0 Reserved 0 Reserved

7.8 Register 7: Winbond Chip ID (Default: 01h) (Read Only)

BIT NAME PWD DESCRIPTION

7 CHPI_ID [7] 0 Winbond Chip ID. W83194BR-803 (SA5901-003)

6 CHPI_ID [6] 0 Winbond Chip ID.

5 CHPI_ID [5] 0 Winbond Chip ID.

4 CHPI_ID [4] 0 Winbond Chip ID.

3 CHPI_ID [3] 0 Winbond Chip ID.

2 CHPI_ID [2] 0 Winbond Chip ID.

1 CHPI_ID [1] 0 Winbond Chip ID.

0 CHPI_ID [0] 1 Winbond Chip ID.

W83194BR-803/W83194BG-803

Publication Release Date: Jan. 2006

- 11 - Revision 0.51

7.9 Register 8: M/N Program (Default: 90h)

BIT NAME PWD DESCRIPTION

7 N_DIV [8] 1 Programmable N divisor value. Bit 7 ~0 are defined in the Register 9.

6 N_DIV [9] 0 Programmable N divisor value. Bit 7 ~0 are defined in the Register 9.

5 M_DIV [5] 0

4 M_DIV [4] 1

3 M_DIV [3] 0

2 M_DIV [2] 0

1 M_DIV [1] 0

0 M_DIV [0] 0

Programmable M divisor value.

7.10 Register 9: M/N Program (Default: BBh)

BIT NAME PWD DESCRIPTION

7 N_DIV [7] 1

6 N_DIV [6] 0

5 N_DIV [5] 1

4 N_DIV [4] 1

3 N_DIV [3] 1

2 N_DIV [2] 0

1 N_DIV [1] 1

0 N_DIV [0] 1

Programmable N divisor value bit 7 ~0. The bit 8 is defined in Register

7.11 Register 10: Reserved (Default: 3Bh)

BIT NAME PWD DESCRIPTION

7 Reserved 0 Reserved

6 Reserved 0

5 Reserved 1

4 Reserved 1

3 Reserved 1

2 Reserved 0

1 Reserved 1

0 Reserved 1

Reserved for Winbond test uses only don’t modify it.

7.12 Register 11: Spread Spectrum Programming (Default: 0Eh)

BIT NAME PWD DESCRIPTION

7 SP_UP [3] 0

6 SP_UP [2] 0

5 SP_UP [1] 0

4 SP_UP [0] 0

Spread Spectrum Up Counter bit 3 ~ bit 0.

3 SP_DOWN [3] 1

2 SP_DOWN [2] 1

1 SP_DOWN [1] 1

0 SP_DOWN [0] 0

Spread Spectrum Down Counter bit 3 ~ bit 0

2’s complement representation.

Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000

W83194BR-803/W83194BG-803

-12-

7.13 Register 12: Divisor Control (Default: 01h)

BIT NAME PWD DESCRIPTION

7 Reserved 0

Reserved for Winbond test uses only don’t modify it.

6 KVAL9 X

5 KVAL5 X

Define the AGP divider ratio

Table-2 integrate the all divider configuration

4 KVAL4 X

3 KVAL3 X

Define the ZCLK divider ratio

Refer to Table-2

2 KVAL2 X

1 KVAL1 X

0 KVAL0 X

Define the CPU divider ratio

Refer to Table-2

Table-2 CPU, AGP, PCI divider ratio selection Table

AGP ZCLK CPU

BIT5 BIT3 BIT1, 0

LSB

MSB 0 1 0 1 00 01 10 11

0 Div8 Div4 Div3 Div4 Div2 Div3 Div4 Div6

Bit2/

Bit4/

Bit9

1 Div5 Div6 Div5 Div6 Div8 Div8 Div8 Div8

7.14 Register 13: Step-less Enable Control (Default: 0Ah)

BIT NAME PWD DESCRIPTION

7 EN_MN_PROG 0

0: Output frequency depend on frequency table

1: Program all clock frequency by changing M/N value

The equation is

VCO =14.318MHz*(N+4)/ M.

Once the watchdog timer timeout, the bit will be clear. Then the

frequency will be decided by hardware default FS<4:0> or desired

frequency select SAF_FREQ [4:0] depend on EN_SAFE_FREQ

(Reg0 - bit 0).

6 Reserved 0

Reserved for Winbond test uses only don’t modify it.

5 Reserved 0

4 Reserved 0 Reserved for Winbond test uses only don’t modify it.

3 IVAL<3> 1

2 IVAL<2> 0

1 IVAL<1> 1

0 IVAL<0> 0

Charge pump current selection

W83194BR-803/W83194BG-803

Publication Release Date: Jan. 2006

- 13 - Revision 0.51

7.15 Register 14: SST Time Control (Default: 10h)

BIT NAME PWD DESCRIPTION

7 CPUT_DRI 0

CPUT output state in during POWER DOWN or Stop mode assertion.

1: Driven (2*Iref)

0: Tristate (Floating)

CPUC always tri-state (floating) in power down Assertion.

6 Reserved 0 Reserved

5 SPCNT [5] 0

4 SPCNT [4] 1

3 SPCNT [3] 0

2 SPCNT [2] 0

1 SPCNT [1] 0

0 SPCNT [0] 0

Spread Spectrum Programmable time, the resolution is 280ns. Default

period is 11.8us

7.16 Register 15: SST Control (Default: 2Ch)

BIT NAME PWD DESCRIPTION

7 INV_CPU 0 Invert the CPU phase, 0: Default, 1: Inverse

6 INV_ZCLK 0 Invert the ZCLK, 0: Default, 1: Inverse

5 SPSP_TYPE 1

Spread spectrum implementation method

1: Pendulum type, 0: Original

4 SPSP1 0

3 SPSP0 1

Spread Spectrum type select.

00: Down 1%

01: Down 0.5%

10: Center +/- 0.5%

11: Center +/- 0.25%

2 ASKEW [2] 1

1 ASKEW [1] 0

0 ASKEW [0] 0

CPU to AGP skew control, Skew resolution is 300ps

The decision of skew direction is same as ASKEW [2:0] setting

7.17 Register 16: Skew Control (Default: 24h)

BIT NAME PWD DESCRIPTION

7 INV_AGP 0 Invert the AGP phase, 0: Default, 1: Inverse

6 INV_PCI 0 Invert the PCI phase, 0: Default, 1: Inverse

5 CSKEW [2] 1

4 CSKEW [1] 0

3 CSKEW [0] 0

CPUCLK1 to CPUCLK0 skew control, Skew resolution is 300ps

The decision of skew direction is same as CSKEW<2:0> setting

2 PSKEW [2] 1

1 PSKEW [1] 0

0 PSKEW [0] 0

CPU to PCI skew control, Skew resolution is 300ps

The decision of skew direction is same as PSKEW [2:0] setting

W83194BR-803/W83194BG-803

-14-

7.18 Register 17: Slew rate Control (Default: 08h)

BIT NAME PWD DESCRIPTION

7 Reserved 0 Reserved

6 INV_12_48MHz 0

Invert the 12_48MHz phase, 0: In phase with 24_48MHz

1: 180 degrees out of phase

5 PCI_F_S2 0

4 PCI_F_S1 0

PCI_F0 slew rate control

11 : Strong , 00 : Weak , 10/01 : Normal

3 Reserved 1 Reserved

2 Reserved 0 Reserved

1 AGP_10_S2 0

0 AGP_10_S1 0

AGP_1 /AGP_0 slew rate control

11 : Strong , 00 : Weak , 10/01 : Normal

7.19 Register 18: Slew rate Control (Default: 00h)

BIT NAME PWD DESCRIPTION

7 Reserved 0 Reserved

6 Reserved 0 Reserved

5 PCI_F4_S2 0

4 PCI_F4_S1 0

PCIF1, 6,5,4 slew rate control

11 : Strong , 00 : Weak , 10/01 : Normal

3 PCI_30_S2 0

2 PCI_30_S1 0

PCI3, 2,1,0 slew rate control

11 : Strong , 00 : Weak , 10/01 : Normal

1 REF_S2 0

0 REF_S1 0

REF2, 0,1, slew rate control

11 : Strong , 00 : Weak , 10/01 : Normal

7.20 Register 19: Control (Default: DBh)

BIT NAME PWD DESCRIPTION

7 CPU1S_EN 1

CLK_STOP# pin control, 1: Enable CPUCLK1 stop feature

0: Disable stop feature

6 CPU0S_EN 1

CLK_STOP# pin control, 1: Enable CPUCLK0 stop feature

0: Disable stop feature

5 Reserved 0

4 Reserved 1

3 Reserved 1

Reserved

2 48MHz_S2 0

1 48MHz_S1 1

12_48MHz/24_48MHz slew rate control

11 : Strong , 00 : Weak , 10/01 : Normal

0 MODE X

Desktop / Mobile Mode selection, 1: Mobile mode, 0: Desktop mode

(Default), Default value follow hardware trapping data on MODE&

REF

pin.

W83194BR-803/W83194BG-803

Publication Release Date: Jan. 2006

- 15 - Revision 0.51

7.21 Register 20: Watch dog timer (Default: 88h)

BIT NAME PWD DESCRIPTION

7 Reserved 1

Reserved for Winbond test uses only don’t modify it.

6 WD_TIME [6] 0

5 WD_TIME [5] 0

4 WD_TIME [4] 0

3 WD_TIME [3] 1

2 WD_TIME [2] 0

1 WD_TIME [1] 0

0 WD_TIME [0] 0

Setting the down count depth (Failure decision). One bit resolution

represents 250ms. Default time depth is 8*250ms = 2.0 second. If the

watchdog timer is counting, this register will return present down count

value.

7.22 Register21: Control (Default: 00h)

BIT NAME PWD DESCRIPTION

7 Tri-state 0 Tri-state all output if set 1

6 Reserved 1 Reserved

5 Reserved 1 Reserved

4 SEL12 X

12 / 48 MHz output selection, 1: 12 MHz. (default), 0: 48 MHz. Default

value follow hardware trapping data on SEL12_48#&/12_48M pin.

3 F12EN 1 PUSB12 output control, 1: Enable, 0: Disable

2 ASEL_2 0

1 ASEL_1 0

0 ASEL_0 0

Asynchronous ZCLK/AGP/PCI frequency table selection

FIX_ADDR<2:0> =>

001: 132 / 66 / 33M 010:132 / 75.43 / 37.7M

011: 132 / 88 / 44M 100:176 / 88 / 44M

101: 132 / 66 / 33M 110:132 / 75.43 / 33M

111: 132 / 88 / 33M 000: Output from PLL1

7.23 Register 80: Winbond Test (Default: 00h)

BIT NAME PWD DESCRIPTION

7:0 TEST_REG1 00h

Winbond Test Register. User don’t write it, otherwise this chip will get an

unexpected result.

BIT

AFFECTED

PIN/FUNCTION

NAME(S)

PWD FUNCTION DESCRIPTION

7 TESTKEY [3] 0

6 TESTKEY [2] 0

5 TESTKEY [1] 0

4 TESTKEY [0] 0

TESTKEY [3:0] is filled 4’b 1011 to enter test mode

3 TESTMODE [3] 0

2 TESTMODE [2] 0

1 TESTMODE [1] 0

0 TESTMODE [0] 0

TESTMODE [3:0] is filled 4’b1000 Î WD test mode

TESTMODE [3:0] is filled 4’b0010 Î force to 1

TESTMODE [3:0] is filled 4’b0001 Î force to 0

W83194BR-803/W83194BG-803

8. ACCESS INTERFACE

The W83194BR-803 provides I2C Serial Bus for microprocessor to read/write internal registers. In the

W83194BR-803 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C

address is defined at 0xD2.

Block Read and Block Write Protocol

8.1 Block Write protocol

8.2 Block Read protocol

## In block mode, the command code must filled 8’h00

8.3 Byte Write protocol

8.4 Byte Read protocol

-16-

W83194BR-803/W83194BG-803

Publication Release Date: Jan. 2006

- 17 - Revision 0.51

9. SPECIFICATIONS

9.1 ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in this table may cause permanent damage to the device.

Precautions should be taken to avoid application of any voltage higher than the maximum rated

voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability.

Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD).

PARAMETER RATING

Absolute 3.3V Core Supply Voltage -0.5V to +4.6V

Absolute 3.3V I/O Supple Voltage - 0.5 V to + 4.6 V

Operating 3.3V Core Supply Voltage 3.135V to 3.465V

Operating 3.3V I/O Supple Voltage 3.135V to 3.465V

Storage Temperature - 65°C to + 150°C

Ambient Temperature - 55°C to + 125°C

Operating Temperature 0°C to + 70°C

Input ESD protection (Human body model) 2000V

9.2 General Operating Characteristics

VDDA=VDDAGP=VDDCPU=VDDREF=VDDPCI= 3.3V

5 %, TA = 0

C to +70

C, Cl=10pF

PARAMETER SYMBOL MIN MAX UNITS TEST CONDITIONS

Input Low Voltage VIL 0.8 Vdc

Input High Voltage VIH 2.0 Vdc

Output Low Voltage VOL 0.4 Vdc All outputs using 3.3V power

Output High Voltage VOH 2.4 Vdc All outputs using 3.3V power

Operating Supply Current Idd 350 mA

CPU = 100 to 279 MHz

PCI = 33.3 Mhz with load

Input pin capacitance Cin 5 pF

Output pin capacitance Cout 6 pF

Input pin inductance Lin 7 nH

W83194BR-803/W83194BG-803

-18-

9.3 Skew Group timing clock

VDDA=VDDAGP=VDDCPU=VDDREF=VDDPCI = 3.3V

5 %, TA = 0

C to +70

C, Cl=10pF

PARAMETER MIN TYP MAX UNITS TEST CONDITIONS

AGP to PCI Skew 1.5 2.6 3.5 ns Measured at 1.5V

CPU to CPU Skew 150 ps Crossing point

SRC to SRC skew 150 ps Crossing point

AGP to AGP Skew 250 ps Measured at 1.5V

PCI to PCI Skew 500 ps Measured at 1.5V

48MHz to 48MHz Skew 1000 ps Measured at 1.5V

REF to REF Skew 500 ps Measured at 1.5V

9.4 CPU Electrical Characteristics

VDDA=VDDCPU= 3.3V

5 %, TA = 0

C to +70

C, Cl=20pF,

PARAMETER MIN MAX UNITS TEST CONDITIONS

Rise Time 2 7 V/ns 20~80%

Fall Time 2 7 V/ns 80~20%

Absolute crossing point

Voltages mV

Cycle to Cycle jitter 200 ps 100 to 200Mhz

Duty Cycle 45 55 % 100 to 200Mhz

9.5 ZCLK Electrical Characteristics

VDDZCLK= 3.3V

5 %, TA = 0

C to +70

C, Test load, Cl=10pF,

PARAMETER MIN MAX UNITS TEST CONDITIONS

Rise Time 500 2000 ps Vol=0.4V, Voh=2.4V

Fall Time 500 2000 ps Voh=2.4V, Vol=0.4V

Cycle to Cycle jitter 250 ps Measured at 1.5V

Duty Cycle 45 55 % Measured at 1.5V

Pull-Up Current Min -33 mA Vout=1.0V

Pull-Up Current Max -33 mA Vout=3.135V

Pull-Down Current Min 30 mA Vout=1.95V

Pull-Down Current Max 38 mA Vout=0.4V

W83194BR-803/W83194BG-803

Publication Release Date: Jan. 2006

- 19 - Revision 0.51

9.6 AGP Electrical Characteristics

VDDAGP= 3.3V

5 %, TA = 0

C to +70

C, Test load, Cl=10pF,

PARAMETER MIN MAX UNITS TEST CONDITIONS

Rise Time 500 2000 ps Vol=0.4V, Voh=2.4V

Fall Time 500 2000 ps Voh=2.4V, Vol=0.4V

Cycle to Cycle jitter 250 ps Measured at 1.5V

Duty Cycle 45 55 % Measured at 1.5V

Pull-Up Current Min -33 mA Vout=1.0V

Pull-Up Current Max -33 mA Vout=3.135V

Pull-Down Current Min 30 mA Vout=1.95V

Pull-Down Current Max 38 mA Vout=0.4V

9.7 PCI Electrical Characteristics

VDDPCI= 3.3V

5 %, TA = 0

C to +70

C, Test load, Cl=10pF,

PARAMETER MIN MAX UNITS TEST CONDITIONS

Rise Time 500 2000 ps Vol=0.4V, Voh=2.4V

Fall Time 500 2000 ps Voh=2.4V, Vol=0.4V

Cycle to Cycle jitter 500 ps Measured at 1.5V

Duty Cycle 45 55 % Measured at 1.5V

Pull-Up Current Min -33 mA Vout=1.0V

Pull-Up Current Max -33 mA Vout=3.135V

Pull-Down Current Min 30 mA Vout=1.95V

Pull-Down Current Max 38 mA Vout=0.4V

9.8 12M, 24M, 48M Electrical Characteristics

VDD48= 3.3V

5 %, TA = 0

C to +70

C, Test load, Cl=10pF,

PARAMETER MIN MAX UNITS TEST CONDITIONS

Rise Time 500 2000 ps Vol=0.4V, Voh=2.4V

Fall Time 500 2000 ps Voh=2.4V, Vol=0.4V

Long term jitter 500 ps Measured at 1.5V

Duty Cycle 45 55 % Measured at 1.5V

Pull-Up Current Min -33 mA Vout=1.0V

Pull-Up Current Max -33 mA Vout=3.135V

Pull-Down Current Min 30 mA Vout=1.95V

Pull-Down Current Max 38 mA Vout=0.4V

W83194BR-803/W83194BG-803

-20-

9.9 REF Electrical Characteristics

VDDREF= 3.3V

5 %, TA = 0

C to +70

C, Test load, Cl=10pF,

PARAMETER MIN MAX UNITS TEST CONDITIONS

Rise Time 4000 ps Vol=0.4V, Voh=2.4V

Fall Time 4000 ps Voh=2.4V, Vol=0.4V

Cycle to Cycle jitter 1000 ps Measured at 1.5V

Duty Cycle 45 55 % Measured at 1.5V

Pull-Up Current Min -33 mA Vout=1.0V

Pull-Up Current Max -33 mA Vout=3.135V

Pull-Down Current Min 30 mA Vout=1.95V

Pull-Down Current Max 38 mA Vout=0.4V

W83194BR-803/W83194BG-803

Publication Release Date: Jan. 2006

- 21 - Revision 0.51

10. ORDERING INFORMATION

PART NUMBER PACKAGE TYPE PRODUCTION FLOW

W83194BR-803 48 PIN SSOP Commercial, 0°C to +70°C

W83194BG-803 48 PIN SSOP(Lead free) Commercial, 0°C to +70°C

11. HOW TO READ THE TOP MARKING

W83194BG-803

28051234

420GAASA

W83194BR-803

28051234

420GAASA

1st line: Winbond logo and the type number:

Normal :W83194BR-803 Lead free part:W83194BG-803

2nd line: Tracking code 2 8051234

2: wafers manufactured in Winbond FAB 2

8051234: wafer production series lot number

3rd line: Tracking code 420 G A A SA

420: packages made in '2004, week 20

G: assembly house ID; O means OSE, G means GR

A: Internal use code

A: IC revision

SA: Internal use code

All the trademarks of products and companies mentioned in this data sheet belong to their respective

owners.

W83194BR-803/W83194BG-803

12. PACKAGE DRAWING AND DIMENSIONS

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components

in systems or equipment intended for surgical implantation, atomic energy control

instruments, airplane or spaceship instruments, transportation instruments, traffic signal

instruments, combustion control instruments, or for other applications intended to support or

sustain life. Further more, Winbond products are not intended for applications wherein failure

of Winbond products could result or lead to a situation wherein personal injury, death or

severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their

own risk and agree to fully indemnify Winbond for any damages resulting from such improper

use or sales.

-22-