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A28F010

1024K (128K x 8) CMOS FLASH MEMORY

(Automotive)

YAutomotive Temperature Range:

b40§Ctoa

125§C

YFlash Memory Electrical Chip-Erase

Ð 1 Second Typical Chip-Erase

YQuick-Pulse Programming Algorithm

Ð10 ms Typical Byte-Program

Ð 2 Second Chip-Program

Y1,000 Erase/Program Cycles Minimum

over Automotive Temperature Range

Y12.0V g5% VPP

YHigh-Performance Read

Ð 120 ns Maximum Access Time

YCMOS Low Power Consumption

Ð 30 mA Maximum Active Current

Ð 300 mA Maximum Standby Current

YIntegrated Program/Erase Stop Timer

YCommand Register Architecture for

Microprocessor/Microcontroller

Compatible Write Interface

YNoise Immunity Features

Ðg10% VCC Tolerance

Ð Maximum Latch-Up Immunity

through EPI Processing

YETOXTM III Flash Nonvolatile Memory

Technology

Ð EPROM-Compatible Process Base

Ð High-Volume Manufacturing

Experience

YJEDEC-Standard Pinouts

Ð 32-Pin Plastic DIP

Ð 32-Lead PLCC

(See Packaging Spec., Order Ý231369)

Intel’s 28F010 CMOS flash memory offers the most cost-effective and reliable alternative for read/write

random access nonvolatile memory. The 28F010 adds electrical chip-erasure and reprogramming to familiar

EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; on-

board during subassembly test; in-system during final test; and in-system after-sale. The 28F010 increases

memory flexibility, while contributing to time- and cost-savings.

The 28F010 is a 1024-kilobit nonvolatile memory organized as 131,072 bytes of 8 bits. Intel’s 28F010 is

offered in 32-pin Plastic DIP or 32-lead PLCC packages. Pin assignments conform to JEDEC standards.

Extended erase and program cycling capability is designed into Intel’s ETOXTM III (EPROM Tunnel Oxide)

process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field

combine to extend reliable cycling beyond that of traditional EEPROMs. With the 12.0V VPP supply, the

28F010 performs a minimum of 1,000 erase and program cycles well within the time limits of the Quick-Pulse

Programming and Quick-Erase algorithms.

Intel’s 28F010 employs advanced CMOS circuitry for systems requiring high-performance access speeds, low

power consumption, and immunity to noise. Its 120 nanosecond access time provides no-WAIT-state perform-

ance for a wide range of microprocessors and microcontrollers. Maximum standby current of 300 mA trans-

lates into power savings when the device is deselected. Finally, the highest degree of latch-up protection is

achieved through Intel’s unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA

on address and data pins, from b1V to VCC a1V.

With Intel’s ETOX III process base, the 28F010 leverages years of EPROM experience to yield the highest

levels of quality, reliability, and cost-effectiveness.

In order to meet the rigorous environmental requirements of automotive applications, Intel offers the 28F010 in

extended automotive temperature range. Read and write characteristics are guaranteed over the range of

b40§Ctoa

125§C ambient.

A28F010

290266–1

Figure 1. 28F010 Block Diagram

AUTOMOTIVE TEMPERATURE FLASH

MEMORIES

The Intel Automotive Flash memories have received

additional processing to enhance product character-

istics. The automotive temperature range is b40§C

to a125§C during the read/write/erase/program

operations.

Versions

Speed Packaging Options

Plastic DIP PLCC

150 AP AN

120 AP AN

A28F010

28F010

290266–2

290266–3

Figure 2. 28F010 Pin Configurations

Table 1. Pin Description

Symbol Type Name and Function

A0–A16 INPUT ADDRESS INPUTS for memory addresses. Addresses are internally

latched during a write cycle.

DQ0–DQ7INPUT/OUTPUT DATA INPUT/OUTPUT: Inputs data during memory write cycles;

outputs data during memory read cycles. The data pins are active high

and float to tri-state OFF when the chip is deselected or the outputs

are disabled. Data is internally latched during a write cycle.

CEÝINPUT CHIP ENABLE: Activates the device’s control logic, input buffers,

decoders and sense amplifiers. CEÝis active low; CEÝhigh

deselects the memory device and reduces power consumption to

standby levels.

OEÝINPUT OUTPUT ENABLE: Gates the devices output through the data buffers

during a read cycle. OEÝis active low.

WEÝINPUT WRITE ENABLE: Controls writes to the control register and the array.

Write enable is active low. Addresses are latched on the falling edge

and data is latched on the rising edge of the WEÝpulse.

Note: With VPP s6.5V, memory contents cannot be altered.

VPP ERASE/PROGRAM POWER SUPPLY for writing the command

VCC DEVICE POWER SUPPLY (5V g10%)

VSS GROUND

NC NO INTERNAL CONNECTION to device. Pin may be driven or left

floating.

A28F010

APPLICATIONS

The 28F010 flash-memory adds electrical chip-era-

sure and reprogrammability to EPROM non-volatility

and ease of use. The 28F010 is ideal for storing

code or data-tables in applications where periodic

updates are required. The 28F010 also serves as a

dense, nonvolatile data acquisition and storage me-

dium.

The need for code updates pervades all phases of a

system’s lifeÐfrom prototyping to system manufac-

ture to after-sale service. In the factory, during proto-

typing, revisions to control code necessitate ultravio-

let erasure and reprogramming of EPROM-based

prototype codes. The 28F010 replaces the 15- to

20-minute ultraviolet erasure with one-second elec-

trical erasure. Electrical chip-erasure and repro-

gramming occur in the same workstation or PROM-

programmer socket.

Diagnostics, performed at subassembly or final as-

sembly stages, often require the socketing of

EPROMs. Socketed test codes are ultimately re-

placed with EPROMs containing the final program.

With electrical chip-erasure and reprogramming, the

28F010 is soldered to the circuit board. Test codes

are programmed into the 28F010 as it resides on the

circuit board. Ultimately, the final code can be down-

loaded to the device. The 28F010’s in-circuit altera-

bility eliminates unnecessary handling and less-reli-

able socketed connections, while adding greater

test flexibility.

Material and labor costs associated with code

changes increase at higher levels of system integra-

tionÐthe most costly being code updates after sale.

Code ‘‘bugs’’, or the desire to augment system func-

tionality, prompt after-sale code updates. Field revi-

sions to EPROM-based code require the removal of

EPROM components or entire boards.

Designing with the in-circuit alterable 28F010 elimi-

nates socketed memories, reduces overall material

costs, and drastically cuts the labor costs associat-

ed with code updates. With the 28F010, code up-

dates are implemented locally via an edge-connec-

tor, or remotely over a serial communication link.

The 28F010’s electrical chip-erasure, byte repro-

grammability, and complete nonvolatility fit well with

data accumulation needs. Electrical chip-erasure

gives the designer a ‘‘blank-slate’’ in which to log

data. Data can be periodically off-loaded for analy-

sisÐerasing the slate and repeating the cycle. Or,

multiple devices can maintain a ‘‘rolling window’’ of

accumulated data.

With high density, nonvolatility, and extended cycling

capability, the 28F010 offers an innovative alterna-

tive for mass storage. Integrating main memory and

backup storage functions into directly executable

flash memory boosts system performance, shrinks

system size, and cuts power consumption. Reliability

exceeds that of electromechanical media, with

greater durability in extreme environmental condi-

tions.

A high degree of on-chip feature integration simpli-

fies memory-to-processor interfacing. Figure 3 de-

picts two 28F010s tied to the 80C186 system bus.

The 28F010’s architecture minimizes interface cir-

cuitry needed for complete in-circuit updates of

memory contents.

With cost-effective in-system reprogramming and

extended cycling capability, the 28F010 fills the

functionality gap between traditional EPROMs and

EEPROMs. EPROM-compatible specifications,

straightforward interfacing, and in-circuit alterability

allows designers to easily augment memory flexibili-

ty and satisfy the need for updatable nonvolatile

storage in today’s designs.

A28F010

290266–4

Figure 3. 28F010 in a 80C186 System

PRINCIPLES OF OPERATION

Flash-memory augments EPROM functionality with

in-circuit electrical erasure and reprogramming. The

28F010 introduces a command register to manage

this new functionality. The command register allows

for: 100% TTL-level control inputs; fixed power sup-

plies during erasure and programming; and maxi-

mum EPROM compatibility.

In the absence of high voltage on the VPP pin, the

28F010 is a read-only memory. Manipulation of the

external memory-control pins yields the standard

EPROM read, standby, output disable, and Intelli-

gent Identifier operations.

The same EPROM read, standby, and output disable

operations are available when high voltage is ap-

plied to the VPP pin. In addition, high voltage on VPP

enables erasure and programming of the device. All

functions associated with altering memory con-

tentsÐIntelligent Identifier, erase, erase verify, pro-

gram, and program verifyÐare accessed via the

command register.

Commands are written to the register using standard

microprocessor write timings. Register contents

serve as input to an internal state-machine which

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data

needed for programming or erase operations. With

the appropriate command written to the register,

standard microprocessor read timings output array

data, access the Intelligent Identifier codes, or out-

put data for erase and program verification.

Integrated Program/Erase Stop Timer

Successive command write cycles define the dura-

tions of program and erase operations; specifically,

the program or erase time durations are normally

terminated by associated program or erase verify

commands. An integrated stop timer provides simpli-

fied timing control over these operations; thus elimi-

nating the need for maximum program/erase timing

specifications. Program and erase pulse durations

are minimums only. When the stop timer terminates

a program or erase operation, the device enters an

inactive state and remains inactive until receiving the

appropriate verify or reset command.

Write Protection

The command register is only alterable when VPP is

at high voltage. Depending upon the application, the

system designer may choose to make the VPP pow-

er supply switchableÐavailable only when memory

updates are desired. When high voltage is removed,

A28F010

Table 2. 28F010 Bus Operations

Pins VPP(1) A0A9CEÝOEÝWEÝDQ0–DQ7

Operation

Read VPPL A0A9VIL VIL VIH Data Out

Output Disable VPPL XXV

IL VIH VIH Tri-State

READ-ONLY Standby VPPL XXV

IH X X Tri-State

Intelligent Identifier (Mfr)(2) VPPL VIL VID(3) VIL VIL VIH Data e89H

Intelligent Identifier (Device)(2) VPPL VIH VID(3) VIL VIL VIH Data eB4H

Read VPPH A0A9VIL VIL VIH Data Out(4)

READ/WRITE Output Disable VPPH XXV

IL VIH VIH Tri-State

Standby(5) VPPH XXV

IH X X Tri-State

Write VPPH A0A9VIL VIH VIL Data In(6)

NOTES:

1. VPPL may be ground, a no-connect with a resistor tied to ground, or s6.5V. VPPH is the programming voltage specified

for the device. Refer to D.C. Characteristics. When VPP eVPPL memory contents can be read but not written or erased.

2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other

addresses low.

3. VID is the Intelligent Identifier high voltage. Refer to DC Characteristics.

4. Read operations with VPP eVPPH may access array data or the Intelligent Identifier codes.

5. With VPP at high voltage, the standby current equals ICC aIPP (standby).

6. Refer to Table 3 for valid Data-In during a write operation.

7. X can be VIL or VIH.

the contents of the register default to the read com-

mand, making the 28F010 a read-only memory.

Memory contents cannot be altered.

Or, the system designer may choose to ‘‘hardwire’’

VPP, making the high voltage supply constantly

available. In this instance, all operations are per-

formed in conjunction with the command register.

The 28F010 is designed to accommodate either de-

sign practice, and to encourage optimization of the

processor-memory interface.

The two-step Program/Erase write sequence to the

Command Register provides additional software

write protection.

BUS OPERATIONS

Read

The 28F010 has two control functions, both of which

must be logically active, to obtain data at the out-

puts. Chip-Enable (CEÝ) is the power control and

should be used for device selection. Output-Enable

(OEÝ) is the output control and should be used to

gate data from the output pins, independent of de-

vice selection. Figure 6 illustrates read timing wave-

forms.

When VPP is low (VPPL), the read only operation is

active. This permits reading the data in the array and

outputting the Intelligent Identifier codes (see Ta-

ble 2). When VPP is high (VPPH), the default condi-

tion of the device is the read only mode. This allows

reading the data in the array. Further functionality is

achieved though the Command Register as shown

in Table 3.

Output Disable

With Output-Enable at a logic-high level (VIH), output

from the device is disabled. Output pins are placed

in a high-impedance state.

Standby

With Chip-Enable at a logic-high level, the standby

operation disables most of the 28F010’s circuitry

and substantially reduces device power consump-

tion. The outputs are placed in a high-impedance

state, independent of the Output-Enable signal. If

the 28F010 is deselected during erasure, program-

ming, or program/erase verification, the device

draws active current until the operation is terminat-

ed.

Intelligent Identifier Operation

The Intelligent Identifier operation outputs the manu-

facturer code (89H) and device code (B4H). Pro-

gramming equipment automatically matches the

device with its proper erase and programming

algorithms.

A28F010

With Chip-Enable and Output-Enable at a logic low

level, raising A9 to high voltage VID (see DC Charac-

teristics) activates the operation. Data read from lo-

cations 0000H and 0001H represent the manufac-

turer’s code and the device code, respectively.

The manufacturer- and device-codes can also be

read via the command register, for instances where

the 28F010 is erased and reprogrammed in the tar-

get system. Following a write of 90H to the com-

mand register, a read from address location 0000H

outputs the manufacturer code (89H). A read from

address 0001H outputs the device code (B4H).

Write

Device erasure and programming are accomplished

via the command register, when high voltage is ap-

plied to the VPP pin. The contents of the register

serve as input to the internal state-machine. The

state-machine outputs dictate the function of the

device.

The command register itself does not occupy an ad-

dressable memory location. The register is a latch

used to store the command, along with address and

data information needed to execute the command.

The command register is written by bringing Write-

Enable to a logic-low level (VIL), while Chip-Enable is

low. Addresses are latched on the falling edge of

Write-Enable, while data is latched on the rising

edge of the Write-Enable pulse. Standard microproc-

essor write timings are used.

Refer to A.C. Write Characteristics and the Erase/

Programming Waveforms for specific timing

parameters.

COMMAND DEFINITIONS

When low voltage is applied to the VPP pin, the con-

tents of the command register default to 00H, en-

abling read-only operations.

Placing high voltage on the VPP pin enables read/

write operations. Device operations are selected by

writing specific data patterns into the command reg-

ister. Table 3 defines these 28F010 register

commands.

Table 3. Command Definitions

Bus First Bus Cycle Second Bus Cycle

Command Cycles

Req’d Operation(1) Address(2) Data(3) Operation(1) Address(2) Data(3)

Read Memory 1 Write X 00H

Read Intelligent Identifier Codes(4) 2 Write X 90H Read IA ID

Set-up Erase/Erase(5) 2 Write X 20H Write X 20H

Erase Verify(5) 2 Write EA A0H Read X EVD

Set-up Program/Program(6) 2 Write X 40H Write PA PD

Program Verify(6) 2 Write X C0H Read X PVD

Reset(7) 2 Write X FFH Write X FFH

NOTES:

1. Bus operations are defined in Table 2.

2. IA eIdentifier address: 00H for manufacturer code, 01H for device code.

EA eAddress of memory location to be read during erase verify.

PA eAddress of memory location to be programmed.

Addresses are latched on the falling edge of the Write-Enable pulse.

3. ID eData read from location IA during device identification (Mfr e89H, Device eB4H).

EVD eData read from location EA during erase verify.

PD eData to be programmed at location PA. Data is latched on the rising edge of Write-Enable.

PVD eData read from location PA during program verify. PA is latched on the Program command.

4. Following the Read Intelligent ID command, two read operations access manufacturer and device codes.

5. Figure 5 illustrates the Quick-Erase Algorithm.

6. Figure 4 illustrates the Quick-Pulse Programming Algorithm.

7. The second bus cycle must be followed by the desired command register write.

A28F010

Read Command

While VPP is high, for erasure and programming,

memory contents can be accessed via the read

command. The read operation is initiated by writing

00H into the command register. Microprocessor

read cycles retrieve array data. The device remains

enabled for reads until the command register con-

tents are altered.

The default contents of the register upon VPP pow-

er-up is 00H. This default value ensures that no spu-

rious alteration of memory contents occurs during

the VPP power transition. Where the VPP supply is

hard-wired to the 28F010, the device powers-up and

remains enabled for reads until the command-regis-

ter contents are changed. Refer to the A.C. Read

Characteristics and Waveforms for specific timing

parameters.

Intelligent Identifier Command

Flash-memories are intended for use in applications

where the local CPU alters memory contents. As

such, manufacturer- and device-codes must be ac-

cessible while the device resides in the target sys-

tem. PROM programmers typically access signature

codes by raising A9 to a high voltage. However, mul-

tiplexing high voltage onto address lines is not a de-

sired system-design practice.

The 28F010 contains an inteligent Identifier opera-

tion to supplement traditional PROM-programming

methodology. The operation is initiated by writing

90H into the command register. Following the com-

mand write, a read cycle from address 0000H re-

trieves the manufacturer code of 89H. A read cycle

from address 0001H returns the device code of

B4H. To terminate the operation, it is necessary to

write another valid command into the register.

Set-up Erase/Erase Commands

Set-up Erase is a command-only operation that

stages the device for electrical erasure of all bytes in

the array. The set-up erase operation is performed

by writing 20H to the command register.

To commence chip-erasure, the erase command

(20H) must again be written to the register. The

erase operation begins with the rising edge of the

Write-Enable pulse and terminates with the rising

edge of the next Write-Enable pulse (i.e., Erase-Veri-

fy Command).

This two-step sequence of set-up followed by execu-

tion ensures that memory contents are not acciden-

tally erased. Also, chip-erasure can only occur when

high voltage is applied to the VPP pin. In the absence

of this high voltage, memory contents are protected

against erasure. Refer to A.C. Erase Characteristics

and Waveforms for specific timing parameters.

Erase-Verify Command

The erase command erases all bytes of the array in

parallel. After each erase operation, all bytes must

be verified. The erase verify operation is initiated by

writing A0H into the command register. The address

for the byte to be verified must be supplied as it is

latched on the falling edge of the Write-Enable

pulse. The register write terminates the erase opera-

tion with the rising edge of its Write-Enable pulse.

The 28F010 applies an internally-generated margin

voltage to the addressed byte. Reading FFH from

the addressed byte indicates that all bits in the byte

are erased.

The erase-verify command must be written to the

command register prior to each byte verification to

latch its address. The process continues for each

byte in the array until a byte does not return FFH

data, or the last address is accessed.

In the case where the data read is not FFH, another

erase operation is performed. (Refer to Set-up

Erase/Erase). Verification then resumes from the

address of the last-verified byte. Once all bytes in

the array have been verified, the erase step is com-

plete. The device can be programmed. At this point,

the verify operation is terminated by writing a valid

command (e.g. Program Set-up) to the command

trates how commands and bus operations are com-

bined to perform electrical erasure of the 28F010.

Refer to A.C. Erase Characteristics and Waveforms

for specific timing parameters.

Set-up Program/Program Commands

Set-up program is a command-only operation that

stages the device for byte programming. Writing 40H

into the command register performs the set-up

operation.

Once the program set-up operation is performed,

the next Write-Enable pulse causes a transition to

an active programming operation. Addresses are in-

ternally latched on the falling edge of the Write-En-

able pulse. Data is internally latched on the rising

edge of the Write-Enable pulse. The rising edge of

Write-Enable also begins the programming opera-

tion. The programming operation terminates with the

next rising edge of Write-Enable, used to write the

program-verify command. Refer to A.C. Program-

A28F010

ming Characteristics and Waveforms for specific

timing parameters.

Program-Verify Command

The 28F010 is programmed on a byte-by-byte basis.

Byte programming may occur sequentially or at ran-

dom. Following each programming operation, the

byte just programmed must be verified.

The program-verify operation is initiated by writing

C0H into the command register. The register write

terminates the programming operation with the ris-

ing edge of its Write-Enable pulse. The program-ver-

ify operation stages the device for verification of the

byte last programmed. No new address information

is latched.

The 28F010 applies an internally-generated margin

voltage to the byte. A microprocessor read cycle

outputs the data. A successful comparison between

the programmed byte and true data means that the

byte is successfully programmed. Programming then

proceeds to the next desired byte location. Figure 4,

the 28F010 Quick-Pulse Programming algorithm, il-

lustrates how commands are combined with bus op-

erations to perform byte programming. Refer to A.C.

Programming Characteristics and Waveforms for

specific timing parameters.

Reset Command

A reset command is provided as a means to safely

abort the erase- or program-command sequences.

Following either set-up command (erase or program)

with two consecutive writes of FFH will safely abort

the operation. Memory contents will not be altered.

A valid command must then be written to place the

device in the desired state.

EXTENDED ERASE/PROGRAM CYCLING

EEPROM cycling failures have always concerned

users. The high electrical field required by thin oxide

EEPROMs for tunneling can literally tear apart the

oxide at defect regions. To combat this, some sup-

pliers have implemented redundancy schemes, re-

ducing cycling failures to insignificant levels. Howev-

er, redundancy requires that cell size be doubledÐ

an expensive solution.

Intel has designed extended cycling capability into

its ETOX-II flash memory technology. Resulting im-

provements in cycling reliability come without in-

creasing memory cell size or complexity. First, an

advanced tunnel oxide increases the charge carry-

ing ability ten-fold. Second, the oxide area per cell

subjected to the tunneling electric field is one-tenth

that of common EEPROMs, minimizing the probabili-

ty of oxide defects in the region. Finally, the peak

electric field during erasure is approximately 2 MV/

cm lower than EEPROM. The lower electric field

greatly reduces oxide stress and the probability of

failureÐincreasing time to wearout by a factor of

100,000,000.

The device is programmed and erased using Intel’s

Quick-Pulse Programming and Quick-Erase algo-

rithms. Intel’s algorithmic approach uses a series of

operations (pulses), along with byte verification, to

completely and reliably erase and program the de-

vice.

QUICK-PULSE PROGRAMMING ALGORITHM

The Quick-Pulse Programming algorithm uses pro-

gramming operations of 10 ms duration. Each opera-

tion is followed by a byte verification to determine

when the addressed byte has been successfully pro-

grammed. The algorithm allows for up to 25 pro-

gramming operations per byte, although most bytes

verify on the first or second operation. The entire

sequence of programming and byte verification is

performed with VPP at high voltage. Figure 4 illus-

trates the Quick-Pulse Programming algorithm.

QUICK-ERASE ALGORITHM

Intel’s Quick-Erase algorithm yields fast and reliable

electrical erasure of memory contents. The algo-

rithm employs a closed-loop flow, similar to the

Quick-Pulse Programming algorithm, to simulta-

neously remove charge from all bits in the array.

Erasure begins with a read of memory contents. The

28F010 is erased when shipped from the factory.

Reading FFH data from the device would immedi-

ately be followed by device programming.

For devices being erased and reprogrammed, uni-

form and reliable erasure is ensured by first pro-

gramming all bits in the device to their charged state

(Data e00H). This is accomplished, using the

Quick-Pulse Programming algorithm, in approxi-

mately two seconds.

Erase execution then continues with an initial erase

operation. Erase verification (data eFFH) begins at

address 0000H and continues through the array to

the last address, or until data other than FFH is en-

countered. With each erase operation, an increasing

number of bytes verify to the erased state. Erase

efficiency may be improved by storing the address of

the last byte verified in a register. Following the next

erase operation, verification starts at that stored ad-

dress location. Erasure typically occurs in one sec-

ond. Figure 5 illustrates the Quick-Erase algorithm.

A28F010

290266–5

Bus Command Comments

Operation

Standby Wait for VPP Ramp to VPPH(1)

Initialize Pulse-Count

Write Set-up Data e40H

Program

Write Program Valid Address/Data

Standby Duration of Program

Operation (tWHWH1)

Write Program(3) Data eC0H; Stops Program

Verify Operation(2)

Standby tWHGL

Read Read Byte to Verify

Programming

Standby Compare Data Output to Data

Expected

Write Read Data e00H, Resets the

Standby Wait for VPP Ramp to VPPL(1)

NOTES:

1. See DC Characteristics for value of VPPH. The VPP

power supply can be hard-wired to the device or

switchable. When VPP is switched, VPPL may be

ground, no-connect with a resistor tied to ground, or

less than 6.5V. Refer to Principles of Operation.

2. Refer to Principles of Operation.

3. Program Verify is only performed after byte program-

ming. A final read/compare may be performed (option-

al) after the register is written with the Read command.

4. CAUTION: The algorithm MUST BE FOLLOWED

to ensure proper and reliable operation of the de-

vice.

Figure 4. 28F010 Quick-Pulse Programming Algorithm

A28F010

290266–6

Bus Command Comments

Operation

Entire Memory Must e00H

Before Erasure

Use Quick-Pulse

Programming Algorithm

(Figure 4)

Standby Wait for VPP Ramp to VPPH(1)

Initialize Addresses and

Pulse-Count

Write Set-up Data e20H

Erase

Write Erase Data e20H

Standby Duration of Erase Operation

(tWHWH2)

Write Erase(3) Addr eByte to Verify;

Verify Data eA0H; Stops Erase

Operation(2)

Standby tWHGL

Read Read Byte to Verify Erasure

Standby Compare Output to FFH

Increment Pulse-Count

Write Read Data e00H, Resets the

Standby Wait for VPP Ramp to VPPL(1)

NOTES:

1. See DC Characteristics for value of VPPH. The VPP

power supply can be hard-wired to the device or

switchable. When VPP is switched, VPPL may be

ground, no-connect with a resistor tied to ground, or

less than 6.5V. Refer to Principles of Operation.

2. Refer to Principles of Operation.

3. Erase Verify is performed only after chip-erasure. A

final read/compare may be performed (optional) after

the register is written with the read command.

4. CAUTION: The algorithm MUST BE FOLLOWED

to ensure proper and reliable operation of the de-

vice.

Figure 5. A28F010 Quick-Erase Algorithm

A28F010

DESIGN CONSIDERATIONS

Two-Line Output Control

Flash-memories are often used in larger memory ar-

rays. Intel provides two read-control inputs to ac-

commodate multiple memory connections. Two-line

control provides for:

a. the lowest possible memory power dissipation

and,

b. complete assurance that output bus contention

will not occur.

To efficiently use these two control inputs, an ad-

dress-decoder output should drive chip-enable,

while the system’s read signal controls all flash-

memories and other parallel memories. This assures

that only enabled memory devices have active out-

puts, while deselected devices maintain the low

power standby condition.

Power Supply Decoupling

Flash memory power-switching characteristics re-

quire careful device decoupling. System designers

are interested in three supply current (ICC) issuesÐ

standby, active, and transient current peaks pro-

duced by falling and rising edges of chip-enable. The

capacitive and inductive loads on the device outputs

determine the magnitudes of these peaks.

Two-line control and proper decoupling capacitor

selection will suppress transient voltage peaks.

Each device should have a 0.1 mF ceramic capacitor

connected between VCC and VSS, and between VPP

and VSS.

Place the high-frequency, low-inherent-inductance

capacitors as close as possible to the devices. Also,

for every eight devices, a 4.7 mF electrolytic capaci-

tor should be placed at the array’s power supply

connection, between VCC and VSS. The bulk capaci-

tor will overcome voltage slumps caused by printed-

circuit-board trace inductance, and will supply

charge to the smaller capacitors as needed.

VPP Trace on Printed Circuit Boards

Programming flash-memories, while they reside in

the target system, requires that the printed circuit

board designer pay attention to the VPP power sup-

ply trace. The VPP pin supplies the memory cell cur-

rent for programming. Use similar trace widths and

layout considerations given the VCC power bus. Ad-

equate VPP supply traces and decoupling will de-

crease VPP voltage spikes and overshoots.

Power Up/Down Protection

The 28F010 is designed to offer protection against

accidental erasure or programming, caused by spur-

ious system-level signals that may exist during pow-

er transitions. Also, with its control register architec-

ture, alteration of memory contents only occurs after

successful completion of the two-step command se-

quences. Power supply sequencing is not required.

Internal circuitry of the 28F010 ensures that the

command register architecture is reset to the read

mode on power up.

A system designer must guard against active writes

for VCC voltages above the VLKO when VPP is ac-

tive. Since both WEÝand CEÝmust be low for a

command write, driving either to VIH will prohibit

writes. The control register architecture provides an

added level of protection since alteration of memory

contents only occurs after successful completion of

the two-step command sequences.

28F010 Power Dissipation

When designing portable systems, designers must

consider battery power consumption not only during

device operation, but also for data retention during

system idle time. Flash nonvolatility increases the

usable battery life of your system because the

28F010 does not consume any power to retain code

or data when the system is off. Table 4 illustrates the

power dissipated when updating the 28F010.

Table 4. 28F010 Typical Update

Power Dissipation(4)

Operation Power Dissipation Notes

(Watt-Seconds)

Array Program/ 0.171 1

Program Verify

Array Erase/ 0.136 2

Erase Verify

One Complete 0.478 3

Cycle

NOTES:

1. Formula to calculate typical Program/Program Verify

Power e[VPP cÝBytes ctypical ÝProg Pulses

(tWHWH1 cIPP2 typical atWHGL cIPP4 typical)]a[VCC

cÝBytes ctypical ÝProg Pulses (tWHWH1 cICC2 typi-

cal atWHGL cICC4 typical].

2. Formula to calculate typical Erase/Erase Verify Power

e[VPP (VPP3 typical ctERASE typical aIPP5 typical c

tWHGL cÝBytes)]a[VCC (ICC3 typical ctERASE typical

cICC5 typical ctWHGL cÝBytes)].

3. One Complete Cycle eArray Preprogram aArray

Erase aProgram.

4. ‘‘Typicals’’ are not guaranteed, but based on a limited

number of samples from production lots.

A28F010

ABSOLUTE MAXIMUM RATINGS*

Operating Temperature

During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀb40§Ctoa

125§C(1)

During Erase/Program ÀÀÀÀÀÀÀb40§Ctoa

125§C

Temperature Under BiasÀÀÀÀÀÀÀÀb40§Ctoa

125§C

Storage Temperature ÀÀÀÀÀÀÀÀÀÀb65§Ctoa

150§C

Voltage on Any Pin with

Respect to Ground ÀÀÀÀÀÀÀÀÀÀb2.0V to a7.0V(2)

Voltage on Pin A9with

Respect to Ground ÀÀÀÀÀÀÀb2.0V to a13.5V(2, 3)

VPP Supply Voltage with

Respect to Ground

During Erase/Program ÀÀÀÀb2.0V to a14.0V(2, 3)

VCC Supply Voltage with

Respect to Ground ÀÀÀÀÀÀÀÀÀÀb2.0V to a7.0V(2)

Output Short Circuit CurrentÀÀÀÀÀÀÀÀÀÀÀÀÀ100 mA(4)

Maximum Junction Temperature (TJ) ÀÀÀÀÀÀa140§C

NOTICE: This is a production data sheet. The specifi-

cations are subject to change without notice.

WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

NOTES:

1. Operating temperature is for automotive product defined by this specification.

2. Minimum DC input voltage is b0.5V. During transitions, inputs may undershoot to b2.0V for periods less than 20 ns.

Maximum DC voltage on output pins is VCC a0.5V, which may overshoot to VCC a2.0V for periods less than 20 ns.

3. Maximum DC voltage on A9or VPP may overshoot to a14.0V for periods less than 20 ns.

4. Output shorted for no more than one second. No more than one output shorted at a time.

OPERATING CONDITIONS

Symbol Parameter Limits Unit Comments

Min Max

TAOperating Temperature b40 a125 §C For Read-Only and

Read/Write Operations

VCC VCC Supply Voltage 4.50 5.50 V

DC CHARACTERISTICSÐTTL/NMOS COMPATIBLE

Symbol Parameter Notes Limits Unit Test Conditions

Min Typical Max

ILI Input Leakage Current 1 g1.0 mAV

CC eVCC Max

VIN eVCC or VSS

ILO Output Leakage Current 1 g10 mAV

CC eVCC Max

VOUT eVCC or VSS

ICCS VCC Standby Current 1 1.0 mA VCC eVCC Max

CEÝeVIH

ICC1 VCC Active Read Current 1 10 30 mA VCC eVCC Max, CEÝeVIL

fe6 MHz, IOUT e0mA

CC2 VCC Programming Current 1, 2 1.0 30 mA Programming in Progress

ICC3 VCC Erase Current 1, 2 5.0 30 mA Erasure in Progress

ICC4 VCC Program Verify Current 1, 2 5.0 30 mA VPP eVPPH Program Verify in Progress

ICC5 VCC Erase Verify Current 1, 2 5.0 30 mA VPP eVPPH Erase Verify in Progress

IPPS VPP Leakage Current 1 g10 mAV

PP sVCC

IPP1 VPP Read Current or 1 90 200 mAV

PP lVCC

Standby Current g10 mAV

PP sVCC

A28F010

DC CHARACTERISTICSÐTTL/NMOS COMPATIBLE (Continued)

Symbol Parameter Notes Limits Unit Test Conditions

Min Typical Max

IPP2 VPP Programming Current 1, 2 8.0 30 mA VPP eVPPH

Programming in Progress

IPP3 VPP Erase Current 1, 2 4.0 30 mA VPP eVPPH

Erasure in Progress

IPP4 VPP Program Verify Current 1, 2 2.0 5.0 mA VPP eVPPH

Program Verify in Progress

IPP5 VPP Erase Verify Current 1, 2 2.0 5.0 mA VPP eVPPH

Erase Verify in Progress

VIL Input Low Voltage b0.5 0.8 V

VIH Input High Voltage 2.0 VCC a0.5 V

VOL Output Low Voltage 0.45 V IOL e2.1 mA

VCC eVCC Min

VOH1 Output High Voltage 2.4 V IOH eb

2.5 mA

VCC eVCC Min

VID A9Intelligent Identifer Voltage 11.50 13.00 V A9eVID

IID VCC ID Current 110 30 mA A9eVID

VPP ID CURRENT 90 500 mA

VPPL VPP during Read-Only Operations 0.00 6.5 V NOTE: Erase/Program are

Inhibited when VPP eVPPL

VPPH VPP during Read/Write Operations 11.40 12.60 V

VLKO VCC Erase/Write Lock Voltage 2.5 V

DC CHARACTERISTICSÐCMOS COMPATIBLE

Symbol Parameter Notes Limits Unit Test Conditions

Min Typical Max

ILI Input Leakage Current 1 g1.0 mAV

CC eVCC Max

VIN eVCC or VSS

ILO Output Leakage Current 1 g10 mAV

CC eVCC Max

VOUT eVCC or VSS

ICCS VCC Standby Current 1 300 mAV

CC eVCC Max

CEÝeVCC g0.2V

ICC1 VCC Active Read Current 1 10 30 mA VCC eVCC Max, CE eVIL

fe6 MHz, IOUT e0mA

CC2 VCC Programming Current 1, 2 1.0 30 mA Programming in Progress

ICC3 VCC Erase Current 1, 2 5.0 30 mA Erasure in Progress

IPPS VPP Leakage Current 1 g10 mAV

PP sVCC

IPP1 VPP Read Current or 1 90 200 mAV

PP lVCC

Standby Current g10 VPP sVCC

A28F010

DC CHARACTERISTICSÐCMOS COMPATIBLE (Continued)

Symbol Parameter Notes Limits Unit Test Conditions

Min Typical Max

IPP2 VPP 1, 2 8.0 30 mA VPP eVPPH

Programming Programming in Progress

Current

IPP3 VPP Erase 1, 2 4.0 30 mA VPP eVPPH

Current Erasure in Progress

IPP4 VPP Program 1, 2 2.0 5.0 mA VPP eVPPH Program

Verify Current Verify in Progress

IPP5 VPP Erase Verify 1, 2 5.0 5.0 mA VPP eVPPH

Current Erase Verify in Progress

VIL Input Low b0.5 0.8 V

Voltage

VIH Input High 0.7 VCC VCC a0.5 V

Voltage

VOL Output Low 0.45 V IOL e2.1 mA

Voltage VCC eVCC Min

VOH1 Output High 0.85 VCC VIOH eb

2.5 mA,

Voltage VCC eVCC Min

VOH2 VCC b0.4 IOH eb

100 mA,

VCC eVCC Min

VID A9Intelligent 11.50 13.00 V

Identifier Voltage

IID VCC ID Current 1 10 30 mA A9eID

IID VPP ID Current 1 90 500 mAA

VPPL VPP during Read- 0.00 6.5 V NOTE: Erase/Programs

Only Operations are Inhibited when

VPP eVPPL

VPPH VPP during 11.40 12.60 V

Read/Write

Operations

VLKO VCC Erase/Write 2.5 V

Lock Voltage

CAPACITANCE(3) TAe25§C, f e1.0 MHz

Symbol Parameter Limits Unit Conditions

Min Max

CIN Address/Control Capacitance 8 pF VIN e0V

COUT Output Capacitance 12 pF VOUT e0V

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at VCC e5.0V, VPP e12.0V, Te25§C.

2. Not 100% tested: characterization data available.

3. Sampled, not 100% tested.

4. ‘‘Typicals’’ are not guaranteed, but are based on a limited number of samples from production lots.

A28F010

AC TESTING INPUT/OUTPUT WAVEFORM

290266–7

AC Testing: Inputs are driven at 2.4V for a logic ‘‘1’’ and 0.45V for

a logic ‘‘0’’. Testing measurements are made at 2.0V for a logic

‘‘1’’ and 0.8V for a logic ‘‘0’’. Rise/Fall time s10 ns.

AC TESTING LOAD CIRCUIT

290266–8

CLe100 pF

CLincludes Jig Capacitance

AC TEST CONDITIONS

Input Rise and Fall Times (10% to 90%)ÀÀÀÀÀÀ10 ns

Input Pulse Levels ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0.45V and 2.4V

Input Timing Reference Level ÀÀÀÀÀÀÀ0.8V and 2.0V

Output Timing Reference Level ÀÀÀÀÀÀ0.8V and 2.0V

AC CHARACTERISTICSÐRead-Only Operations(2)

Versions Notes 28F010-120 28F010-150 Unit

Symbol Characteristic Min Max Min Max

tAVAV/tRC Read Cycle Time 3 120 150 ns

tELQV/tCE Chip Enable Access Time 120 150 ns

tAVQV/tACC Address Access Time 120 150 ns

tGLQV/tOE Output Enable 50 55 ns

Access Time

tELQX/tLZ Chip Enable to 3 0 0 ns

Output in Low Z

tEHQZ Chip Disable to 3 55 55 ns

Output in High Z

tGLQX/tOLZ Output Enable to 3 0 0 ns

Output in Low Z

tGHQZ/tDF Output Disable to 4 30 35 ns

Output in High Z

tOH Output Hold from Address, 1, 3 0 0 ns

CEÝ,orOE

ÝChange

tWHGL Write Recovery Time 6 6 ms

before Read

NOTES:

1. Whichever occurs first.

2. Rise/Fall Time s10 ns.

3. Not 100% tested: characterization data available.

4. Guaranteed by design.

A28F010

Figure 6. AC Waveforms for Read Operations

290266–9

A28F010

AC CHARACTERISTICSÐWrite/Erase/Program Operations(1, 3)

Versions Notes 28F010-120 28F010-150 Unit

Symbol Characteristic Min Max Min Max

tAVAV/tWC Write Cycle Time 120 150 ns

tAVWL/tAS Address Set-Up Time 0 0 ns

tWLAX/tAH Address Hold Time 2 60 60 ns

tDVWH/tDS Data Set-up Time 50 50 ns

tWHDX/tDH Data Hold Time 10 10 ns

tWHGL Write Recovery Time before Read 6 6 ms

tGHWL Read Recovery Time before Write 0 0 ms

tELWL/tCS Chip Enable 2 20 20 ns

Set-Up Time before Write

tWHEH/tCH Chip Enable Hold Time 0 0 ns

tWLWH/tWP Write Pulse Width(2) 280 80 ns

ELEH Alternative Write(2) 280 80 ns

Pulse Width

tWHWL/tWPH Write Pulse Width High 20 20 ns

tWHWH1 Duration of Programming Operation 4 10 10 ms

tWHWH2 Duration of Erase Operation 4 9.5 9.5 ms

tVPEL VPP Set-Up 1.0 1.0 ms

Time to Chip Enable Low

NOTES:

1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Char-

acteristics for Read-Only Operations.

2. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In

systems where Chip-Enable defines the write pulse width (within a longer Write-Enable timing waveform) all set-up, hold, and

inactive Write-Enable times should be measured relative to the Chip-Enable waveform.

3. Rise/Fall time s10 ns.

4. The internal stop timer terminates the programming/erase operations, thereby eliminating the need for a maximum speci-

fication.

ERASE AND PROGRAMMING PERFORMANCE

Parameter Notes Limits Unit Comments

Min Typ Max

Chip Erase Time 1, 3, 4, 6 1 60 Sec Excludes 00H Programming

Prior to Erasure

Chip Program Time 1, 2, 4 2 12.5 Sec Excludes System-Level Overhead

Erase/Program Cycles 1, 5 1,000 100,000 Cycles

NOTES:

1. ‘‘Typicals’’ are not guaranteed, but based on a limited number of samples taken from production lots. Data taken at

Te25§C, VPP e12.0V, VCC e5.0V.

2. Minimum byte programming time excluding system overhead is 16 msec (10 msec program a6msec write recovery),

while maximum is 400 msec/byte (16 msec x 25 loops allowed by algorithm). Max chip programming time is specified lower

than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case

byte.

3. Excludes 00H programming prior to erasure.

4. Excludes system-level overhead.

5. Refer to RR-60 ‘‘ETOX Flash Memory Reliability Data Summary’’ for typical cycling data and failure rate calculations.

6. Maximum erase specification is determined by algorithmic limit and accounts for cumulative effect of erasure at

Teb

40§C, 1,000 cycles, VPP e11.4V, VCC e4.5V.

A28F010

290266–17

Figure 7. 28F010 Typical Programming Capability

See Note 1, Page 18.

290266–18

Figure 8. 28F010 Typical Program Time at 12V

A28F010

290266–19

Figure 9. 28F010 Typical Erase Capability

See Note 1, Page 18.

290266–20

Figure 10. 28F010 Typical Erase Time at 12V

A28F010

Figure 11. AC Waveforms for Programming Operations

Alternative Write Timing

290266–14

A28F010

Figure 12. AC Waveforms for Erase Operations

290266–15

A28F010

Ordering Information

290266–16

Valid Combinations:

AP28F010-120

AP28F010-150

AN28F010-120

AN28F010-150

ADDITIONAL INFORMATION Order Number

ER-20, ‘‘ETOXTM II Flash Memory Technology’’ 294005

ER-24, ‘‘Intel Flash Memory’’ 294008

RR-60, ‘‘ETOXTM Flash Memory Reliability Data Summary’’ 293002

AP-316, ‘‘Using Flash Memory for In-System Reprogrammable 292046

Nonvolatile Storage’’

AP-325, ‘‘Guide to Flash Memory Reprogramming’’ 292059

REVISION HISTORY

Number Description

003 Changed Erase/Program Cycles to 1,000 minimum

004 Added 120 ns Characteristics