Always order by complete part number, e.g., A3935KLQ .
Data Sheet
26301.102a
3-PHASE POWER MOSFET CONTROLLER
— For Automotive Applications
3935
The A3935 is designed specifically for automotive applications that
require high-power motors. Each provides six high-current gate drive
outputs capable of driving a wide range of n-channel power MOSFETs.
A requirement of automotive systems is steady operation over a
varying battery input range. The A3935 integrates a pulse-frequency
modulated boost converter to create a constant supply voltage for
driving the external MOSFETs. Bootstrap capacitors are utilized to
provide the above battery supply voltage required for n-channel FETs.
Direct control of each gate output is possible via six TTL-compat-
ible inputs. A differential amplifier is integrated to allow accurate
measurement of the current in the three-phase bridge.
Diagnostic outputs can be continuously monitored to protect the
driver from short-to-battery, short-to-supply, bridge-open, and battery
under/overvoltage conditions. Additional protection features include
dead-time, VDD undervoltage, and thermal shutdown.
The A3935 is supplied in a choice of three packages, a 44-lead
PLCC with copper batwing tabs (suffix ED), a 48-lead low profile QFP
with exposed thermal pad (suffix JP), and a 36-lead 0.8 mm pitch SOIC
(suffix LQ).
FEATURES
!!
!!
!Drives wide range of n-channel MOSFETs in 3-phase bridges
!!
!!
!PFM boost converter for use with low-voltage battery supplies
!!
!!
!Internal LDO regulator for gate-driver supply
!!
!!
!Bootstrap circuits for high-side gate drivers
!!
!!
!Current monitor output
!!
!!
!Adjustable battery overvoltage detection.
!!
!!
!Diagnostic outputs
!Motor lead short-to-battery, short-to-ground, and
bridge-open protection
!Undervoltage protection
!!
!!
!-40 °C to +150 °C, TJ operation
!!
!!
!Thermal shutdown
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltages, VBAT, VDRAIN,
VBOOST, BOOSTD ... -0.6 V to 40 V
Output Voltage Ranges,
GHA/GHB/GHC, VGHX .. -4 V to 55 V
SA/SB/SC, VSX ............... -4 V to 40 V
GLA/GLB/GLC, VGLX.... -4 V to 16 V
CA/CB/CC, VCX .......... -0.6 V to 55 V
Sense Circuit Voltages,
CSP,CSN, LSS............... -4 V to 6.5 V
Logic Supply Voltage,
VDD ........................... -0.3 V to +6.5 V
Logic Input/Outputs and OVSET, BOOSTS,
CSOUT, VDSTH ......... -0.3 V to 6.5 V
Operating Temperature Range,
TA........................... -40°C to +135°C
Junction Temperature, TJ........... +150°C
Storage Temperature Range,
TS........................... -55°C to +150°C
* Fault conditions that produce excessive
junction temperature will activate device
thermal shutdown circuitry. These conditions
can be tolerated, but should be avoided.
Package ED, 44-Pin PLCC
Package JP, 48-Pin LQFP
Package LQ, 36-Pin SOIC
3935
THREE-PHASE POWER
MOSFET CONTROLLER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
2
Functional Block Diagram
Copyright © 2003 Allegro MicroSystems, Inc.
See pages 8 and 9 for terminal assignments and descriptions.
3935
THREE-PHASE POWER
MOSFET CONTROLLER
www.allegromicro.com
3
* Measured on “High-K” multi-layer PWB per JEDEC Standard JESD51-7.
† Measured on typical two-sided PWB with power tabs (terminals 1, 2, 11, 12, 22, 23, 34, and 35) connected to copper foil with an
area of 3.8 square inches (2452 mm2) on each side. See Application Note 29501.5, Improving Batwing Power Dissipation, for
additional information.
A3935KLQ (SOIC)A3935KED (PLCC)
3935
THREE-PHASE POWER
MOSFET CONTROLLER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
4
ELECTRICAL CHARACTERISTICS: unless otherwise noted at TJ = -40°C to +150°C, VBAT = 7 V to 16 V,
VDD = 4.75 V to 5.25 V, ENABLE = 22.5 kHz, 50% Duty Cycle, Two Phases Active.
Limits
Characteristics Symbol Conditions Min Typ Max Units
Power Supply
VDD Supply Current IDD All logic inputs = 0 V – – 7.0 mA
VBAT Supply Current IBAT All logic inputs = 0 V – – 3.0 mA
Battery Voltage Operating Range VBAT 7.0 – 40 V
Bootstrap Diode Forward Voltage VDBOOT IDBOOT = -Icx = 10 mA, VDBOOT = VREG – VCX 0.8 – 2.0 V
IDBOOT = -Icx = 100 mA 1.5 – 2. 3 V
Bootstrap Diode Resistance rDBOOT rD(100 mA) = [VD(150 mA) – VD(50 mA)]/100 mA 2.5 – 7. 5 Ω
Bootstrap Diode Current Limit IDM 3 V < [VREG – VCX] < 12 V -150 – -1150 mA
Bootstrap Quiescent Current ICX VCX = 40 V, GHx = ON 10 – 30 µA
Bootstrap Refresh Time trefresh VSX = low to guarantee ∆V = +0.5 V refresh of – – 2.0 µs
0.47 µF Boot Cap at Vcx – Vsx = +10 V
VREG Output Voltage 1VREG VBAT = 7 V to 40 V, VBOOST from Boost Reg 12.7 – 14 V
VREG Dropout Voltage 2VREGDO VREGDO = Vboost – Vreg, Ireg = 40 mA – 0.9 – V
Gate Drive Avg. Supply Current IREG No external dc load at VREG, CREG = 10 µF – – 40 mA
VREG Input Bias Current IREGBIAS Current into VBOOST, ENABLE = 0 – – 4.0 mA
Boost Supply
VBOOST Output Voltage Limit VBOOSTM VBAT = 7 V 14.9 – 16.3 V
VBOOST Output Volt. Limit Hyst. ∆VBOOSTM 35 – 180 mV
Boost Switch ON Resistance rDS(on) IBOOSTD < 300 mA – 1.4 3.3 Ω
Max. Boost Switch Current IBOOSTSW – – 300 mA
Boost Current Limit Threshold Volt.
VBI(th) Increasing VBOOSTS 0.45 – 0.55 V
OFF Time toff 3.0 – 8.0 µs
Blanking Time tblank 100 – 220 ns
NOTES: Typical Data and Typical Characteristics are for design information only.
Negative current is defined as coming out of (sourcing) the specified device terminal.
1. For VBOOSTM < VBOOST < 40 V power dissipation in the VREG LDO increases. Observe TJ < 150 °C limit.
2. With VBOOST decreasing Dropout Voltage measured at VREG = VREGref – 200 mV where VREG(ref) = VREG at VBOOST = 16 V.
Continued next page …
3935
THREE-PHASE POWER
MOSFET CONTROLLER
www.allegromicro.com
5
ELECTRICAL CHARACTERISTICS: unless otherwise noted at TJ = -40°C to +150°C, VBAT = 7 V to 16 V,
VDD = 4.75 V to 5.25 V, ENABLE = 22.5 kHz, 50% Duty Cycle, Two Phases Active.
Limits
Characteristics Symbol Conditions Min Typ Max Units
Control Logic
Logic Input Voltages VI(1) Minimum high level input for logical “one” 2.0 – – V
VI(0) Maximum low level input for logical “zero” – – 0.8 V
Logic Input Currents II(1) VI = VDD – – 500 µA
II(0) VI = 0.8 V 50 – – µA
Input Hysteresis Vhys 100 – 300 mV
Logic Output High Voltage VO(H) IO(H) = -800 uA VDD-0.8 – – V
Logic Output Low Voltage VI(L) IO(L) = 1.6 mA – – 0.4 V
Gate Drives, GHx ( internal SOURCE or upper switch stages)
Output High Voltage VDSL(H) GHx: IxU = -10 mA, Vsx = 0 VREG-2.26 – VREG V
GLx: IxU = -10 mA, Vlss = 0 VREG-0.26 – VREG V
Source Current (pulsed) IxU VSDU = 10 V, TJ = 25 °C – 800 – mA
VSDU = 10 V, TJ = 135 °C 400 – – mA
Source ON Resistance rSDU(on) IxU = -150 mA, Tj = 25 °C 4.0 – 10 Ω
IxU = -150 mA, TJ = 135 °C 7.0 – 15 Ω
Gate Drives, GLx ( internal SINK or lower switch stages)
Sink Current (pulsed) IxL VDSL = 10 V, TJ = 25 °C – 850 – mA
VDSL = 10 V, TJ = 135 °C 550 – – mA
Sink ON Resistance rDSL(on) IxL = +150 mA, TJ = 25 °C 1.8 – 6. 0 Ω
IxL = +150 mA, TJ = 135 °C 3.0 – 7.5 Ω
Gate Drives, GHx, GLx (General)
Propagation Delay, Logic only tpd Logic input to unloaded GHx, GLx – – 150 ns
Output Skew Time tsk(o) Grouped by edge, phase-to-phase – – 50 ns
Dead Time tdead Between GHx, GLx transitions of same phase 75 – 180 n s
(Shoot-Through Prevention)
NOTES: Typical Data and Typical Characteristics are for design information only.
Negative current is defined as coming out of (sourcing) the specified device terminal.
For GHX: VSDU = VCX – VGHX, VDSL = VGHX – VSX, VDSL(H) = VCX – VSDU – VSX.
For GLX: VSDU = VREG – VGLX, VDSL = VGLX – VLSS, VDSL(H) = VREG – VSDU – VLSS.
3935
THREE-PHASE POWER
MOSFET CONTROLLER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6
ELECTRICAL CHARACTERISTICS: unless otherwise noted at TJ = -40°C to +150°C, VBAT = 7 V to 16 V,
VDD = 4.75 V to 5.25 V, ENABLE = 22.5 kHz, 50% Duty Cycle, Two Phases Active.
Limits
Characteristics Symbol Conditions Min Typ Max Units
Sense Amplifier
Input Bias Current Ibias CSP = CSN = 0 V -180 – -360 µA
Input Offset Current IIO CSP = CSN = 0 V – – ±35 µA
Input Resistance riCSP with respect to GND – 80 – kΩ
CSN with respect to GND – 4.0 – kΩ
Diff. Input Operating Voltage VID VID = CSP – CSN, -1.3V < CSP,N < 4V – – ±200 mV
Output Offset Voltage VOO CSP = CSN = 0 V 77 250 450 mV
Output Offset Voltage Drift ∆VOO CSP = CSN = 0 V – 100 – µV/°C
Input Com-Mode Oper. Range VIC CSP = CSN -1.5 – 4.0 V
Voltage Gain AVVID = 40 mV to 200 mV 18.6 19.2 19.8 V/V
Low Output Voltage Error EvVid = 0 to 40 mV, Vo = (19.2 x VID) + Vo + Ev– – ±25 mV
DC Common-Mode Attenuation AVC CSP = CSN = 200 mV 28 – – dB
Output Resistance roVCSOUT = 2.0 V – 8.0 – Ω
Output Dynamic Range VCSOUT ICSOUT = -100 µA at top rail, 100 µA at bottom rail 0.075 – VDD-0.25 V
Output Current, Sink Isink VCSOUT = 2.5 V 20 – – mA
Output Current, Source Isource VCSOUT = 2.5 V -1.0 – – mA
VDD Supply Ripple Rejection PSRR CSP = CSN = GND, freq. = 0 to 1 MHz 20 – – dB
VREG Supply Ripple Rejection PSRR CSP = CSN = GND, freq. = 0 to 300 kHz 45 – – dB
Small Signal 3-dB Bandwidth f3db 10 mV input – 1.6 – MHz
AC Common-Mode Attenuation Avc Vcm = 250 mV/pp, freq. = 0 to 800 kHz 26 – – dB
Output Slew Rate SR 200 mV step input, meas. 10/90% points 10 – – V/µs
(positive or negative)
NOTES: Typical Data and Typical Characteristics are for design information only.
Negative current is defined as coming out of (sourcing) the specified device terminal.
3935
THREE-PHASE POWER
MOSFET CONTROLLER
www.allegromicro.com
7
ELECTRICAL CHARACTERISTICS: unless otherwise noted at TJ = -40°C to +150°C, VBAT = 7 V to 16 V,
VDD = 4.75 V to 5.25 V, ENABLE = 22.5 kHz, 50% Duty Cycle, Two Phases Active.
Limits
Characteristics Symbol Conditions Min Typ Max Units
Fault Logic
VDD Undervoltage VDD(uv) Decreasing VDD 3.8 – 4.3 V
VDD Undervoltage Hysteresis ∆VDD(uv) VDD(recovery) - VDD(uv) 100 – 300 mV
OVSET Operating Volt. Range VSET(ov) 0–V
DD V
OVSET Calibrated Volt. Range VSET(ov) 0 – 2.5 V
OVSET Input Current Range ISET(ov) -1.0 – +1.0 µA
VBAT Overvoltage Range VBAT(ov) 0 V < VSET(ov) < 2.5 V 19.4 – 40 V
VBAT Overvoltage VBAT(ov) Increasing VBAT, VSET(ov) = 0 V 19.4 22.4 25.4 V
VBAT Overvoltage Hysteresis ∆VBAT(ov) Percent of VBAT(ov) value set by VSET(ov) 9.0 – 15 %
VBAT Overvoltage Gain Constant
KBAT(ov) VBAT(ov) = (KBAT(ov) x VSET(ov)) + VBAT(ov) [0] – 12 – V/V
VBAT Undervoltage VBAT(uv) Decreasing VBAT 5.0 5.25 5.5 V
VBAT Undervoltage Hysteresis ∆VBAT(uv) Percent of VBAT(uv) 8.0 – 12 %
VREG Undervoltage VREG(uv) Decreasing VREG 9.9 – 11.1 V
VDSTH Input Range VDSTH 0.5 – 3.0 V
VDSTH Input Current IDSTH VDSTH > 0.8 V 40 – 100 µA
Short-to-Ground Threshold VSTG(th) With a high-side driver “on”, as VSX decreases, VDSTH-0.3 – VDSTH+0.2 V
VDRAIN - VSX > VSTG causes a fault
Short-to-Battery Threshold VSTB(th) With a low-side driver “on”, as VSX increases, VDSTH-0.3 – VDSTH+0.2 V
VSX - VLSS > VSTB causes a fault
VDRAIN /Open Bridge Oper. Range VDRAIN 7 V < VBAT < 40 V -0.3 – VBAT+2.0 V
VDRAIN /Open Bridge Current IVDRAIN 7 V < VBAT < 40 V 0 – 1.0 mA
V
DRAIN
/Open Bridge Threshold Volt.
VBDGO(th) If VDRAIN < VBDGOTH then a bridge fault occurs 1. 0 – 3.0 V
Thermal Shutdown Temp. TJ160 170 180 °C
Thermal Shutdown Hysteresis ∆TJ7.0 10 13 °C
NOTES: Typical Data and Typical Characteristics are for design information only.
Negative current is defined as coming out of (sourcing) the specified device terminal.
3935
THREE-PHASE POWER
MOSFET CONTROLLER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8
Terminal Functions
A3935KED A3935KJP A3935KLQ
Terminal Name Function (PLCC) (QLFP) (SOIC)
CSP Current-sense input, positive-side 31 19 1
VDSTH DC input, drain-to-source monitor threshold voltage 32 20 2
LSS Gate-drive source return, low-side 33 21 3
GLC Gate-drive C output, low-side 36 22 4
SC Load phase C input 37 26 5
GHC Gate-drive C output, high-side 38 27 6
CC Bootstrap capacitor C 39 2 8 7
GLB Gate-drive B output, low-side 40 29 8
SB Load phase B input 41 30 9
GHB Gate-drive B output, high-side 42 31 10
CB Bootstrap capacitor B 43 32 11
GLA Gate-drive A output, low-side 44 33 1 2
SA Load phase A input 3 34 13
GHA Gate-drive A output, high-side 4 38 14
CA Bootstrap capacitor A 5 39 15
VREG Gate drive supply, positive 6 40 16
VDRAIN Kelvin connection to MOSFET high-side drains 7 41 17
VBOOST Boost supply output 8 42 18
BOOSTS Boost switch, source 9 43 19
BOOSTD Boost switch, drain 10 44 20
VBAT Battery supply, positive 13 46 2 2
UVFLT VBAT undervoltage fault output 14 3 23
OVFLT VBAT overvoltage fault output 15 4 24
FAULT Active-low fault output, primary 16 5 25
ALO Gate control input A, low-side 17 6 26
AHI Gate control input A, high-side 18 7 27
BHI Gate control input B, high-side 19 8 28
BLO Gate control input B, low-side 20 9 29
CLO Gate control input C, low-side 21 10 3 0
CHI Gate control input C, high-side 24 11 3 1
ENABLE Gate output enable 25 1 2 3 2
OVSET DC input, overvoltage threshold setting for VBAT 2 6 15 33
NC Not connected, no external connection allowed 27 1,2,13,14,23,24, –
25,35,36,37,47,48
CSOUT Current-sense amplifier output 28 16 3 4
VDD Logic supply, nominally +5 V 29 1 7 35
CSN Current-sense input, negative-side 30 18 3 6
GND Ground, dc supply returns, negative, and (for ED package) 1, 2, 11, 12, 45 21
heat sink tab
22, 23, 34, 35
3935
THREE-PHASE POWER
MOSFET CONTROLLER
www.allegromicro.com
9
Terminal Descriptions
AHI/BHI/CHI. Direct control of high-side gate outputs GHA/
GHB/GHC. Logic “1” drives the gate “on”. Logic ”0” pulls the
gate down, turning off the external power MOSFET. Internally
pulled down when terminal is open.
ALO/BLO/CLO. Direct control of low-side gate outputs GLA/
GLB/GLC. Logic “1” drives the gate “on”. Logic ”0” pulls the
gate down, turning off the external power MOSFET. Internally
pulled down when terminal is open.
BOOSTD. Boost converter switch drain connection.
BOOSTS. Boost converter switch source connection.
CA/CB/CC. High-side connection for bootstrap capacitor,
positive supply for high-side gate drive. The bootstrap capacitor
is charged to VREG when the output Sx terminal is low. When
the output swings high, the voltage on this terminal rises with
the output to provide the boosted gate voltage needed for n-
channel power MOSFETs.
CSN. Input for current-sense, differential amplifier, inverting,
negative side. Kelvin connection for ground side of current-
sense resistor.
CSOUT. Amplifier output voltage proportional to current
sensed across an external low-value resistor placed in the
ground-side of the power FET bridge.
CSP. Input for current-sense differential amplifier, non-
inverting, positive side. Connected to positive side of sense
resistor.
ENABLE. Logic “0” disables the gate control signals and
switches off all the gate drivers “low” causing a “coast”. Can be
used in conjunction with the gate inputs to PWM the load
current. Internally pulled down when terminal is open.
FAULT. Diagnostic logic output signal, when “low” indicates
that one or more fault condition have occurred.
GHA/GHB/GHC. High-side gate-drive outputs for n-channel
MOSFET drivers. External series gate resistors can control slew
rate seen at the power driver gate; thereby, controlling the di/dt
and dv/dt of Sx outputs.
GLA/GLB/GLC. Low-side gate drive outputs for external, n-
channel MOSFET drivers. External series gate resistors can
control slew rate.
GND. Ground or negative side of VDD and VBAT supplies.
LSS. Low-side gate driver returns. Connects to the common
sources in the low-side of the power MOSFET bridge.
OVFLT. Logic “1” means that the VBAT exceeded the VBAT
overvoltage trip point set by OVSET level. It will recover after
a hysteresis below that maximum value. Normally has a high-
impedance state.
OVSET. A positive, dc level that controls the VBAT overvolt-
age trip point. Usually, provided from precision resistor divider
network between VDD and GND, but can be held grounded for a
preset value. When terminal is open, sets unspecified but high
overvoltage trip point.
SA/SB/SC. Directly connected to the motor terminals, these
terminals sense the voltages switched across the load and are
connected to the negative side of the bootstrap capacitors. Also,
are the negative supply connection for the floating, high-side
drivers.
UVFLT. Logic “1” means that VBAT is below its minimum
value and will recover after a hysteresis above that minimum
value. Has a high-impedance state. [If UVFLT and OVFLT are
both in high-impedance state; then, at least, a thermal shutdown
or VDD undervoltage has occurred.]
VBAT. Battery voltage, positive input and is usually connected
to the motor voltage supply.
VBOOST. Boost converter output, nominally 16 V, is also
input to regulator for VREG. Has internal boost current and
boost voltage control loops. In high-voltage systems is approxi-
mately one diode drop below VBAT.
VDD. Logic supply, nominally +5 V.
VDRAIN. Kelvin connection for drain-to-source voltage
monitor and is connected to high-side drains of MOSFET
bridge. High impedance when terminal is open and registers as
a short-to-ground fault on all motor phases.
VDSTH. A positive, dc level that sets the drain-to-source
monitor threshold voltage. Internally pulled down when
terminal is open.
VREG. High-side, gate-driver supply, nominally, 13.5 V. Has
low-voltage dropout (LDO) feature.
3935
THREE-PHASE POWER
MOSFET CONTROLLER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
10
Functional Description
Motor Lead Protection. A fault detection circuit monitors
the voltage across the drain to source of the external MOSFETs.
A fault is asserted “low” on the output terminal, FAULT, if the
drain-to-source voltage of any MOSFET that is instructed to turn
on is greater than the voltage applied to the VDSTH input terminal.
When a high-side switch is turned on, the voltage from VDRAIN to
the appropriate motor phase output, VSX, is examined. If the
motor lead is shorted to ground before the high side is turned on,
the measured voltage will exceed the threshold and the FAULT
terminal will go “low”. Similarly, when a low-side MOSFET is
turned on, the differential voltage between the motor phase
(drain) and the LSS terminal (source) is monitored. VDSTH is set
by a resistor divider to VDD.
The VDRAIN is intended to be a Kelvin connection for the high-
side, drain-source monitor circuit. Voltage drops across the
power bus are eliminated by connecting an isolated PCB trace
from the VDRAIN terminal to the drain of the MOSFET bridge.
This allows improved accuracy in setting the VDSTH threshold
voltage. The low-side, drain-source monitor uses the LSS
terminal, rather than VDRAIN, in comparing against VDSTH.
The A3935 merely reports these motor faults.
Fault Outputs. Transient faults on any of the fault outputs are
to be expected during switching and will not disable the gate
drive outputs. External circuitry or controller logic must
determine if the faults represent a hazardous condition.
FAULT. This terminal will go active “low” when any of the
following conditions occur:
VBAT overvoltage,
VBAT undervoltage,
VREG undervoltage,
Motor lead short-to-ground,
Motor lead short-to-supply (or battery),
Bridge (or VDRAIN) open,
VDD undervoltage, or
Thermal shutdown.
OVFLT. Asserts “high” when a VBAT overvoltage fault occurs
and resets “low” after a recovery hysteresis. It has a high-
impedance state when a thermal shutdown or VDD undervoltage
occurs. The voltage at the OVSET terminal, VOVSET, controls
the VBAT overvoltage set point VBAT(ov), i.e.,
VBAT(ov) = (KBAT(ov) x VSET(ov)) + VBAT(ov)(0),
where KBAT(ov) is the gain (12) and VBAT(ov)(0) is the value of
VBAT(ov) when VSET(ov) is zero (~22.4). For valid formula, all
variables must be in range and below maximum operating
specification.
UVFLT. Asserts “high” when a VBAT undervoltage fault occurs
and resets “low” after a recovery hysteresis. It has a high-
impedance state when a thermal shutdown or VDD undervoltage
occurs. OVFLT and UVFLT are mutually exclusive by defini-
tion.
Current Sensing. A current-sense amplifier is provided to
allow system monitoring of the load current. The differential
amplifier inputs are intended to be Kelvin connected across a
low-value sense resistor or current shunt. The output voltage is
represented by:
VCSOUT = ( ILOAD x AV x RS) + VOS
where VOS is the output voltage calibrated at zero load current
and AV is the differential amplifier gain of about 19.2.
Shutdown. If a fault occurs because of excessive junction
temperature or undervoltage on VDD or VBAT, all gate driver
outputs are driven “low” until the fault condition is removed. In
addition, the boost supply switch and the VREG are turned “off”
until those undervoltages and junction temperatures recover.
Boost Supply. VBOOST is controlled by an inner current-
control loop, and by an outer voltage-feedback loop. The
current-control loop turns “off” the boost switch for 5 µs
whenever the voltage across the boost current-sense resistor
exceeds 500 mV. A diode reverse-recovery current flows
through the sense resistor whenever the boost switch turns “on”,
which could turn it “off” again if not for the “blanking time”
circuit. Adjustment of this external sense resistor determines the
maximum current in the inductor. Whenever VBOOST exceeds the
predefined threshold, nominally 16 V, the boost switch is
inhibited.
3935
THREE-PHASE POWER
MOSFET CONTROLLER
www.allegromicro.com
11
Functional Description (cont’d)
Input Logic
ENABLE xLO xHI GLx GHx Mode of Operation
0 X X 0 0 All gate drive outputs low
1 0000Both gate drive outputs low
1 0101High side on
1 1010Low side on
1 1100XOR circuitry prevents shoot-through
Fault Responses
ENABLE Boost VREG
Fault Mode Input FAULT OVFLT UVFLT Reg. Reg. GHx GLx
No Fault X 1 0 0 ON ON ""
Short-to-Battery 1#0 0 0 ON ON ""
Short-to-Ground 1$0 0 0 ON ON ""
Bridge (VDRAIN) Fault 1%0 0 0 ON ON ""
VREG Undervoltage X 0 0 0 ON ON ""
VBAT Overvoltage X 0 1 0 OFF&ON ""
VBAT Undervoltage'X 0 0 1 OFF OFF 0 0
VDD Undervoltage'X 0 Z Z OFF OFF 0 0
Thermal Shutdown'X 0 Z Z OFF OFF 0 0
NOTES: x = “Little x ”indicates A, B, or C phase.
X = “Capital X “ indicates a “don’t care”.
Z = High-impedance state.
" = Depends on xLO input, xHI input, and ENABLE. See Input Logic table.
# = Short-to-battery can only be detected when the corresponding GLx = 1. This fault is not detected when ENABLE = 0.
$ = Short-to-ground can only be detected when the corresponding GHx = 1. This fault is not detected when ENABLE = 0.
% = Bridge fault appears as a short-to-ground fault on all motor phases. This fault is not detected when ENABLE = 0.
& = Off, only because VBOOST ≈ VBAT is above the voltage threshold of the regulator’s voltage control loop.
' = These faults are not only reported but action is taken by the internal logic to protect the A3935 and the system.
3935
THREE-PHASE POWER
MOSFET CONTROLLER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
12
NC
42
43
44
45
46
47
NC 48
40
41
CA
VREG
VDRAIN
VBOOST
BOOSTS
BOOSTD
GND
VBAT
37
NC
GHA
NC
20
19
18
17
16
21
22 GLC
LSS
VDSTH
CSP
CSN
VDD
CSOUT
23
24
38
39
14
13 NC
NC
NC
OVSET
15
NC
31
30
29
28
27
32
33 GLA
CB
GHB
SB
GLB
CC
GHC
34
35
25
26
NC
36 NC
SA
SC
ENABLE
11
10
9
8
7
6
5
12
4
3
2
1
OVFLT
FAULT
ALO
AHI
BHI
BLO
CLO
CHI
NC
UVFLT
NC
Package JP, 48-Pin LQFP
Package ED, 44-Pin PLCC
Package LQ, 36-Pin SOIC
ALO
12
13
14
15
16
17
10
11
9
BOOSTS
BOOSTD
GND
GND
VBAT
UVFLT
OVFLT
FAULT
8
7
VDRAIN
VBOOST
CSOUT
27
26
25
24
23
22
21
28
20
19
18
BLO
CLO
GND
GND
CHI
ENABLE
OVSET
NC
AHI
BHI
VDD
35
34
33
32
31
36
37 SC
GLC
GND
GND
LSS
VDSTH
CSP
38
39
29
CC
GHC
CSN
GLB
2
1
44
43
42
3
4GHA
SA
GND
GND
GLA
CB
GHB
5
6
40
41
VREG
CA
SB
30
CB
GLA
SA
GHA
CA
VREG
VDRAIN
VBOOST
ALO
FAULT
OVFLT
UVFLT
VBAT
GND
BOOSTD
BOOSTS
5
6
7
8
9
10
11
12
13
14
15
16
17
18
4
3
32
31
30
29
28
33
34
LSS
GLC
SC
GHC
CC
GLB
SB
GHB
CSOUT1
OVSET
ENABLE
CHI
CLO
BLO
BHI
2
1
35
36
23
22
21
20
19
24
25
26
27
CSP
VDSTH
CSN
VDD
AHI
3935
THREE-PHASE POWER
MOSFET CONTROLLER
www.allegromicro.com
13
A3935KED (PLCC)
Dimensions in Millimeters
(controlling dimensions)
Dimensions in Inches
(for reference only)
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Webbed lead frame. Terminals 1, 2, 11, 12, 22, 23, 34, and 35 are internally one piece.
4. Supplied in standard sticks/tubes of 27 devices or add “TR” to part number for tape and reel.
3935
THREE-PHASE POWER
MOSFET CONTROLLER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
14
Exposed thermal pad (bottom surface)
A
A
.20
.09 0.008
0.004
7º
0º
.75
.45 0.030
0.018
.15
.05 0.006
0.002
.27
.17 0.011
0.007
1
REF
0.039
5
BSC
0.197
.50
BSC .020
.25
BSC 0.010
7
BSC
0.276
9
BSC
0.354
1.60
1.40 0.063
0.055
21
48
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
Gauge Plane
Seating Plane
A3935KJP (LQFP)
3935
THREE-PHASE POWER
MOSFET CONTROLLER
www.allegromicro.com
15
A3935KLQ (SOIC)
Dimensions in Millimeters
(controlling dimensions)
Dimensions in Inches
(for reference only)
NOTES: 1. Lead spacing tolerance is non-cumulative.
2. Exact body and lead configuration at vendor’s option within limits shown.
3. Supplied in standard sticks/tubes of 31 devices or add “TR” to part number for tape and reel.
3935
THREE-PHASE POWER
MOSFET CONTROLLER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
16
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be required
to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.
