Datasheet PD48576109 PD48576118 R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 576M-BIT Low Latency DRAM Separate I/O Description The PD48576109 is a 67,108,864-word by 9 bit and the PD48576118 is a 33,554,432 word by 18 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell. The PD48576109 and PD48576118 integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (CK and CK#) are latched on the positive edge of CK and CK#. These products are suitable for application which require synchronous operation, high speed, low voltage, high density and wide bit configuration. Specification Features * Density: 576M bit * SRAM-type interface * Organization * Double-data-rate architecture - Separate I/O: 8M words x 9 bits x 8 banks 4M words x 18 bits x 8 banks * Operating frequency: 533 / 400 / 300 MHz * Interface: HSTL I/O * Package: 144-pin TAPE FBGA - Package size: 18.5 x 11 - Leaded and Lead free * Power supply - 2.5 V VEXT - 1.8 V VDD - 1.5 V or 1.8 V VDDQ * Refresh command - Auto Refresh - 16K cycle / 32 ms for each bank - 128K cycle / 32 ms for total * Operating case temperature : Tc = 0 to 95C R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 * PLL circuitry * Cycle time: 1.875 ns @ tRC = 15 ns 2.5 ns @ tRC = 15 ns 2.5 ns @ tRC = 20 ns 3.3 ns @ tRC = 20 ns * Non-multiplexed addresses * Multiplexing option is available. * Data mask for WRITE commands * Differential input clocks (CK and CK#) * Differential input data clocks (DK and DK#) * Data valid signal (QVLD) * Programmable burst length: 2 / 4 / 8 (x9 / x18) * User programmable impedance output (25 - 60 ) * JTAG boundary scan Page 1 of 51 PD48576109, PD48576118 Ordering Information Part number Cycle Clock Time Frequency Random Organization Core Supply Core Supply Output Supply Cycle ns MHz ns PD48576109FF-E18-DW1-A 1.875 533 15 PD48576109FF-E24-DW1-A 2.5 400 15 PD48576109FF-E25-DW1-A 2.5 400 20 PD48576109FF-E33-DW1-A 3.3 300 20 PD48576118FF-E18-DW1-A 1.875 533 15 PD48576118FF-E24-DW1-A 2.5 400 15 PD48576118FF-E25-DW1-A 2.5 400 20 PD48576118FF-E33-DW1-A 3.3 300 20 PD48576109FF-E18-DW1 1.875 533 15 PD48576109FF-E24-DW1 2.5 400 15 PD48576109FF-E25-DW1 2.5 400 20 PD48576109FF-E33-DW1 3.3 300 20 PD48576118FF-E18-DW1 1.875 533 15 PD48576118FF-E24-DW1 2.5 400 15 PD48576118FF-E25-DW1 2.5 400 20 PD48576118FF-E33-DW1 3.3 300 20 R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 (word x bit) 64 M x 9 Voltage Voltage Voltage (VEXT) (VDD) (VDDQ) V V V 2.5 + 0.13 1.8 0.1 1.5 0.1 144-pin or TAPE FBGA 1.8 0.1 (18.5 x 11) 2.5 - 0.12 32 M x 18 64 M x 9 Lead-free 2.5 + 0.13 2.5 - 0.12 32 M x 18 Package 1.8 0.1 1.5 0.1 144-pin or TAPE FBGA 1.8 0.1 (18.5 x 11) Lead Page 2 of 51 PD48576109, PD48576118 Pin Arrangement # indicates active LOW signal. 144-pin TAPE FBGA (18.5 x 11) (Top View) [Separate I/O x9] A B 1 2 3 4 VREF VSS VEXT VDD C VTT Note 1 D (A22) E A21 Note 3 DNU Note 3 DNU Note 3 DNU Note 3 DNU Note 3 Note 3 DNU Note 3 DNU Note 3 DNU Note 3 DNU Note 3 5 6 7 8 9 10 11 12 VSS VSS VEXT TMS TCK VSSQ VSSQ Q0 D0 VDD VDDQ VDDQ Q1 D1 VTT VSSQ VSSQ QK0# QK0 VSS VDDQ VDDQ Q2 D2 A20 F A5 DNU DNU VSSQ VSSQ Q3 D3 QVLD G A8 A6 A7 VDD VDD A2 A1 A0 H BA2 A9 VSS VSS VSS VSS A4 A3 Note 2 Note 2 J NF NF VDD VDD VDD VDD BA0 CK K DK DK# VDD VDD VDD VDD BA1 CK# L REF# CS# VSS VSS VSS VSS A14 A13 M WE# A16 A17 VDD VDD A12 A11 A10 VSSQ VSSQ Q4 D4 A19 VDDQ VDDQ Q5 D5 DM VSSQ VSSQ Q6 D6 VSS VDDQ VDDQ Q7 D7 VTT N P R T A18 A15 VSS VTT Note 3 DNU Note 3 DNU Note 3 DNU Note 3 DNU Note 3 Note 3 DNU Note 3 DNU Note 3 DNU Note 3 DNU Note 3 U VDD DNU DNU VSSQ VSSQ Q8 D8 VDD V VREF ZQ VEXT VSS VSS VEXT TDO TDI Notes 1. Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal. This may optionally be connected to VSS, or left open. 2. No function. This signal is internally connected and has parasitic characteristics of a clock input signal. This may optionally be connected to VSS, or left open. 3. Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may optionally be connected to VSS. CK, CK# CS# WE# REF# A0-A21 A22 BA0-BA2 D0-D8 Q0-Q8 DK, DK# DM QK0, QK0# QVLD : Input clock : Chip select : WRITE command : Refresh command : Address inputs : Reserved for the future : Bank address input : Data input : Data output : Input data clock : Input data Mask : Output data clock : Data Valid R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 ZQ TMS TDI TCK TDO VREF VEXT VDD VDDQ VSS VSSQ VTT NF DNU : Output impedance matching : IEEE 1149.1 Test input : IEEE 1149.1 Test input : IEEE 1149.1 Clock input : IEEE 1149.1 Test output : HSTL input reference input : Power Supply : Power Supply : DQ Power Supply : Ground : DQ Ground : Power Supply : No function : Do not use Page 3 of 51 PD48576109, PD48576118 # indicates active LOW signal. 144-pin TAPE FBGA (18.5 x 11) (Top View) [Separate I/O x18] 1 2 3 4 A VREF VSS VEXT B VDD D4 C VTT Note 1 D (A22) Note 1 5 6 7 8 9 10 11 12 VSS VSS VEXT TMS TCK Q4 VSSQ VSSQ Q0 D0 VDD D5 Q5 VDDQ VDDQ Q1 D1 VTT D6 Q6 VSSQ VSSQ QK0# QK0 VSS E (A21) D7 Q7 VDDQ VDDQ Q2 D2 A20 F A5 D8 Q8 VSSQ VSSQ Q3 D3 QVLD G A8 A6 A7 VDD VDD A2 A1 A0 H BA2 A9 VSS VSS VSS VSS A4 A3 Note 2 Note 2 J NF NF VDD VDD VDD VDD BA0 CK K DK DK# VDD VDD VDD VDD BA1 CK# L REF# CS# VSS VSS VSS VSS A14 A13 M WE# A16 A17 VDD VDD A12 A11 A10 N A18 D14 Q14 VSSQ VSSQ Q9 D9 A19 P A15 D15 Q15 VDDQ VDDQ Q10 D10 DM R VSS QK1 QK1# VSSQ VSSQ Q11 D11 VSS T VTT D16 Q16 VDDQ VDDQ Q12 D12 VTT U VDD D17 Q17 VSSQ VSSQ Q13 D13 VDD V VREF ZQ VEXT VSS VSS VEXT TDO TDI Notes 1. Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal. This may optionally be connected to VSS, or left open. 2. No function. This signal is internally connected and has parasitic characteristics of a clock input signal. This may optionally be connected to VSS, or left open. CK, CK# CS# WE# REF# A0-A20 A21-A22 BA0-BA2 D0-D17 Q0-Q17 DK, DK# DM QK0-QK1,QK0#-QK1# QVLD R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 : Input clock : Chip select : WRITE command : Refresh command : Address inputs : Reserved for the future : Bank address input : Data input : Data output : Input data clock : Input data Mask : Output data clock : Data Valid ZQ TMS TDI TCK TDO VREF VEXT VDD VDDQ VSS VSSQ VTT NF : Output impedance matching : IEEE 1149.1 Test input : IEEE 1149.1 Test input : IEEE 1149.1 Clock input : IEEE 1149.1 Test output : HSTL input reference input : Power Supply : Power Supply : DQ Power Supply : Ground : DQ Ground : Power Supply : No function Page 4 of 51 PD48576109, PD48576118 Pin Description (1/2) Symbol CK, CK# Type Input Description Clock inputs: CK and CK# are differential clock inputs. This input clock pair registers address and control inputs on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK. CS# Input Chip select CS# enables the commands when CS# is LOW and disables them when CS# is HIGH. When the command is disabled, new commands are ignored, but internal operations continue. WE#, REF# Input WRITE command pin, Refresh command pin: WE#, REF# are sampled at the positive edge of CK, WE#, and REF# define (together with CS#) the command to be executed. A0-A21 Input Address inputs: A0-A21 define the row and column addresses for READ and WRITE operations. During a MODE REGISTER SET, the address inputs define the register settings. They are sampled at the rising edge of CK. In the x18 configuration, A21 is reserved for address expansion. This expansion address can be treated as address input, but it does not affect the operation of the device. A22 Input Reserved for future use: These signals should be tied to VSS or leave open. BA0-BA2 Input Bank address inputs; Select to which internal bank a command is being applied. D0-Dxx Input Data input: The D signals form the 18-bit input data bus. During WRITE commands, the data is referenced to both edges of DK. x 9 device uses D0 to D8. x18 device uses D0 to D17. Q0-Qxx Output Data output: The Q signals form the 18-bit output data bus. During READ commands, the data is referenced to both edges of QK. x 9 device uses Q0 to Q8. x18 device uses Q0 to Q17. QKx, QKx# Output Output data clocks: QKx and QKx# are opposite polarity, output data clocks. They are always free running and edgealigned with data output from the PD48576109/18. QKx# is ideally 180 degrees out of phase with QKx. For the x18 device, QK0 and QK0# are aligned with Q0-Q8. QK1 and QK1# are aligned with Q9- Q17. For the x9 device, QK0 and QK0# are aligned with Q0-Q8. DK, DK# Input Input data clock; DK and DK# are the differential input data clocks. All input data is referenced to both edges of DK. DK# is ideally 180 degrees out of phase with DK. In both x9 and x18 configurations, all Ds are referenced to DK and DK#. DM Input Input data mask; The DM signal is the input mask signal for WRITE data. Input data is masked when DM is sampled HIGH along with the WRITE input data. DM is sampled on both edges of DK. The signal should be VSS if not used. QVLD Output Data valid; The QVLD indicates valid output data. QVLD is edge-aligned with QKx and QKx#. R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 5 of 51 PD48576109, PD48576118 (2/2) Symbol ZQ Type Description Input External impedance [25 - 60 ]; /Output This signal is used to tune the device outputs to the system data bus impedance. Q output impedance is set to 0.2 x RQ, where RQ is a resistor from this signal to VSS. Connecting ZQ to VSS invokes the minimum impedance mode. Connecting ZQ to VDDQ invokes the maximum impedance mode. Refer to Figure 2-5. Mode Register Bit Map to activate this function. TMS , TDI Input JTAG function pins: IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used in the circuit TCK Input JTAG function pin; IEEE 1149.1 clock input: This ball must be tied to VSS if the JTAG function is not used in the circuit. TDO Output JTAG function pin; IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if JTAG function is not used. VREF Input Input reference voltage; Nominally VDDQ/2. Provides a reference voltage for the input buffers. VEXT Supply Power supply; 2.5 V nominal. See Recommended DC Operating Conditions for range. VDD Supply Power supply; 1.8 V nominal. See Recommended DC Operating Conditions for range. VDDQ Supply DQ power supply; Nominally, 1.5 V or 1.8 V. Isolated on the device for improved noise immunity. See Recommended DC Operating Conditions for range. VSS Supply Ground VSSQ Supply DQ ground; Isolated on the device for improved noise immunity. VTT Supply Power supply; Isolated termination supply. Nominally, VDDQ/2. See Recommended DC Operating Conditions for range. NF No function; These balls may be connected to VSS. DNU Do not use; These balls may be connected to VSS. R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 6 of 51 PD48576109, PD48576118 Block Diagram A0-Axx , B0, B1, B2 Row Address Buffer Refresh Counter Memory Array Memory Array Bank 0 Bank 1 Bank 2 Sense Amp and Data Bus Memory Array Column Decoder Memory Array Column Decoder Row Decoder Sense Amp and Data Bus Row Decoder Column Decoder Row Decoder Sense Amp and Data Bus Row Decoder Bank 3 Memory Array Memory Array Memory Array Bank 6 Qxx R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 VREF Dxx DM QKx, QKx# Control Logic and Timing Generator CS# QVLD Bank 7 REF# Output Buffers WE# Input Buffers DK Output Data Clock DK# Output Data Valid CK Bank 5 CK# Bank 4 Sense Amp and Data Bus Memory Array Column Decoder Row Decoder Column Decoder Row Decoder Sense Amp and Data Bus Row Decoder Column Decoder Row Decoder Sense Amp and Data Bus Column Decoder Column Decoder Sense Amp and Data Bus Sense Amp and Data Bus Column Address Buffer Page 7 of 51 PD48576109, PD48576118 Contents 1. Electrical Characteristics .................................................................................................. 9 2. Operation ............................................................................................................................ 16 2.1 Command Operation .............................................................................................. 16 2.2 Description of Commands ..................................................................................... 16 2.3 Initialization ............................................................................................................. 17 2.4 Power-On Sequence ............................................................................................... 18 2.5 Programmable Impedance Output Buffer ............................................................. 18 2.6 PLL Reset ................................................................................................................18 2.7 Clock Input ..............................................................................................................18 2.8 Mode Register Set Command (MRS) ..................................................................... 20 2.9 Read & Write configuration (Non Multiplexed Address Mode) ........................... 21 2.10 Write Operation (WRITE) ........................................................................................ 22 2.11 Read Operation (READ) .......................................................................................... 25 2.12 Refresh Operation: AUTO REFRESH Command (AREF) ..................................... 30 2.13 On-Die Termination................................................................................................. 31 2.14 Operation with Multiplexed Address ..................................................................... 33 2.15 Address Mapping in Multiplexed Mode................................................................. 35 2.16 Read & Write configuration in Multiplexed Address Mode ................................. 36 2.17 Refresh Command in Multiplexed Address Mode................................................ 36 2.18 Input Slew Rate Derating ........................................................................................ 38 3. JTAG Specification .......................................................................................................... 42 4. Package Dimension .........................................................................................................49 5. Recommended Soldering Condition .............................................................................. 50 R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 8 of 51 PD48576109, PD48576118 1. Electrical Characteristics Absolute Maximum Ratings Parameter Symbol Conditions Rating Unit Supply voltage VEXT -0.3 to +2.8 V Supply voltage VDD -0.3 to +2.1 V VDDQ -0.3 to +2.1 V Input / Output voltage VIH / VIL -0.3 to +2.1 V Junction temperature Tj MAX. 110 C Storage temperature Tstg -55 to +125 C Output supply voltage, Input voltage, Input / Output voltage Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions 0C TC 95C; 1.7 V VDD 1.9 V, unless otherwise noted. Parameter Symbol Conditions MIN. TYP. MAX. Unit Note Supply voltage VEXT 2.38 2.5 2.63 V 1 Supply voltage VDD 1.7 1.8 1.9 V 1 Output supply voltage VDDQ 1.4 VDD V 1, 2, 3 Reference Voltage VREF 0.49 x VDDQ 0.5 x VDDQ 0.51 x VDDQ V 1, 4, 5 Termination voltage VTT 0.95 x VREF VREF 1.05 x VREF V 1, 6 Input HIGH voltage VIH (DC) VREF + 0.1 V 1 Input LOW voltage VIL (DC) V 1 VREF - 0.1 Notes 1. All voltage referenced to VSS (GND). 2. During normal operation, VDDQ must not exceed VDD. 3. VDDQ can be set to a nominal 1.5 V 0.1 V or 1.8 V 0.1 V supply. 4. Typically the value of VREF is expect to be 0.5 x VDDQ of the transmitting device. VREF is expected to track variations in VDDQ. 5. Peak-to-peak AC noise on VREF must not exceed 2% VREF(DC). 6. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF. R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 9 of 51 PD48576109, PD48576118 DC Characteristics 0C TC 95C; 1.7 V VDD 1.9 V, unless otherwise noted Parameter Symbol Test condition MIN. MAX. Unit Note Input leakage current ILI -5 +5 A 1,2 Output leakage current ILO -5 +5 A 1,2 Reference voltage current IREF -5 +5 A 1,2 Output high current IOH VOH = VDDQ/2 (VDDQ/2) / (1.15 x RQ/5) (VDDQ/2) / (0.85 x RQ/5) mA 3,4 Output low current IOL VOL = VDDQ/2 (VDDQ/2) / (1.15 x RQ/5) (VDDQ/2) / (0.85 x RQ/5) mA 3,4 Notes 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) for values of 125 RQ 300 . 2. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 125 RQ 300 . 3. IOH and IOL are defined as absolute values and are measured at VDDQ/2. IOH flows from the device, IOL flows into the device. 4. If MRS bit A8 is 0, use RQ = 250 in the equation in lieu of presence of an external impedance matched resistor. Capacitance (TA = 25 C, f = 1MHz) Parameter Symbol Test conditions MIN. MAX. Unit Address / Control Input capacitance CIN VIN = 0 V 1.5 2.5 pF I/O, Output, Other capacitance CI/O VI/O = 0 V 3.5 5.0 pF Clock Input capacitance Cclk Vclk = 0 V 2.0 3.0 pF JTAG pins CJ VJ = 0 V 2.0 5.0 pF (D, Q, DM, QK, QVLD) Remark These parameters are periodically sampled and not 100% tested. Capacitance is not tested on ZQ pin. Recommended AC Operating Conditions 0C TC 95C; 1.7 V VDD 1.9 V, unless otherwise noted Parameter Symbol Input HIGH voltage VIH (AC) Input LOW voltage VIL (AC) Conditions MIN. MAX. VREF + 0.2 VREF - 0.2 Unit Note V 1 V 1 Note 1. Overshoot: VIH (AC) VDDQ + 0.7 V for t tCK/2 Undershoot: VIL (AC) - 0.5 V for t tCK/2 Control input signals may not have pulse widths less than tCKH (MIN.) or operate at cycle rates less than tCK (MIN.). R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 10 of 51 PD48576109, PD48576118 DC Characteristics IDD / ISB Operating Conditions Parameter Symbol Test condition MAX. Unit -E18 -E24 -E25 -E33 Standby current Active standby ISB1 ISB2 current Operating current IDD1 tCK = Idle VDD 55 55 55 55 All banks idle, no inputs toggling VEXT 5 5 5 5 CS# = HIGH, No commands, half bank / address / VDD 250 215 215 190 data change once every four clock cycles VEXT 5 5 5 5 BL=2, sequential bank access, bank transitions VDD 390 331 321 291 VEXT 10 10 10 10 VDD 422 367 357 336 VEXT 10 10 10 10 VDD 439 381 371 350 VEXT 15 15 15 15 Eight bank cyclic refresh, continuous VDD 692 540 540 419 address/data, command bus remains in refresh VEXT 45 30 30 25 Single bank refresh, sequential bank access, VDD 286 265 260 194 half address transitions once every tRC, VEXT 10 10 10 10 BL=2, cyclic bank access, half of address bits VDD 1078 872 872 716 change every clock cycle, continuous data, VEXT 40 35 35 30 BL=4, cyclic bank access, half of address bits VDD 784 645 645 538 change every two clocks, continuous data, VEXT 25 20 20 20 BL=8, cyclic bank access, half of address bits VDD 625 520 520 442 change every four clocks, continuous data, VEXT 25 20 20 20 BL=2, cyclic bank access, half of address bits VDD 949 735 735 566 change every clock cycle, measurement is taken VEXT 40 35 35 30 BL=4, cyclic bank access, half of address bits VDD 659 503 503 400 change every two clocks, measurement is taken VEXT 25 20 20 20 BL=8, cyclic bank access, half of address bits VDD 497 389 389 308 change every four clocks, measurement is taken VEXT 25 20 20 20 mA mA mA once every tRC, half address transitions once every tRC, read followed by write sequence, continuous data during WRITE commands. Operating current IDD2 BL=4, sequential bank access, bank transitions mA once every tRC, half address transitions once every tRC, read followed by write sequence, continuous data during WRITE commands. Operating current IDD3 BL=8, sequential bank access, bank transitions mA once every tRC, half address transitions once every tRC, read followed by write sequence, continuous data during WRITE commands. Burst refresh IREF1 current mA for all banks Disturbed IREF2 refresh current mA continuous data Operating burst IDD2W write current mA measurement is taken during continuous WRITE Operating burst IDD4W write current mA measurement is taken during continuous WRITE Operating burst IDD8W write current mA measurement is taken during continuous WRITE Operating burst IDD2R read current mA during continuous READ Operating burst IDD4R read current mA during continuous READ Operating burst read current IDD8R mA during continuous READ R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 11 of 51 PD48576109, PD48576118 Remarks 1. IDD specifications are tested after the device is properly initialized. 0C TC 95C; 1.7 V VDD 1.9 V, 2.38 V VEXT 2.63 V, 1.4 V VDDQ VDD, VREF = VDDQ/2 2. tCK = tDK = MIN., tRC = MIN. 3. Input slew rate is specified in Recommended DC Operating Conditions and Recommended AC Operating Conditions. 4. IDD parameters are specified with ODT disabled. 5. Continuous data is defined as half the D or Q signals changing between HIGH and LOW every half clock cycles (twice per clock). 6. Continuous address is defined as half the address signals between HIGH and LOW every clock cycles (once per clock). 7. Sequential bank access is defined as the bank address incrementing by one ever tRC. 8. Cyclic bank access is defined as the bank address incrementing by one for each command access. For BL=4 this is every other clock. 9. CS# is HIGH unless a READ, WRITE, AREF, or MRS command is registered. CS# never transitions more than per clock cycle. R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 12 of 51 PD48576109, PD48576118 AC Characteristics AC Test Conditions Input waveform VDDQ VIH(AC) MIN. VIL(AC) MAX. VSS Rise Time: 2 V/ns Fall Time: 2 V/ns Output waveform Test Points VDDQ / 2 VDDQ / 2 Output load condition VTT 50 Q Test point 10pF R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 13 of 51 PD48576109, PD48576118 AC Characteristics <Read and Write Cycle> Parameter Symbol -E18 -E24 -E25 -E33 Unit (533 MHz) (400 MHz) (400 MHz) (300 MHz) MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Note Clock Clock cycle time (CK,CK#,DK,DK#) tCK, tDK 1.875 5.7 2.5 5.7 2.5 5.7 3.3 5.7 ns Clock frequency (CK,CK#,DK,DK#) tCK, tDK 175 533 175 400 175 400 175 300 MHz Random Cycle time tRC 15 Clock Jitter: period tJIT PER -100 Clock Jitter: cycle-to-cycle tJIT CC 15 100 -150 200 20 150 -150 300 20 150 -200 300 ns 200 ps 400 ps Clock HIGH time (CK,CK#,DK,DK#) tCKH, tDKH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 Cycle Clock LOW time (CK,CK#,DK,DK#) tCKL, tDKL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 Cycle Clock to input data clock tCKDK -0.3 0.3 -0.45 0.5 -0.45 0.5 -0.45 1.0 ns Mode register set cycle time tMRSC 6 6 6 6 Cycle 1, 2 to any command PLL Lock time tCK Lock 15 15 15 15 s Clock static to PLL reset tCK Reset 30 30 30 30 ns Output data clock HIGH time tQKH 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCKH Output data clock LOW time tQKL 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCKL QK edge to clock edge skew tCKQK -0.2 0.2 -0.25 0.25 -0.25 0.25 -0.3 0.3 ns QK edge to output data edge tQKQ0, tQKQ1 -0.12 0.12 -0.2 0.2 -0.2 0.2 -0.25 0.25 ns 3, 5 tQKQ -0.22 0.22 -0.3 0.3 -0.3 0.3 -0.35 0.35 ns 4, 5 tQKVLD -0.22 0.22 -0.3 0.3 -0.3 0.3 -0.35 0.35 ns Address/command and input tAS/tCS 0.3 0.4 0.4 0.5 ns Data-in and data mask to DK tDS 0.17 0.25 0.25 0.3 ns Address/command and input tAH/tCH 0.3 0.4 0.4 0.5 ns Data-in and data mask to DK tDH 0.17 0.25 0.25 0.3 ns Output Times QK edge to any output data QK edge to QVLD Setup Times Hold Times Notes 1. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 2. Frequency drift is not allowed. 3. tQKQ0 is referenced to Q0-Q8 and tQKQ1 is referenced to Q9-Q17 for a x18 device. For a x9 device, Q0-Q8 are referenced to tQKQ0. 4. tQKQ takes into account the skew between any QKx and any Q. 5. tQKQ, tQKQX are guaranteed by design. Remark All timing parameters are measured relative to the crossing point of CK/CK#, DK/DK# and to the crossing point with VREF of the command, address, and data signals. R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 14 of 51 PD48576109, PD48576118 Figure 1-1. Clock / Input Data Clock Command / Address Timings tCK tCKH tCKL CK# CK COMMAND, ADDRESS VALID tCKDK VALID VALID tCKDK tAS tAH DKx# DKx tDK tDKH tDKL Don't care Temperature and Thermal Impedance Temperature Limits Parameter Symbol MIN. MAX. Unit Note Reliability junction temperature TJ 0 +110 C 1 Operating junction temperature TJ 0 +100 C 2 Operating case temperature TC 0 +95 C 3 Notes 1. Temperatures greater than 110C may cause permanent damage to the device. This is a stress rating only and functional operation of the device at or above this is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability of the part. 2. Junction temperature depends upon cycle time, loading, ambient temperature, and airflow. 3. MAX operating case temperature; TC is measured in the center of the package. Device functionality is not guaranteed if the device exceeds maximum TC during operation. Thermal Impedance Substrate ja (C/W) jb jc Air Flow = 0 m/s Air Flow = 1 m/s Air Flow = 2 m/s (C/W) (C/W) Ball 4 - Layer Lead 21.49 17.33 16.15 10.29 1.22 4 - Layer Lead free 21.32 17.18 16.01 10.13 1.22 R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 15 of 51 PD48576109, PD48576118 2. Operation 2.1 Command Operation According to the functional signal description, the following command sequences are possible. All input states or sequences not shown are illegal or reserved. All command and address inputs must meet setup and hold times around the rising edge of CK. Table 2-1. Address Widths at Different Burst Lengths Burst Length Configuration x9 x18 BL=2 A0-A21 A0-A20 BL=4 A0-A20 A0-A19 BL=8 A0-A19 A0-A18 Table 2-2. Command Table Operation A0-An Note1 BA0-BA2 Note CS# WE# REF# Device DESELECT / No Operation DESEL / NOP H X X X X MRS: Mode Register Set MRS L L L OPCODE X 2 READ READ L H H A BA 3 WRITE WRITE L L H A BA 3 AUTO REFRESH AREF L H L X BA Notes Code 1. n = 21. 2. Only A0-A17 are used for the MRS command. 3. See Table 2-1. Remark X = "Don't Care", H = logic HIGH, L = logic LOW, A = valid address, BA = valid bank address 2.2 Description of Commands DESEL / NOP Note1 The NOP command is used to perform a no operation to the PD48576209/18/36, which essentially deselects the chip. Use the NOP command to prevent unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Output values depend on command history. MRS The mode register is set via the address inputs A0-A17. See Figure 2-5. Mode Register Bit Map for further information. The MRS command can only be issued when all banks are idle and no bursts are in progress. READ The READ command is used to initiate a burst read access to a bank. The value on the BA0-BA2 inputs selects the bank, and the address provided on inputs A0-A21 selects the data location within the bank. WRITE The WRITE command is used to initiate a burst write access to a bank. The value on the BA0-BA2 inputs selects the bank, and the address provided on inputs A0-A21 selects the data location within the bank. Input data appearing on the D is written to the memory array subject to the DM input logic level appearing coincident with the data. If the DM signal is registered LOW, the corresponding data will be written to memory. If the DM signal is registered HIGH, the corresponding data inputs will be ignored (i.e., this part of the data word will not be written). R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 16 of 51 PD48576109, PD48576118 AREF The AREF is used during normal operation of the PD48576109/18 to refresh the memory content of a bank. The command is non-persistent, so it must be issued each time a refresh is required. The value on the BA0-BA2 inputs selects the bank. The refresh address is generated by an internal refresh controller, effectively making each address bit a "Don't Care" during the AREF command. The PD48576109/18 requires 64K cycles at an average periodic interval of 0.244s Note2 (MAX.). To improve efficiency, eight AREF commands (one for each bank) can be posted to PD48576109/18 at periodic intervals of 1.95 s Note3. Within a period of 32 ms, the entire memory must be refreshed. The delay between the AREF command and a subsequent command to same bank must be at least tRC as continuous refresh. Other refresh strategies, such as burst refresh, are also possible. Notes 1. When the chip is deselected, internal NOP commands are generated and no commands are accepted. 2. Actual refresh is 32 ms / 16k / 8 = 0.244 s. 3. Actual refresh is 32 ms / 16k = 1.95 s. 2.3 Initialization The PD48576109/18 must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operations or permanent damage to the device. The following sequence is used for Power-Up: 1. Apply power (VEXT, VDD, VDDQ, VREF, VTT) and start clock as soon as the supply voltages are stable. Apply VDD and VEXT before or at the same time as VDDQ. Apply VDDQ before or at the same time as VREF and VTT. Although there is no timing relation between VEXT and VDD, the chip starts the power-up sequence only after both voltages are at their nominal levels. VDDQ supply must not be applied before VDD supply. CK/CK# must meet VID(DC) prior to being applied. Maintain all remaining balls in NOP conditions. Note No rule of apply power sequence is the design target. 2. Maintain stable conditions for 200 s (MIN.). 3. Issue at least three or more consecutive MRS commands: two dummies or more plus one valid MRS. It is recommended that all address pins are held LOW during the dummy MRS commands. 4. tMRSC after valid MRS, an AUTO REFRESH command to all 8 banks must be issued and wait for 15 s with CK/CK# toggling in order to lock the PLL prior to normal operation. 5. After tRC, the chip is ready for normal operation. R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 17 of 51 PD48576109, PD48576118 2.4 Power-On Sequence Figure 2-1. Power-Up Sequence VEXT VDD VDDQ VREF VTT CK# CK NOP COMMAND NOP MRS Note 1, 2 ADDRESS A MRS Note 1, 2 A MRS NOP RF0 RF1 RF7 AC Note 2 A tMRSC 200s MIN. tRC Refresh all banks 15s Don't care Notes 1. Recommended all address pins held LOW during dummy MRS commands. 2. A10-A17 must be LOW. Remark MRS : MRS command RFp : REFRESH bank p AC : Any command 2.5 Programmable Impedance Output Buffer The PD48576109/18 is equipped with programmable impedance output buffers. This allows a user to match the driver impedance to the system. To adjust the impedance, an external precision resistor (RQ) is connected between the ZQ ball and VSS. The value of the resistor must be five times the desired impedance. For example, a 300 resistor is required for an output impedance of 60 . To ensure that output impedance is one fifth the value of RQ (within 15 percent), the range of RQ is 125 to 300 . Output impedance updates may be required because, over time, variations may occur in supply voltage and temperature. The device samples the value of RQ. An impedance update is transparent to the system and does not affect device operation. All data sheet timing and current specifications are met during an update. 2.6 PLL Reset The PD48576109/18 utilizes internal Phase-locked loops for maximum output, data valid windows. It can be placed into a stopped-clock state to minimize power with a modest restart time of 15 s. The clock (CK/CK#) must be toggled for 15 s in order to stabilize PLL circuits for next READ operation. 2.7 Clock Input Table 2-3. Clock Input Operation Conditions Parameter Symbol Conditions MIN. MAX. Unit Note Clock Input Voltage Level VIN (DC) CK and CK# -0.3 VDDQ + 0.3 V Clock Input Differential Voltage Level VID (DC) CK and CK# 0.2 VDDQ + 0.6 V 8 Clock Input Differential Voltage Level VID (AC) CK and CK# 0.4 VDDQ + 0.6 V 8 Clock Input Crossing Point Voltage Level VIX (AC) CK and CK# VDDQ/2 - 0.15 VDDQ/2 + 0.15 V 9 R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 18 of 51 PD48576109, PD48576118 Figure 2-2. Clock Input Maximum Clock Level VIN(DC) MAX. CK# VIX(AC) MAX. VDDQ/2 + 0.15 Note11 VDDQ/2 Note 10 VID(DC) Note12 VID(AC) VDDQ/2 - 0.15 VIX(AC) MIN. CK Minimum Clock Level VIN(DC) MIN. Notes 1. DKx and DKx# have the same requirements as CK and CK#. All voltages referenced to VSS. Tests for AC timing, IDD and electrical AC and DC characteristics may be conducted at normal reference/supply voltage levels; but the related specifications and device operations are tested for the full voltage range specified. 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or the crossing point for CK/CK#), and parameters specifications are tested for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 2V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the HSTL Standard (i.e. the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above[below] the DC input LOW[HIGH] level). 6. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross. The input reference level for signal other than CK/CK# is VREF. 7. CK and CK# input slew rate must be >= 2V/ns (>=4V/ns if measured differentially). 8. VID is the magnitude of the difference between the input level on CK and input level on CK#. 9. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same. 10. CK and CK# must cross within the region. 11. CK and CK# must meet at least VID(DC) (MIN.) when static and centered around VDDQ/2. 12. Minimum peak-to-peak swing. 2. 3. R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 19 of 51 PD48576109, PD48576118 2.8 Mode Register Set Command (MRS) The mode register stores the data for controlling the operating modes of the memory. It programs the PD48576109/18 configuration, burst length, and I/O options. During a MRS command, the address inputs A0-A17 are sampled and stored in the mode register. tMRSC must be met before any command can be issued to the PD48576109/18. The mode register may be set at any time during device operation. However, any pending operations are not guaranteed to successfully complete, and all memory cell data are not guaranteed. Since MRS is used for internal test mode entry, bits A10-A17 must be set to all "0" at the MRS setting. Figure 2-3. Mode Register Set Timing tMRSC CK# CK COMMAND MRS NOP NOP AC QVLD QKx QKx# Don't care Remark MRS : MRS command AC : any command Figure 2-4. Mode Register Set CK# CK CS# WE# REF# ADDRESS COD BANK ADDRESS Don't care Remark COD: code to be loaded into the register. R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 20 of 51 PD48576109, PD48576118 Figure 2-5. Mode Register Bit Map A17-A10 A9 Note 1 Reserved A8 Impedance On-Die Termination Matching On-Die Termination A9 A7 A6 A5 PLL Reset Unused Address Mux PLL Reset Termination A4 A3 A2 A1 Configuration Burst Length Configuration Burst Length A7 PLL Reset A4 A3 A0 BL A2 A1 A0 Configuration 0 Disabled (default) 0 PLL reset (default) 0 0 2 (default) 1 0 0 0 1 Note 2 (default) Enabled 1 PLL enabled 0 1 4 0 0 1 1 Note 2 1 0 8 Note 2 0 1 0 2 1 1 Not valid 0 1 1 3 1 0 0 4 Address Mux 1 0 1 5 Nonmultiplexed (default) 1 1 0 Reserved 0 1 1 1 Reserved 1 Address multiplexed Impedance Matching A8 Address Mux Resistor 0 Internal 50 (default) 1 External A5 Note 3 Note 4 Note 2 Notes 1. Bits A10-A17 must be set to all `0'. A18-An are "Don't Care". 2. BL=8 is not available for configuration 1 and 4. 3. 30% temperature variation. 4. Within 15%. 2.9 Read & Write configuration (Non Multiplexed Address Mode) Table 2-4 shows, for different operating frequencies, the different PD48576109/18 configurations that can be programmed into the mode register. The READ and WRITE latency (tRL and tWL) values along with the row cycle times (tRC) are shown in clock cycles as well as in nanoseconds. Table 2-4. Configuration Table Parameter Configuration 1 Note2 2 3 Unit 4 Note2, 3 5 tRC 4 6 8 3 5 tCK tRL 4 6 8 3 5 tCK tWL 5 7 9 4 6 tCK Valid frequency range 266-175 400-175 533-175 200-175 333-175 MHz Notes 1. Apply to the entire table. tRC < 20 ns in any configuration only available with -E24 and -E18 speed grades. 2. BL= 8 is not available. 3. The minimum tRC is typically 3 cycles, except in the case of a WRITE followed by a READ to the same bank. In this instance the minimum tRC is 4 cycles. R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 21 of 51 PD48576109, PD48576118 2.10 Write Operation (WRITE) Write accesses are initiated with a WRITE command, as shown in Figure 2-6. Row and bank addresses are provided together with the WRITE command. During WRITE commands, data will be registered at both edges of DK according to the programmed burst length (BL). A WRITE latency (WL) one cycle longer than the programmed READ latency (RL + 1) is present, with the first valid data registered at the first rising DK edge WL cycles after the WRITE command. Any WRITE burst may be followed by a subsequent READ command. Figure 2-10. WRITE Followed By READ: BL=2, RL=4, WL=5, Configuration 1 and Figure 2-11. WRITE Followed By READ: BL=4, RL=4, WL=5, Configuration 1 illustrate the timing requirements for a WRITE followed by a READ for bursts of two and four, respectively. Setup and hold times for incoming input data relative to the DK edges are specified as tDS and tDH. The input data is masked if the corresponding DM signal is HIGH. The setup and hold times for data mask are also tDS and tDH. Figure 2-6. WRITE Command CK# CK CS# WE# REF# ADDRESS A BANK ADDRESS BA Don't care Remark A : Address BA : Bank address Figure 2-7. Basic WRITE Burst / DM Timing CK# CK tCKDK DK# DK Write Latency D tDS tDH tDS D0 D1 D2 tDH D3 DM Data masked tDS tDH Data masked Don't care R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 22 of 51 PD48576109, PD48576118 Figure 2-8. WRITE Burst Basic Sequence: BL=2, RL=4, WL=5, Configuration 1 0 1 2 3 4 5 6 7 8 COMMAND WR WR WR WR WR WR WR WR WR ADDRESS A BA0 A BA1 A BA2 A BA3 A BA0 A BA4 A BA5 A BA6 A BA7 D0a D0b D1a D1b D2a D2b D3a CK# CK WL = 5 DK# DK D D3 Don't care Figure 2-9. WRITE Burst Basic Sequence: BL=4, RL=4, WL=5, Configuration 1 0 1 2 3 4 5 6 7 8 COMMAND WR NOP WR NOP WR NOP WR NOP WR ADDRESS A BA0 CK# CK A BA1 A BA0 A BA3 A BA0 WL = 5 DK# DK D0a D0b D D0c D0d D1a D1b D1c D1 Don't care Remarks 1. 2. WR A/Bap WL Dpq : WRITE command : Address A of bank p : WRITE latency : Data q to bank p Any free bank may be used in any given command. The sequence shown is only one example of a bank sequence. R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 23 of 51 PD48576109, PD48576118 Figure 2-10. WRITE Followed By READ: BL=2, RL=4, WL=5, Configuration 1 0 1 2 3 4 5 6 7 8 9 COMMAND WR RD RD NOP NOP NOP NOP NOP NOP NOP ADDRESS A BA0 A BA1 A BA2 CK# CK WL = 5 RL = 4 DK# DK D D0a D0b Q1a Q1b Q2a Q2b Q QKx QKx# Don't care Undefined Figure 2-11. WRITE Followed By READ: BL=4, RL=4, WL=5, Configuration 1 0 1 2 3 4 5 6 7 8 9 COMMAND WR RD WR RD NOP NOP NOP NOP NOP NOP ADDRESS A BA0 A BA1 A BA2 A BA3 CK# CK WL = 5 RL = 4 DK# DK D D0a Q D0b D0c D0d D2a D2b D2c D2d Q1a Q1b Q1c Q1d Q3a Q3b Q3c Q3d QKx QKx# Don't care Remark Undefined WR : WRITE command RD : READ command A/BAp : Address A of bank p WL : WRITE latency RL : READ latency Dpq : Data q to bank p Qpq : Data q from bank p R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 24 of 51 PD48576109, PD48576118 2.11 Read Operation (READ) Read accesses are initiated with a READ command, as shown in Figure 2-12. Row and bank addresses are provided with the READ command. During READ bursts, the memory device drives the read data edge-aligned with the QK signal. After a programmable READ latency, data is available at the outputs. The data valid signal indicates that valid data will be present in the next half clock cycle. The skew between QK and the crossing point of CK is specified as tCKQK. tQKQ0 is the skew between QK0 and the last valid data edge considered the data generated at the Q0-Q8. tQKQ1 is the skew between QK1 and the last valid data edge considered the data generated at the Q9-Q17. tQKQx is derived at each QKx clock edge and is not cumulative over time. After completion of a burst, assuming no other commands have been initiated, Q will go High-Z. Back-to-back READ commands are possible, producing a continuous flow of output data. Minimum READ data valid window can be expressed as MIN.(tQKH, tQKL) - 2 x MAX.(tQKQx) Any READ burst may be followed by a subsequent WRITE command. Figure 2-16. READ followed by WRITE, BL=2, RL=4, WL=5, Configuration 1 and Figure 2-17. READ followed by WRITE, BL=4, RL=4, WL=5, Configuration 1 illustrate the timing requirements for a READ followed by a WRITE. Figure 2-12. READ Command CK# CK CS# WE# REF# ADDRESS A BANK ADDRESS BA Don't care Remark A : Address BA : Bank address R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 25 of 51 PD48576109, PD48576118 Figure 2-13. Basic READ Burst Timing tCKH tCKL tCK CK# CK tQKL tCKQK tQKH QKx QKx# tQKVLD tQKVLD QVLD Q0 Q Q1 Q2 Q3 tQKQ tQKQ tQKQ Note 1 Undefined Note 1. Minimum READ data valid window can be expressed as MIN.(tQKH, tQKL) - 2 x MAX.(tQKQx) tCKH and tCKL are recommended to have 50% / 50% duty. Remarks 1. 2. 3. R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 tQKQ0 is referenced to Q0-Q8. tQKQ1 is referenced to Q9-Q17. tQKQ takes into account the skew between any QKx and any Q. tCKQK is specified as CK rising edge to QK rising edge. Page 26 of 51 PD48576109, PD48576118 Figure 2-14. READ Burst Basic Sequence: BL=2, RL=4, Configuration 1 0 1 2 3 4 5 6 7 8 COMMAND RD RD RD RD RD RD RD RD RD ADDRESS A BA0 A BA1 A BA2 A BA3 A BA0 A BA7 A BA6 A BA5 A BA4 CK# CK RL = 4 QKx QKx# QVLD Q0a Q0b Q1a Q1b Q2a Q2b Q3a Q3b Q0a Q Undefined Don't care Figure 2-15. READ Burst Basic Sequence: BL=4, RL=4, Configuration 1 0 1 2 3 4 5 6 7 8 COMMAND RD NOP RD NOP RD NOP RD NOP RD ADDRESS A BA0 CK# CK A BA1 A BA0 A BA1 A BA3 RL = 4 QKx QKx# QVLD Q0a Q0b Q Q0c Q0d Q1a Q1b Q1c Q1d Q0a Don't care Remark RD A/BAp RL Qpq R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Undefined : READ command : Address A of bank p : READ latency : Data q from bank p Page 27 of 51 PD48576109, PD48576118 Figure 2-16. READ followed by WRITE, BL=2, RL=4, WL=5, Configuration 1 0 1 2 3 4 5 6 7 COMMAND RD WR WR NOP NOP NOP NOP NOP ADDRESS A BA0 A BA1 A BA2 D1a D1b D2a D2b CK# CK WL = 5 RL = 4 DK# DK D Q0a Q0b Q QKx QKx# Undefined Don't care Figure 2-17. READ followed by WRITE, BL=4, RL=4, WL=5, Configuration 1 0 1 2 3 4 5 6 7 COMMAND RD WR RD NOP NOP NOP NOP NOP ADDRESS A BA0 A BA1 A BA2 CK# CK WL = 5 RL = 4 DK# DK D D1a D1b D1c D1d Q Q0a Q0b Q0c Q0d Q2a Q2b Q2c QKx QKx# Don't care Remark WR RD A/BAp WL RL Dpq Qpq R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Undefined : WRITE command : READ command : Address A of bank p : WRITE latency : READ latency : Data q to bank p : Data q from bank p Page 28 of 51 PD48576109, PD48576118 Figure 2-18. READ/WRITE Interleave: BL=4, tRC=6, WL=7, Configuration 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 COMMAND RD WR RD WR RD WR RD WR RD WR RD WR RD WR RD ADDRESS A BA0 A BA1 A BA2 A BA3 A BA4 A BA5 A BA0 A BA1 A BA2 A BA3 A BA2 A BA5 A BA0 A BA1 A BA2 D1a D1b D1c D1d D3a D3b D5a D5b D5c D5d D1a CK# CK WL = 7 tRC = 6 D D3c D3d D1 RL = 6 QKx# QKx Q Q0a Q0b Q0c Q0d Q2a Q2b Q2c Q2d Q4a Q4b Q4c Q4d Q0a Q0b Q0c Q0d Q2a Don't care Undefined Figure 2-19. READ/WRITE Interleave: BL=4, tRC=8, WL=9, Configuration 3 0 1 2 7 8 9 10 11 12 13 14 15 16 17 C OMMAND RD WR RD WR RD WR RD WR RD WR RD WR RD WR ADDRESS A BA0 A BA1 A BA2 A BA7 A BA0 A BA1 A BA2 A BA3 A BA4 A BA5 A BA6 A BA7 A BA0 A BA1 D1a D1b D1c D1d D3a D3b D3c D3d D5a D5c D5d D7a D7b D7c C K# CK WL = 9 tRC = 8 D D5b D7 RL = 8 QKx# QKx Q Q0a Q0b Q0c Q0d Q2a Q2b Q2c Q2d Q4a Q4b Q4c Q4d Q6a Q6b Q6c Q6d Q0a Q0b Don't care Remark WR RD A/BAp WL RL Dpq Qpq R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Q0c Undefined : WRITE command : READ command : Address A of bank p : WRITE latency : READ latency : Data q to bank p : Data q from bank p Page 29 of 51 PD48576109, PD48576118 2.12 Refresh Operation: AUTO REFRESH Command (AREF) AREF is used to perform a REFRESH cycle on one row in a specific bank. The row addresses are generated by an internal refresh counter; external address balls are "Don't Care." The delay between the AREF command and a subsequent command to the same bank must be at least tRC. Within a period of 32 ms (tREF), the entire memory must be refreshed. Figure 2-21 illustrates an example of a continuous refresh sequence. Other refresh strategies, such as burst refresh, are also possible. Figure 2-20. AUTO REFRESH Command CK# CK CS# WE# REF# ADDRESS BANK ADDRESS BA Don't care Remark BA: Bank address Figure 2-21. AUTO REFRESH Cycle CK# CK COMMAND ARFx ACy ACx tRC Remarks 1. ACx ACy Don't care : Any command on bank x ARFx : Auto refresh bank x ACy 2. : Any command on different bank. tRC is configuration-dependent. Refer to Table 2-4. Configuration Table. R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 30 of 51 PD48576109, PD48576118 2.13 On-Die Termination On-die termination (ODT) is enabled by setting A9 to "1" during an MRS command. With ODT on, all the Ds and DM are terminated to VTT with a resistance RTT. The command, address, and clock signals are not terminated. Figure 2-22. below shows the equivalent circuit of a D receiver with ODT. ODTs are dynamically switched off during READ commands and are designed to be off prior to the PD48576109/18 driving the bus. Similarly, ODTs are designed to switch on after the PD48576109/18 has issued the last piece of data. ODT at the D inputs and DM are always on. Table 2-5. On-Die Termination DC Parameters Description Symbol MIN. MAX. Units Note Termination voltage VTT 0.95 x VREF 1.05 x VREF V 1, 2 On-Die termination RTT 125 185 3 Notes 1. All voltages referenced to VSS (GND). 2. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF. 3. The RTT value is measured at 95C TC. Figure 2-22. On- Die Termination-Equivalent Circuit VTT sw RTT D Receiver Figure 2-23. READ Burst with ODT: BL=2, Configuration 1 0 1 2 3 4 5 6 7 8 RD RD RD NOP NOP NOP NOP NOP NOP A BA0 A BA1 A BA2 CK# CK COMMAND ADDRESS RL = 4 QKx QKx# QVLD Q Q0a Q0b ODT ODT ON Q1a Q1b Q2a Q2b ODT OFF Don't care Remark RD A/BAp RL Qpq R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 ODT ON Undefined : READ command : Address A of bank p : READ latency : Data q from bank p Page 31 of 51 PD48576109, PD48576118 Figure 2-24. READ NOP READ with ODT: BL=2, Configuration 1 0 1 2 3 4 5 6 7 8 RD NOP RD NOP NOP NOP NOP NOP NOP CK# CK COMMAND ADDRESS A BA0 A BA2 RL = 4 QKx QKx# QVLD Q0a Q0b Q ODT ODT ON ODT OFF Q2a Q2b ODT ON ODT ON ODT OFF Undefined Don't care Figure 2-25. READ NOP NOP READ with ODT: BL=2, Configuration 1 0 1 2 3 4 5 6 7 8 RD NOP NOP RD NOP NOP NOP NOP NOP 9 CK# CK COMMAND ADDRESS A BA0 A BA2 RL = 4 QKx QKx# QVLD Q Q0a Q0b ODT ODT ON ODT OFF Q2a Q2b ODT ON ODT OFF Don't care Remark ODT ON Undefined RD : READ command A/BAp : Address A of bank p RL : READ latency Qpq : Data q from bank p R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 32 of 51 PD48576109, PD48576118 2.14 Operation with Multiplexed Address In multiplexed address mode, the address can be provided to the PD48576109/18 in two parts that are latched into the memory with two consecutive rising clock edges. This provides the advantage that a maximum of 11 address balls are required to control the PD48576109/18, reducing the number of balls on the controller side. The data bus efficiency in continuous burst mode is not affected for BL=4 and BL=8 since at least two clocks are required to read the data out of the memory. The bank addresses are delivered to the PD48576109/18 at the same time as the WRITE command and the first address part, Ax. This option is available by setting bit A5 to "1" in the mode register. Once this bit is set, the READ, WRITE, and MRS commands follow the format described in Figure 2-26. See Figure 2-28. Power-Up Sequence in Multiplexed Address Mode for the power-up sequence. Figure 2-26. Command Description in Multiplexed READ WRITE MRS CK# CK CS# WE# REF# ADDRESS Ax BANK ADDRESS BA Ay Ax Ay Ax Ay BA Don't care Remarks 1. 2. Ax, Ay : Address BA : Bank Address The minimum setup and hold times of the two address parts are defined tAS and tAH. R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 33 of 51 PD48576109, PD48576118 Figure 2-27. Mode Register Set Command in Multiplexed Address Mode Ax A17 ***** A10 Ay A17 ***** A10 Reserved Note 1 A8 A9 A5 Impedance On-Die Termination Matching On-Die Termination A9x Termination A9 A8 PLL Reset Unused A4 A4 Address Mux PLL Reset PLL Reset A4x A3x Configuration BL A4y A3y A0x Configuration Disabled (default) 0 PLL reset (default) 0 0 2 (default) 1 0 0 0 1 Note 2 (default) Enabled 1 PLL enabled 0 1 4 0 0 1 1 Note 2 1 0 8 Note 2 0 1 0 2 1 1 Not valid 0 1 1 3 1 0 0 4 Note 2 1 0 1 5 1 1 0 Reserved 1 1 1 Reserved A8x 0 1 Remark Configuration 0 Impedance Matching Notes 1. 2. 3. 4. A3 Burst Length Burst Length A9y A0 A3 Resistor (default) External Address Mux A5x Note 3 Note 4 0 Nonmultiplexed (default) 1 Address multiplexed Bits A10-A17 must be set to all `0'. BL=8 is not available for configuration 1 and 4. 30% temperature variation. Within 15%. The address A0, A3, A4, A5, A8, and A9 must be set as follows in order to activate the mode register in the multiplexed address mode. Figure 2-28. Power-Up Sequence in Multiplexed Address Mode VEXT VDD VDDQ VREF VTT CK# CK COMMAND NOP NOP ADDRESS MRS MRS MRS Note 1, 2 Note 1, 2 Note 2, 3 A 200s MIN. 1 cycle MIN. MRS NOP RF0 RF1 RF7 AC Note 4 A A 1 cycle MIN. NOP Ax tMRSC Ay tMRSC Refresh all banks tRC 15s Don't care Notes 1. Recommended all address pins held LOW during dummy MRS command. 2. A10-A17 must be LOW. 3. Address A5 must be set HIGH (muxed address mode setting when PD48576209/18/36 is in normal mode of operation). 4. Address A5 must be set HIGH (muxed address mode setting when PD48576209/18/36 is already in muxed address mode). Remark MRS : MRS command RFp : REFRESH Bank p AC : any command R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 34 of 51 PD48576109, PD48576118 2.15 Address Mapping in Multiplexed Mode The address mapping is described in Table 2-6 as a function of data width and burst length. Table 2-6. Address Mapping in Multiplexed Address Mode Data Burst Ball Width Length x18 BL=2 BL=4 BL=8 x9 BL=2 BL=4 BL=8 Address A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18 Ax A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18 Ay A20 A1 A2 X A6 A7 A19 A11 A12 A16 A15 Ax A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18 Ay X A1 A2 X A6 A7 A19 A11 A12 A16 A15 Ax A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18 Ay X A1 A2 X A6 A7 X A11 A12 A16 A15 Ax A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18 Ay A20 A1 A2 A21 A6 A7 A19 A11 A12 A16 A15 Ax A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18 Ay A20 A1 A2 X A6 A7 A19 A11 A12 A16 A15 Ax A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18 Ay X A1 A2 X A6 A7 A19 A11 A12 A16 A15 Remark X means "Don't care". R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 35 of 51 PD48576109, PD48576118 2.16 Read & Write configuration in Multiplexed Address Mode In multiplexed address mode, the READ and WRITE latencies are increased by one clock cycle. The PD48576109/18 cycle time remains the same, as described in Table 2-7. Table 2-7. Configuration in Multiplexed Address Mode Parameter Configuration 1 Note2 2 3 Unit 4 Note2, 3 5 tRC 4 6 8 3 5 tCK tRL 5 7 9 4 6 tCK tWL 6 8 10 5 7 tCK Valid frequency range 266-175 400-175 533-175 200-175 333-175 MHz Notes 1. Apply to the entire table. tRC < 20 ns in any configuration is only available with -E24 and -E18 speed grades. 2. BL = 8 is not available. 3. The minimum tRC is typically 3 cycles, except in the case of a WRITE followed by a READ to the same bank. In this instance the minimum tRC is 4 cycles. 2.17 Refresh Command in Multiplexed Address Mode Similar to other commands, the refresh command is executed on the next rising clock edge when in the multiplexed address mode. However, since only bank address is required for AREF, the next command can be applied on the following clock. The operation of the AREF command and any other command is represented in Figure 2-29. Figure 2-29. Burst REFRESH Operation 0 CK# 1 2 3 4 5 6 7 8 9 10 11 10 11 0 1 2 3 4 5 6 7 8 9 CK COMMAND AC NOP AREF AREF AREF AREF AREF AREF AREF AREF AC COMMAND AC NOP AREF AREF AREF AREF AREF AREF AREF AREF AC ADDRESS Ax Ay Ax Ay ADDRESS Ax Ay Ax Ay BANK ADDRESS BANK ADDRESS BAp BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 BAp BAp BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 BAp CK# CK Don't care Don't care Remark AREF AC Ax Ay BAp R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 : AUTO REFRESH : Any command : First part Ax of address : Second part Ay of address : Bank p is chosen so that tRC is met. Page 36 of 51 PD48576109, PD48576118 Figure 2-30. WRITE Burst Basic Sequence: BL=4, with Multiplexed Addresses, Configuration 1 0 1 2 3 4 5 6 7 8 WR NOP WR NOP WR NOP WR NOP WR Ax BA0 Ay Ax BA1 Ay Ax BA2 Ay Ax BA3 Ay Ax BA0 D0c D0d D1a CK# CK COMMAND ADDRESS WL = 6 DK# DK D0a D D0b D1 Don't care Figure 2-31. READ Burst Basic Sequence: BL=4, with Multiplexed Addresses, Configuration 1, RL=5 0 1 2 3 4 5 6 7 8 COMMAND RD NOP RD NOP RD NOP RD NOP RD ADDRESS Ax BA0 Ay Ax BA1 Ay Ax BA2 Ay Ax BA0 Ay Ax BA1 CK# CK RL = 5 QKx QKx# QVLD Q0a Q0b Q Q0c Q0d Don't care Remark WR RD Ax/BAp Ay Dpq Qpq WL RL R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Q1a Q1b Q1c Undefined : WRITE command : READ command : Address Ax of bank p : Address Ay of bank p : Data q to bank p : Data q from bank p : WRITE latency : READ latency Page 37 of 51 PD48576109, PD48576118 2.18 Input Slew Rate Derating Table 2-8 on page 39 and Table 2-9 on page 40 define the address, command, and data setup and hold derating values. These values are added to the default tAS/tCS/tDS and tAH/tCH/tDH specifications when the slew rate of any of these input signals is less than the 2 V/ns the nominal setup and hold specifications are based upon. To determine the setup and hold time needed for a given slew rate, add the tAS/tCS default specification to the "tAS/tCS VREF to CK/CK# Crossing" and the tAH/tCH default specification to the "tAH/tCH CK/CK# Crossing to VREF" derated values on Table 2-8. The derated data setup and hold values can be determined in a like manner using the "tDS VREF to CK/CK# Crossing" and "tDH to CK/CK# Crossing to VREF" values on Table 2-9. The derating values on Table 2-8 and Table 2-9 apply to all speed grades. The setup times on Table 2-8 and Table 2-9 represent a rising signal. In this case, the time from which the rising signal crosses VIH(AC) MIN to the CK/CK# cross point is static and must be maintained across all slew rates. The derated setup timing represents the point at which the rising signal crosses VREF(DC) to the CK/CK# cross point. This derated valueis calculated by determining the time needed to maintain the given slew rate and the delta between VIH(AC) MIN and the CK/CK# cross point. The setup values in Table 2-8 and Table 2-9 are also valid for falling signals (with respect to VIL[AC] MAX and the CK/CK# cross point). The hold times in Table 2-8 and Table 2-9 represent falling signals. In this case, the time from the CK/CK# cross point to when the signal crosses VIH(DC) MIN is static and must be maintained across all slew rates. The derated hold timing represents the delta between the CK/CK# cross point to when the falling signal crosses VREF(DC). This derated value is calculated by determining the time needed to maintain the given slew rate and the delta between the CK/CK# cross point and VIH(DC). The hold values in Table 2-8 and Table 2-9 are also valid for rising signals (with respect to VIL[DC] MAX and the CK and CK# cross point). Note: The above descriptions also pertain to data setup and hold derating when CK/CK# are replaced with DK/DK#. R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 38 of 51 PD48576109, PD48576118 Table 2-8. Address and Command Setup and Hold Derating Values Command/ Address Slew Rate (V/ns) tAS/tCS VREF to CK/CK# Crossing tAS/tCS VIH(AC) MIN to CK/CK# Crossing tAH/tCH CK/CK# Crossing to VREF tAH/tCH CK/CK# Crossing to VIH(DC) MIN Unit CK, CK# Differential Slew Rate: 2.0 V/ns 2.0 0 -100 0 -50 ps 1.9 5 -100 3 -50 ps 1.8 11 -100 6 -50 ps 1.7 18 -100 9 -50 ps 1.6 25 -100 13 -50 ps 1.5 33 -100 17 -50 ps 1.4 43 -100 22 -50 ps 1.3 54 -100 27 -50 ps 1.2 67 -100 34 -50 ps 1.1 82 -100 41 -50 ps 1.0 100 -100 50 -50 ps CK, CK# Differential Slew Rate: 1.5 V/ns 2.0 30 -70 30 -20 ps 1.9 35 -70 33 -20 ps 1.8 41 -70 36 -20 ps 1.7 48 -70 39 -20 ps 1.6 55 -70 43 -20 ps 1.5 63 -70 47 -20 ps 1.4 73 -70 52 -20 ps 1.3 84 -70 57 -20 ps 1.2 97 -70 64 -20 ps 1.1 112 -70 71 -20 ps 1.0 130 -70 80 -20 ps CK, CK# Differential Slew Rate: 1.0 V/ns 2.0 60 -40 60 10 ps 1.9 65 -40 63 10 ps 1.8 71 -40 66 10 ps 1.7 78 -40 69 10 ps 1.6 85 -40 73 10 ps 1.5 93 -40 77 10 ps 1.4 103 -40 82 10 ps 1.3 114 -40 87 10 ps 1.2 127 -40 94 10 ps 1.1 142 -40 101 10 ps 1.0 160 -40 110 10 ps R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 39 of 51 PD48576109, PD48576118 Table 2-9. Data Setup and Hold Derating Values Data Slew Rate (V/ns) tDS VREF to DK/DK# Crossing tDS VIH(AC) MIN to DK/DK# Crossing tDH DK/DK# Crossing to VREF tDH DK/DK# Crossing to VIH(DC) MIN Unit DK, DK# Differential Slew Rate: 2.0 V/ns 2.0 0 -100 0 -50 ps 1.9 5 -100 3 -50 ps 1.8 11 -100 6 -50 ps 1.7 18 -100 9 -50 ps 1.6 25 -100 13 -50 ps 1.5 33 -100 17 -50 ps 1.4 43 -100 22 -50 ps 1.3 54 -100 27 -50 ps 1.2 67 -100 34 -50 ps 1.1 82 -100 41 -50 ps 1.0 100 -100 50 -50 ps DK, DK# Differential Slew Rate: 1.5 V/ns 2.0 30 -70 30 -20 ps 1.9 35 -70 33 -20 ps 1.8 41 -70 36 -20 ps 1.7 48 -70 39 -20 ps 1.6 55 -70 43 -20 ps 1.5 63 -70 47 -20 ps 1.4 73 -70 52 -20 ps 1.3 84 -70 57 -20 ps 1.2 97 -70 64 -20 ps 1.1 112 -70 71 -20 ps 1.0 130 -70 80 -20 ps DK, DK# Differential Slew Rate: 1.0 V/ns 2.0 60 -40 60 10 ps 1.9 65 -40 63 10 ps 1.8 71 -40 66 10 ps 1.7 78 -40 69 10 ps 1.6 85 -40 73 10 ps 1.5 93 -40 77 10 ps 1.4 103 -40 82 10 ps 1.3 114 -40 87 10 ps 1.2 127 -40 94 10 ps 1.1 142 -40 101 10 ps 1.0 160 -40 110 10 ps R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 40 of 51 PD48576109, PD48576118 Figure 2-32. Nominal tAS/tCS/tDS and tAH/tCH/tDH Slew Rate VDDQ VIL(DC) MAX. VIL(AC) MAX. VREF to AC region VSWING (MAX) VRFE(DC) VREF to AC region VIH(DC) MIN. VREF to DC VREF to DC region region VIH(AC) MIN. VSSQ R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 41 of 51 PD48576109, PD48576118 3. JTAG Specification These products support a limited set of JTAG functions as in IEEE standard 1149.1. Table 3-1. Test Access Port (TAP) Pins Pin name Pin assignments Description TCK 12A Test Clock Input. All input are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS 11A Test Mode Select. This is the command input for the TAP controller state TDI 12V Test Data Input. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently TDO 11V Test Data Output. This is the output side of the serial registers placed between TDI and TDO. Output changes in response to the falling edge of TCK. Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH for five rising edges of TCK. The TAP controller state is also reset on the POWER-UP. Table 3-2. JTAG DC Characteristics (0C TC 95C, 1.7 V VDD 1.9 V, unless otherwise noted) Parameter Symbol JTAG Input leakage current ILI JTAG I/O leakage current ILO Conditions MIN. MAX. Unit Notes 0 V VIN VDD -5.0 +5.0 A 0 V VIN VDD Q , -5.0 +5.0 A Outputs disabled JTAG input HIGH voltage VIH VREF + 0.15 VDD + 0.3 V 1, 2 JTAG input LOW voltage VIL VSSQ - 0.3 VREF - 0.15 V 1, 2 JTAG output HIGH voltage JTAG output LOW voltage Note VOH1 | IOHC | = 100 A VDDQ - 0.2 V VOH2 | IOHT | = 2 mA VDDQ - 0.4 V VOL1 IOLC = 100 A 0.2 V 1 VOL2 IOLT = 2 mA 0.4 V 1 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH (AC) VDD + 0.7 V for t tCK/2. Undershoot: VIL (AC) -0.5 V for t tCK/2. During normal operation, VDDQ must not exceed VDD. R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 42 of 51 PD48576109, PD48576118 JTAG AC Test Conditions Input waveform VDDQ VIH(AC) MIN. VIL(AC) MAX. VSS Rise Time: 2 V/ns Fall Time: 2 V/ns Output waveform Test Points VDDQ / 2 VDDQ / 2 Output load condition VTT 50 TDO Test point 10pF R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 43 of 51 PD48576109, PD48576118 Table 3-3. JTAG AC Characteristics (0C TC 95C) Parameter Symbol Conditions MIN. MAX. Unit 50 MHz Note Clock Clock cycle time tTHTH Clock frequency fTF 20 ns Clock HIGH time tTHTL 10 ns Clock LOW time tTLTH 10 ns TCK LOW to TDO tTLOX 0 ns TCK LOW to TDO valid tTLOV Output time 10 ns Setup time TMS setup time tMVTH 5 ns TDI valid to TCK HIGH tDVTH 5 ns Capture setup time tCSJ 5 ns TMS hold time tTHMX 5 ns TCK HIGH to TDI invalid tTHDX 5 ns Capture hold time tCHJ 5 ns 1 Hold time 1 Note 1. tCSJ and tCHJ refer to the setup and hold time requirements of latching data from the boundary scan register. JTAG Timing Diagram tTHTH TCK tMVTH tTHTL tTLTH TMS tTHMX tDVTH TDI tTHDX tTLOX tTLOV TDO R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 44 of 51 PD48576109, PD48576118 Table 3-4. Scan Register Definition (1) Register name Description Instruction register The 8 bit instruction registers hold the instructions that are executed by the TAP controller. The register can be loaded when it is placed between the TDI and TDO pins. The instruction register is automatically preloaded with the IDCODE instruction at powerup whenever the controller is placed in test-logic-reset state. Bypass register The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAMs TAP to another device in the scan chain with as little delay as possible. The bypass register is set LOW (VSS) when the bypass instruction is executed. ID register The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when the controller is put in capture-DR state with the IDCODE command loaded in the instruction register. The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR state. Boundary register The boundary register, under the control of the TAP controller, is loaded with the contents of the RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to activate the boundary register. The Scan Exit Order tables describe which device bump connects to each boundary register location. The first column defines the bit's position in the boundary register. The second column is the name of the input or I/O at the bump and the third column is the bump number. Table 3-5. Scan Register Definition (2) Register name Bit size Unit Instruction register 8 bit Bypass register 1 bit ID register 32 bit Boundary register 113 bit Table 3-6. ID Register Definition Part number Organization ID [31:28] vendor revision no. ID [27:12] part no. ID [11:1] vendor ID no. ID [0] fix bit PD48576109-A 64M x 9 0000 0001 1001 1010 0111 00000010000 1 0001 0001 1001 1010 0111 00000010000 1 PD48576118-A 32M x 18 R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 45 of 51 PD48576109, PD48576118 Table 3-7. SCAN Exit Order Bit Signal name Bump Bit Signal name Bump Bit Signal name no. x9 x18 ID no. x9 1 DK DK K1 39 2 DK# DK# K2 3 CS# CS# 4 REF# 5 Bump x18 ID no. x9 x18 ID D6 D11 R11 77 D1 D1 C11 40 D6 D11 R11 78 D1 D1 C11 L2 41 D5 D10 P11 79 Q1 Q1 C10 REF# L1 42 D5 D10 P11 80 Q1 Q1 C10 WE# WE# M1 43 Q5 Q10 P10 81 D0 D0 B11 6 A17 A17 M3 44 Q5 Q10 P10 82 D0 D0 B11 7 A16 A16 M2 45 D4 D9 N11 83 Q0 Q0 B10 8 A18 A18 N1 46 D4 D9 N11 84 Q0 Q0 B10 9 A15 A15 P1 47 Q4 Q9 N10 85 DNU Q4 B3 10 DNU Q14 N3 48 Q4 Q9 N10 86 DNU Q4 B3 11 DNU Q14 N3 49 DM DM P12 87 DNU D4 B2 12 DNU D14 N2 50 A19 A19 N12 88 DNU D4 B2 13 DNU D14 N2 51 A11 A11 M11 89 DNU Q5 C3 14 DNU Q15 P3 52 A12 A12 M10 90 DNU Q5 C3 15 DNU Q15 P3 53 A10 A10 M12 91 DNU D5 C2 16 DNU D15 P2 54 A13 A13 L12 92 DNU D5 C2 17 DNU D15 P2 55 A14 A14 L11 93 DNU Q6 D3 18 DNU QK1 R2 56 BA1 BA1 K11 94 DNU Q6 D3 19 DNU QK1# R3 57 CK# CK# K12 95 DNU D6 D2 20 DNU D16 T2 58 CK CK J12 96 DNU D6 D2 21 DNU D16 T2 59 BA0 BA0 J11 97 DNU D7 E2 22 DNU Q16 T3 60 A4 A4 H11 98 DNU D7 E2 23 DNU Q16 T3 61 A3 A3 H12 99 DNU Q7 E3 24 DNU D17 U2 62 A0 A0 G12 100 DNU Q7 E3 25 DNU D17 U2 63 A2 A2 G10 101 DNU D8 F2 26 DNU Q17 U3 64 A1 A1 G11 102 DNU D8 F2 27 DNU Q17 U3 65 A20 A20 E12 103 DNU Q8 F3 28 ZQ ZQ V2 66 QVLD QVLD F12 104 DNU Q8 F3 29 Q8 Q13 U10 67 Q3 Q3 F10 105 A21 A21 E1 30 Q8 Q13 U10 68 Q3 Q3 F10 106 A5 A5 F1 31 D8 D13 U11 69 D3 D3 F11 107 A6 A6 G2 32 D8 D13 U11 70 D3 D3 F11 108 A7 A7 G3 33 Q7 Q12 T10 71 Q2 Q2 E10 109 A8 A8 G1 34 Q7 Q12 T10 72 Q2 Q2 E10 110 BA2 BA2 H1 35 D7 D12 T11 73 D2 D2 E11 111 A9 A9 H2 36 D7 D12 T11 74 D2 D2 E11 112 NF NF J2 37 Q6 Q11 R10 75 QK0 QK0 D11 113 NF NF J1 38 Q6 Q11 R10 76 QK0# QK0# D10 Note Any unused balls that are in the order will read as a logic "0". R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 46 of 51 PD48576109, PD48576118 JTAG Instructions Many different instructions (28) are possible with the 8-bit instruction register. All used combinations are listed in Table 3-8, Instruction Codes. These six instructions are described in detail below. The remaining instructions are reserved and should not be used. The TAP controller used in this RAM is fully compliant to the 1149.1 convention. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. Table 3-8 Instructions EXTEST Instruction Code [7:0] Description 0000 0000 The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-scan register cells at output pins are used to apply test vectors, while those at input pins capture test results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST, the output drive is turned on and the PRELOAD data is driven onto the output pins. IDCODE 0010 0001 The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. SAMPLE / PRELOAD 0000 0101 SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input and Q pins into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable input will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins. CLAMP 0000 0111 When the CLAMP instruction is loaded into the instruction register, the data driven by the output balls are determined from the values held in the boundary scan register. Selects the bypass register to be connected between TDI and TDO. Data driven by output balls are determined from values held in the boundary scan register. High-Z 0000 0011 The High-z instruction causes the boundary scan register to be connected between the TDI and TDO. This places all RAMs outputs into a High-Z state. Selects the bypass register to be connected between TDI and TDO. All outputs are forced into high impedance state. BYPASS 1111 1111 When the BYPASS instruction is loaded in the instruction register, the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Reserved for Future Use - The remaining instructions are not implemented but are reserved for future use. Do not use these instructions. R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 47 of 51 PD48576109, PD48576118 TAP Controller State Diagram 1 Test-Logic-Reset 0 1 0 1 Run-Test / Idle 1 Select-DR-Scan Select-IR-Scan 0 0 1 1 Capture-DR Capture-IR 0 0 0 Shift-DR 0 Shift-IR 1 1 1 1 Exit1-DR Exit1-IR 0 0 0 Pause-DR 1 1 0 0 Exit2-DR Exit2-IR 1 1 Update-DR 1 R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 0 Pause-IR Update-IR 0 1 0 Page 48 of 51 PD48576109, PD48576118 4. Package Dimension 144-PIN TAPE FBGA ( BGA) (18.5x11) D w S A D1 D A ZE ZD B SD eD 12 11 10 9 8 7 6 5 4 3 2 1 A E1 E SE eE 4xC0.2 INDEX MARK E2 V U T R P N M L K J H G F E D C B A w S B INDEX MARK D2 10 A y1 S A2 S y S A1 b (UNIT:mm) Detail of A pa rt x M S AB A3 ITEM DIMENSIONS D 18.50 0.10 D1 17.90 D2 14.52 E 11.000.10 E1 10.70 E2 2.184 w 0.20 A 1.070.10 A1 0.390.05 A2 0.68 A3 0.08 MAX. eD 1.00 eE 0.80 SD 0.50 SE 2.00 b 0.510.05 x 0.15 y 0.10 y1 0.20 ZD 0.75 ZE 1.10 P144FF-80-DW1 R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 49 of 51 PD48576109, PD48576118 5. Recommended Soldering Condition Please consult with our sales offices for soldering conditions of these products. Types of Surface Mount Devices PD48576109FF-DW1 : 144-pin TAPE FBGA (18.5 x 11) PD48576118FF-DW1 : 144-pin TAPE FBGA (18.5 x 11) Quality Grade * A quality grade of the products is "Standard". * Anti-radioactive design is not implemented in the products. * Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to the ground and so forth. R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 Page 50 of 51 PD48576109, PD48576118 Revision History Rev. Date Rev.0.01 Rev.1.00 '10.11.08 '11.09.27 Rev.2.00 '12.05.10 Rev.3.00 '12.10.01 Page P3 P11 P15 P38, P39 P40, P41 P17,P18 P34 Description Summary New Preliminary Data Sheet New Data Sheet Add Lead device Update DC Characteristics Update Thermal Impedance Update Input Slew Rate Derating Update Power-On Sequence All trademarks and registered trademarks are the property of their respective owners. C - 51 Notice 1. All information included in this document is current as of the date this document is issued. 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You may not use any Renesas Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support. "Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. 9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada Tel: +1-905-898-5441, Fax: +1-905-898-3220 Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K Tel: +44-1628-585-100, Fax: +44-1628-585-900 Renesas Electronics Europe GmbH Arcadiastrasse 10, 40472 Dusseldorf, Germany Tel: +49-211-65030, Fax: +49-211-6503-1327 Renesas Electronics (China) Co., Ltd. 7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China Tel: +86-10-8235-1155, Fax: +86-10-8235-7679 Renesas Electronics (Shanghai) Co., Ltd. Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898 Renesas Electronics Hong Kong Limited Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong Tel: +852-2886-9318, Fax: +852 2886-9022/9044 Renesas Electronics Taiwan Co., Ltd. 13F, No. 363, Fu Shing North Road, Taipei, Taiwan Tel: +886-2-8175-9600, Fax: +886 2-8175-9670 Renesas Electronics Singapore Pte. Ltd. 1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632 Tel: +65-6213-0200, Fax: +65-6278-8001 Renesas Electronics Malaysia Sdn.Bhd. Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: +60-3-7955-9390, Fax: +60-3-7955-9510 Renesas Electronics Korea Co., Ltd. 11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea Tel: +82-2-558-3737, Fax: +82-2-558-5141 (c) 2012 Renesas Electronics Corporation. All rights reserved. Colophon 1.1