7 XC1700D Family of > XILINX Serial Configuration PROMs November 25, 1997 (Version 1.1) Product Specification Features Description * Extended family of one-time programmable (OTP) The XC1700 family of serial configuration PROMs (SCPs) bit-serial read-only memories used for storing the provides an easy-to-use, cost-effective method for storing configuration bitstreams of Xilinx FPGAs Xilinx FPGA configuration bitstreams. * On-chip address counter, incremented by each rising edge on the clock input * Simple interface to the FPGA requires only one user 1/0 pin When the FPGA is in master serial mode, it generates a configuration clock that drives the SCP. A short access time after the rising clock edge, data appears on the SCP DATA . . . output pin that is connected to the FPGA DIN pin. The * Cascadable for storing longer or multiple bitstreams FPGA generates the appropriate number of clock puises to * Programmable reset polarity (active High or active Low) complete the configuration. Once configured, it disables the for compatibility with different FPGA solutions SCP. When the FPGA is in slave mode, the SCP and the XC17 128D or XC17256D supports XC4000 fast FPGA must both be clocked by an incoming signal. configuration mode (12.5 MHz) * Low-power CMOS EPROM process Multiple devices can be concatenated by using the CEO * Available in 5 V and 3.3 V versions output to drive the CE input of the following device. The Available in plastic and ceramic packages, and clock inputs and the DATA outputs of all SCPs in this chain commercial, industrial and military temperature ranges are interconnected. All devices are compatible and can be * Space efficient 8-pin DIP, 8-pin SOIC, 8-pin VOIC, or cascaded with other members of the family. 20-pin surface-mount packages. Far device programming, the XACT development system * Programming support by leading programmer compiles the FPGA design file into a standard Hex format, manufacturers. which is then transferred to the programmer. Veco Vpp GND ce CEO RESET/ OE or OE/ RESET CLK Address Counter EPROM Cel DATA Matrix X3185 Figure 1: Simplified Block Diagram (does not show programming circuit) November 25, 1997 (Version 1.1) 5-11XC1700D Family of Serial Configuration PROMs Pin Description DATA Data output, 3-stated when either CE or OE are inactive. During programming, the DATA pin is 1/0. Note that OE can be programmed to be either active High or active Low. CLK Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active. RESET/OE When High, this input holds the address counter reset and 3-states the DATA output. The polarity of this input pin is programmable as either RESET/OE or OE/RESET. To avoid contusion, this document describes the pin as RESET/OE, although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at zero, and the DATA output is 3-stated. The polarity of this input is programmable. The default is active High RESET, but the preferred option is active Low RESET, because it can be driven by the FPGAs INIT pin. The polarity of this pin is controlled in the programmer inter- face. This input pin is easily inverted using the Xilinx HW- 130 programmer software. Third-party programmers have different methods to invert this pin. CE When High, this pin disables the internal address counter, 3-states the DATA output, and forces the device into low-igg standby mode. CEO Chip Enable output, to be connected to the CE input of the next SCP in the daisy chain. This output is Low when the CE and OE inputs are both active AND the internal address counter has been incremented beyond its Terminal Count (TC) value. In other words: when the PROM has been read, CEO will follow CE as long as OE is active. When OE goes inactive, CEG stays High until the PROM is reset. Note that OE can be programmed to be either active High or active Low. Vpp Programming voltage. No overshoot above the specified max voltage is permitted on this pin. For normal read oper- ation, this pin must be connected to Voc. Failure to do so may lead to unpredictable, temperature-dependent opera- tion and severe problems in circuit debugging. Do not leave VPP floating! Vec and GND Vcc is positive supply pin and GND is ground pin. Serial PROM Pinouts i 8-Pin 20-Pin DATA 1 2 CLK 2 4 -RESET/OE (OE/RESET) 3 6 CE 4 8 'GND 5 10 CEO 6 14 Vep 7 17 Vec 8 30 Capacity Device Configuration Bits XC1718D or L 18,144 XC1736D 36,288 XC1765D or L 65,536 XC17128D or 131,072 XC17256D ork 262,144 XC17612L 524,288 XC1701 orl 1,048,576 5-12 November 25, 1997 (Version 1.1)Number of Configuration Bits, Including Header for all Xilinx FPGAs and Compatible SCP Type Device Configuration Bits scp XC3x20A/L 14,819 XC1718D XC3x30A/L 22,216 XC1736D XC3x42A/L. 30,824 XC1736D XC3x64A/L 46,104 XC1765D XC3x90A/L 64,200 XC1765D XC3195A 94,984 XC17128D XC4003E 53,984 XC1765D XC4005E 95,008 XC17128D/L XC4006E 119,840 XC17128D XC4008E 147,552 XC17256D XC4010E 178,144 X017256D/L XC4013E 247,968 XC17256D/. XC4020E 329,312 XCi1701. XC4025E 422,176 XC1701 XC4005XL "451,960 XC17256L -XC4010XL 283,424 XC17512L 'XC4013XL 393,623 XC17512L. XC4020XL 521,880 XC17512L XC4028EX/XL 668,184 XC1701L XC4036EX/XL 832,528 ~ XC1701L XC4044XL 1,014,928 XC1701L XC4052XL 1,215,368 XC1701L + XC17256L XC4062XL 1,433,864 XCI701L + XC17512L XC4085XL 1,924,992 2 XC1701L XC5202 42,416 XC1765D XC5204 70,704 XC17128D XC5206 "106,288 XC17128D XC5210 165,488 XC17256D XC5215 237,744 XC17256D Controlling Serial PROMs Most connections between the FPGA device and the Serial PROM are simple and self-explanatory. The DATA output(s) of the of the Serial PROM(s) drives the DIN input of the lead FPGA device. * The master FPGA CCLK output drives the CLK input(s) of the Serial PROM(s). * The CEO output of a Serial PROM drives the CE input of the next Serial PROM in a daisy chain (if any). The RESET/OE input of all Serial PROMs is best driven by the INIT output of the XC3000 or XC4000 lead FPGA device. This connection assures that the Serial PROM address counter is reset before the start of any (reconfiguration, even when a reconfiguration is initiated by a Voc glitch. Other methods such as driving RESET/OE from LDC or system reset assume that the Serial PROM internal power-on-reset is always $= XILINX in step with the FPGAs internal power-on-reset, which may not be a safe assumption. The CE input of the lead (or only) Serial PROM is driven by the DONE/PRGM or DONE output of the lead FPGA device, provided that DONE/PRGM is not permanently grounded. Otherwise, CD can be used to drive CE, but must then be unconditionally High during user operation. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA maximum. FPGA Master Serial Mode Summary The I/O and logic functions of the Logic Cell Array and their associated interconnections are established by a configu- ration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Mode, the FPGA automatically loads the configuration program from an external memory. The Serial Configuration PROM has been designed for compatibility with the Master Serial Mode. Upon power-up or reconfiguration, an FPGA enters the Master Serial Mode whenever all three of the FPGA mode- select pins are Low (MO=0, M1=0, M2=0). Data is read from the Serial Configuration PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated during con- figuration. Master Serial Mode provides a simple configuration inter- face. Only a serial data line and two control fines are required to configure an FPGA. Data from the Serial Con- figuration PROM is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK. if the user-programmable, dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. The XC3000 and XC4000 families take care of this auitomatically with an on- chip default pull-up resistor. With XC2000-family devices, the user must either configure DIN as an active output, or provide a defined level, e.g., by using an external pull-up resistor, if DIN is configured as an input. Programming the FPGA With Counters Unchanged Upon Completion When multiple FPGA-configurations for a single FPGA are stored in a Serial Configuration PROM, the OE pin should be tied Low. Upon power-up, the internal address counters are reset and configuration begins with the first program stored in memory. Since the OE pin is held Low, the address counters are left unchanged after configuration is complete. Therefore, to reprogram the FPGA with another program, the D/P line is pulled Low and configuration begins at the last value of the address counters. November 25, 1997 (Version 1.1)XC1700D Family of Serial Configuration PROMs This method fails if a user applies RESET during the FPGA configuration process. The FPGA aborts the configuration and then restarts a new configuration, as intended, but the Serial PROM does not reset its address counter, since it never saw a High level on its OE input. The new configura- tion, therefore, reads the remaining data in the PROM and interprets it as preamble, length count etc. Since the FPGA is the master, it issues the necessary. number of CCLK pulses, up to 16 million (224) and D/P goes High. However, the FPGA configuration will be completely wrong, with potential contentions inside the FPGA and on its output pins. This method must, therefore, never be used when there is any chance of external reset during configuration. Cascading Serial Configuration PROMs For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cas- caded SCPs provide additional memory. After the fast bit from the first SCP is read, the next clock signal to the SCP asserts its CEO output Low and disables its DATA line. The second SCP recognizes the Low level on its CE input and enables its DATA output. See Figure 2. After configuration is complete, the address counters of all cascaded SCPs are reset if the FPGA RESET pin goes Low, assuming the SCP reset polarity option has been inverted. To reprogram the FPGA with another program, the D/P line goes Low and configuration begins where the address counters had stopped. In this case, avoid contention between DATA and the configured 1/O use of DIN. 5-14 November 25, 1997 (Version 1.1)$< XILINX * if Readback is Activated, a ; * +5V 5-kQ Resistor is I | I Required in Series With M1 Mo M1 PWRDWN During Configuration = r | the 5 kQ M2 Pull-Down | DOUT Resistor Overcomes the L--_ | ~1 m2 Li, OPTIONAL internal Pull-Up, 1 Daisy-chained but it Alows M2 to | ~~] HDC FPGAs with be User /O. Different General- 4 Loc Configurations Purpose ol INIT User /O | Pins | I ) | : + Other | | VO Pins 4000 OPTIONAL ie A ] Slave FPGAs Device with Identical Configurations +5 V | | rT RESET ol RESET i | jot oon 1 Vcc -Vpp | DIN DATA 4 DATA CCLK CLK L.____-] CLK Cascaded | -- SCP I Serial i D/P -_] CE CEO pc] CE Memory | iNiT OB/RESET [+] OB/MESET Da ee 1 {Low Resets the Address Pointer) CCGLK (OUTPUT) Ke | on x \ Y (oureun X x xX 6090 Figure 2: Master Serial Mode. The one-time-programmable Serial Configuration PROM supports automatic loading of configuration programs. Multiple devices can be cascaded to support additional FPGA. An early D/P inhibits the PROM data output one CCLK cycle before the FPGA I/Os become active. November 25, 1997 (Version 1.1) 5-15XC1700D Family of Serial Configuration PROMs Standby Mode The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high imped- ance state regardless of the state of the OE input. Table 1: Truth Table for XC1700 Control Inputs Programming the XC1700 Family Serial PROMs The devices can be programmed cn programmers supplied by Xilinx or qualified third-party vendors. The user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. The wrong choice can permanently damage the device. Control Inputs Outputs Internal Address RESET CE DATA CEO loc Inactive Low if address < TC: increment active High active if address > TC: dont change 3-state Low reduced Active Low Held reset 3-state High active Inactive High Nat changing 3-state High standby Active High Held reset 3-state High standby Notes: 1. The XC1700 RESET input has programmable polarity 2. TC = Terminal Count = highest address value. TC+1 = address 0. November 25, 1997 (Version 1.1)$< XILINX XC1718D, XC1736D, XC1765D, XC17128D and XC17256D Absolute Maximum Ratings Symbol Description Units Voc Supply voltage relative to GND -0.5 to +7.0 Vv Vep Supply voltage relative to GND -0.5 to +12.5 Vv VIN Input voltage relative to GND -0.5 to Vee +0.5 Vv Vrs Voltage applied to 3-state output -0.5 to Voc +0.5 Vv Tste Storage temperature (ambient) -65 to +150 C Tso. Maximum soldering temperature (10 s @ 1/16 in.) +260 C Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions Symbol Description Min Max Units Vee Commercial Supply voltage relative to GND 0C to +70C junction 4.75 5.25 Vv Industrial Supply voltage relative to GND -40C to +85C junction 4.50 5.50 Vv Military Supply voltage relative to GND -55C to +125C case 4.50 5.50 Vv DC Characteristics Over Operating Condition Symboi Description Min Max Units Vie High-level input voltage 2.0 Voc Vv Vit Low-level input voltage 0 0.8 Vv Vou High-level output voltage (loy = -4 mA) Commercial 3.86 Vv Vor Low-level output voltage (ig, = +4 mA) 0.32 Vv Vou High-level output voltage (igy = -4 mA) Industrial 3.76 Vv Vot Low-level output voltage (Io, = +4 mA) 0.37 Vv Vou High-level output voltage (Igy = -4 mA) Military 3.7 Vv Vor Low-level output voltage (Io, = +4 mA) 0.4 v Ioca Supply current, active mode 10.0 mA lees Supply current, standby mode, XC17128D, XC17256D 50.0 pA Supply current, standby mode, XC1718D, XC1736D, XC1765D 15 mA IL input or output leakage current -10.0 10.0 pA Note: During normal read operation Vpp must be connected to Vec November 25, 1997 (Version 1.1) ; 5-17XC1700D Family of Seriai Configuration PROMs XC1718L, XC1765L, XC17128L and XC17256L Absolute Maximum Ratings Symbol Description Units Voc Supply voltage relative to GND -0.5 to +6.0 v Vpp Supply voltage relative to GND -0.5 to +12.5 Vv Vin Input voltage with respect to GND -0.5 to Veg +0.5 Vv Vig Voltage applied to 3-state output 0.5 to Veg +0.5 Vv Tstg Storage temperature (ambient) -65 to +150 C Tso. Maximum soldering temperature (10s @ 1/16 in.) +260 C Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not irnplied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions Symbol Description Min Max Units Vee Commercial Supply voltage relative to GND 0C to +70C junction 3.0 3.6 Vv DC Characteristics Over Operating Condition Symbol Description Min Max Units Vin High-level input voltage 2.0 Veco v Vit Low-level input voltage 0 0.8 Vv Vou High-level output voltage (Igy = -4 MA) 2.4 Vv Vou Low-level output voltage (Io, = +4 mA) 0.4 V loca Supply current, active mode 5.0 mA locs Supply current, standby mode, XC1718L, XC1765L 1.5 mA Supply current, standby mode, XC17128L, XC17265L 50.0 pA I Input or output leakage current -10.0 10.0 pA Note: During normal read operation Vpp must be connected to Voc 5-18 November 25, 1997 (Version 1.1)$= XILINX AC Characteristics Over Operating Condition e N RESET/OE \ &) THoe po The i Tue ) Tove | i CLK @ J | Toe a) ~ Teac f 6) tor ~ @ Tce \ 7 DATA X K } d I ~ @Tox X2634 ner ep XC1718L. XC17128D XC17128L Symboi Description XC1765D XC1765L XC17256D XC17256L Units Min | Max | Min | Max | Min | Max | Min | Max 1 [Tog [OE to Data Delay 45 45 25 30 ns 2 |Tce {CE to Data Delay 60 60 45 60 ns 3 |Teac |CLK to Data Delay 150 200 50 60 ns 4 [Toy {Data Hold From CE, OE, or CLK 0 0 0 0 ns 5 |Tpe |CE or OE to Data Float Delay? 50 50 et) 50 ns 6 |Teyc | Clock Periods 200 400 80 100 ns 7 |Tye |CLK Low Time? 100 100 20 25 ns 8 |THC |CLK High Time? 100 100 20 25 ns 9 |TSCE |CE Setup Time to CLK (to guarantee 25 40 20 25 ns proper counting) 10 |Tuce | CE Hold Time to CLK (to guarantee 0 0 0 0 ns proper counting) 11 |Tuoe | OE Hold Time (guarantees counters are | 100 100 20 25 ns reset) Notes: 1. AC test load = 50 pF 2. Float delays are measured with minimum tester ac load and maximum dc load. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with V) = 0.0 V and Vj, = 3.0 V. November 25, 1997 (Version 1.1) 5-19XC1700D Family of Serial Contiguration PROMs AC Characteristics Over Operating Condition (continued) RESET/OE fo \ CLK ee DATA First Bit | + Groce &6 \ G4 Toce ->| be > |. 64 Toce ates veraep | xet7isL | xct71ze0 | xc17128L Symbol Description XC1765D XC1765L XC17256D XC17256L Units Min | Max | Min | Max | Min | Max | Min | Max 12 [Tepe |CLK to Data Float Delay 50 50 50 50 ns 13 [Tock |GLK to CEO Delay 65 65 30 30 ns 14 {/Toce |CE to CEO Delay 45 45 35 35 ns 15|Toor [RESET/OE to CEO Delay 40 40 30 30 ns Notes: 1. AC test load = 50 pF 2. Float delays are measured with minimum tester ac load and maximum de load. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with Vy, = 0.0 V and Vy; = 3.0 V. 5-20 November 25, 1997 (Version 1.1)2< XILINX Ordering Information XC1736D - PC20 C Device Number --________ Operating Range/Processing xor7t 80 C = Commercial (0 to +70C) a | = Industrial (~40 to +85C XC1736D Package Type - stic DIP M = Military (~55 to peed xe r7es0 Bde = Bn CoP ete te ee x17 S8D SO8 = &Pin Plastic Small-Outline Package STD-883 Level B compliant XC17128L VO8 = 8-Pin Plastic Small-Outline Thin Package XC17256D PC20 = 20-Pin Plastic Leaded Chip Carrier XC17256L Valid Ordering Combinations XC17128DPD8C XC1718DPD8C XC17256DPD8C XC1736DPD8C XC1765DPD8C XC17128DVO8G XC1718DSO8C XC17256DVO8C XC1736DS08C XC1765DSO08C XC17128DPC20C XC1718DVO8C XC17256DPC20C XC1736DVO8C XC1765DVO8C XC17128DPD8I XC1718DPC20C XC17256DPD8! XG1736DPC20C XC1765DPC20C XC17128DV08! XC1718DPD8I XC17256DVO8I XC1736DPD8l XC1765DPD8I XC17128DPC20! XC1718DSO8! XC17256DPC20I XC1736DS08! XC1765DS08i XC017128DDD8M XC1718DVO8I XC17256DDD8M XC1736DVO8I XC1765DVO8I XC1718DPC20! XC17256DDD8B XC1736DPC20I XC1765DPC201 XC1736DDD8M XC1765DDD8M XC17650DD8B XC17128LPD8C XC1718LPD8c XC17256LPD8C XC1765LPD8C XC17128LVO8C XC1718LSO8C AC 17256LVO8C XC1765LSO08C XC1712BLPC20C XC1718LVO8C XC17256LPC20C XC1765LVO8C XC17128LPD81 XC1718LPC20C XC17256LPD8! XC1765LPC20C XC17128LVO8! XC1718LPD8I XC17256LVOBI XC1765LPD8i XCi7128LPC20! XC1718LSO08! XC17256LPC201 XC1765LS08! XC1718LVO8I XC1765LVO8I XC1718LPC201 XC1765LPC201 Marking Information Due to the smail size of the serial PROM package, the complete ordering part number cannot be marked on the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows. 1736D P C Lo Operating Range/Processing Device Number XC1718D = Commercial (0 to +70C) XC1718L Package Type r = Industrial (-40 to +85C) XC1736D P <x 8-Pin Plastic DIP M = Military (~55 to +125C} XC1765D D = 8-Pin CerDIP B = Military (~55 to +125C} XC17651. S = 8-Pin Plastic Smail-Outline Package MIL-STD-883 Level B compliant XC17128D VV = 8-Pin Plastic Small-Outline Thin Package XC17128L J = 20-Pin Plastic Leaded Chip Carrier XC17256D XC17256L November 25, 1997 (Version 1.1) 5-21