16-Bit, 2 MSPS/1 MSPS/500 kSPS,
Precision, Pseudo Differential, SAR ADCs
Data Sheet
AD4000/AD4004/AD4008
Rev. C Document Feedback
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FEATURES
Throughput: 2 MSPS/1 MSPS/500 kSPS options
INL: ±1.0 LSB maximum
Guaranteed 16-bit, no missing codes
Low power
9.75 mW at 2 MSPS, 4.9 mW at 1 MSPS, 2.5 mW at 500 kSPS
(VDD only)
70 µW at 10 kSPS, 14 mW at 2 MSPS (total)
SNR: 93 dB typical at 1 kHz, VREF = 5 V; 90 dB typical at 100 kHz
THD: −115 dB typical at 1 kHz, VREF = 5 V; −95 dB typical at 100 kHz
Ease of use features reduce system power and complexity
Input overvoltage clamp circuit
Reduced nonlinear input charge kickback
High-Z mode
Long acquisition phase
Input span compression
Fast conversion time allows low SPI clock rates
SPI-programmable modes, read/write capability, status word
Pseudo differential (single-ended) analog input range
0 V to VREF with VREF from 2.4 V to 5.1 V
Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface
SAR architecture: no latency/pipeline delay, valid first conversion
First conversion accurate
Guaranteed operation: −40°C to +125°C
SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface
Ability to daisy-chain multiple ADCs and busy indicator
10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP
APPLICATIONS
Automatic test equipment
Machine automation
Medical equipment
Battery-powered equipment
Precision data acquisition systems
GENERAL DESCRIPTION
The AD4000/AD4004/AD4008 are low noise, low power, high
speed, 16-bit, precision successive approximation register (SAR)
analog-to-digital converters (ADCs). The AD4000, AD4004,
and AD4008 offer 2 MSPS, 1 MSPS, and 500 kSPS throughputs,
respectively. They incorporate ease of use features that reduce
signal chain power consumption, reduce signal chain complexity,
and enable higher channel density. The high-Z mode, coupled
with a long acquisition phase, eliminates the need for a dedicated
high power, high speed ADC driver, thus broadening the range
of low power precision amplifiers that can drive these ADCs
directly while still achieving optimum performance. The input
span compression feature enables the ADC driver amplifier and
the ADC to operate off of common supply rails without the need
for a negative supply while preserving the full ADC code range.
The low serial peripheral interface (SPI) clock rate requirement
reduces the digital input/output power consumption, broadens
processor options, and simplifies the task of sending data across
digital isolation.
Operating from a 1.8 V supply, the AD4000/AD4004/AD4008
sample an analog input (IN+) from 0 V to VREF with respect to
a ground sense (IN−) with VREF ranging from 2.4 V to 5.1 V.
The AD4000 consumes only 14 mW at 2 MSPS with a minimum
SCK rate of 70 MHz in turbo mode, the AD4004 consumes only
7 mW at 1 MSPS, and the AD4008 consumes only 3.5 mW at
500 kSPS. The AD4000/AD4004/AD4008 all achieve ±1.0 LSB
integral nonlinearity error (INL) maximum, guaranteed no
missing codes at 16 bits, and 93 dB signal-to-noise ratio (SNR)
for 1 kHz inputs. The reference voltage is applied externally and
can be set independently of the supply voltage.
The SPI-compatible versatile serial interface features seven
different modes including the ability, using the SDI input, to
daisy-chain several ADCs on a single 3-wire bus, and provides
an optional busy indicator. The AD4000/AD4004/AD4008 are
compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the
separate VIO supply.
The AD4000/AD4004 are available in a 10-lead MSOP and a
10-lead LFCSP, and the AD4008 is available in a 10-lead LFCSP,
with operation specified from −40°C to +125°C. The devices are
pin compatible with the 18-bit, 2 MSPS AD4003 (see Table 8).
FUNCTIONAL BLOCK DIAGRAM
GND
IN+
IN–
SDI
SCK
SDO
CNV
AD4000/
AD4004/
AD4008
16-BIT
SAR ADC
SERIAL
INTERFACE
VIO
REF VDD
V
REF
0
V
REF
/2 HIGH-Z
MODE
CLAMP SPAN
COMPRESSION
TURBO
MODE
STATUS
BITS
2.4V TO 5.1V 1.8V
10µF
1.8V TO 5V
3-W IRE O R 4- WIRE
SPI INT E RFACE
(DAI SY CHAIN, CS )
14956-001
Figure 1.
AD4000/AD4004/AD4008 Data Sheet
Rev. C | Page 2 of 36
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
Timing Specifications .................................................................. 7
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 17
Circuit Information .................................................................... 17
Converter Operation .................................................................. 18
Transfer Functions...................................................................... 18
Applications Information .............................................................. 19
Typical Application Diagrams .................................................. 19
Analog Inputs ............................................................................. 20
Driver Amplifier Choice ........................................................... 21
Ease of Drive Features ............................................................... 22
Voltage Reference Input ............................................................ 23
Power Supply ............................................................................... 24
Digital Interface .......................................................................... 24
Register Read/Write Functionality........................................... 25
Status Word ................................................................................. 27
CS Mode, 3-Wire Turbo Mode ................................................. 28
CS Mode, 3-Wire Without Busy Indicator ............................. 29
CS Mode, 3-Wire with Busy Indicator .................................... 30
CS Mode, 4-Wire Turbo Mode ................................................. 31
CS Mode, 4-Wire Without Busy Indicator ............................. 32
CS Mode, 4-Wire with Busy Indicator .................................... 33
Daisy-Chain Mode ..................................................................... 34
Layout Guidelines....................................................................... 35
Evaluating the AD4000/AD4004/AD4008 Performance .......... 35
Outline Dimensions ....................................................................... 36
Ordering Guide .......................................................................... 36
Data Sheet AD4000/AD4004/AD4008
Rev. C | Page 3 of 36
REVISION HISTORY
10/2017—Rev. B to Rev. C
Changes to Features Section ............................................................ 1
Added Multiplexed Applications Section .................................... 21
Changes to Ordering Guide ........................................................... 36
9/2017—Rev. A to Rev. B
Added AD4008 ................................................................... Universal
Changes to Title, Features Section, General Description Section,
and Figure 1 ........................................................................................ 1
Changes to Table 1 ............................................................................ 4
Changes to Timing Specifications Section and Table 2................ 7
Changes to Table 4 ............................................................................ 8
Changes to Table 5 ............................................................................ 9
Changes to Typical Performance Characteristics Section Layout .. 11
Changes to Figure 19 ............................................................................... 13
Added Figure 25; Renumbered Sequentially ............................... 14
Changes to Figure 28 ...................................................................... 14
Change to Zero Error Definition, Terminology Section............ 16
Changes to Circuit Information Section and Table 8 ................. 17
Changes to Converter Operation Section and Note 1 and
Note 2, Table 9 ................................................................................. 18
Changes to High Frequency Input Signals Section, Figure 36
Caption, and Figure 37 Caption .................................................... 21
Added Figure 38 .............................................................................. 21
Changes to Input Span Compression Section, High-Z Mode
Section, Figure 40, and Figure 41 Caption ................................... 22
Changes to Figure 42 Caption, Figure 43 Caption, Power Supply
Section, and Figure 44 Caption ..................................................... 23
Changes to Figure 45, Digital Interface Section, and Table 11 ........ 24
Changes to Register Read/Write Functionality Section and
Figure 46 Caption ............................................................................ 25
Changes to CS Mode, 3-Wire Turbo Mode Section ................... 28
Changes to CS Mode, 3-Wire with Busy Indicator Section ....... 30
Changes to CS Mode, 4-Wire Turbo Mode Section ................... 31
Changes to CS Mode, 4-Wire with Busy Indicator Section ....... 33
Changes to Daisy-Chain Mode Section ....................................... 34
Changed Evaluating the AD4000/AD4004 Performance Section
to Evaluating the AD4000/AD4004/AD4008 Performance
Section .............................................................................................. 35
Changes to Evaluating the AD4000/AD4004/AD4008
Performance Section ....................................................................... 35
Changes to Ordering Guide ........................................................... 36
4/2017—Rev. 0 to Rev. A
Added AD4004 ................................................................... Universal
Changes to Title, Features Section, General Description Section,
and Figure 1 ....................................................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 6
Changes to Table 4 ............................................................................ 7
Changes to Table 7 ............................................................................ 9
Changes to Figure 19 and Figure 21 ............................................. 12
Changes to Figure 24 ...................................................................... 13
Added Figure 25; Renumbered Sequentially ............................... 13
Moved Terminology Section ......................................................... 15
Changes to Circuit Information Section and Table 8 ................. 16
Changes to Figure 33 ...................................................................... 18
Changes to RC Filters Section ....................................................... 19
Changes to High Frequency Input Signals Section .................... 20
Changes to High-Z Mode Section, Figure 38, and Figure 39 .... 21
Changes to Long Acquisition Phase Section and Figure 43 ...... 22
Changes to Digital Interface Section and Register Read/Write
Functionality Section ...................................................................... 23
Changes to Figure 45 ...................................................................... 24
Changes to CS Mode, 3-Wire Turbo Mode Section ................... 26
Added Figure 48 .............................................................................. 26
Changes to CS Mode, 4-Wire Turbo Mode ................................. 29
Added Figure 54 .............................................................................. 29
Changes to Figure 56 and Figure 57 ............................................. 30
Changes to Layout Guidelines Section and Evaluating the
AD4000/AD4004 Performance Section ....................................... 33
Updated Outline Dimensions ........................................................ 34
Changes to Ordering Guide Section ............................................. 34
10/2016—Revision 0: Initial Version
AD4000/AD4004/AD4008 Data Sheet
Rev. C | Page 4 of 36
SPECIFICATIONS
VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled,
turbo mode enabled, and sampling frequency (fS) = 2 MSPS for the AD4000, fS = 1 MSPS for the AD4004, and fS = 500 kSPS for the AD4008,
unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range
IN+ voltage (V
IN+
) − IN− voltage (V
IN−
)
0
V
REF
Operating Input Voltage VIN+ to GND −0.1 VREF + 0.1 V
VIN− to GND −0.1 +0.1 V
Span compression enabled 0.1 × VREF 0.9 × VREF V
Analog Input Current Acquisition phase, T = 25°C 0.3 nA
High-Z mode enabled, converting dc
input at 2 MSPS
1 µA
THROUGHPUT
Complete Cycle
AD4000 500 ns
AD4004 1000 ns
AD4008 2000 ns
Conversion Time 270 290 320 ns
Acquisition Phase1
AD4000
290
AD4004 790 ns
AD4008 1790 ns
Throughput Rate2
AD4000 0 2 MSPS
AD4004 0 1 MSPS
AD4008 0 500 kSPS
Transient Response3 150 ns
DC ACCURACY
No Missing Codes 16 Bits
Integral Nonlinearity Error (INL) −1.0 ±0.2 +1.0 LSB
T = 0°C to 85°C −0.8 ±0.2 +0.8 LSB
Differential Nonlinearity Error (DNL) −0.5 ±0.15 +0.5 LSB
Transition Noise 0.5 LSB
Zero Error
−4.5
+4.5
Zero Error Drift4 −0.55 +0.55 ppm/°C
Gain Error −20 ±3 +20 LSB
Gain Error Drift4 −0.92 +0.92 ppm/°C
Power Supply Sensitivity VDD = 1.8 V ± 5% 0.5 LSB
1/f Noise5 Bandwidth = 0.1 Hz to 10 Hz 6 µV p-p
AC ACCURACY
Dynamic Range 93.5 dB
Total RMS Noise 37 µV rms
fIN = 1 kHz, −0.5 dBFS, VREF = 5 V
Signal-to-Noise Ratio (SNR) 91 93 dB
Spurious-Free Dynamic Range (SFDR) 112 dB
Total Harmonic Distortion (THD) −115 dB
Signal-to-Noise-and-Distortion Ratio
(SINAD)
91 92.5 dB
Oversampled Dynamic Range Oversampling ratio (OSR) = 256,
VREF = 5 V
117 dB
Data Sheet AD4000/AD4004/AD4008
Rev. C | Page 5 of 36
Parameter Test Conditions/Comments Min Typ Max Unit
fIN = 1 kHz, −0.5 dBFS, VREF = 2.5 V
SNR 85.5 87.5 dB
SFDR 115 dB
THD −113 dB
SINAD
85.5
87
fIN = 100 kHz, −0.5 dBFS, VREF = 5 V
SNR 90 dB
THD −95 dB
SINAD 89 dB
fIN = 400 kHz, −0.5 dBFS, VREF = 5 V
SNR
85
THD −91 dB
SINAD 84 dB
−3 dB Input Bandwidth 10 MHz
Aperture Delay 1 ns
Aperture Jitter 1 ps rms
REFERENCE
Voltage Range, VREF 2.4 5.1 V
Current
V
REF
= 5 V
AD4000 2 MSPS 0.75 mA
AD4004 1 MSPS 0.325 mA
AD4008 500 kSPS 0.185 mA
INPUT OVERVOLTAGE CLAMP
IN+/IN− Current, IIN+/IIN− VREF = 5 V 50 mA
VREF = 2.5 V 50 mA
VIN+/VIN− at Maximum IIN+/IIN− VREF = 5 V 5.4 V
VREF = 2.5 V 3.1 V
V
IN+
/V
IN−
Clamp On/Off Threshold
V
REF
= 5 V
5.25
5.4
VREF = 2.5 V 2.68 2.8 V
Deactivation Time 360 ns
REF Current at Maximum IIN+ VIN+ > VREF 100 µA
DIGITAL INPUTS
Logic Levels
Input Low Voltage, VIL VIO > 2.7 V −0.3 +0.3 × VIO V
VIO ≤ 2.7 V −0.3 +0.2 × VIO V
Input High Voltage, V
IH
VIO > 2.7 V
0.7 × VIO
VIO + 0.3
VIO ≤ 2.7 V 0.8 × VIO VIO + 0.3 V
Input Low Current, IIL −1 +1 µA
Input High Current, IIH −1 +1 µA
Input Pin Capacitance 6 pF
DIGITAL OUTPUTS
Data Format Serial 16 bits, straight binary
Pipeline Delay Conversion results available
immediately after completed
conversion
Output Low Voltage, VOL ISINK = 500 µA 0.4 V
Output High Voltage, VOH ISOURCE = −500 µA VIO − 0.3 V
POWER SUPPLIES
VDD 1.71 1.8 1.89 V
VIO 1.71 5.5 V
Standby Current VDD and VIO = 1.8 V, T = 25°C 1.6 µA
AD4000/AD4004/AD4008 Data Sheet
Rev. C | Page 6 of 36
Parameter Test Conditions/Comments Min Typ Max Unit
Power Dissipation VDD = 1.8 V, VIO = 1.8 V, VREF = 5 V
10 kSPS, high-Z mode disabled 70 µW
500 kSPS, high-Z mode disabled 3.5 4.2 mW
1 MSPS, high-Z mode disabled 7 8.2 mW
2 MSPS, high-Z mode disabled
14
16
500 kSPS, high-Z mode enabled 4 5 mW
1 MSPS, high-Z mode enabled 8 9.9 mW
2 MSPS, high-Z mode enabled 16 19 mW
VDD Only 500 kSPS, high-Z mode disabled 2.5 mW
1 MSPS, high-Z mode disabled 4.9 mW
2 MSPS, high-Z mode disabled
9.75
REF Only 500 kSPS, high-Z mode disabled 0.9 mW
1 MSPS, high-Z mode disabled 1.9 mW
2 MSPS, high-Z mode disabled 3.75 mW
VIO Only 500 kSPS, high-Z mode disabled 0.1 mW
1 MSPS, high-Z mode disabled 0.2 mW
2 MSPS, high-Z mode disabled 0.5 mW
Energy per Conversion 7 nJ/sample
TEMPERATURE RANGE
Specified Performance TMIN to TMAX −40 +125 °C
1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the
AD4000, 1 MSPS for the AD4004, and 500 kSPS for the AD4008.
2 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. Refer to Table 4 for the maximum achievable
throughput for different modes of operation.
3 Transient response is the time required for the ADC to acquire a full-scale input step to ±0.5 LSB accuracy.
4 The minimum and maximum values are guaranteed by characterization, but not production tested.
5 See the 1/f noise plot in Figure 23.
Data Sheet AD4000/AD4004/AD4008
Rev. C | Page 7 of 36
TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled,
turbo mode enabled, and fS = 2 MSPS for the AD4000, fS = 1 MSPS for the AD4004, and fS = 500 kSPS for the AD4008, unless otherwise noted.
See Figure 2 for the timing voltage levels.
Table 2. Digital Interface Timing
Parameter Symbol Min Typ Max Unit
CONVERSION TIME—CNV RISING EDGE TO DATA AVAILABLE tCONV 270 290 320 ns
ACQUISITION PHASE1 tACQ
AD4000 290 ns
AD4004 790 ns
AD4008 1790 ns
TIME BETWEEN CONVERSIONS tCYC
AD4000 500 ns
AD4004 1000 ns
AD4008 2000 ns
CNV PULSE WIDTH (CS MODE)2 tCNVH 10 ns
SCK PERIOD (CS MODE)3 tSCK
VIO > 2.7 V 9.8 ns
VIO > 1.7 V 12.3 ns
SCK PERIOD (DAISY-CHAIN MODE)4 tSCK
VIO > 2.7 V 20 ns
VIO > 1.7 V 25 ns
SCK LOW TIME tSCKL 3 ns
SCK HIGH TIME tSCKH 3 ns
SCK FALLING EDGE TO DATA REMAINS VALID DELAY tHSDO 1.5 ns
SCK FALLING EDGE TO DATA VALID DELAY tDSDO
VIO > 2.7 V 7.5 ns
VIO > 1.7 V 10.5 ns
CNV OR SDI LOW TO SDO D15 MOST SIGNIFICANT BIT (MSB) VALID DELAY (CS MODE) tEN
VIO > 2.7 V 10 ns
VIO > 1.7 V 13 ns
CNV RISING EDGE TO FIRST SCK RISING EDGE DELAY tQUIET1 190 ns
LAST SCK FALLING EDGE TO CNV RISING EDGE DELAY
5
t
QUIET2
60
ns
CNV OR SDI HIGH OR LAST SCK FALLING EDGE TO SDO HIGH IMPEDANCE (CS MODE) tDIS 20 ns
SDI VALID SETUP TIME FROM CNV RISING EDGE tSSDICNV 2 ns
SDI VALID HOLD TIME FROM CNV RISING EDGE (CS MODE)
t
HSDICNV
2
ns
SCK VALID HOLD TIME FROM CNV RISING EDGE (DAISY-CHAIN MODE) tHSCKCNV 12 ns
SDI VALID SETUP TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE) tSSDISCK 2 ns
SDI VALID HOLD TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE) tHSDISCK 2 ns
1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the
AD4000, 1 MSPS for the AD4004, and 500 kSPS for the AD4008.
2 For turbo mode, tCNVH must match the tQUIET1 minimum.
3 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. Refer to Table 4 for the maximum achievable
throughput for different modes of operation.
4 A 50% duty cycle is assumed for SCK.
5 See Figure 22 for SINAD, SNR, and ENOB vs. tQUIET2.
X% VIO
1
Y% VIO
1
V
IH2
V
IL2
V
IL2
V
IH2
t
DELAY
t
DELAY
1
FOR VIO ≤ 2.7V, X = 80, AND Y = 20; FOR VIO > 2.7V, X = 70, AND Y = 30.
2
MINIMUM V
IH
AND MAXI M UM V
IL
USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 1.
14956-002
Figure 2. Voltage Levels for Timing
AD4000/AD4004/AD4008 Data Sheet
Rev. C | Page 8 of 36
Table 3. Register Read/Write Timing
Parameter Symbol Min Typ Max Unit
READ/WRITE OPERATION
CNV Pulse Width1 tCNVH 10 ns
SCK Period tSCK
VIO > 2.7 V 9.8 ns
VIO > 1.7 V 12.3 ns
SCK Low Time tSCKL 3 ns
SCK High Time tSCKH 3 ns
READ OPERATION
CNV Low to SDO D15 MSB Valid Delay tEN
VIO > 2.7 V 10 ns
VIO > 1.7 V 13 ns
SCK Falling Edge to Data Remains Valid tHSDO 1.5 ns
SCK Falling Edge to Data Valid Delay
t
DSDO
VIO > 2.7 V 7.5 ns
VIO > 1.7 V 10.5 ns
CNV Rising Edge to SDO High Impedance tDIS 20 ns
WRITE OPERATION
SDI Valid Setup Time from SCK Rising Edge tSSDISCK 2 ns
SDI Valid Hold Time from SCK Rising Edge tHSDISCK 2 ns
CNV Rising Edge to SCK Edge Hold Time tHCNVSCK 0 ns
CNV Falling Edge to SCK Active Edge Setup Time tSCNVSCK 6 ns
1 For turbo mode, tCNVH must match the tQUIET1 minimum.
Table 4. Achievable Throughput for Different Modes of Operation
Parameter Test Conditions/Comments Min Typ Max Unit
THROUGHPUT, CS MODE
3-Wire and 4-Wire Turbo Mode fSCK = 100 MHz, VIO ≥ 2.7 V 2 MSPS
fSCK = 80 MHz, VIO < 2.7 V 2 MSPS
3-Wire and 4-Wire Turbo Mode and Six Status Bits fSCK = 100 MHz, VIO ≥ 2.7 V 2 MSPS
fSCK = 80 MHz, VIO < 2.7 V 1.86 MSPS
3-Wire and 4-Wire Mode fSCK = 100 MHz, VIO ≥ 2.7 V 1.82 MSPS
fSCK = 80 MHz, VIO < 2.7 V 1.69 MSPS
3-Wire and 4-Wire Mode and Six Status Bits fSCK = 100 MHz, VIO ≥ 2.7 V 1.64 MSPS
fSCK = 80 MHz, VIO < 2.7 V 1.5 MSPS
Data Sheet AD4000/AD4004/AD4008
Rev. C | Page 9 of 36
ABSOLUTE MAXIMUM RATINGS
Note that the input overvoltage clamp cannot sustain the
overvoltage condition for an indefinite amount of time.
Table 5.
Parameter Rating
Analog Inputs
IN+, IN− to GND1 −0.3 V to VREF + 0.4 V
or ±130 mA2
Supply Voltage
REF, VIO to GND −0.3 V to +6.0 V
VDD to GND −0.3 V to +2.1 V
VDD to VIO −6 V to +2.4 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Lead Temperature Soldering
260°C reflow as per
JEDEC J-STD-020
ESD Ratings
Human Body Model 4 kV
Machine Model 200 V
Field Induced Charged Device Model 1.25 kV
1 See the Analog Inputs section for an explanation of IN+ and IN−.
2 Current condition tested over a 10 ms time interval.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 6. Thermal Resistance
Package Type1 θJA2 θJC3 Unit
RM-10 147 38 °C/W
CP-10-9
114
33
°C/W
1 Test Condition 1: thermal impedance simulated values are based upon use
of 2S2P JEDEC PCB. See the Ordering Guide.
2 θJA is the natural convection junction-to-ambient thermal resistance
measured in a one cubic foot sealed enclosure.
3 θJC is the junction-to-case thermal resistance.
ESD CAUTION
AD4000/AD4004/AD4008 Data Sheet
Rev. C | Page 10 of 36
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF
1
VDD
2
IN+
3
IN–
4
GND
5
VIO
10
SDI
9
SCK
8
SDO
7
CNV
6
14956-003
AD4000/
AD4004
TOP VIEW
(No t t o Scal e)
Figure 3. 10-Lead MSOP Pin Configuration
1REF
2VDD
3IN+
4IN–
5GND
10 VIO
9SDI
8SCK
7SDO
6CNV
AD4000/
AD4004/
AD4008
TOP VIEW
(No t t o Scal e)
14956-004
NOTES
1. CONNECT T HE E X P OSED P AD TO GND.
THIS CONNECTION IS NOT REQUIRED TO
MEET THE SPECIFI ED PERFORMANCE.
Figure 4. 10-Lead LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type 1 Description
1 REF AI Reference Input Voltage. The VREF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and must be
decoupled closely to the GND pin with a 10 µF, X7R ceramic capacitor.
2 VDD P 1.8 V Power Supply. The VDD range is 1.71 V to 1.89 V. Bypass VDD to GND with a 0.1 μF ceramic capacitor.
3
IN+
AI
Analog Input. This input is referred to analog ground sense pin (IN−). The device samples the voltage
differential between IN+ and IN− on the leading edge on CNV. The operating input range of IN+ − IN− is
0 V to VREF.
4 IN− AI Analog Input Ground Sense. Connect this pin to the analog ground plane or to a remote sense ground.
5 GND P Power Supply Ground.
6 CNV DI Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects
the interface mode of the device: daisy-chain mode or CS mode. In CS mode, the SDO pin is enabled
when CNV is low. In daisy-chain mode, the data is read when CNV is high.
7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock.
9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows.
Daisy-chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data
input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data
level on SDI is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator
feature is enabled. With CNV low, the device can be programmed by clocking in a 16-bit word on SDI on
the rising edge of SCK.
10 VIO P Input/Output Interface Digital Power. Nominally, this pin is at the same supply as the host interface (1.8 V,
2.5 V, 3 V, or 5 V). Bypass VIO to GND with a 0.1 μF ceramic capacitor.
N/A2 EPAD P Exposed Pad (LFCSP Only). Connect the exposed pad to GND. This connection is not required to meet
the specified performance.
1 AI is analog input, P is power, DI is digital input, and DO is digital output.
2 N/A means not applicable.
Data Sheet AD4000/AD4004/AD4008
Rev. C | Page 11 of 36
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled,
turbo mode enabled, and fS = 2 MSPS for the AD4000, fS = 1 MSPS for the AD4004, and fS = 500 kSPS for the AD4008, unless otherwise noted.
065536
CODE
0.5
–0.5
INL (LSB)
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
8192 16384 24576 32768 40960 49152 57344
+125°C
+25°C
–40°C
14956-200
Figure 5. INL vs. Code for Various Temperatures, VREF = 5 V
0.3
–0.3
INL (LSB)
–0.2
–0.1
0
0.1
0.2
065536
CODE
8192 16384 24576 32768 40960 49152 57344
+125°C
+25°C
–40°C
14956-201
Figure 6. INL vs. Code for Various Temperatures, VREF = 2.5 V
0.4
–0.4
INL (LSB)
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
065536
CODE
8192 16384 24576 32768 40960 49152 57344
14956-202
SPAN COMPRESSION ENABLED
HIG H- Z ENABLED
Figure 7. INL vs. Code, High-Z and Span Compression Modes Enabled,
VREF = 5 V
0.20
–0.20
DNL ( LSB)
065536
CODE
8192 16384 24576 32768 40960 49152 57344
+125°C
+25°C
–40°C
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
14956-203
Figure 8. DNL vs. Code for Various Temperatures, VREF = 5 V
0.20
–0.20
DNL ( LSB)
065536
CODE
8192 16384 24576 32768 40960 49152 57344
+125°C
+25°C
–40°C
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
14956-204
Figure 9. DNL vs. Code for Various Temperatures, VREF = 2.5 V
0.20
–0.20
DNL ( LSB)
065536
CODE
8192 16384 24576 32768 40960 49152 57344
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
14956-205
SPAN COMPRESSION ENABLED
HIG H-Z E NABLED
Figure 10. DNL vs. Code, High-Z and Span Compression Modes Enabled,
VREF = 5 V
AD4000/AD4004/AD4008 Data Sheet
Rev. C | Page 12 of 36
50000
0
32760
32780
CODE COUNT
ADC CODE
5000
10000
15000
20000
25000
30000
35000
40000
45000
32761
32762
32763
32764
32765
32766
32767
32768
32769
32770
32771
32772
32773
32774
32775
32776
32777
32778
32779
V
REF
= 2.5V
V
REF
= 5V
14956-206
Figure 11. Histogram of a DC Input at Code Center, VREF = 2.5 V and VREF = 5 V
0
–180
100 1k 10k 100k 1M
FUNDAM E NTAL AM P LITUDE (dB)
FREQUENCY ( Hz )
–160
–140
–120
–100
–80
–60
–40
–20 V
REF
= 5V
SNR = 92. 47dB
THD = –115.10d B
SINAD = 92.41d B
14956-207
Figure 12. 1 kHz, −0.5 dBFS Input Tone Fast Fourier Transform (FFT),
Wide View, VREF = 5 V
0
–1801k 10k 100k 1M
FUNDAM E NTAL AM P LITUDE (dB)
FREQUENCY ( Hz )
–160
–140
–120
–100
–80
–60
–40
–20 VREF = 5V
SNR = 90. 16 dB
THD = –94.52d B
SINAD = 88.33d B
14956-211
Figure 13. 100 kHz, −0.5 dBFS Input Tone FFT, Wide View
90000
0
32760
32780
CODE COUNT
ADC CODE
32761
32762
32763
32764
32765
32766
32767
32768
32769
32770
32771
32772
32773
32774
32775
32776
32777
32778
32779
V
REF
= 2.5V
V
REF
= 5V
10000
20000
30000
40000
50000
60000
70000
80000
14956-209
Figure 14. Histogram of a DC Input at Code Transition, VREF = 2.5 V and VREF = 5 V
0
–180
100 1k 10k 100k 1M
FUNDAM E NTAL AM P LITUDE (dB)
FRE Q UE NCY ( Hz )
–160
–140
–120
–100
–80
–60
–40
–20 V
REF
= 2.5V
SNR = 87. 54dB
THD = –112.33d B
SINAD = 87.49d B
14956-210
Figure 15. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, VREF = 2.5 V
0
–1801k 10k 100k 1M
FUNDAM E NTAL AM P LITUDE (dB)
FREQUENCY ( Hz )
–160
–140
–120
–100
–80
–60
–40
–20 VREF = 5V
SNR = 84. 65 dB
THD = –90.80d B
SINAD = 83.89d B
14956-208
Figure 16. 400 kHz, −0.5 dBFS Input Tone FFT, Wide View
Data Sheet AD4000/AD4004/AD4008
Rev. C | Page 13 of 36
94
93
92
91
90
89
88
87
SNR, S INAD (dB)
2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1
REFERENCE VOLTAGE (V)
15.3
14.3
ENOB (Bit s)
14.4
14.5
14.6
14.7
14.8
14.9
15.0
15.1
15.2
ENOB
SINAD
SNR
14956-213
Figure 17. SNR, SINAD, and Effective Number of Bits (ENOB) vs.
Reference Voltage, fIN = 1 kHz
SNR, S INAD (dB)
TEMPERATURE (°C)
14.90
14.95
15.00
15.05
15.10
15.15
91.4
91.6
91.8
92.0
92.2
92.4
92.6
92.8
93.0
93.2
ENOB (Bit s)
–40 –20 04020 60 80 100 120
SNR
SINAD
ENOB
14956-220
Figure 18. SNR, SINAD, and ENOB vs. Temperature, fIN = 1 kHz
14956-214
90
95
100
105
110
115
120
125
1 2 4 8 16 32 64 128 256 512 1024 2048
SNR (dB)
DECIMATION RATE
DYNAMIC RANGE
f
IN
= 1kHz
f
IN
= 10kHz
Figure 19. SNR vs. Decimation Rate for Various Input Frequencies, 2 MSPS
–110
–1182.4 5.1
THD (dB)
REFERENCE VOLTAGE (V)
THD
SFDR
–117
–116
–115
–114
–113
–112
–111
2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8
113
106
107
108
107
108
109
110
111
112
SFDR ( dB)
14956-216
Figure 20. THD and SFDR vs. Reference Voltage, fIN = 1 kHz
THD (dB)
TEMPERATURE (°C)
SFDR ( dB)
–40 –20 04020 60 80 100 120 102
103
104
105
106
107
108
109
110
111
–118
–116
–114
–112
–110
–108
–106
–104
–102
–100 THD
SFDR
14956-222
Figure 21. THD and SFDR vs. Temperature, fIN = 1 kHz
93.4
92.0 010 20 30 40 50 60 70
SNR, S INAD (dB)
t
QUIET2 (ns)
ENOB
SINAD
SNR
92.2
92.4
92.6
92.8
93.0
93.2
15.25
14.95
ENOB ( Bits)
15.00
15.05
15.10
15.15
15.20
14956-217
Figure 22. SNR, SINAD, and ENOB vs. tQUIET2
AD4000/AD4004/AD4008 Data Sheet
Rev. C | Page 14 of 36
ADC OUTPUT READING (µV)
TIME (Seconds)
0246810
948
949
950
951
952
953
954
955
14956-218
Figure 23. 1/f Noise for 0.1 Hz to 10 Hz Bandwidth, 50 kSPS, 2500 Samples
Averaged per Reading
–40 –20 0 4020 60 80 100 120
TEMPERATURE (°C)
OPERATING CURRENT (mA)
VDD HIGH-Z ENABLED
VDD HIGH-Z DISABLED
REF HIGH-Z ENABLED
REF HIGH-Z DISABLED
VIO HIGH-Z ENABLED
VIO HIGH-Z DISABLED
0
1
2
3
4
5
6
7
8
14956-226
Figure 24. Operating Current vs. Temperature, AD4000, 2 MSPS
–40 –20 0 4020 60 80 100 120
TEMPERATURE (°C)
OPERATING CURRENT (mA)
0
14956-325
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VDD HIGH-Z ENABLED
VDD HIGH-Z DISABLED
REF HIGH-Z ENABLED
REF HIGH-Z DISABLED
VIO HIGH-Z ENABLED
VIO HIGH-Z DISABLED
Figure 25. Operating Current vs. Temperature, AD4008, 500 kSPS
ZERO ERROR AND GAIN ERROR (LSB)
TEMPERATURE (°C)
–40 –20 0 4020 60 80 100 120
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
ZERO ERROR
GAIN ERROR
14956-223
Figure 26. Zero Error and Gain Error vs. Temperature
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
–40–20 0 20406080100120
OPER
A
TING CURRENT (mA)
TEMPERATURE (°C)
14956-232
VDD HIGH-Z ENABLED
VDD HIGH-Z DISABLED
REF HIGH-Z ENABLED
REF HIGH-Z DISABLED
VIO HIGH-Z ENABLED
VIO HIGH-Z DISABLED
Figure 27. Operating Current vs. Temperature, AD4004, 1 MSPS
14956-219
2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1
REFERENCE CURRENT (mA)
REFERENCE VOLTAGE (V)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
2MSPS
1MSPS
500kSPS
Figure 28. Reference Current vs. Reference Voltage
Data Sheet AD4000/AD4004/AD4008
Rev. C | Page 15 of 36
–40 –20 04020 60 80 100 120
ST ANDBY CURRE NT (µ A)
TEMPERATURE (°C)
0
2
4
6
8
10
1
3
5
7
9
11
12
14956-224
Figure 29. Standby Current vs. Temperature
020 40 60 80 100 120 140 160 180 200 220
tDSDO
(n s)
LO AD CAP ACIT ANCE ( pF)
5
7
9
11
13
15
17
19
21
23 VIO = 5.0V
VIO = 3.3V
VIO = 1.8V
14956-228
Figure 30. tDSDO vs. Load Capacitance
AD4000/AD4004/AD4008 Data Sheet
Rev. C | Page 16 of 36
TERMINOLOGY
Integral Nonlinearity Error (INL)
INL is the deviation of each individual code from a line drawn
from negative full scale through positive full scale. The point
used as negative full scale occurs ½ LSB before the first code
transition. Positive full scale is defined as a level 1½ LSB beyond
the last code transition. The deviation is measured from the
middle of each code to the true straight line (see Figure 32).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Zero Error
Zero error is the difference between the ideal voltage that
results in the first code transition (½ LSB above analog ground)
and the actual voltage producing that code.
Gain Error
The first transition (from 100 ... 00 to 100 ... 01) occurs at a level
½ LSB above nominal negative full scale (−4.999981 V for the
±5 V range). The last transition (from 011 … 10 to 011 … 11)
occurs for an analog voltage 1½ LSB below the nominal full
scale (+4.999943 V for the ±5 V range). The gain error is the
deviation of the difference between the actual level of the last
transition and the actual level of the first transition from the
difference between the ideal levels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD as follows:
ENOB = (SINADdB − 1.76)/6.02
ENOB is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured. The value for dynamic range is
expressed in decibels. It is measured with a signal at −60 dBFS
so that it includes all noise sources and DNL artifacts.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components that are less than
the Nyquist frequency, including harmonics but excluding dc.
The value of SINAD is expressed in decibels.
Aperture Delay
Aperture delay is the measure of the acquisition performance
and is the time between the rising edge of the CNV input and
when the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to acquire a
full-scale input step to ±0.5 LSB accuracy.
Power Supply Rejection Ratio (PSRR)
PSRR is the ratio of the power in the ADC output at the
frequency, f, to the power of a 200 mV p-p sine wave applied to
the ADC VDD supply of frequency, f.
PSRR (dB) = 10 log(PVDD_IN/PADC_OUT)
where:
PVDD_IN is the power at the frequency, f, at the VDD pin.
PADC_OUT is the power at the frequency, f, in the ADC output.
Data Sheet AD4000/AD4004/AD4008
Rev. C | Page 17 of 36
THEORY OF OPERATION
COMP CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
CC2C16,384C 4C
32,768C
LSB SW+
MSB
LSB SW–
MSB
CC2C16,384C 4C32,768C
IN+
REF
GND
IN–
14956-006
Figure 31. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD4000/AD4004/AD4008 are high speed, low power, single-
supply, precise, 16-bit pseudo differential ADCs based on a SAR
architecture.
The AD4000 is capable of converting 2,000,000 samples per
second (2 MSPS), the AD4004 is capable of converting
1,000,000 samples per second (1 MSPS), and the AD4008 is
capable of converting 500,000 samples per second (500 kSPS).
The power consumption of the AD4000/AD4004/AD4008
scales with throughput because they power down in between
conversions. When operating at 10 kSPS, for example, they
typically consume 70 µW, making them ideal for battery-
powered applications. The AD4000/AD4004/AD4008 also
have a valid first conversion after being powered down for
long periods, which can further reduce power consumed in
applications in which the ADC does not need to be constantly
converting.
The AD4000/AD4004/AD4008 provide the user with an on-chip
track-and-hold and do not exhibit any pipeline delay or latency,
making them ideal for multiplexed applications.
The AD4000/AD4004/AD4008 incorporate a multitude of
unique ease of use features that result in a lower system power
and smaller footprint.
The AD4000/AD4004/AD4008 each have an internal voltage
clamp that protects the device from overvoltage damage on the
analog inputs.
The analog input incorporates circuitry that reduces the
nonlinear charge kickback seen from a typical switched
capacitor SAR input. This reduction in kickback, combined
with a longer acquisition phase, means reduced settling
requirements on the driving amplifier. This combination
allows the use of lower bandwidth and lower power amplifiers
as drivers. It has the additional benefit of allowing a larger
resistor value in the input RC filter and a corresponding smaller
capacitor, which results in a smaller RC load for the amplifier,
improving stability and power dissipation.
High-Z mode can be enabled via the SPI interface by programming
a register bit (see Table 14). When high-Z mode is enabled,
the ADC input has a low input charging current at low input
signal frequencies as well as improved distortion over a wide
frequency range up to 100 kHz. For frequencies greater than
100 kHz and multiplexing, disable high-Z mode.
For single-supply applications, a span compression feature
creates additional headroom and footroom for the driving
amplifier to access the full range of the ADC.
The fast conversion time of the AD4000/AD4004/AD4008,
along with turbo mode, allows low clock rates to read back
conversions, even when running at their respective maximum
throughput rates. Note that, for the AD4000, the full throughput
rate of 2 MSPS can be achieved only with turbo mode enabled.
The AD4000/AD4004/AD4008 can interface with any 1.8 V to
5 V digital logic family. These devices are available in a 10-lead
MSOP or a tiny 10-lead LFCSP that allows space savings and
flexible configurations.
The AD4000/AD4004/AD4008 are pin for pin compatible with
some of the 14-/16-/18-/20-bit precision SAR ADCs listed in
Table 8.
Table 8. MSOP, LFCSP 14-/16-/18-/20-Bit Precision SAR ADCs
Bits 100 kSPS 250 kSPS
400 kSPS to
500 kSPS ≥1000 kSPS
201 AD40202
181 AD7989-12 AD76912 AD40112,
AD76902,
AD7989-52
AD40032,
AD40072,
AD79822,
AD79842
161 AD7684 AD76872 AD76882,
AD76932,
AD79162
AD40012,
AD40052,
AD79152
163 AD7680,
AD7683,
AD7988-12
AD76852,
AD7694
AD76862,
AD7988-52,
AD40082
AD40002,
AD40042,
AD79802,
AD79832
143 AD7940 AD79422 AD79462 Not applicable
1 True differential.
2 Pin for pin compatible.
3 Pseudo differential.
AD4000/AD4004/AD4008 Data Sheet
Rev. C | Page 18 of 36
CONVERTER OPERATION
The AD4000/AD4004/AD4008 are SAR-based ADCs using a
charge redistribution sampling digital-to-analog converter
(DAC). Figure 31 shows the simplified schematic of the ADC.
The capacitive DAC consists of two identical arrays of 16 binary
weighted capacitors, which are connected to the comparator
inputs.
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to GND via the SW+
and SW− switches. All independent switches connect the other
terminal of each capacitor to the analog inputs. The capacitor
arrays are used as sampling capacitors and acquire the analog
signal on the IN+ and IN− inputs.
When the acquisition phase is complete and the CNV input
goes high, a conversion phase initiates. When the conversion
phase begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. The differential voltage between the IN+ and
IN− inputs captured at the end of the acquisition phase is
applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and VREF, the comparator input varies by
binary weighted voltage steps (VREF/2, VREF/4, …, VREF/65,536).
The control logic toggles these switches, starting with the MSB,
to bring the comparator back into a balanced condition. After
the completion of this process, the control logic generates the
ADC output code and a busy signal indicator.
Because the AD4000, the AD4004, and the AD4008 have on-
board conversion clocks, the serial clock, SCK, is not required
for the conversion process.
TRANSFER FUNCTIONS
The ideal transfer characteristics for the AD4000/AD4004/AD4008
are shown in Figure 32 and Table 9.
000...000
000...001
000...010
111...101
111...110
111...111
ADC CODE ( S TRAIGHT BINARY)
ANALO G I NP UT
+FS R – 1.5 L SB
+FS R – 1 LSB
–FSR + 1 LSB
–FSR
–FSR + 0.5 L SB
14956-007
Figure 32. ADC Ideal Transfer Function (FSR Is Full-Scale Range)
Table 9. Output Codes and Ideal Input Voltages
Description Analog Input, VREF = 5 V VREF = 5 V with Span Compression Enabled (V) Digital Output Code
FSR − 1 LSB 4.999924 V 4.499939 0xFFFF1
Midscale + 1 LSB 2.500076 V 2.500061 0x8001
Midscale 2.5 V 2.5 0x8000
Midscale − 1 LSB 2.499924 V 2.499939 0x7FFF
−FSR + 1 LSB 76.3 µV 0.50006103 0x0001
−FSR 0 V 0.5 0x00002
1 This output code is also the code for an overranged analog input (VIN+ − VIN− above VREF with span compression disabled and above 0.9 × VREF with span compression
enabled).
2 This output code is also the code for an underranged analog input (VIN+ − VIN− below 0 V with span compression disabled and below 0.1 × VREF with span compression
enabled).
Data Sheet AD4000/AD4004/AD4008
Rev. C | Page 19 of 36
APPLICATIONS INFORMATION
TYPICAL APPLICATION DIAGRAMS
Figure 33 shows an example of the recommended connection
diagram for the AD4000/AD4004/AD4008 when multiple
supplies are available. This configuration is used for best
performance because the amplifier supplies can be selected to
allow the maximum signal range.
Figure 34 shows a recommended connection diagram when
using a single-supply system. This setup is preferable when only
a limited number of rails are available in the system and power
dissipation is of critical importance.
C
R
V+
REF VDD VIO
GND
IN+
IN–
SDI
SCK
SDO
CNV
AD4000/
AD4004/
AD4008
3-WIRE/4-WIRE
INTERFACE
1.8V
1.8V TO 5V
V+ ≥ +6.5V
DIGITAL HOST
(MICROPROCESSOR/
FPGA)
V– ≤ –0.5V
HOST
SUPPLY
100nF 100nF
5V
V–
AMP
VREF
0V
VCM = VREF/2
REF1LDO
AMP
VCM = VREF/2
10µF
10kΩ
10kΩ
14956-008
Figure 33. Typical Application Diagram with Multiple Supplies
C
R
REF VDD VIO
GND
IN+
IN–
SDI
SCK
SDO
CNV
AD4000/
AD4004/
AD4008
2
1.8V
1.8V TO 5V
V+ = 5V
DIGITAL HOST
(MICROPROCESSOR/
FPGA)
HOST
SUPPLY
100nF 100nF
4.096V
AMP
0.9 × V REF
0.1 × V REF
VCM = VREF/2
REF1LDO
AMP
VCM = VREF/2
10µF1
10kΩ
10kΩ
3-WIRE/4-WIRE
INTERFACE
14956-009
3
1SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. CREF IS US UALLY A 10µ F CERAMIC CAPACITOR (X7R) .
2SPAN COMPRESSION MODE ENABLED.
3SEE TABLE 10 FOR RC FILTER AND AMPLIFIER SELECTION.
Figure 34. Typical Application Diagram with a Single Supply
AD4000/AD4004/AD4008 Data Sheet
Rev. C | Page 20 of 36
ANALOG INPUTS
Figure 35 shows an equivalent circuit of the analog input structure,
including the overvoltage clamp of the AD4000/AD4004/AD4008.
C
EXT
R
EXT
V
IN
REF
D1
IN+
GND
CLAMP
0V TO 15V R
IN
C
IN
D2
C
PIN
14956-010
Figure 35. Equivalent Analog Input Circuit
Input Overvoltage Clamp Circuit
Most ADC analog inputs, IN+ and IN−, have no overvoltage
protection circuitry apart from ESD protection diodes. During
an overvoltage event, an ESD protection diode from an analog
input pin (IN+ or IN−) to REF forward biases and shorts the
input pin to REF, potentially overloading the reference or
causing damage to the device. The AD4000/AD4004/AD4008
internal overvoltage clamp circuit with a larger external resistor
(REXT = 200 Ω) eliminates the need for external protection
diodes and protects the ADC inputs against dc overvoltages.
In applications where the amplifier rails are greater than VREF
and less than ground, it is possible for the output to exceed
the input voltage range of the device. In this case, the
AD4000/AD4004/AD4008 internal voltage clamp circuit
ensures that the voltage on the input pin does not exceed VREF +
0.4 V and prevents damage to the device by clamping the input
voltage in a safe operating range and avoiding disturbance of
the reference, which is particularly important for systems that
share the reference among multiple ADCs.
If the analog input exceeds the reference voltage by 0.4 V, t he
internal clamp circuit turns on and the current flows through
the clamp into ground, preventing the input from rising further
and potentially causing damage to the device. The clamp turns
on before D1 (see Figure 35) and can sink up to 50 mA of current.
When the clamp is active, it sets the overvoltage (OV) clamp flag
bit in the register that can be read back (see Table 14), which is
a sticky bit that must be read to be cleared. The status of the
clamp can also be checked in the status bits using an OV clamp
flag (see Table 15). The clamp circuit does not dissipate static
power in the off state. Note that the clamp cannot sustain the
overvoltage condition for an indefinite amount of time.
The external RC filter is usually present at the ADC input
to band limit the input signal. During an overvoltage event,
excessive voltage is dropped across REXT, and REXT becomes part
of a protection circuit. The REXT value can vary from 200 Ω to
20 kΩ for 15 V protection. The CEXT value can be as low as 100 pF
for correct operation of the clamp. See Table 1 for input overvoltage
clamp specifications.
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
By using IN− to sense a remote signal ground, ground potential
differences between the sensor and the local ADC ground are
eliminated.
Switched Capacitor Input
During the acquisition phase, the impedance of the analog
inputs (IN+ or IN−) can be modeled as a parallel combination
of Capacitor CPIN and the network formed by the series connection
of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically
400 Ω and is a lumped component composed of serial resistors
and the on resistance of the switches. CIN is typically 40 pF and
is mainly the ADC sampling capacitor.
During the conversion phase, where the switches are open, the
input impedance is limited to CPIN. RIN and CIN make a single-
pole, low-pass filter that reduces undesirable aliasing effects and
limits noise.
RC Filter Values
The RC filter value (represented by R and C in Figure 33 and
Figure 34) and driving amplifier can be selected depending on
the input signal bandwidth of interest at the full throughput.
Lower input signal bandwidth means that the RC cutoff can be
lower, thereby reducing noise into the converter. For optimum
performance at various throughputs, use the recommended RC
values (200 Ω, 180 pF) and the ADA4805-1.
The RC values shown in Table 10 are chosen for ease of drive
considerations and greater ADC input protection. The
combination of a large R value (200 Ω) and small C value
results in a reduced dynamic load for the amplifier to drive.
The smaller value of C means fewer stability and phase margin
concerns with the amplifier. The large value of R limits the current
into the ADC input when the amplifier output exceeds the ADC
input range.
Table 10. RC Filter and Amplifier Selection for Various Input Bandwidths
Input Signal Bandwidth (kHz) R (Ω) C (pF) Recommended Amplifier
<10 See the High-Z Mode section See the High-Z Mode section See the High-Z Mode section
<200 200 180 ADA4805-1
>200 200 120 ADA4897-1
Multiplexed
200
120
ADA4897-1
Data Sheet AD4000/AD4004/AD4008
Rev. C | Page 21 of 36
DRIVER AMPLIFIER CHOICE
Although the AD4000/AD4004/AD4008 are easy to drive, the
driver amplifier must meet the following requirements:
•The noise generated by the driver amplifier must be kept
low enough to preserve the SNR and transition noise
performance of the AD4000/AD4004/AD4008. The noise
from the driver is filtered by the single-pole, low-pass filter
of the analog input circuit made by RIN and CIN, or by the
external filter, if one is used. Because the typical noise of the
AD4000/AD4004/AD4008 is 37 µV rms, the SNR
degradation due to the amplifier is
( )
+
=
−2
2)(
2
π
μV37
μV37
log20
N
dB3
LOSS
Nef
SNR
where:
f−3 dB is the input bandwidth, in megahertz, of the AD4000/
AD4004/AD4008 (10 MHz) or the cutoff frequency of the
input filter, if one is used.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp, in
nV/√Hz.
•For ac applications, the driver must have a THD
performance commensurate with the AD4000/
AD4004/AD4008.
•For multichannel multiplexed applications, the driver
amplifier and the analog input circuit of the AD4000/
AD4004/AD4008 must settle for a full-scale step onto the
capacitor array at a 16-bit level (0.0001525%, 15.25 ppm).
In the data sheet of the amplifier, settling at 0.1% to 0.01%
is more commonly specified. This settling may differ
significantly from the settling time at a 16-bit level and
must be verified prior to driver selection.
High Frequency Input Signals
The AD4000/AD4004/AD4008 ac performance over a wide
input frequency range using a 5 V reference voltage is shown
in Figure 36 and Figure 37. Unlike other traditional SAR ADCs, the
AD4000/AD4004/AD4008 maintain exceptional ac performance
for input frequencies up to the Nyquist frequency with minimal
performance degradation. Note that the input frequency is
limited to the Nyquist frequency of the sample rate in use.
94
801k 10k 100k 1M
SNR, S INAD (dB)
INPUT F RE QUENCY ( Hz )
15.2
13.2
ENOB (Bit s)
82
84
86
88
90
92
13.4
13.6
13.8
14.0
14.2
14.4
14.6
14.8
15.0
ENOB
SINAD
SNR
14956-212
Figure 36. SNR, SINAD, and ENOB vs. Input Frequency, VDD = 1.8 V,
VIO = 3.3 V, VREF = 5 V, 25°C
–80
–120
–110
–115
–105
–95
–85
–100
–90
1k 10k 100k 1M
THD ( dB)
INPUT F RE QUENCY ( Hz )
80
120
SFDR (dB)
85
90
95
100
105
110
115
THD
SFDR
14956-215
Figure 37. THD and SFDR vs. Input Frequency, VDD = 1.8 V, VIO = 3.3 V,
VREF = 5 V, 25°C
Multiplexed Applications
The AD4000/AD4004/AD4008 significantly reduce system
complexity and cost for multiplexed applications that require
superior performance in terms of noise, power, and throughput.
Figure 38 shows a simplified block diagram of a multiplexed
data acquisition system including a multiplexer, an ADC driver,
and the precision SAR ADC.
SAR ADC
ADC
DRIVER
MULTIPLEXER
SENSORS
R
R
RCC
C
C
14956-040
Figure 38. Multiplexed Data Acquisition Signal Chain Using the
AD4000/AD4004/AD4008
AD4000/AD4004/AD4008 Data Sheet
Rev. C | Page 22 of 36
Switching multiplexer channels typically results in large voltage
steps at the ADC inputs. To ensure an accurate conversion result,
the step must be given adequate time to settle before the ADC
samples its inputs (on the rising edge of CNV). The settling
time error is dependent on the drive circuitry (multiplexer
and ADC driver), RC filter values, and the time when the
multiplexer channels are switched. Switch the multiplexer
channels immediately after tQUIET1 has elapsed from the start
of the conversion to maximize settling time and to prevent
corruption of the conversion result. To avoid conversion
corruption, do not switch the channels during the tQUIET1 time.
If the analog inputs are multiplexed during the quiet conversion
time (tQUIET1), the current conversion may be corrupted.
EASE OF DRIVE FEATURES
Input Span Compression
In single-supply applications, it is desirable to use the full range
of the ADC; however, the amplifier can have some headroom
and footroom requirements, which can be a problem, even if it
is a rail-to-rail input and output amplifier. The AD4000/AD4004/
AD4008 include a span compression feature, which increases
the headroom and footroom available to the amplifier by reducing
the input range by 10% from the top and bottom of the range
while still accessing all available ADC codes (see Figure 39). The
SNR decreases by approximately 1.9 dB (20 × log(8/10)) for the
reduced input range when span compression is enabled. Span
compression is disabled by default but can be enabled by writing
to the relevant register bit (see the Digital Interface section).
14956-300
ADC
VREF = 4.096V
DIGITAL OUTPUT
ALL 2N
CODES
+FSR
–FSR
90% OF VREF = 3.69V
10% OF VREF = 0.41V
ANALOG
INPUT
5V
IN+
Figure 39. Span Compression
High-Z Mode
The AD4000/AD4004/AD4008 incorporate high-Z mode, which
reduces the nonlinear charge kickback when the capacitor DAC
switches back to the input at the start of acquisition. Figure 40
shows the input current of the AD4000/AD4004/AD4008 with
high-Z mode enabled and disabled. The low input current makes
the ADC easier to drive than the traditional SAR ADCs available
in the market, even with high-Z mode disabled. The input current
reduces further to submicroampere range when high-Z mode is
enabled. The high-Z mode is disabled by default but can be
enabled by writing to the register (see Table 14). Disable high-Z
mode for input frequencies above 100 kHz or when multiplexing.
14956-221
–25
–20
–15
–10
–5
0
5
10
15
20
25
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
INPUT CURRENT (μA)
INPUT DIFFERENTIAL VOLTAG E (V)
HIG H-Z DISABL E D, 2MSP S
HIG H-Z DISABL E D, 1MSP S
HIG H-Z DISABL E D, 500kSPS
HIG H-Z E NABLED, 2M S P S
HIG H-Z E NABLED, 1M S P S
HIG H-Z E NABLED, 500kS P S
Figure 40. Input Current vs. Input Differential Voltage, VDD = 1.8 V,
VIO = 3.3 V, VREF = 5 V, 25°C
To achieve the optimum data sheet performance from high
resolution precision SAR ADCs, system designers are often forced
to use a dedicated high power, high speed amplifier to drive the
traditional switched capacitor SAR ADC inputs for their precision
applications, which is commonly encountered in designing a
precision data acquisition signal chain. The benefits of high-Z
mode are low input current for slow (<10 kHz) or dc type signals
and improved distortion (THD) performance over a frequency
range of up to 100 kHz. High-Z mode allows a choice of lower
power and lower bandwidth precision amplifiers with a lower
RC filter cutoff to drive the ADC, removing the need for dedicated
high speed ADC drivers, which saves system power, size, and cost
in precision, low bandwidth applications. High-Z mode allows the
amplifier and RC filter in front of the ADC to be chosen based on
the signal bandwidth of interest and not based on the settling
requirements of the switched capacitor SAR ADC inputs.
Additionally, the AD4000/AD4004/AD4008 can be driven with a
much higher source impedance than traditional SARs, which
means the resistor in the RC filter can have a value 10 times larger
than previous SAR designs and with high-Z mode enabled can
tolerate even larger impedance. Figure 41 shows the THD
performance for various source impedances with high-Z mode
disabled and enabled.
1 2 10520 50
THD ( dB)
INPUT F RE QUENCY ( kHz )
–115
–110
–105
–100
–95
–90
–85
–80
–75
14956-225
500Ω HIGH-Z OFF
500Ω HIGH-Z ON
1000Ω HIGH-Z OFF
1000Ω HIGH-Z ON
200Ω HIGH-Z OFF
200Ω HIGH-Z ON
Figure 41. THD vs. Input Frequency for Various Source Impedances,
VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C
Data Sheet AD4000/AD4004/AD4008
Rev. C | Page 23 of 36
Figure 42 and Figure 43 show the AD4000/AD4004/AD4008
SNR and THD performance using the ADA4077-1 (supply
current per amplifier (ISY) = 400 µA) and ADA4610-1 (ISY =
1.50 mA) precision amplifiers when driving the AD4000/AD4004/
AD4008 at full throughput for high-Z mode both enabled and
disabled with various RC filter values. These amplifiers achieve
91 dB to 92 dB typical SNR and close to −100 dB typical THD
with high-Z enabled for a 2.27 MHz RC bandwidth. THD is
approximately 5 dB better with high-Z mode enabled, even for
large R values greater than 200 Ω. SNR maintains close to 85 dB
even with a very low RC filter cutoff.
When high-Z mode is enabled, the ADC consumes approximately
1 mW per MSPS of extra power; however, this is still significantly
lower than using dedicated ADC drivers like the ADA4807-1.
For any system, the front end usually limits the overall ac/dc
performance of the signal chain. The data sheets of the selected
precision amplifiers, shown in Figure 42 and Figure 43, show
that their own noise and distortion performance dominates the
SNR and THD specification at a certain input frequency.
SNR (dB)
70
80
75
85
90
95
260.482kHz
1.3kΩ
470pF
497.981kHz
680Ω
470pF
1.3MHz
680Ω
180pF
2.27MHz
390Ω
180pF
4.42MHz
200Ω
180pF
ADA4077-1 HI GH-Z E NABLED
ADA4077-1 HI GH-Z DISABL E D
ADA4610-1 HI GH-Z E NABLED
ADA4610-1 HI GH-Z DISABL E D
RC FILTER BANDW IDTHS ( Hz ) ,
RESISTOR (Ω), CAPACITOR (pF)
14956-229
Figure 42. SNR vs. RC Filter Bandwidths for Various Precision ADC Drivers,
fIN = 1 kHz (Turbo Mode On, High-Z Enabled/Disabled),
VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C
RC FILTER BANDW IDTHS ( Hz ) ,
RESISTOR (Ω), CAPACITOR (pF)
THD ( dB)
–115
–105
–110
–100
–95
–90
–85
–80
–70
–75
260.482kHz
1.3kΩ
470pF
497.981kHz
680Ω
470pF
1.3MHz
680Ω
180pF
2.27MHz
390Ω
180pF
4.42MHz
200Ω
180pF
ADA4077-1 HI GH-Z E NABLED
ADA4077-1 HI GH-Z DISABL E D
ADA4610-1 HI GH-Z E NABLED
ADA4610-1 HI GH-Z DISABL E D
14956-231
Figure 43. THD vs. RC Filter Bandwidths for Various Precision ADC Drivers,
fIN = 1 kHz (Turbo Mode On, High-Z Enabled/Disabled),
VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C
Long Acquisition Phase
The AD4000/AD4004/AD4008 also feature a fast conversion
time of 290 ns, which results in a long acquisition phase. The
acquisition is further extended by a key feature of the AD4000/
AD4004/AD4008: the ADC returns to the acquisition phase
typically 100 ns before the end of the conversion. This feature
provides an even longer time for the ADC to acquire the new
input voltage. A longer acquisition phase reduces the settling
requirement on the driving amplifier, and a lower power/
bandwidth amplifier can be chosen. The longer acquisition
phase means that a lower RC filter (represented by R and C in
Figure 33 and Figure 34) cutoff can be used, which means a
noisier amplifier can also be tolerated. A larger value of R can
be used in the RC filter with a corresponding smaller value of C,
reducing amplifier stability concerns without affecting distortion
performance significantly. A larger value of R also results in
reduced dynamic power dissipation in the amplifier.
See Table 10 for details on setting the RC filter bandwidth and
choosing a suitable amplifier.
VOLTAGE REFERENCE INPUT
A 10 µF (X7R, 0805 size) ceramic chip capacitor is appropriate
for the optimum performance of the reference input.
For higher performance and lower drift, use a reference such as
the ADR4550. Use a low power reference such as the ADR3450
at the expense of a slight decrease in the noise performance. It is
recommended to use a reference buffer such as the ADA4807-1
between the reference and the ADC reference input. It is important
to consider the optimum capacitance necessary to keep the
reference buffer stable as well as to meet the minimum ADC
requirement stated previously in this section (that is, a 10 µF
ceramic chip capacitor, CREF).
AD4000/AD4004/AD4008 Data Sheet
Rev. C | Page 24 of 36
POWER SUPPLY
The AD4000/AD4004/AD4008 use two power supply pins: a core
supply (VDD) and a digital input/output interface supply (VIO).
VIO allows direct interface with any logic between 1.8 V and 5.5 V.
To reduce the number of supplies needed, VIO and VDD can be
tied together for 1.8 V operation. The ADP7118 low noise,
CMOS, low dropout (LDO) linear regulator is recommended to
power the VDD and VIO pins. The AD4000/AD4004/AD4008
are independent of power supply sequencing between VIO and
VDD. Additionally, the AD4000/AD4004/AD4008 are insensitive
to power supply variations over a wide frequency range, as
shown in Figure 44.
100 1k 10k 100k 1M
PSRR ( dB)
FREQUENCY ( Hz )
55
60
65
70
75
80
14956-230
Figure 44. PSRR vs. Frequency, VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C
The AD4000/AD4004/AD4008 power down automatically at
the end of each conversion phase; therefore, the power scales
linearly with the sampling rate. This feature makes the device
ideal for low sampling rates (even a few samples per second)
and battery-powered applications. Figure 45 shows the
AD4000/AD4004/AD4008 total power dissipation and individual
power dissipation for each rail.
10 100 1k 10k 100k 1M 2M
POWER DISSIPATI O N (µW)
THROUGHP UT (SP S )
0.01
0.1
1
10
100
1k
10k
100k VDD
VIO
REF
TOTAL POWER
14956-227
POWER DISSIPATION
MEASUREMENT S APPLY T O
EACH PRO DUCT O V E R ITS
SPECIF IED T HROUGHP UT RANGE .
Figure 45. Power Dissipation vs. Throughput, VDD = 1.8 V, VIO = 1.8 V,
VREF = 5 V, 25°C
DIGITAL INTERFACE
Although the AD4000/AD4004/AD4008 have a reduced number
of pins, they offer flexibility in their serial interface modes. The
AD4000/AD4004/AD4008 can also be programmed via 16-bit
SPI writes to the configuration registers.
When in CS mode, the AD4000/AD4004/AD4008 are compatible
with SPI, QSPI™, MICROWIRE®, digital hosts, and DSPs. In this
mode, the AD4000/AD4004/AD4008 can use either a 3-wire or 4-
wire interface. A 3-wire interface using the CNV, SCK, and SDO
signals minimizes wiring connections, which is useful, for instance,
in isolated applications. A 4-wire interface using the SDI, CNV,
SCK, and SDO signals allows CNV, which initiates the conversions,
to be independent of the readback timing (SDI). This interface
is useful in low jitter sampling or simultaneous sampling
applications.
The AD4000/AD4004/AD4008 provide a daisy-chain feature using
the SDI input for cascading multiple ADCs on a single data line,
similar to a shift register.
The mode in which the device operates depends on the SDI
level when the CNV rising edge occurs. CS mode is selected if
SDI is high, and daisy-chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, daisy-chain mode is always selected.
In either 3-wire or 4-wire mode, the AD4000/AD4004/AD4008
offer the option of forcing a start bit in front of the data bits.
This start bit can be used as a busy signal indicator to interrupt
the digital host and trigger the data reading. Otherwise, without a
busy indicator, the user must time out the maximum conversion
time prior to readback.
The busy indicator feature is enabled in CS mode if CNV or SDI
is low when the ADC conversion ends.
The state of SDO on power-up is either low or high-Z, depending
on the states of CNV and SDI, as shown in Table 11.
Table 11. State of SDO on Power-Up
CNV SDI SDO
0 0 Low
0 1 Low
1 0 Low
1 1 High-Z
The AD4000/AD4004/AD4008 have turbo mode capability in
both 3-wire and 4-wire mode. Turbo mode is enabled by writing
to the configuration register and replaces the busy indicator
feature when enabled. Turbo mode allows a slower SPI clock rate,
making interfacing simpler. The maximum throughput of
2 MSPS for the AD4000 can be achieved only with turbo mode
enabled and a minimum SCK rate of 70 MHz.
Data Sheet AD4000/AD4004/AD4008
Rev. C | Page 25 of 36
The SCK rate must be sufficiently fast to ensure that the
conversion result is clocked out before another conversion is
initiated. The minimum required SCK rate for an application
can be derived based on the sample period (tCYC), the number of
bits that must be read (including data and optional status bits),
and which digital interface mode is used. Timing diagrams and
explanations for each digital interface mode are given in the
digital modes of operation sections (see the CS Mode, 3-Wire
Turbo Mode section through the Daisy-Chain Mode section).
Status bits can also be clocked out at the end of the conversion
data if the status bits are enabled in the configuration register.
There are six status bits in total as described in Table 15.
The AD4000/AD4004/AD4008 are configured by 16-bit SPI writes
to the desired configuration register. The 16-bit word can be
written via the SDI line while CNV is held low. The 16-bit word
consists of an 8-bit header and 8-bit register data. For isolated
systems, the ADuM141D is recommended, which can support
the 70 MHz SCK rate required to run the AD4000 at its full
throughput of 2 MSPS.
REGISTER READ/WRITE FUNCTIONALITY
The AD4000/AD4004/AD4008 register bits are programmable
and their default statuses are shown in Table 12. The register map
is shown in Table 14. The OV clamp flag is a read only sticky bit,
and it is cleared only if the register is read and the overvoltage
condition is no longer present. The OV clamp flag gives an
indication of overvoltage condition when it is set to 0.
Table 12. Register Bits
Register Bits Default Status
OV Clamp Flag 1 bit, 1 = inactive (default)
Span Compression 1 bit, 0 = disabled (default)
High-Z Mode 1 bit, 0 = disabled (default)
Turbo Mode 1 bit, 0 = disabled (default)
Enable Six Status Bits
1 bit, 0 = disabled (default)
All access to the register map must start with a write to the 8-bit
command register in the SPI interface block. The AD4000/
AD4004/AD4008 ignore all 1s until the first 0 is clocked in
(represented by WEN in Figure 46, Figure 47, and Table 12);
the value loaded into the command register is always a 0
followed by seven command bits. This command determines
whether that operation is a write or a read. The AD4000/AD4004/
AD4008 command register is shown in Table 13.
Table 13. Command Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WEN R/W 0 1 0 1 0 0
All register read/writes must occur while CNV is low. Data on
SDI is clocked in on the rising edge of SCK. Data on SDO is
clocked out on the falling edge of SCK. At the end of the data
transfer, SDO is put in a high impedance state on the rising
edge of CNV if daisy-chain mode is not enabled. If daisy-chain
mode is enabled, SDO goes low on the rising edge of CNV.
Register reads are not allowed in daisy-chain mode.
A register write requires three signal lines: SCK, CNV, and SDI.
During a register write, to read the current conversion results
on SDO, the CNV pin must be brought low after the conversion
is completed; otherwise, the conversion results may be incorrect
on SDO. However, the register write occurs regardless.
The LSB of each configuration register is reserved because a
user reading 16-bit conversion data may be limited to a 16-bit
SPI frame. The state of SDI on the last bit in the SDI frame may
be the state that then persists when CNV rises. Because interface
mode is partly set based on the SDI state when CNV rises, in
this scenario, the user may need to set the final SDI state.
The timing diagrams in Figure 46 through Figure 48 show how
data is read and written when the AD4000/AD4004/AD4008 are
configured in register read, write, and daisy-chain mode.
Table 14. Register Map
ADDR[1:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
0x0 Reserved Reserved Reserved Enable six
status bits
Span
compression
High-Z mode Turbo
mode
OV clamp flag (read only
sticky bit)
0xE1
AD4000/AD4004/AD4008 Data Sheet
Rev. C | Page 26 of 36
t
CYC
t
SCK
t
DIS
t
SCKL
t
SCKH
t
SCNVSCK
t
SSDISCK
t
HSDISCK
t
CNVH
t
EN
CNV
SCK 1234567
0 1
1
01 0 1 0 0
B0B1B2B3B4B5B6
WEN R/W 010 1 ADDR[1:0]
8 9 10 11 12 13 14 15 16
SDI
SDO
t
HSDO
t
DSDO
B7 XD15 D14 D13 D12 D11 D10 D9 D8
14956-018
Figure 46. Register Read Timing Diagram (X Means Don’t Care)
1
CONVE RS IO N RE S ULT ON BITS[D15: D0]
D15
1THE US E R M US T WAIT tCONV WHEN READING BACK THE CO NV E RS ION RE S ULT AND P E RFORM ING A RE GI S TER W RITE AT THE S AM E TIM E .
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
tCYC tSCK
tSCKL
tSCKH
tSCNVSCK
tSSDISCK
tHSDISCK
tCNVH1
EN
CNV
SCK 12345
0 0
1
0 1 0 1 0 0
WEN R/W 0 1 0 1 ADDR[1:0]
910 11 12 13 14 15 16
SDI
SDO
B0B1B2B3B4B5B6B7
tHSDO
tDSDO
tHCNVSCK
14956-019
Figure 47. Register Write Timing Diagram
SDI
A
SDO
A
/SDI
B
SDO
B
00
COMM AND ( 0x14)
0 0COMM AND ( 0x14)
0 0COMM AND ( 0x14)
t
CYC
t
SCK
t
SCKL
t
SCKH
t
SCNVSCK
CNV
SCK 124
t
DIS
t
CNVH
DATA (0xAB)
DATA (0xAB)
14956-020
Figure 48. Register Write Timing Diagram, Daisy-Chain Mode
Data Sheet AD4000/AD4004/AD4008
Rev. C | Page 27 of 36
STATUS WORD
The 6-bit status word can be appended to the end of a conversion
result, and the default conditions of these bits are shown in
Table 15. The status bits must be enabled in the register setting.
When the OV clamp flag is a 0, it indicates an overvoltage
condition. The OV clamp flag status bit updates on a per
conversion basis.
The SDO line returns to high impedance after the sixth status
bit is clocked out (except in daisy-chain mode). The user is not
required to clock out all status bits to start the next conversion.
The serial interface timing for CS mode, 3-wire without busy
indicator, including status bits, is shown in Figure 49.
SDO D15 D14 D13 D1 D0
SCK 1 2 3 14 15 16
t
SCK
t
SCKL
t
SCKH
tHSDO
t
DSDO
CNV
CONVERSIONACQUISITION
t
CYC
ACQUISITION
SDI = 1
t
CNVH
ACQ
t
EN
21 22
t
QUIET2
STATUS BI TS[ 5: 0]
B1
t
DIS
B0
20
t
CONV
14956-021
Figure 49. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram, Including Status Bits (SDI High)
Table 15. Status Bits (Default Conditions)
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OV clamp flag Span compression High-Z mode Turbo mode Reserved Reserved
AD4000/AD4004/AD4008 Data Sheet
Rev. C | Page 28 of 36
CS MODE, 3-WIRE TURBO MODE
This mode is typically used when a single AD4000/AD4004/
AD4008 device is connected to an SPI-compatible digital host. It
provides additional time during the end of the ADC conversion
process to clock out the previous conversion result, providing a
lower SCK rate. The AD4000 can achieve a throughput rate of
2 MSPS only when turbo mode is enabled and using a minimum
SCK rate of 70 MHz. With turbo mode enabled, the AD4004
can also achieve its maximum throughput rate of 1 MSPS with a
minimum SCK rate of 22 MHz, and the AD4008 can achieve its
maximum throughput rate of 500 kSPS with a minimum SCK rate
of 10 MHz. The connection diagram is shown in Figure 50, and
the corresponding timing diagram is shown in Figure 51.
This mode replaces the 3-wire with busy indicator mode by
programming the turbo mode bit, Bit 1 (see Table 14).
When SDI is forced high, a rising edge on CNV initiates a
conversion. The previous conversion data is available to read
after the CNV rising edge. The user must wait tQUIET1 time after
CNV is brought high before bringing CNV low to clock out the
previous conversion result. The user must also wait tQUIET2 time
after the last falling edge of SCK to when CNV is brought high.
When the conversion is complete, the AD4000/AD4004/AD4008
enter the acquisition phase and power down. When CNV goes
low, the MSB is output to SDO. The remaining data bits are
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 16th SCK
falling edge or when CNV goes high (whichever occurs first),
SDO returns to high impedance.
AD4000/
AD4004/
AD4008
SDI SDO
CNV
SCK
CONVERT
DATA I N
CLK
DIGITAL HOST
VIO
14956-147
Figure 50. CS Mode, 3-Wire Turbo Mode Connection Diagram (SDI High)
SDI = 1
tCYC
CNV
ACQUISITION ACQUISITION
t
ACQ
tSCK
tSCKL
CONVERSION
SCK
D0D1D13D14D15
SDO
tEN
tHSDO
123 14 15 16
tDSDO tDIS
tSCKH
tQUIET1 QUIET2
CONV
14956-026
Figure 51. CS Mode, 3-Wire Turbo Mode Serial Interface Timing Diagram (SDI High)
Data Sheet AD4000/AD4004/AD4008
Rev. C | Page 29 of 36
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is typically used when a single AD4000/AD4004/
AD4008 device is connected to an SPI-compatible digital host.
The connection diagram is shown in Figure 52, and the
corresponding timing diagram is shown in Figure 53.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. After a conversion is initiated, it continues until
completion irrespective of the state of CNV. This feature can be
useful, for instance, to bring CNV low to select other SPI
devices, such as analog multiplexers; however, CNV must be
returned high before the minimum conversion time elapses and
then held high for the maximum possible conversion time to
avoid the generation of the busy signal indicator.
When the conversion is complete, the AD4000/AD4004/AD4008
enter the acquisition phase and power down. When CNV goes
low, the MSB is output onto SDO. The remaining data bits are
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 16th SCK
falling edge or when CNV goes high (whichever occurs first),
SDO returns to high impedance.
There must not be any digital activity on SCK during the
conversion.
AD4000/
AD4004/
AD4008
SDI SDO
CNV
SCK
CONVERT
DATA I N
CLK
DIGITAL HOST
VIO
14956-022
Figure 52. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)
SDO D15 D14 D13 D1 D0
t
DIS
SCK 1 2 3 14 15 16
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSIONACQUISITION
t
CYC
ACQUISITION
SDI = 1
t
CNVH
t
ACQ
t
EN
t
QUIET2
t
CONV
14956-023
Figure 53. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram (SDI High)
AD4000/AD4004/AD4008 Data Sheet
Rev. C | Page 30 of 36
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is typically used when a single AD4000/AD4004/
AD4008 device is connected to an SPI-compatible digital host
with an interrupt input (IRQ).
The connection diagram is shown in Figure 54, and the
corresponding timing diagram is shown in Figure 55.
With SDI tied to VIO, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. SDO
is maintained in high impedance until the completion of the
conversion, irrespective of the state of CNV. Prior to the minimum
conversion time, CNV can select other SPI devices, such as analog
multiplexers; however, CNV must be returned low before the
minimum conversion time elapses and then held low for the
maximum possible conversion time to guarantee the generation
of the busy signal indicator.
When the conversion is complete, SDO goes from high impedance
to low impedance. With a pull-up resistor of 1 kΩ on the SDO
line, this transition can be used as an interrupt signal to initiate
the data reading controlled by the digital host. The AD4000/
AD4004/AD4008 then enter the acquisition phase and power
down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can capture the data, a digital
host using the SCK falling edge allows a faster reading rate,
provided it has an acceptable hold time. After the optional 17th
SCK falling edge or when CNV goes high (whichever occurs
first), SDO returns to high impedance.
If multiple AD4000/AD4004/AD4008 devices are selected at the
same time, the SDO output pin handles this contention without
damage or induced latch-up. It is recommended to keep this
contention as short as possible to limit extra power dissipation.
There must not be any digital activity on the SCK during the
conversion.
SDI SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
VIO
IRQ
VIO
1kΩ
AD4000/
AD4004/
AD4008
14956-024
Figure 54. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High)
SDO D15 D14 D1 D0
t
DIS
SCK 123 15 16 17
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSIONACQUISITION
t
CONV
t
CYC
ACQUISITION
SDI = 1
t
CNVH
t
ACQ
t
QUIET2
14956-025
Figure 55. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing Diagram (SDI High)
Data Sheet AD4000/AD4004/AD4008
Rev. C | Page 31 of 36
CS MODE, 4-WIRE TURBO MODE
This mode is typically used when a single AD4000/AD4004/
AD4008 device is connected to an SPI-compatible digital host.
It provides additional time during the end of the ADC conversion
process to clock out the previous conversion result, providing a
lower SCK rate. The AD4000 can achieve a throughput rate of
2 MSPS only when turbo mode is enabled and using a minimum
SCK rate of 70 MHz. With turbo mode enabled, the AD4004
can also achieve its maximum throughput rate of 1 MSPS with a
minimum SCK rate of 22 MHz, and the AD4008 can achieve its
maximum throughput rate of 500 kSPS with a minimum SCK
rate of 10 MHz. The connection diagram is shown in Figure 56,
and the corresponding timing diagram is shown in Figure 57.
This mode replaces the 4-wire with busy indicator mode by
programming the turbo mode bit, Bit 1 (see Table 14).
With SDI high, a rising edge on CNV initiates a conversion.
The previous conversion data is available to read after the CNV
rising edge. The user must wait tQUIET1 time after CNV is
brought high before bringing SDI low to clock out the previous
conversion result. The user must also wait tQUIET2 time after the
last falling edge of SCK to when CNV is brought high.
When the conversion is complete, the AD4000/AD4004/
AD4008 enter the acquisition phase and power down. The
ADC result can be read by bringing the SDI input low, which
consequently outputs the MSB onto SDO. The remaining data
bits are then clocked by subsequent SCK falling edges. The data
is valid on both SCK edges. Although the rising edge can capture
the data, a digital host using the SCK falling edge allows a faster
reading rate, provided it has an acceptable hold time. After the
16th SCK falling edge or when SDI goes high (whichever occurs
first), SDO returns to high impedance.
AD4000/
AD4004/
AD4008
SDI SDO
CNV
SCK
CONVERT
DATA I N
CLK
DIGITAL HOST
IRQ
VIO
1kΩ
CS1
14956-153
Figure 56. CS Mode, 4-Wire Turbo Mode Connection Diagram
ACQUISITION
SDO
SCK
ACQUISITION
SDI
CNV
tSSDICNV
tHSDICNV
tCYC
tSCK
tSCKL
tEN
tHSDO
1 2 3 14 15 16
tDSDO tDIS
tSCKH
D15 D14 D13 D1 D0
t
QUIET1
t
QUIET2
t
ACQ
CONVERSION
t
CONV
14956-031
Figure 57. CS Mode, 4-Wire Turbo Mode Timing Diagram
AD4000/AD4004/AD4008 Data Sheet
Rev. C | Page 32 of 36
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is typically used when multiple AD4000/AD4004/
AD4008 devices are connected to an SPI-compatible digital host.
A connection diagram example using two AD4000/AD4004/
AD4008 devices is shown in Figure 58, and the corresponding
timing diagram is shown in Figure 59.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. If SDI and CNV are low, SDO is
driven low. Prior to the minimum conversion time, SDI can
select other SPI devices, such as analog multiplexers; however,
SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator.
When the conversion is complete, the AD4000/AD4004/
AD4008 enter the acquisition phase and power down. Each
ADC result can be read by bringing its SDI input low, which
consequently outputs the MSB onto SDO. The remaining data
bits are then clocked by subsequent SCK falling edges. The data
is valid on both SCK edges. Although the rising edge can capture
the data, a digital host using the SCK falling edge allows a faster
reading rate, provided it has an acceptable hold time. After the
16th SCK falling edge or when SDI goes high (whichever occurs
first), SDO returns to high impedance and another AD4000/
AD4004/AD4008 can be read.
AD4000/
AD4004/
AD4008
SDI SDO
CNV
SCK
DEVICE A
CONVERT
DATA I N
CLK
DIGITAL HOST
AD4000/
AD4004/
AD4008
SDI SDO
CNV
SCK
DEVICE B
14956-027
CS1
CS2
Figure 58. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
SDO D15 D14 D13 D1 D0
t
DIS
SCK 1 2 3 30 31 32
t
HSDO
t
DSDO
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
SDI(CS1)
CNV
t
SSDICNV
t
HSDICNV
D1
14 15
t
SCK
t
SCKL
t
SCKH
D0 D15 D14
17 1816
SDI(CS2)
t
QUIET2
14956-028
Figure 59. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing Diagram
Data Sheet AD4000/AD4004/AD4008
Rev. C | Page 33 of 36
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is typically used when a single AD4000/AD4004/
AD4008 device is connected to an SPI-compatible digital host
with an interrupt input (IRQ), and when it is desired to keep
CNV, which samples the analog input, independent of the
signal used to select the data reading. This independence is
particularly important in applications where low jitter on CNV
is desired.
The connection diagram is shown in Figure 60, and the
corresponding timing diagram is shown in Figure 61.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. If SDI and CNV are low, SDO is
driven low. Prior to the minimum conversion time, SDI can
select other SPI devices, such as analog multiplexers; however,
SDI must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
When the conversion is complete, SDO goes from high impedance
to low impedance. With a pull-up resistor of 1 kΩ on the SDO
line, this transition can be used as an interrupt signal to initiate
the data readback controlled by the digital host. The AD4000/
AD4004/AD4008 then enter the acquisition phase and power
down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can capture the data, a digital
host using the SCK falling edge allows a faster reading rate,
provided it has an acceptable hold time. After the optional 17th
SCK falling edge or when SDI goes high (whichever occurs
first), SDO returns to high impedance.
AD4000/
AD4004/
AD4008
SDI SDO
CNV
SCK
CONVERT
DATA I N
CLK
DIGITAL HOST
IRQ
VIO
1kΩ
CS1
14956-029
Figure 60. CS Mode, 4-Wire with Busy Indicator Connection Diagram
SDO D15 D14 D1 D0
t
DIS
SCK 1 2 3 15 16 17
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
SDI
CNV
t
SSDICNV
t
HSDICNV
t
QUIET2
14956-030
Figure 61. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing Diagram
AD4000/AD4004/AD4008 Data Sheet
Rev. C | Page 34 of 36
DAISY-CHAIN MODE
Use this mode to daisy-chain multiple AD4000/AD4004/AD4008
devices on a 3-wire or 4-wire serial interface. This feature is
useful for reducing component count and wiring connections,
for example, in isolated multiconverter applications or for
systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using two AD4000/AD4004/
AD4008 devices is shown in Figure 62, and the corresponding
timing diagram is shown in Figure 63.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects daisy-chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback.
When the conversion is complete, the MSB is output onto SDO,
and the AD4000/AD4004/AD4008 enter the acquisition phase
and power down. The remaining data bits stored in the internal
shift register are clocked out of SDO by subsequent SCK falling
edges. For each ADC, SDI feeds the input of the internal shift
register and is clocked by the SCK rising edges. Each ADC in
the daisy-chain outputs its data MSB first, and 16 × N clocks are
required to read back the N ADCs. The data is valid on both
SCK edges. The maximum conversion rate is reduced because of
the total readback time.
It is possible to write to each ADC register in daisy-chain mode.
The timing diagram is shown in Figure 48. This mode requires
4-wire operation because data is clocked in on the SDI line with
CNV held low. The same command byte and register data can
be shifted through the entire chain to program all ADCs in the
chain with the same register contents, which requires 8 × (N + 1)
clocks for N ADCs. It is possible to write different register contents
to each ADC in the chain by writing to the furthest ADC in the
chain first, using 8 × (N + 1) clocks, and then the second furthest
ADC with 8 × N clocks, and so forth until reaching the nearest
ADC in the chain, which requires 16 clocks for the command
and register data. It is not possible to read register contents in
daisy-chain mode; however, the six status bits can be enabled if
the user wants to determine the ADC configuration. Note that
enabling the status bits requires six extra clocks to clock out the
ADC result and the status bits per ADC in the chain. Turbo
mode cannot be used in daisy-chain mode.
CONVERT
DATA I N
CLK
DIGITAL HOST
DEVICE B
DEVICE A
AD4000/
AD4004/
AD4008
SDI SDO
CNV
SCK
AD4000/
AD4004/
AD4008
SDI SDO
CNV
SCK
14956-032
Figure 62. Daisy-Chain Mode, Connection Diagram
SDO
A
= SDI
B
D
A
15
D
B
15 D
B
14 D
B
13
D
A
14 D
A
13 D
A
1 D
A
0
D
A
1 D
A
0
D
B
1 D
B
0
SCK 1 2 3 30 31 32
tSSDISCK tHSDISCK
CONVERSIONACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV
14 15
tSCK
tSCKL
tSCKH
17 1816
SDI
A
= 0
SDO
B
D
A
15 D
A
14
tHSDO
t
DSDO
t
QUIET2
tHSCKCNV
tDIS
tQUIET2
tEN
14956-033
Figure 63. Daisy-Chain Mode, Serial Interface Timing Diagram
Data Sheet AD4000/AD4004/AD4008
Rev. C | Page 35 of 36
LAYOUT GUIDELINES
The PCB that houses the AD4000/AD4004/AD4008 must be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD4000/AD4004/AD4008, with its analog signals on the left
side and its digital signals on the right side, eases this task.
Avoid running digital lines under the device because they
couple noise onto the die, unless a ground plane under the
AD4000/AD4004/AD4008 is used as a shield. Fast switching
signals, such as CNV or clocks, must not run near analog signal
paths. Avoid crossover of digital and analog signals.
At least one ground plane must be used. It can be common or
split between the digital and analog sections. In the latter case,
join the planes underneath the AD4000/AD4004/AD4008 devices.
The AD4000/AD4004/AD4008 voltage reference input (REF)
has a dynamic input impedance. Decouple the REF pin with
minimal parasitic inductances by placing the reference
decoupling ceramic capacitor close to (ideally right up against)
the REF and GND pins and connect them with wide, low
impedance traces.
Finally, decouple the VDD and VIO power supplies of the
AD4000/AD4004/AD4008 with ceramic capacitors, typically
0.1 µF, placed close to the AD4000/AD4004/AD4008 and
connected using short, wide traces to provide low impedance
paths and to reduce the effect of glitches on the power supply
lines.
An example of the AD4000 layout following these rules is
shown in Figure 64 and Figure 65. Note that the AD4004/
AD4008 layout is equivalent to the AD4000 layout.
EVALUATING THE AD4000/AD4004/AD4008
PERFORMANCE
Other recommended layouts for the AD4000/AD4004/AD4008
are outlined in the user guide of the evaluation board for the
AD4000 (EVAL-AD4000FMCZ). The evaluation board package
includes a fully assembled and tested evaluation board with the
AD4000, documentation, and software for controlling the board
from a PC via the EVAL-SDP-CH1Z. The EVAL-AD4000FMCZ
can also be used to evaluate the AD4004/AD4008 by limiting
the throughput to 1 MSPS/500 kSPS, respectively, in its software
(see the UG-1042).
14956-034
Figure 64. Example Layout of the AD4000 (Top Layer)
14956-035
Figure 65. Example Layout of the AD4000 (Bottom Layer)
AD4000/AD4004/AD4008 Data Sheet
Rev. C | Page 36 of 36
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50 BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 66. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
0.50
0.40
0.30
10
1
6
5
0.30
0.25
0.20
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.74
1.64
1.49
0.20 REF
0.05 M AX
0.02 NO M
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
COPLANARITY
0.08
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.20 M I N
PKG-004362
02-07-2017-C
FO R P ROPE R CONNECT ION OF
THE EXPOSED PAD, REFER TO
THE P IN CO NFIGURATION AND
FUNCTION DESCRIPT IONS
SECTION OF THIS DATA SHEET.
PIN 1
INDIC ATOR AREA OPTI ONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
Figure 67. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
Integral
Nonlinearity (INL)
Temperature
Range Package Description
Ordering
Quantity
Package
Option Branding
AD4000BRMZ ±1.0 LSB −40°C to +125°C 10-Lead MSOP, Tube 50 RM-10 Y61
AD4000BRMZ-RL7
±1.0 LSB
−40°C to +125°C
10-Lead MSOP, Reel
1000
RM-10
Y61
AD4000BCPZ-RL7 ±1.0 LSB −40°C to +125°C 10-Lead LFCSP, Reel 1500 CP-10-9 Y61
AD4004BRMZ ±1.0 LSB −40°C to +125°C 10-Lead MSOP, Tube 50 RM-10 C8F
AD4004BRMZ-RL7 ±1.0 LSB −40°C to +125°C 10-Lead MSOP, Reel 1000 RM-10 C8F
AD4004BCPZ-RL7 ±1.0 LSB −40°C to +125°C 10-Lead LFCSP, Reel 1500 CP-10-9 C8F
AD4008BCPZ-RL7 ±1.0 LSB −40°C to +125°C 10-Lead LFCSP, Reel 1500 CP-10-9 C8S
EVAL-AD4000FMCZ AD4000 Evaluation Board
Compatible with EVAL-SDP-CH1Z
1 Z = RoHS Compliant Part.
2 The EVAL-AD4000FMCZ can also be used to evaluate the AD4004 and AD4008 by setting the throughput to 1 MSPS and 500 kSPS in its software, respectively (see UG-1042).
©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14956-0-10/17(C)