73S8010R-DB - Maxim Integrated

73S8010R

Lo w Cost Smart Card Interface

Simplifying System Integ ration™ D ATA SHEET

DS_8010R_022 August 2009

DESCRIPTION

The Teridian 73S8010R is a single smart card

interface IC that provides ful l electr ical compl i ance

with ISO-7816-3 and EMV 4.0 (EMV2000)

specifications.

Interfacing with the host i s done through the two-wire

I2C bus and one i nterr upt output to inform the

system controll er of the car d pr esence and faul ts.

The card clock si gnal can b e generated by an

on-chip oscillator using an external crystal, or by

connection t o a clock signal .

The Teridian 73S8010R incorporates an ISO-7816-3

activation/deactivation sequencer that controls the

car d signals. Level-shifters drive the card signals with

the sel ected card voltage (3 V or 5 V ), coming from a n

internal Low Drop-Out (LDO) voltage regulat or. This

LDO re gul ato r is powere d by a dedi ca ted power

supply input, VPC. Digital circuitry is separately

powere d by a digi tal pow er supply, VDD.

With its em bedded LD O regulat or , the Teridian

73S 8010R is a cost-effective solution for any

application wher e a 5 V (typically -5% +10%) power

suppl y is available. H ar dwar e support for auxiliary

I/O lines, C4 / C8 contacts is provided.

Emergency card deact ivati on i s initiat ed upon

card extraction or upon any fault generated by

th e pr otection c ircuit r y. The fault can be a card

over-current, a V DD (dig ital power suppl y), a VPC

(regulator power supply), a VCC (card power supply)

or an ove r -heating fault.

The card over-current circuitr y is a true current detect

f unc tio n, as o ppo se d to VCC voltage drop detection, as

usual ly i mple me nte d i n ICC interfa ce ICs.

The VDD voltag e faul t has a threshold voltag e that

can be adj ust ed with an external r esistor or resistor

network. It allows au tomated card deacti vat ion at a

custom ized VDD voltage threshold valu e. It can be

used, for instan ce, to match th e system controller

operating volt age r ange.

APPLICATIONS

• Set-Top-Bo x C on d iti onal A c c ess an d

Pay-per-View

• P oint of Sales & Transacti on Termi nal s

• Control Access & Identificat ion

• Multiple car d and SAM reader configurations

ADVANTAGES

• S ingle smart car d in terface

• IC firmware compatible with TDA8020

• Tradit i onal step-u p convert er i s replaced by

an LDO regulator

 Greatl y reduce d power dissipati on

 Fewer ext er nal components are requir ed

 Better noise performance

 High current capability (90 mA supplied to

t he card)

• S mall form at (5x5x0.8 mm) QFN32 package option

• True card over-current det ection

FEATURES

• Card I nterface

• Complies with ISO-7816-3 a n d EM V 4.0

• An LDO volt age r egul ator pr ovides 3 V / 5 V to

t he card from an ext er nal power supply in put

• ISO-7816-3 Acti vation / Deactivation

sequencer wit h emer gency automated

deactivation on ca r d r emoval or fault

det ected by th e pr otection ci r cuitry

• P r otection includes 3 voltage super visors

that detect voltage drops on VCC card and

on power supplies VDD and VPC

• Over-current detection 150 mA max

• 1 card detection input

• Auxiliary I/O lines, for C4 / C8 contact

signals

• Host Interface

• Fast m ode, 400 kbp s I2C slave bus

• 8 possible devices in parallel

• O ne cont r ol register an d one stat us

• Int er rup t output to the host for faul t

detection

• Crystal oscillator or host clock, up to 27 MHz

• 6 kV ESD pr otection on t he card interface

• S O28 or QF N32 package

73S 8010R Dat a Sheet DS_8010R_022

Rev. 1 .6 2

FUNCTIONAL DI AGRAM

Pin numbers reference the SO28 pack age

[Pin numbers] reference the QFN32 Package

Figure 1: 73S8010R Block D iagram

[2] 5

GND

ICC I/O BUFFERS

VDD VOLTAGE SUPERVISOR

VOLTAGE REFERENCE

DIGITAL

FAULT LOGIC

VDD FAULT

VCC FAULT

Int_Clk

VDD VPC

RST

CLK

PRES

TEMP FAULT

[3] 6

[7] 10

[8] 11

[10] 12

[11]13

[13] 15

[14] 16

[20] 21 [17] 18

[26] 26

[28] 28

[27]27

[21]22

ISO-7816

SEQUENCER

R-C

OSC.

LDO

REGULATOR

VOLTAGE

SUPERVISORS

ICC RESET

BUFFER

ICC CLOCK

BUFFER

OVER

TEMP

I/O

AUX1

AUX2

IOUC

AUX1UC

AUX2UC

GND

VDDF_ADJ

XTAL

OSC CLOCK

GENERATION

XTALIN

XTALOUT

[24] 25

[23] 24

[4, 5, 6, 9,

16, 25, 32]

7, 8, 9

[31] 3

SAD2

[29]1

SAD0

[30] 2

SAD1

VCC

GND

[12] 14

[15] 17

GND

[1] 4

[22] 23

INT

[19] 20

SDA

[18] 19

SCL

VPC FAULT

DS_8010R_022 73S 8010R Dat a Sheet

Rev. 1 .6 3

Table of Contents

1 Pinout ............................................................................................................................................. 5

2 Electrical Specifications ................................................................................................................ 8

2.1 Abso lu te Maximum Rat i ngs ..................................................................................................... 8

2.2 Recommended Operating Cond it i ons ...................................................................................... 8

2.3 Smar t Car d Interface Requirements ........................................................................................ 9

2.4 Digital S ign als Characteristics ............................................................................................... 11

2.5 DC Characteristics ................................................................................................................ 11

2.6 I2C Interface Characteristics .................................................................................................. 12

2.7 Voltage / Tem per ature Fault Detecti on C ircuit s ...................................................................... 12

3 Appl i cati ons Information ............................................................................................................. 13

3.1 Example 73S8010R Sche matics ........................................................................................... 13

3.2 System C ontrol ler In terface (I2C Bus) .................................................................................... 14

3.3 Power Suppl y and Voltage Sup er vision ................................................................................. 17

3.4 Card Power Supply ............................................................................................................... 18

3.5 Over-temperature M oni tor ..................................................................................................... 18

3.6 On-chip Oscillator and Card Clock......................................................................................... 18

3.7 Activation Sequence ............................................................................................................. 19

3.8 Deactivat i on Sequence ......................................................................................................... 19

3.9 Interrupt ................................................................................................................................ 20

3.10 Warm Reset .......................................................................................................................... 21

3.11 I/O Circuitry and Timing......................................................................................................... 21

4 Mechanical Draw in gs .................................................................................................................. 22

4.1 32-pin QFN ........................................................................................................................... 22

4.2 28-Pin S O ............................................................................................................................. 23

5 Order i ng Informa ti on ................................................................................................................... 24

6 Related Documentation ............................................................................................................... 24

7 Contact Informatio n ..................................................................................................................... 24

Revisi on H istor y .................................................................................................................................. 25

73S8010R Data Sheet DS_8010R_022

4 Rev. 1 .6

Figures

Figure 1: 73S8010R Block Diagram ......................................................................................................... 2

Figure 2: 73S8010R 32-Pin QFN Pinout .................................................................................................. 5

Figure 3: 73S8010R 28-Pin SO Pinout ..................................................................................................... 5

Figure 4: Typical 73S8010R Application Schematic ............................................................................... 13

Figure 5: I2C Bus Write Protocol ............................................................................................................ 15

Figure 6: I2C Bus Read Protocol ............................................................................................................ 16

Figure 7: I2C Bus Timing Diagram .......................................................................................................... 16

Figure 8: Activation Sequence ............................................................................................................... 19

Figure 9: Deactivation Sequence ........................................................................................................... 20

Fi gur e 10: Int er r upt operation due to F aul t and Stat us Condi tions .......................................................... 20

Figure 11: Warm Reset Operation ......................................................................................................... 21

Figure 12: I/O Timing Diagram ............................................................................................................... 21

Fi gur e 13: 32-p in QF N P ackage Dimensions ......................................................................................... 22

Fi gur e 14: 28-Pin SO Package Dimensions ........................................................................................... 23

Tables

Table 1: 73S8010R Pin Definitions .......................................................................................................... 6

Tabl e 2: Absolut e M aximum Device R ati ngs ............................................................................................ 8

Tabl e 3: Recommended Operating C ondit i ons ......................................................................................... 8

Tabl e 4: DC S mart C ar d Interface Requirements ..................................................................................... 9

Table 5 : Digital Sig nals Charact erist ics .................................................................................................. 11

Table 6 : DC Characterist ics ................................................................................................................... 11

Tabl e 7: I2C Characterist ics ................................................................................................................... 12

Tabl e 8: Voltage / Temper ature Fault Detecti on Circuits ......................................................................... 12

Tabl e 9: Device Ad dr ess Sel ection ........................................................................................................ 14

Tabl e 10: Control Register Description ................................................................................................... 14

Tabl e 11: Car d C lock Rate Selection ..................................................................................................... 14

Tabl e 12: St atus Register Descript i on .................................................................................................... 15

Tabl e 13: I2C Bus Timi ng Par ameters ................................................................................................... 16

Table 14: Choice of V CC Pin Cap acitor ................................................................................................. 18

Table 1 5: Card Clock Divisor Options .................................................................................................... 18

Tabl e 16: Order N um ber s and Packaging Mar ks .................................................................................... 24

DS_8010R_022 73S 8010R Dat a Sheet

Rev. 1 .6 5

1 Pinout

The 73S8010R is suppl i ed as a 32-pi n QF N packa ge and as a 28-pin SO package.

GND

VPC

PRES

I/O

XTALOUT

XTALIN

INT

GND

VDD

SDA

SCL

VDDF_ADJ

AUX2

AUX1

GND

CLK

RST

VCC

TERIDIAN

73S8010R

SAD2

SAD1

SAD0

AUX2UC

AUX1UC

I/OUC

Figure 2: 73S8010R 32-Pin QFN Pinout

73S8010R

SAD0

SAD1

SAD2

GND

VPC

PRES

I/O

AUX2

AUX1

GND

AUX2UC

AUX1UC

I/OUC

XTALIN

XTALOUT

INT

VDD

SDA

SCL

VCC

RST

CLK

GND

VDDF_ADJ

GND

Figure 3: 73S8010R 28-Pin SO Pinout

73S8010R Data Sheet DS_8010R_022

6 Rev. 1 .6

Tabl e 1 describes the pin functions for the device.

Table 1: 73S8010R Pin De fi ni ti ons

Name Pin

(SO28) Pin

(QFN32) Type Description

Card Interface

I/O 11 8 IO Card I/O : D ata signal to/from ca r d. Includes a pul l -up

resistor to VCC.

AUX1 13 11 IO AU X1: Auxili ary data si gnal to/from card. In cludes a

pull-up resistor t o VCC.

AUX2 12 10 IO AU X2: Auxili ary data si gnal to/from card. In cludes a

pull-up r esistor t o VCC.

RST 16 14 O Card r eset : provides reset (RS T) signal to ca r d.

CLK 15 13 O Card clock: p r ovides cl ock signal ( CLK ) to ca r d. The

cr ystal oscillator frequency and C LKSEL bits in t he

control r egister determine t he r ate of t hi s clock.

PRES 10 7 I Card Presence swi tch: active hig h indica tes car d i s

present. Includes a pull-down resistor.

VCC 17 15 PSO Card power supply – l ogi call y co ntrol led by the

sequencer, outp ut of LDO regulator. R equi r es an

external filt er capaci tor to GND .

GND 14 12 GND Card ground.

M i scellaneous Inputs a nd Outputs

XTALIN 24 23 I Cryst al oscillator inpu t: can be co nnected to crystal o r

driven as a source for th e card clock.

XTALOUT 25 24 O Crystal oscillator output: connected to cr ystal . Left

open if XTALIN is being used as an external clock

input.

VDDF_ADJ 18 17 I VDD threshold adjustment input: this pin can be used

t o overwrite a higher VD D F valu e ( that co ntrol s

deactivation of t he card). Must be left open if unused.

NC 7, 8, 9 4,5,6,9,

16,25,32 – Non-connected pin.

Pow er S upply and Ground

VDD 21 20 S ystem int er face supply voltage and supp ly voltage

for internal circuitry.

VPC 6 3 LDO regulator pow er supply source.

GND 4 1 GND LD O regul ator gr ound.

GND 14 12 GND S mart card I/ O ground.

GND 5, 22 2,21 GND Dig ital ground .

DS_8010R_022 73S 8010R Dat a Sheet

Rev. 1 .6 7

Name Pin

(SO28) Pin

(QFN32) Type Description

M icrocontroller Interface

INT 23 22 O I nterr upt output signal (negat ive asser tion) to the

proce ssor . A 20 kΩ pull up to VDD is pr o vide d

internally.

SAD0

SAD1

SAD2

S er ial device address bit s. Digi tal inpu ts for address

sel ection that al lo ws for the co nnection of u p to 8

devices in paral lel. Addr ess selections is as fol lows:

SAD2 SAD1 SAD0 (7 bi t) I

Address

0x40

0x42

0 1 0 0x44

0 1 1 0x46

1 0 0 0x48

1 0 1 0x4A

1 1 0 0x4C

1 1 1 0x4E

Pins SAD0 and SAD1 are internally pulled down and

S AD 2 is i nternally p ul led up. The defau lt address

when unconnected is 0x48.

SCL 19 18 I I2C clock si gn al in put.

SDA 20 19 I/O I2C b i-dir ectional serial dat a signal.

I/OUC 26 26 IO System controller data I/O to/from the car d. Includes

an internal pull-u p r esistor to VDD.

AUX1UC 27 27 IO S ystem controller auxili ar y data I/O to/ from the card.

I ncludes an internal pul l -up resistor to VDD.

AUX2UC 28 28 IO S ystem controller auxili ar y data I/O to/ from the card.

I ncludes an internal pul l -up resistor to VDD.

73S8010R Data Sheet DS_8010R_022

8 Rev. 1 .6

2 Electrical Specifications

This section provides the following:

 A bsolute Maximum Rat ing s

 Reco mmended Op er ating C ondit i ons

 S mart C ar d Interface R equi r emen ts

 Digital Signals Characteristics

 DC Characterist ics

 I2C Int er face Character istics

 V olt age / Temperatu r e Fault Detection Cir cuits

2.1 Absolute Maximum Ratings

Table 2 lists th e m aximum oper ati ng conditions for t he 73S8010R. Permanent device damage may occur

if absolut e maximum r ati ngs are exceeded. E xposure to the extr emes of th e absolute maximum r ati ng for

extended peri ods may affect device reliab ility.

Table 2: Absolute Maximum De vice Ratings

Parameter Rating

Supply voltage VDD -0.5 t o 6. 0 VDC

Supply voltage VPC -0.5 t o 6. 0 VDC

Input voltage f or digital inputs -0.3 to (VDD +0.5) VDC

Storage temperature -60 °C to +150 °C

Pin voltage ( except ca r d int er face ) -0.3 to (VDD + 0.5) VDC

Pin voltage ( card interface) -0.3 to ( VCC + 0.5) VDC

ESD tolerance – C ar d int er face pins +/- 6 kV

ESD tolerance – Other pins +/- 2 kV

Note: ESD testing on sm ar t ca r d pi ns is HBM condition, 3 pulses, each p ol ar it y reference d to ground.

2.2 Recommended Operating Conditions

Funct i on oper ation should be restricted to the recommended operating conditions specified i n Table 3.

Table 3: Recommended Opera ti ng Conditions

Parameter Rating

Supply voltage VDD 2.7 t o 5.5 VDC

Supply voltage VPC 4.75 to 5.5 VDC

Ambient operating tem perature -40 °C to +85 °C

I nput voltag e for digital i nputs 0 V to VDD to +0.3 V

DS_8010R_022 73S 8010R Dat a Sheet

Rev. 1 .6 9

2.3 Smart Card Interface Requirements

Table 4 lists the 73S8010R Smart Card interface req ui r ements.

Table 4: DC Smart Card Inte rface Requirements

Symbol Parameter Condition Min Nom Max Unit

Card Power Supply (VCC) Reg ulator

Ge neral Conditions: -40 °C < T < 85 °C, 4.75 V < VPC < 5.5 V, 2.7 V < VDD < 5.5 V

VCC Card supply voltage

including ripple and

noise

I nactive m ode -0.1 – 0.1 V

I nactive m ode ICC = 1 mA -0.1 – 0.4 V

A ctive mode; ICC < 65 mA; 5 V 4.60 – 5.25 V

A ctive mode; ICC < 90 mA; 5 V 4.55 – V

A ctive mode; ICC < 90 mA; 3 V 2.80 – 3.2 V

Active mode ; single pulse of

100 mA fo r 2 µs; 5 V, fixed

load = 25 mA

4.6 – 5.25 V

Active mode ; single pulse of

100 mA for 2 µs; 3 V, fi xed

load = 25 mA

2.76 – 3.2 V

A ctive mode; current pulses

of 40 nAs with peak |ICC |

< 200 mA, t < 400 ns; 5 V

4.6 – 5.25 V

A ctive mode; current pulses

of 40 nAs with peak |ICC |

< 200 mA, t <400 ns; 3 V

2.76 – 3.2 V

ICCmax Maximum supply cur r ent

t o the ca r d Static load current , VCC>4.6 or

2. 7 volts as selected 90 – – mA

ICCF ICC fault current 100 – 150 mA

VSR V cc slew rate, r i se rate

on activate CF = 3.3 µF on V CC 0.02 0.05 0.08 V/μs

VSF V cc slew rate, fall rate on

de-activate CF = 3.3 µF on V CC 0.025 0.06 0.08 V/μs

CF External filt er capacit or

(VCC to GND) 1 3.3 5 µF

73S8010R Data Sheet DS_8010R_022

10 Rev. 1 .6

Symbol Parameter Condition Min Nom Max Unit

I nter f ace Re quirements – Da ta Signals: I/O, AUX1, AUX2, and host int erfaces: I /OUC, AUX1UC,

AUX2UC. ISHORTL, ISHORTH, and VINACT requirements do not per tain to I/OUC, AUX1UC, AUX2UC.

VOH Output level, high (I/O,

AUX1, AUX2) IOH = 0 µA 0.9 * VCC – VCC+0.1 V

IOH = -40 µA 0.75 * V CC – VCC+0.1 V

VOH O utput level, high

(I/OUC, AUX1UC,

AUX2UC)

IOH = 0 µA 0.9 * VCC – VDD+0.1 V

IOH = -40 µA 0.75 * V CC – VDD+0.1 V

VOL O utput level, low IOL = 1 mA – – 0.3 V

VIH Input level, high (I/O,

AUX1, AUX2) 1.8 – VCC+0.30 V

VIH Input level, high (I/OUC,

AUX1 UC, AUX2 UC) 1.8 – VCC+0.30 V

VIL Input level, low -0.3 – 0.8 V

VINACT Output volt age wh en

out side of se ssion IOL = 0 – – 0.1 V

IOL = 1 mA – – 0.3 V

ILEAK Input leakage VIH = VCC – – 10 µA

IIL Input current, low VIL = 0 – – 0.65 mA

ISHORTL Short circuit output

current For output low, shorted

t o VCC through 33 Ω – – 15 mA

ISHORTH Short circuit output

current For output high, shorted

to ground through 33 Ω – – 15 mA

tR, tF O utput rise time, fall

time Fo r I/O, AUX 1, AU X 2,

CL = 80 pF, 10% to 90 %.

Fo r I/OUC , AUX1U C ,

AUX2 UC, CL=50 pF,

10% to 90%.

– – 100 ns

tIR, tIF I nput rise, fall ti mes – – 1 µs

RPU Internal pul l-up r esistor Ou tput stabl e for >200 ns 8 11 14 kΩ

FDMAX Maximum data rate – – 1 MHz

TFDIO Delay , I/O to I/OUC,

I/OUC to I/O, AUX1 to

AUX1UC, AUX1UC to

AUX1, AU X2 to AU X2UC,

AUX2UC to AUX2

Falling edge from master

t o slave measured at

50% point

60 100 200 ns

TRDIO Delay , I/O to I/OUC,

I/OUC to I/O, AUX1 to

AUX1UC, AUX1UC to

AUX1, AU X2 to AU X2UC,

AUX2UC to AUX2

Rising edge from m aster

t o slave measured at

50% point

– 25 90 ns

CIN Input ca pacitance – – 10 pF

DS_8010R_022 73S 8010R Dat a Sheet

Rev. 1 .6 11

Symbol Parameter Condition Min Nom Max Unit

Reset a nd Clock for card interface, RST, CLK

VOH Output level, high IOH = -200 µA 0.9 * VCC – VCC V

VOL O utput level, low IOL = 200 µA 0 – 0.3 V

VINACT Output volt age wh en

out side of se ssion IOL = 0 – – 0.1 V

IOL = 1 mA – – 0.3 V

IRST_LIM Output current limit, RS T – – 30 mA

ICLK_LIM Output current limit, CLK – – 70 mA

tR, tF Output rise time, fall time CL = 35 pF for CLK,

10% to 90% – – 8 ns

CL = 200 pF for RST,

10% to 90% – – 100 ns

δ Dut y cycle for CL K CL = 35 pF, FCLK ≤ 20MHz 45 – 55 %

2.4 Digital Signals Characteristics

Table 5 lists the 73S8010R digital signals characteristics.

Table 5: Digital Signals Characteristics

Symbol Parameter Condition Min Nom Max Unit

Digit al I /O ex cept for OSC I/O

VIL Input low voltage -0.3 – 0.8 V

VIH Input high voltage 0.7 * VDD – VDD+0.3 V

VOL Output low voltage IOL = 2 mA – 0.45 V

VOH Output high voltage IOH = -1 mA VDD-0.45 – V

ROUT Pull-up r esistor; INT – 20 – kΩ

|IIL1| Input leakage current G ND < VIN < VDD -5 – 5 μA

Oscilla tor (XT ALIN) I/O

VILXTAL Input low voltage - XTALIN -0.3

–

0.5 V

VIHXTAL Input high voltage - XTALIN 0.7*VDD

–

VDD+0.3 V

IILXTAL Input current - XTALIN GND < VIN < VDD -30

–

30 μA

2.5 DC Characteristics

Table 6 lists the DC characteristics.

Table 6: DC Characteristics

Symbol Parameter Condition Min Nom Max Unit

IDD Supply cu r r ent on VDD – 1.5 3.0 mA

IPC Supply current on VPC VCC on, ICC = 0

I/O, AUX1, AUX2 = high – 0.45 0.65 mA

73S8010R Data Sheet DS_8010R_022

12 Rev. 1 .6

2.6 I2C Interface Characteristics

Table 7 lists the I2C Interface characteristics.

Table 7: I2C Ch aracteri st ics

Symbol Parameter Condition Min Nom Max Unit

VIL I nput low voltage -0.3 – 0.3 * VDD V

VIH Input high voltage 0.7 * VDD – VDD+0.3 V

VOL O utput low voltage IOL = 3 mA – – 0.40 V

CIN Pi n capacit ance – – 10 pF

IIN Output high voltage IOH = -1 mA VDD - 0.45 – V

TF Output fall time CL = 0 to 400 pF 20 + 0.1* CL – 250 ns

TSP Pulse width of sp ikes

t hat are suppressed Tr ansition from valid logic

level to opp osite level – – 50 ns

2.7 Voltage / Temperature Fault Detection Circuits

Table 8 lists th e voltage / t emp er ature fault detection circuits.

Table 8: Volt age / Tem peratu re F au lt D etecti on Ci r cu it s

Symbol Parameter Condition Min Nom Max Unit

VDDF VP over-current fault No exter nal r esistor on

VDDF_A DJ pin 2.15 – 2.4 V

VPCF VPC fault ( VPC Voltage

Supervisor threshold) VPC < VCC, a tr ansient

event – VCC - 0.2 – V

VCCF VCC fault (VCC Voltage

S uper visor threshold) VCC = 5 V 4.20 – 4.55 V

VCC = 3 V 2.5 – 2.7 V

TF Die over temperature fault 115 – 145 °C

DS_8010R_022 73S 8010R Data Sh eet

Rev. 1 .6 13

3 Applications Information

This section provides general usage informati on for the design and impl emen tation of the 7 3S8010R .

3.1 Example 73S8010R Schematics

Figure 4 shows a typ ical applica ti on schemati c for t he implementation of the 73S8 010R . Note t hat min or changes may occur to the reference

material from ti me to tim e and the reader i s enco ur aged to co ntact Teridian for the l atest information

SO28

See NOTE 4

VDD

CRYSTAL

22pF

ISO7816=1uF, EMV =3.3uF

SDA_to/from_uC

SAD1

CLK track shoul d be r outed

far from RST, I /O, C4 and

C8.

NOTES:

1) VDD = 2.7V to 5. 5V DC.

2) VPC = 4.75V(EMV, ISO) to 5.5V DC

3) Required if extern al clock from uP is u sed.

4) Required if crystal is used.

Y1, C2 and C3 must be r em oved if external clock i s use d.

5) Opt i onal. Can be left open.

6) R1 and R3 are exter na l resistors that ad j ust the VDD

fault voltage. Can be left open.

I/OUC_to/from_uC

Rext1

See NOTE 1

Card detection

switch is

normally closed

VPC

100nF

VDD

External_clock_f r om uC

100nF

22pF

AUX1UC_to.from_uC See NOTE 5

10uF

AUX2UC_to/from_uC

See NOTE 3

See note 2 VDD

Low ESR (<100m ohms) C1

should be placed near the SC

connecter co ntact

SAD0

SCK_from_uC

73S8010R

14 15

SAD0

SAD1

SAD2

GND

VPC

AUX2

PRES

I/O

AUX1

GND CLK

RST

VCC

VDDF_ADJ

SCL

SDA

VDD

GND

INT

AUX2UC

AUX1UC

XTALOUT

XTALIN

I/OUC

SAD2

INT_interrupt_to_uC

Rext2

- OR -

20K

See note 6

Smar t Card Connector

VCC

RST

CLK

GND

VPP

I/O

SW-1

SW-2

R4 R5

2K 2K

7) Hardware to define address of device

See note 7

Figure 4: Typ ic al 7 3S 80 10R Applicati on Schema tic

73S 8010R Dat a Sheet DS_8010R_022

14 Rev. 1 .6

3.2 System Controller Interface (I2C Bus)

A fast-m ode 400 kHz I2C bus slave interface i s use d for cont r ol ling the 73S8010R device and reading the

status of the device via the data pin SDA and clock pin SC L. Th e bus has 3 addr ess select p i ns, SAD0,

S AD 1, and SAD2. This al lows u p to 8 device s t o be connected in parallel. Table 9 li sts the device

address se lections for t he SAD 2:0 se ttings.

Table 9: Device Address Sel ect io n

SAD2 SAD1 SAD0 (7 bi t) I

Address

0 0 0 0x40

0 0 1 0x42

0 1 0 0x44

0 1 1 0x46

1 0 0 0x48

1 0 1 0x4A

0x4C

0x4E

B it 0 of the I 2C addr ess is the R/W bi t. Refer to Figure 5 and Figure 6 for usage.

Table 10 describes t he Cont r ol Register Bi ts.

Table 10: Control Register Descripti on

Power-on-reset value = 0x00

Name Bit Description

Start/Stop 0 When set , init i ates an activation and a co l d r eset pr ocedure; when reset,

initiat es a deacti vation se quence.

Warm r eset 1 When set, ini ti ates a warm reset pr ocedure; aut omati call y reset by hardwar e

when the card starts answering or when the card is declared mute.

5 V and 3 V 2 When set, VCC = 3 V; wh en r eset , VCC = 5 V. When de -activ a ting ( se tti ng bit

0 = 0) and operating with 3 V (bit 2 =1), do not simultaneously set bit 2 =0.

Clock Stop 3 When se t, t he card clock is stopped. Bit 4 determi nes the car d clock stop

level.

Clock Stop Level 4 When se t, car d clock stop s high; when reset card clock stops low.

Clksel1 5 Bits 5 and 6 determine t he clock r ate to t he card. See Table 11 for more

details.

Clksel2 6

I/O enable 7 I/O enable bit. When set, I/O is transferred on I/OUC; wh en reset I/O to

I/OUC is high impedance.

Table 11: Card Clock Ra t e Selectio n

Bit Clksel2 Bit Clksel1 Card Clock

0 0 Clkin/8

0 1 Clkin/4

1 0 Clkin/2

1 1 Clkin (Xtalin )

DS_8010R_022 73S 8010R Dat a Sheet

Rev. 1 .6 15

I2C-bus W r i te to Control Regi ster

The I2C-bus Write command to the control r egister follo ws the format shown in Figure 5. Af te r the START

condition, the master sends a sl ave address. This address is seven bits long followed by an eighth bit

which is an opcode bit (R/W) – a ‘zero’ i ndicates the master will wr it e data to t he control r egi ster. After

t he R /W bi t, th e ’zer o’ AC K bi t i s sent to th e m aster by the device . Th e master now start s sending t he 8

bits of data to t he cont r ol r egister during th e D ATA bi ts. After the DATA b its, the ‘zero’ ACK bit is sent to

t he m aster by the device. Th e master shou l d send t he STO P co ndit i on after receiving this A CK b it.

1-7 8 9 1-8 9

ADDRESS bits R/W bit ACK bit DATA bits ACK bit STOP

condition

START

condition

SCL

SDA

MSB MSB LSBLSB

Figure 5: I2C Bus Write Protocol

Table 12 describes t he Status Register bi ts.

Table 12: Status Register Description

Pow er On Reset = 0x04

Name Bit Description

PRES 0

Set when the card is present (pin PRES is high); reset when the card is not present.

PRESL 1 Set when the PRES pin changes state (rising/fall i ng edge) ; reset when the status

I/O 2 S et when I/O is h ig h; reset when I/ O i s low.

SUPL 3 Set when a voltage faul t is detected; rese t when the st atus r egi ster is read.

G ener ates an in terr upt wh en set.

PROT 4 S et wh en an over-curren t or over-heating fault has occurred during a card session;

rese t when the status register is r ead. Generates an in terr upt wh en set .

MUTE 5 Set during ATR when the card has not answered during the ISO 7816-3 time

window (40000 card clock cycles); reset when the next session begins.

EARLY 6 Set duri ng ATR when the ca r d has answered before 400 car d clock cycles; reset

when the next session begins.

ACTIVE 7 Set when the ca r d i s acti ve (VCC is on); rese t wh en the ca r d i s inactive.

I2C-bus Read from S ta tus Regi ster

The I2C-bus R ead Command from the Status Register follows the format shown in Figure 6. After the

S TART conditi on, the master sends a slave addr ess. This ad dress i s seven bits long foll owed by an eighth

bit which is an opcode bit (R/W) – a ‘on e’ indicates the mast er will read data from the status regist er. After

the R/ W bit, t he ’zero ’ ACK bi t is sent to the maste r by t he de vice. The device now starts sendi ng the 8-bit

status register data to the control register during the DATA bits. Af te r the D ATA bi t s, the ‘one ’ ACK bi t is

sent to the device by the ma ster . The master should send the STOP condit i on after receiving the ACK bit.

73S 8010R Dat a Sheet DS_8010R_022

16 Rev. 1 .6

1-7 8 9 1-8 9

ADDRESS bits R/W bit ACK bit DATA bits ACK bit STOP

condition

START

condition

SCL

SDA

LSBMSB LSBMSB

Figure 6: I2C Bus Rea d Protocol

SCL

SDA

Thdsta Tsudat Thddat Tsusto

Tbuf

Tlow

Thi

Figure 7: I2C Bus Timi ng Diagram

Table 13: I2C Bus Timing Parameters

Symbol Parameter Min. Typ. Max. Unit

Fsclk Clock frequency – – 400 kHz

Tlow Clock lo w 1.3 – – µs

Thi Clock high 0.6 – – µs

Thdsta Hold t ime START condition 0.6 – – µs

Tsudat Data setup time 100 – – ns

Thddat D ata hold ti me 5 – 900 ns

Tsusto Set up tim e STO P con dit i on 0.6 – – µs

Tbuf Bus free time b etween a STOP and

START con dit ion 1.3 – – µs

DS_8010R_022 73S 8010R Dat a Sheet

Rev. 1 .6 17

3.3 Power Supply and Voltage Supervision

The Teridian 73S8010R smart ca r d in terface I C incor porates a LDO volt age regul ator. Th e voltage

output is controlled by the digital input 5V/#V. This regulator i s able to provide either 3 V or 5 V card

voltage from the power supply applied on the VPC pin.

Digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the vo lt age

range to interface with t he system controller.

Three voltage super visors constantly check the presence of the volt ages VDD, VPC and VCC. A card

deactivation se quence is forced upon fault of any of these voltage super visors. The t wo voltage

super visors for VPC and VCC are linke d so t hat a fault is generated t o activate a deactivation sequence

when the volt age VPC beco mes lower th an VCC. This all ows the 73S8010R to operate at lower VPC

voltage when using 3 V cards only.

The voltage regulator can provide a cur r ent of at least 90 mA on VCC which easily complies with the

EMV 4.0 specifi cat ion. The VPC voltage sup er visor th r eshold values ar e defined from the EMV 4.0

standard. A third voltage super visor monitors the VDD voltage. It is used to init ialize the ISO-7816-3

sequencer at power-on, and to deacti vat e the ca r d at power-off or upon a fault. The vol tage threshold of

t he VDD voltage super visor is internally set by defau lt to 2.3 V nominal. However, it may be d esir abl e in

some applica ti ons t o m odi fy t hi s threshold valu e. Th e pi n VD DF_ADJ (pin 18 in t he SO package, pin 17

in the Q FN package) is used t o connect an ext er nal r esisto r R EXT to ground to raise the V DD fault voltage

t o another value VDDF. The r esistor val ue i s defined as follo ws:

REXT = 56 kΩ / (VDDF - 2.33)

A n alt er native (mor e accur ate) method of adjusting the VDD faul t voltag e is to use a r esistive netw or k of

R3 from the pin to supply and R1 from the pin to ground (see Figure 4) . In order to se t the new threshold

vol tage, th e equivalen t resistance must be determined. This resistance value will be designated Kx. Kx

is defined as R1/(R1+R3). Kx is calculated as:

Kx = ( 2.7 89 / VTH) - 0.6 125 where VTH is t he desired new thr eshold voltage.

To determine the values of R1 and R3, use the following formulas.

R3 = 24000 / Kx R 1 = R3*(Kx / (1 – Kx))

Taking the exam pl e above, where a VDD fault threshold voltage of 2.7 V i s desired, sol ving for Kx g ives:

 Kx = (2.789 / 2.7) - 0.6125 = 0.42046.

Solving for R3 g ives:  R3 = 24000 / 0.42046 = 57080.

Solving for R1 gives:  R1 = 57080 * ( 0.42046 / (1 – 0.42046)) = 41412.

Using standard 1 % resistor values gives R3 = 57.6 KΩ and R 1 = 42.4 KΩ.

These valu es give an equ ival ent resistan ce of K x = 0.4228, a 0.6% error.

If the 2.3 V default threshold is used, this pin must be left unconnected.

73S 8010R Dat a Sheet DS_8010R_022

18 Rev. 1 .6

3.4 Card P o wer Sup ply

The card power supply is provided by the LDO regulator, and controlled by the digital ISO-7816-3

sequencer. Card voltage se l ection is car r ied out by b it 2 of the control r egister.

Choic e of the V CC capacitor:

Depending on the appli cation, th e r equi r emen ts in terms of b oth the VCC mi nimum voltage and the

t r ansient current s th at the interface must be ab le t o pr ovide to th e card are differ ent. An external

capacitor must b e connected between the VCC pin and the card ground in or der to guarantee stability of

t he LDO r egul ator, and to handle the transient r equi r emen ts. Th e typ e and value of this capacit or can be

opt i mized to meet the desired sp ecificat ion . Table 14 sh ows the recommended capaci tors for each VPC

power supply configuration and applicable specification.

Table 14: Choice of VCC Pin Capacitor

3.5 Over-temperature Monitor

A bu ilt-in det ector monitors die temperature. When an over-temp er ature condition occur s (resulting from

a heavi ly load ed card interface, i ncludin g short circuit s, for exampl e) , a card deacti vation se quence is

initi ated, and a fau l t cond it i on is r epor ted to th e sy stem control l er ( bit 4 of the status reg ister i s se t and an

interrupt is generated).

3.6 On-chip Oscillator and Card Clock

The Terid i an 7 3S801 0 R d evice h as an on -ch ip osci l lat or th at can g en erate t h e sm art ca rd clock u si ng an

external crystal connected between the XTALIN and XTALOUT pins to set the oscillator frequency.

W h en th e car d cl ock si gn al is ava ilab le fr om an oth er so u rce, it can b e conn ect ed to th e p in X TA L IN , and

in this case, the XTALOUT pin should be left unconnected.

The card clock frequency may be chosen from 4 different division rates, defined by the Clksel2 and

Clksel1 bits (bits 5 and 6) of the I2C Cont r ol r egister, as listed i n Table 15.

Table 15: Card Cloc k Divisor Options

Speci fi cati on Requireme nts S yst em Requir ement s

Specification Min VCC Voltage

al lowe d during

transient current

Max Trans ient

Current Charge Min VPC Power

Suppl y re quire d Capacitor

Type Capacitor

Value

EMV 4. 0 4.6 V 30 nAs 4.75 V X5R/X7R

with

ESR < 100 mΩ

3.3 ΩF

ISO-7816-3 4.5 V 20 nAs 4.75 V 1 ΩF

Clksel2 Clksel1 Card Cl ock

0 0 Clkin / 8

0 1 Clkin / 4

1 0 Clkin / 2

1 1 Clkin (Xtalin )

DS_8010R_022 73S 8010R Dat a Sheet

Rev. 1 .6 19

3.7 Activ ati on S eq ue nc e

A fter Power on Reset, t he signal INT is low unt il the V DD is st abl e. When VDD has been stabl e for

approximately 1 0 m s and the si gnal INT is high, the system cont r oller may read the status r egister to se e

if t he card i s prese nt. I f al l the status bits ar e satisfied , the system controller can initiate the activation

sequence by writing a '1' to the Start/Stop bit (bit 0) of the control register.

The following steps and Figure 8 show the acti vation se quence and th e timing of the card contr ol si gnals

when the system controller i ni ti ates the Start/S top bit (bit 0) of the co ntrol r egi ster:

1. V ol tage VCC to the card should be valid by the end of t1. If VCC is not vali d for any reason, then

t he session i s aborted.

2. Turn I/O to recept ion mode at t he end of t1.

3. CLK is applied t o the ca r d at the end of t2.

4. RST (to the ca r d) i s se t high at the end of t3.

Start/Stop

VCC

CLK

RST

t1t2t3

t1 = 0.510 ms (timing by 1.5MHz internal Oscillator), I/O in reception mode

t2 =1.5 μs, CLK starts

t3 = >4 2000 card clock cycles, RST set h igh

Figure 8: Activation Sequ ence

3.8 Dea ctiv ati on Se que nc e

Deactivation i s ini ti ated either by t he system co ntrol l er by reset ting the Start/Stop bit, or automaticall y in

t he event of hardware f aul ts. Hardware faults ar e over-cur rent, over-temper ature, VDD fault, VPC fault, VCC

fau l t, and car d extracti on dur i ng the session.

The following steps and Figure 9 sh ow t he deactivation sequence and the timin g of the ca r d cont r ol

si gnals wh en the system controll er clear s t he start /stop bit:

1. RST goes low at the end of t 1.

2. CLK goes low at t he end of t2.

3. I/O goes l ow at the end of t 3. Out of recept ion mode.

4. Sh ut dow n VCC at the end of time t 4.

73S 8010R Dat a Sheet DS_8010R_022

20 Rev. 1 .6

Start/Stop

RST

CLK

VCC

t1 = > .5 μs t2 = > 7.5 μs

t3 = > 0.5 μs t4 = > 0.5 μs

Figure 9: Deact ivatio n Sequence

3.9 Interrupt

The Interrupt is an active low interrupt. It is set low i f any of the following internal faults are detected:

• VCC fault

• VDD fault

• VPC fault

The i nterr upt will al so be se t if one of t he following status bit conditions is detected:

• Early ATR

• M ute ATR

• Card i nsert or card extract

• P r otection status from Over-cur rent or Over-heating

When the interrupt is set low by the d etecti on o f one of the status bits, it is set high when the status bits

are read. (READ STATUS DONE) Figure 10 shows the interrupt operation resulting from the fault or

status bit conditions.

Figure 10: Inte rrupt operation due to Fa ult and S ta tus Conditions

A power-on-reset eve nt will r eset al l o f the co ntrol and status registers to their defaul t states. A VDD fault

event does not reset these registers, but it will signal an int er r upt con di ti on and by the action of t he timer

t hat creat es the interval “t1,” not clearing the interrupt until VDD is valid for at least t1. A VDD fault can be

considered vali d for VDD as low as 1.5 t o 1.8 volt s. At the lower range of VDD fault, POR will be asserted.

INT

ANY FAULT

STATUS BITS

READ STATUS DONE

DS_8010R_022 73S 8010R Dat a Sheet

Rev. 1 .6 21

3.10 Warm Reset

The 73S8010R automaticall y asserts a warm reset to the ca r d wh en i nstructed through bit 1 of t he I2C

Control r egister ( bi t Warm Reset). Th e warm reset length is au tomati call y defined as 42,000 ca r d clock

cycles. The Warm Reset bi t is automatic al ly reset when the ca r d starts answering or when th e card i s

decl ar ed mu te.

Figure 11: Warm Reset Operation

3.11 I/O Circuitry and Timing

The states of the I/O, AUX1, and AUX2 pin s are l ow after power-on-reset and th ey are high when the

activation se quencer enables t he I/O rece ption st ate. See Section 3.7 Activati on Sequence for more

det ai ls on wh en the I/ O recept ion is enabled . Th e states of t he I/OUC, AUX1UC, an d A UX2 UC are high

after pow er on r eset .

When th e cont r ol I /O enable bit ( bi t 7) of the control r egi ster is set, th e fir st I/O lin e on which a falling edge

is detected becomes the in put I/ O l i ne and the other beco mes the out put I/ O l i ne. When the input I/ O line

rising edge is detected, then both I/ O lin es return to th eir neutral state. Th e del ay bet ween t hese sig nals

is shown in Figure 12.

IOUC

IO_HL

IO_LH

IOUC_HL

IOUC_LH

Delay from I/O to I/OUC: tIO_HL = 1 00ns tIO_LH = 25ns

Delay from I/OUC to I/O: tIOuc_HL = 100ns tIOUC_LH = 25ns

Figure 12: I/O Timin g D iagram

Warm Reset

(bit 1)

RST

t1t2

t1 > 1.5µs, Warm Reset Starts

t2 = 42000 card clock cycles, End of Warm Reset

t3 = Resets Warm Reset bit 1 when detected ATR or Mute

73S 8010R Dat a Sheet DS_8010R_022

22 Rev. 1 .6

4 Mechanical Drawings

4.1 32-pin Q F N

2.5

TOP VIEW

Figure 13: 32-pin QFN Pa ckage Dimensions

0.85 NOM.

0.9MAX. 0.00 / 0.005

0.20 REF.

SEATING

PLANE

SIDE VIEW

0.2 MIN.

0.35 / 0.45

1.5 / 1.875

3.0 / 3.75

0.18 / 0.3

BOTTOM VIEW

0.25

0.5

0.25

3.0 / 3.75

1.5 / 1.875

0.35 / 0.45

CHAMFERED

0.30

DS_8010R_022 73S 8010R Dat a Sheet

Rev. 1 .6 23

4.2 28-Pin SO

.335 (8.509)

.320 (8.128)

.420 (10.668)

.390 (9.906)

.050 TYP. (1.270)

.305 (7.747)

.285 (7.239)

.715 (18.161)

.695 (17.653)

.0115 (0.29)

.003 (0.076)

.016 nom (0.40)

.110 (2.790)

.092 (2.336)

PIN NO. 1

BEVEL

Figure 14: 28-Pin SO Package Dimensions

73S 8010R Dat a Sheet DS_8010R_022

24 Rev. 1 .6

5 Ordering Information

Table 16 lists the order number s and packaging marks used to identify 73S8010R products.

Table 16: Order Numbers and Packaging Mark s

Part Description O rder Number Packaging Mar k

73S8010R–SOL, 28-pi n Lead-Free S O 73S8010R -IL/F 73S8010R -IL

73S8010R–SOL, 28-pi n Le a d-F r ee SO Tape / R eel 73S8010R -ILR/F 73S8010R -IL

73S8010R–QFN, 32-pi n Le a d-Free Q FN 73S8010R -IM/F 73S8010R

73S8010R–QFN, 32-pi n Le a d-Free Q FN Tap e / Reel 73S8010R -IMR/F 73S8010R

6 Related Documentation

The following 73S8010R documents are availab le from Teridian Semi conductor C or por ation:

73S8010R 28SO Demo Board User’s Guide

7 Contact Infor mation

For more information about Teridian Semiconduct or pr oduct s or to check the availability of the

73S8010R, contact us at:

6440 Oak Canyon Road

Suite 100

I r vine, CA 92618-5201

Telephone: (714) 508-8800

FAX : (71 4) 50 8-8878

E mail: scr.sup por t@teri dian .com

For a compl ete list of worldwide sales of fices, go to http://www.teridian.com.

DS_8010R_022 73S 8010R Dat a Sheet

Rev. 1 .6 25

Rev isi on Histor y

Revision Date Description

1.0 7/1/2004 First publicat ion.

1.1 11/10/2004 Make revisions to all references of “I/ O” as it rel ates to the pins for the smart

car d and micr ocont r oller i nterfaces, i.e. IO -> I/O and IOUC -> I/OUC. This

is done to i nsure co nsistency and foll ow t he designations used i n ISO 7816.

Remove t he M LP pin number ing in the pin descript i on.

Correct the clock division tab le u nder CARD CL OCK.

Change the value of R2 on the typical application schem atic. The or ig inal

value is 100 KΩ and the updated valu e i s 10 KΩ. The PRES i nput has a

high impedance pull down resistor and the 100 KΩ for R2 is too high to

insure a valid logic level on this input.

1.3 10/26/2005 Rem ove ND S r eferences i n applica tion sc hemati c.

1.5 1/21/2008 Removed leaded package option, replaced 32QFN punched with SAWN,

up da ted 28SO dimensi o n.

Changed dim ension of bottom expose d pad on 32QFN mechanical package

figure.

1.6 8/28/2009 Added S ection 6, Related Documentat ion and S ection 7, Cont act

Information.

Formatted to th e corporate style. Added document number.

Miscellaneous ed it or i al changes.

Teridian Semiconductor C or por ation is a r egi stered t r ademark of Teridian Semi conductor C or por ation.

S impli fying System Int egr ation i s a trademark of Teridian Semi conductor C or por ation.

A ll other trademar ks ar e the proper ty of their r espective owner s.

Thi s Data Sheet is propr iet ar y t o Teridi an Semiconductor Corporati on ( TS C) and sets fort h design goals

for t he described product. Th e data sheet i s subj ect t o change. TS C assumes no obl igat i on r egar di ng

fu ture manufactur e, unless agr eed to i n writing. If and when m anufactured and sold, this product is sold

subj ect to the terms and co ndi tions of sal e supplied at the time of order acknowledgment, in cludi ng those

pertaining to war r anty, patent infringement and l i mitat i on of liability. Teridian Semiconductor Corporation

(TSC ) r eserves the ri ght to make changes i n specificati ons at any time withou t notice. Accor ding ly, the

reader i s cauti oned to verify that a dat a sheet is current before placing orders. TSC assumes no li ability

for app lica ti ons assistan ce.

Teridian Semiconductor C or p., 6440 O ak Canyon, Sui te 100, I r vine, CA 92618

TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com