M48T559Y 5.0V, 64 Kbit (8 Kbit x8) TIMEKEEPER(R) SRAM with Address/Address/Data Multiplexed FEATURES SUMMARY SOFTWARE and HARDWARE RESET FOR WATCHDOG TIMER REGISTER COMPATIBLE WITH M48T59 TIMEKEEPER SRAM ADDRESS/ADDRESS/DATA MULTIPLEXED I/O PINS WATCHDOG TIMER - MONITORS OUT-OFCONTROL PROCESSOR OR "HUNG" BUS ALARM WITH WAKE-UP IN BATTERY MODE INTEGRATED, ULTRA-LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT AND BATTERY FREQUENCY TEST OUTPUT FOR REAL TIME CLOCK AUTOMATIC POWER-FAIL CHIP DESELECT AND WRITE PROTECTION POWER-FAIL DESELECT VOLTAGE (VPFD = Power-fail Deselect Voltage): - M48T559Y: VCC = 4.5 to 5.5V; 4.2 VPFD 4.5V PACKAGING INCLUDES A 28-LEAD SOIC and SNAPHAT(R) TOP (to be ordered separately) SOIC PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHAT TOP CONTAINS THE BATTERY AND CRYSTAL MICROPROCESSOR POWER-ON RESET (valid even during battery back-up mode) PROGRAMMABLE ALARM OUTPUT ACTIVE IN THE BATTERY BACK-UP MODE Figure 1. Package ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O April 2004 SNAPHAT (SH) Battery & Crystal 28 1 SOH28 (MH) 28-pin SOIC 1/26 M48T559Y TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Table 1. Figure 3. Figure 4. Logic Diagram . . . . . . . . Signal Names . . . . . . . . SOIC Connections . . . . . Block Diagram . . . . . . . . ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... .....4 .....4 .....5 .....5 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 RAM OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 6. WRITE Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Setting the Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 7. Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5. Alarm Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 8. Back-Up Mode Alarm Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reset Inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 9. RSTIN1 & RSTIN2 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 6. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 11.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 12.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/26 M48T559Y DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 8. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 13.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 9. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 10. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 14.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 11. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 12. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Figure 15.SOH28 - 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline . . . . . . . . 21 Table 13. SOH28 - 28-lead Plastic Small Outline, battery SNAPHAT, Package Mech. Data. . . . . 21 Figure 16.SH - 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . . 22 Table 14. SH - 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . . 22 Figure 17.SH - 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 23 Table 15. SH - 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . . 23 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 17. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 18. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3/26 M48T559Y SUMMARY DESCRIPTION The M48T559Y TIMEKEEPER(R) RAM is an 8 Kb x8 non-volatile static RAM and real time clock. The monolithic chip is available in the SNAPHAT(R) package to provide a highly integrated battery backed-up memory and real time clock solution. The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is "M4T28-BR12SH" (see Table 17., page 24). Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery. Figure 2. Logic Diagram Table 1. Signal Names ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O AD0 - AD7 Address/Address/Data AS0 - AS1 Address Strobes W WRITE Enable R READ Enable E Chip Enable WDI Watchdog Input RST Reset Output (Open Drain) RSTIN1 RSTIN1 Reset 1 Input RSTIN2 RSTIN2 Reset 2 Input IRQ/FT Interrupt/Frequency Test Output (Open Drain) VCC Supply Voltage VSS Ground NC Not Connected Internally DU Don't Use; must be connected to VCC or VSS VCC 8 AS0 AD0-AD7 AS1 W R RST M48T559Y IRQ/FT E WDI VSS AI01674B 4/26 M48T559Y Figure 3. SOIC Connections 1 28 2 27 3 26 4 25 5 24 6 23 7 22 M48T559Y 8 21 9 20 10 19 11 18 12 17 13 16 14 15 RST WDI RSTIN1 RSTIN2 DU NC NC NC NC AD0 AD1 AD2 VSS VSS VCC W IRQ/FT DU DU AS1 AS0 R E AD7 AD6 AD5 AD4 AD3 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O AI01675B Figure 4. Block Diagram IRQ/FT WDI OSCILLATOR AND CLOCK CHAIN 16 x 8 BiPORT SRAM ARRAY W DATA TRANSCEIVER 32,768 Hz CRYSTAL R POWER 8176 x 8 SRAM ARRAY LITHIUM CELL UPPER ADDRESS LATCH AD0-AD7 AS1 VOLTAGE SENSE AND SWITCHING CIRCUITRY VPFD LOWER ADDRESS LATCH AS0 RSTIN1 VCC RST VSS E RSTIN2 AI01676B 5/26 M48T559Y OPERATION MODES As Figure 4., page 5 shows, the static memory array and the quartz controlled clock oscillator of the M48T559Y are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDETM clock information in the bytes with addresses 1FF8h-1FFFh. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORTTM READ/WRITE memory cells. The M48T559Y includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T559Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out-of-tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the Battery Back-up Switchover Voltage (VSO), the control circuitry connects the battery which maintains data and clock operation until valid power returns. ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Table 2. Operating Modes E R W AD0-AD7(2) Power VIH X X High Z Standby VIL VIH VIL DIN Active READ VIL VIL VIH DOUT Active READ VIL VIH VIH High Z Active Mode VCC Deselect WRITE 4.5 to 5.5V Deselect VSO to VPFD (min)(1) X X X High Z CMOS Standby Deselect VSO(1) X X X High Z Battery Back-up Mode Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage 1. See Table 12., page 20 for details. 2. AD0-AD7, AS0, AS1 active when E is high and VCC > VPFD. 6/26 M48T559Y RAM OPERATION Four control signals, AS0, AS1, R and W, are used to access the M48T559Y. The address latches are loaded from the address/address/data bus in response to rising edge signals applied to the Address Strobe 0 (AS0) and Address Strobe 1 (AS1) signals. AS0 is used to latch the lower 8 bits of address, and AS1 is used to latch the upper 5 bits of address. It is not however necessary to follow any particular order. The inputs are in parallel for the two address bytes (upper and lower) and can be latched in any order as long as the correct strobe is used. It is necessary to meet the set-up and hold times given in the AC specifications with valid address information in order to properly latch the address. If the upper and/or lower order addresses are cor- rect from a prior cycle, it is not necessary to repeat the address latching sequence. A WRITE operation requires valid data to be placed on the bus (AD0-AD7), followed by the activation of the WRITE Enable (W) line. Data on the bus will be written to the RAM, provided that the WRITE timing specifications are met. During a READ cycle, the READ Enable (R) signal is driven active. Data from the RAM will become valid on the bus provided that the RAM READ access timing specifications are met. The W and R signals should never be active at the same time. In addition, E must be active before any control line is recognized (except for AD0-AD7 and AS0, AS1). ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Figure 5. READ Mode AC Waveforms tELEH E tELRL tEHDZ tASLASH AS0 tASLASH AS1 tASHRL tRLRH R tRLDV tAS AD0-AD7 tAH LOW ADDRESS VALID tAS tRHDZ tAH UPPER ADDRESS VALID DATA OUT VALID AI01671B Note: AD5-AD7 are "Don't care" when latching upper address. 7/26 M48T559Y Figure 6. WRITE Mode AC Waveforms tELEH E tELWL tEHDZ tASLASH AS0 tASLASH AS1 tASHWL tWLWH ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O W tAS AD0-AD7 tAH LOW ADDRESS VALID tAS tDH tDS tAH UPPER ADDRESS VALID DATA IN VALID AI01672B Note: AD5-AD7 are "Don't care" when latching upper address. Table 3. AC Characteristics Parameter(1) Symbol Min Unit tAS Address Setup Time 20 ns tAH Address Hold Time 0 ns tDS Data Setup Time 60 ns tDH Data Hold Time 0 ns tRLDV READ Enable Access Time tRLRH R Pulse Width Low tRHDZ READ Enable High to Output High Z tWLWH W Pulse Width Low 50 ns tELEH E Pulse Width Low 50 ns tASLASH AS0, AS1 Pulse Width Low 15 ns tASHRL AS0, AS1 High to R Low 15 ns tASHWL AS0, AS1 High to W Low 15 ns 70 70 ns ns 25 ns tELRL Chip Enable Low to READ Enable Low 0 ns tEHDZ Chip Enable High to Data Output Hi-Z 0 ns tELWL Chip Enable Low to WRITE Enable Low 0 ns Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V (except where noted). 8/26 Max M48T559Y Data Retention Mode Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as "Don't care." Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T559Y may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. There- fore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data and powers the clock. The internal button cell will maintain data in the M48T559Y for an accumulated period of at least 7 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (max) plus trec. For more information on Battery Storage Life refer to the Application Note AN1012. ) s ( t c u d CLOCK OPERATION o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Reading the Clock Updates to the TIMEKEEPER(R) registers should be halted before clock data is read to prevent reading data in transition. Because the BiPORTTM TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ Bit, D6 in the Control register (1FF8h). As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.' Setting the Clock Bit D7 of the Control register (1FF8h) is the WRITE Bit. Setting the WRITE Bit to a '1,' like the READ Bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table 4., page 10). Resetting the WRITE Bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh) to the actual TIMEKEEPER counters and allows normal operation to resume. After the WRITE Bit is reset, the next clock update will occur in one second. See the Application Note AN923, "TIMEKEEPER rolling into the 21st Century" for information on Century Rollover. Stopping and Starting the Oscillator The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP Bit is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T559Y is shipped from STMicroelectronics with the STOP Bit set to a '1.' When reset to a '0,' the M48T559Y oscillator starts within one second. 9/26 M48T559Y Table 4. Register Map Data Address D7 1FFFh D6 D5 D4 D3 D2 10 Years 0 10 M D1 D0 Function/Range BCD Format Year Year 00-99 Month Month 01-12 Date Date 01-31 Day 01-07 Hours Hours 00-23 1FFEh 0 0 1FFDh 0 0 1FFCh 0 FT 1FFBh 0 0 1FFAh 0 10 Minutes Minutes Minutes 00-59 1FF9h ST 10 Seconds Seconds Seconds 00-59 1FF8h W R S 1FF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog 1FF6h AFE Y ABE Y Y Y Y Y Interrupts 1FF5h RPT4 Y Al. 10 Date Alarm Date Alarm Date 01-31 1FF4h RPT3 Y Al. 10 Hours Alarm Hours Alarm Hours 00-23 1FF3h RPT2 Alarm 10 Minutes Alarm Minutes Alarm Minutes 00-59 1FF2h RPT1 Alarm 10 Seconds Alarm Seconds Alarm Seconds 00-59 1FF1h Y Y Y Y Y Y Y Y Unused 1FF0h WDF AF Z BL Z Z Z Z Flags 10 Date 0 0 0 Day 10 Hours ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Keys: S = SIGN Bit FT = FREQUENCY TEST Bit R = READ Bit W =WRITE Bit ST = STOP Bit 0 = Must be set to '0' Y = '1' or '0' Z = '0' and is Read only AF = Alarm Flag (Read only) 10/26 Calibration Control BL = Battery Low Flag (Read only) WDS = Watchdog Steering Bit BMB0-BMB4 = Watchdog Multiplier Bits RB0-RB1 = Watchdog Resolution Bits AFE = Alarm Flag Enable Flag ABE = Alarm in Battery Back-Up Mode Enable RPT1-RPT4 = Alarm Repeat Mode Bits WDF = Watchdog Flag (Read only) M48T559Y Setting the Alarm Clock Registers 1FF5h-1FF2h contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second or repeat every month, day, hour, minute, or second. It can also be programmed to go off while the M48T559Y is in the battery back-up to serve as a system wake-up call. Bits RPT1-RPT4 put the alarm in the repeat mode of operation. Table 5., page 11 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. Note: User must transition address (or toggle chip enable) to see Flag Bit change. When the clock information matches the alarm clock settings based on the match criteria defined by RPT1-RPT4, the AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set, the alarm condition activates the IRQ/FT pin. To disable alarm, write '0' to the Alarm Date Register and to RPT1RPT4. The Alarm Flag and the IRQ/FT output are cleared by a READ to the Flags Register as shown in Figure 7., page 11. A subsequent READ to the Flags Register is necessary to see that the value of the Alarm Flag has been reset to '0.' Note: If an alarm condition occurs while the Flags Register address is latched into the address buffer, the alarm flag will not be set until an address other than the Flags Register (1FF0h) is latched into the address buffer. This will insure that the alarm flag will not be inadvertently reset while reading the flag register. To properly check to see if an alarm condition has occurred while reading the flag register, the user is required to latch, read or write to an alternate address and then re-read the alarm flag. The IRQ/FT pin can also be activated in the battery back-up mode. The IRQ/FT will go low if an alarm occurs and both ABE (Alarm in Battery Back-up Mode Enable) and AFE are set. The ABE and AFE Bits are reset during power-up, therefore an alarm generated during power-up will only set AF. The user can read the Flag Register at system boot-up to determine if an alarm was generated while the M48T559Y was in the deselect mode during power-up. Figure 8., page 12 illustrates the back-up mode alarm timing. ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Figure 7. Alarm Interrupt Reset Waveform AD0-AD7 ADDRESS 1FF0h R ACTIVE FLAG BIT IRQ/FT AI01677B Table 5. Alarm Repeat Modes RPT4 RPT3 RPT2 RPT1 Alarm Activated 1 1 1 1 Once per Second 1 1 1 0 Once per Minute 1 1 0 0 Once per Hour 1 0 0 0 Once per Day 0 0 0 0 Once per Month 11/26 M48T559Y Figure 8. Back-Up Mode Alarm Waveform trec VCC VPFD (max) VPFD (min) VSO ABE, AFE bits in Interrupt Register ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O AF bit in Flags Register IRQ/FT HIGH-Z HIGH-Z AI01678C Calibrating the Clock The M48T559Y is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not exceed +/-35 ppm (parts per million) oscillator frequency error at 25oC, which equates to about +/-1.53 minutes per month. When the Calibration circuit is properly employed, accuracy improves to better than +1/-2 ppm at 25C. The oscillation rate of crystals changes with temperature (see Figure 10., page 15). Therefore, the M48T559Y design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 11., page 15. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration Bits found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration Bits occupy the five lower order bits (D4-D0) in the Control Register (1FF8h). These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator 12/26 cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or -2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T559Y may require: The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in Application Note AN934: TIMEKEEPER CALIBRATION. This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the Calibration byte. M48T559Y The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT pin. The pin will toggle at 512Hz, when the Stop Bit (ST, D7 of 1FF9h) is '0,' the Frequency Test Bit (FT, D6 of 1FFCh) is '1,' the Alarm Flag Enable Bit (AFE, D7 of 1FF6h) is '0,' and the Watchdog Steering Bit (WDS, D7 of 1FF7h) is '1' or the Watchdog Register (1FF7h = 0) is reset. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring a -10 (XX001010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency test output frequency. The FT Bit is cleared on power-down. For more information on calibration, see the Application Note AN934, "TIMEKEEPER Calibration". The IRQ/FT pin is an open drain output which requires a pull-up resistor for proper operation. A 500-10k resistor is recommended in order to control the rise time. Watchdog Timer The watchdog timer can be used to detect an outof-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the eight-bit Watchdog Register (Address 1FF7h). The five bits (BMB4-BMB0) store a binary multiplier and the two lower order bits (RB1RB0) select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the Watchdog Register = 3 x 1 or 3 seconds). Note: Accuracy of timer is within the selected resolution. If the processor does not reset the timer within the specified period, the M48T559Y sets the WDF (Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset. WDF is reset by reading the Flags Register (Address 1FF0h). The most significant bit of the Watchdog Register is the Watchdog Steering Bit. When set to a '0,' the watchdog will activate the IRQ/FT pin when timedout. When WDS is set to a '1,' the watchdog will output a negative pulse on the RST pin for a duration of 40ms to 200ms. The Watchdog register, FT, AFE, and ABE bits will reset to a '0' at the end of a watchdog time-out when the WDS Bit is set to a '1.' The watchdog timer can be reset by two methods: - a transition (high-to-low or low-to-high) can be applied to the Watchdog input pin (WDI); or - the microprocessor can perform a WRITE of the Watchdog Register. The time-out period then starts over. The WDI pin contains a pull-down resistor and therefore must be grounded if not used. The watchdog timer will be reset on each transition (edge) seen by the WDI pin. In order to perform a software reset of the Watchdog timer, the original time-out period can be written into the Watchdog Register, effectively restarting the count-down cycle. Should the watchdog timer time-out, and the WDS Bit is programmed to output an interrupt, a value of 00h needs to be written to the Watchdog Register in order to clear the IRQ/FT pin. This will also disable the watchdog function until it is again programmed correctly. A READ of the Flags Register will reset the Watchdog Flag (D7; Address 1FF0h). The watchdog function is automatically disabled upon power-down and the Watchdog Register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the frequency test function is activated, the watchdog or alarm function prevails and the frequency test function is denied. Power-on Reset The M48T559Y continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on powerup for 40ms to 200ms after VCC passes VPFD (max). An external pull-up resistor to VCC is required (1K resistor is recommended). The reset pulse remains active with VCC at VSS. ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 13/26 M48T559Y Reset Inputs (RSTIN1 & RSTIN2) The M48T559Y provides two independent inputs which can generate an output reset. The duration and function of these resets is identical to a reset generated by a power cycle. Table 6 and Figure 9 illustrate the AC reset characteristics of this function. Pulses shorter than tR1 and tR2 will not generate a reset condition. RSTIN1 and RSTIN2 are each internally pulled up to VCC through a 100k resistor. Battery Low Warning The M48T559Y checks its battery voltage on power-up. The BL (Battery Low) Bit (D4 of 1FF0h) will be set on power-up if the battery voltage is less than 2.5V (typical). Initial Power-on Defaults Upon application of power to the device, the following register bits are set to a '0' state: WDS; BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; and FT. Figure 9. RSTIN1 & RSTIN2 Timing Waveforms ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O RSTIN1 RSTIN2 tR2 Hi-Z Hi-Z RST tR1 tR1HRZ tR2HRZ AI01679 Table 6. Reset AC Characteristics Symbol Parameter(1) Min Max Unit tR1 RSTIN1 Low to RST Low 50 200 ns tR2 RSTIN2 Low to RST Low 20 100 ms tR1HRZ(2) RSTIN1 High to RST Hi-Z 40 200 ms tR2HRZ(2) RSTIN2 High to RST Hi-Z 40 200 ms Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V (except where noted). 2. CL = 5pF (see Figure 13., page 18). 14/26 M48T559Y Figure 10. Crystal Accuracy Across Temperature ppm 20 0 -20 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O -40 F = -0.038 ppm (T - T )2 10% 0 F C2 -60 T0 = 25 C -80 -100 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 C AI02124 Figure 11. Calibration Waveform NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION AI00594B 15/26 M48T559Y VCC Noise And Negative Going Transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 12) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 12. Supply Voltage Protection VCC VCC 0.1F DEVICE ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 16/26 VSS AI02169 M48T559Y MAXIMUM RATING Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 7. Absolute Maximum Ratings Symbol TA Parameter Ambient Operating Temperature Value Unit 0 to 70 C ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O TSTG TSLD(1,2) Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature for 10 seconds SNAPHAT(R) -40 to 85 C SOIC 0 to 70 C 260 C VIO Input or Output Voltage -0.3 to 7 V VCC Supply Voltage -0.3 to 7 V IO Output Current 20 mA PD Power Dissipation 1 W Note: 1. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225C (total thermal budget not to exceed 180C for between 90 to 150 seconds). 2. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds). CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. 17/26 M48T559Y DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 8. DC and AC Measurement Conditions Parameter M48T559Y VCC Supply Voltage 4.5 to 5.5V Ambient Operating Temperature 0 to 70C ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Load Capacitance (CL) 100pF Input Rise and Fall Times 5ns Input Pulse Voltages 0 to 3V Input and Output Timing Ref. Voltages 1.5V Note: Output High Z is defined as the point where data is no longer driven. Figure 13. AC Testing Load Circuit 5V 1.9k DEVICE UNDER TEST OUT 1k CL = 100pF CL includes JIG capacitance AI01673 Table 9. Capacitance Parameter(1,2) Symbol CIN COUT(3) Min Max Unit Input Capacitance 10 pF Output Capacitance 10 pF Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. 2. At 25C; f = 1MHz. 3. Outputs are deselected. 18/26 M48T559Y Table 10. DC Characteristics Sym Test Condition(1) Parameter ILI Input Leakage Current ILO(2) Output Leakage Current ILRST(3) Input Leakage Current ICC Supply Current ICC1 Supply Current (Standby) TTL Min Typ Max Unit 0V VIN VCC 1 A 0V VOUT VCC 1 A 0V VIN VCC 100 A Outputs open 50 mA E = VIH 10 mA E = VCC - 0.2V 7 mA ICC2(4) Supply Current (Standby) CMOS VIL(5) Input Low Voltage -0.3 0.8 VIH Input High Voltage 2.2 VCC + 0.3 VOL VOH Note: 1. 2. 3. 4. 5. 6. Output Low Voltage IOL = 2.1mA Output Low Voltage (IRQ/FT) (6) IOL = 10mA Output High Voltage IOL = -1mA ct du 2.4 e t e l o r P Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V (except where noted). Outputs Deselected. Input leakage current on input RSTIN1 and RSTIN2 pins. AD0-AD7, AS0, AS1 active when E is high and VCC > VPFD. Negative spikes of -1V allowed for up to 10ns once per cycle. For IRQ/FT pin (Open Drain). o s b O ) s ( t c u d o r P e t e l o s b O ) s ( ct e t le (s) 0.4 V V ) s t( 0.4 c u d V V V o r P o s b O - u d o r P e t e l o s b O 19/26 M48T559Y Figure 14. Power Down/Up Mode AC Waveforms VCC VPFD (max) VPFD (min) VSO tDR tF tR tFB tRB tPD trec RST ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O INPUTS RECOGNIZED DON'T CARE RECOGNIZED HIGH-Z OUTPUTS VALID VALID (PER CONTROL INPUT) (PER CONTROL INPUT) AI01384D Table 11. Power Down/Up AC Characteristics Symbol Parameter(1) Min Typ Max Unit tF(2) VPFD (max) to VPFD (min) VCC Fall Time 300 s tFB(3) VPFD (min) to VSS VCC Fall Time 10 s tPD EX at VIH before Power Down 0 s tR VPFD (min) to VPFD (max) VCC Rise Time 10 s tRB VSS to VPFD (min) VCC Rise Time 1 s trec VPFD (max) to RST High 40 200 ms Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. Table 12. Power Down/Up Trip Points DC Characteristics Symbol Parameter(1,2) VPFD Power-fail Deselect Voltage VSO Battery Back-up Switchover Voltage tDR(3) Expected Data Retention Time Min Typ Max Unit 4.2 4.35 4.5 V 3.0 7 Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V (except where noted). 2. All voltages referenced to VSS. 3. At 25C, VCC = 0V (when using SOH28 + M4T28-BR12SH SNAPHAT(R) top). 20/26 V YEARS M48T559Y PACKAGE MECHANICAL INFORMATION Figure 15. SOH28 - 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline A2 A C B eB e CP D ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O N E H A1 L 1 SOH-A Note: Drawing is not to scale. Table 13. SOH28 - 28-lead Plastic Small Outline, battery SNAPHAT, Package Mech. Data millimeters inches Symbol Typ Min A Max Typ Min 3.05 Max 0.120 A1 0.05 0.36 0.002 0.014 A2 2.34 2.69 0.092 0.106 B 0.36 0.51 0.014 0.020 C 0.15 0.32 0.006 0.012 D 17.71 18.49 0.697 0.728 E 8.23 8.89 0.324 0.350 - - - - eB 3.20 3.61 0.126 0.142 H 11.51 12.70 0.453 0.500 L 0.41 1.27 0.016 0.050 0 8 0 8 N 28 e CP 1.27 0.050 28 0.10 0.004 21/26 M48T559Y Figure 16. SH - 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline A1 A2 A3 A eA B L eB D ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O E SHTK-A Note: Drawing is not to scale. Table 14. SH - 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data millimeters inches Symbol Typ Min A Typ Min 9.78 Max 0.385 A1 6.73 7.24 0.265 0.285 A2 6.48 6.99 0.255 0.275 A3 22/26 Max 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 14.22 14.99 0.560 0.590 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 M48T559Y Figure 17. SH - 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline A1 A2 A3 A eA B L eB D ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O E SHTK-A Note: Drawing is not to scale. Table 15. SH - 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data millimeters inches Symbol Typ Min A Max Typ Min 10.54 Max 0.415 A1 8.00 8.51 0.315 0.335 A2 7.24 8.00 0.285 0.315 A3 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 17.27 18.03 0.680 0.710 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 23/26 M48T559Y PART NUMBERING Table 16. Ordering Information Scheme Example: M48T 559Y MH 6 E Device Type M48T Supply Voltage and Write Protect Voltage ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 559Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V Package MH(1) = SOH28 Temperature Range 1 = 0 to 70C Shipping Method blank = Tubes (Not for New Design - Use E) E = Lead-free Package (ECO PACK(R)), Tubes F = Lead-free Package (ECO PACK(R)), Tape & Reel TR = Tape & Reel (Not for New Design - Use F) Note: 1. The 28-pin SOIC package (SOH28) requires the SNAPHAT(R) battery/crystal package which is ordered separately under the part number "M4TXX-BR12SHX" in plastic tube or "M4TXX-BR12SHXTR" in Tape & Reel form (see Table 17). Caution: Do not place the SNAPHAT battery package "M4TXX-BR12SH" in conductive foam as it will drain the lithium button-cell battery. For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you. Table 17. SNAPHAT Battery Table Part Number 24/26 Description Package M4T28-BR12SH Lithium Battery (48mAh) and Crystal SNAPHAT SH M4T32-BR12SH Lithium Battery (120mAh) and Crystal SNAPHAT SH M48T559Y REVISION HISTORY Table 18. Document Revision History Date Rev. # Revision Details June 1998 1.0 First Issue 07-Feb-00 1.1 Description Paragraph changed; setting Alarm Clock paragraph changed; M4T28-BR12SH SNAPHAT Housing for 48mAh Battery & Crystal Package added (Table 14); Power Down/ Up Mode AC Waveforms changed (Figure 14); Back-up Mode Alarm Waveforms changed (Figure 8) 13-Aug-01 2.0 Reformatted; added temperature information (Tables 9, 10, 3, 11, 12) ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 20-May-02 2.1 Modify reflow time and temperature footnote (Table 7) 31-Mar-03 3.0 v2.2 template applied; data retention condition updated (Table 12) 01-Apr-04 4.0 Reformatted; update Lead-free package information (Table 7, 16) 25/26 M48T559Y ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. 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