M48T559YMH1TR - STMicroelectronics, Inc.

1/26April 2004

M48T559Y

5.0V, 64 Kbit (8 Kbit x8) TIMEKEEPER® SRAM

with Address/Address/Data Multiplexed

FEAT URES SUMMARY

■SOFT WARE and HARDWARE RESET FOR

WA TCHDOG TIMER

■REGISTER COMPATIBLE WITH M48T59

TIMEKEEPER SR AM

■ADDRESS/ADDRESS/DATA MULTIPLEXED

I/O PINS

■WA TCHDOG TIMER - MONITORS OUT-OF-

CONTROL PROCESSOR OR “HUNG” BUS

■ALARM WI TH WAK E- UP IN BATT ER Y

MODE

■INTEGRATED, ULTRA-LOW POWER SRAM,

REAL TIME CLOCK, POWER-FAIL

CONTR OL CIRCUIT AND BATTERY

■FREQUENCY TEST OUTPUT FOR REAL

TIME CLOCK

■AUTOMATIC POWER-FAIL CHIP

DESELECT AND WRITE PRO TECTION

■POWER-F AIL DESELEC T VOLT AGE

(VPFD = Power-fail Deselect Voltage):

– M48T559Y: VCC = 4.5 to 5.5V;

4.2 ≤ VPFD ≤ 4.5V

■PACKAGING INCLUDES A 28-LEAD SOIC

and SNAPHAT® TOP (to be ordered

separately)

■SOIC PACKAGE PROVIDES DIRECT

CONNECTION FOR A SNAPHAT TOP

CONTAINS THE BATTE R Y AND CRYST AL

■MICROPROCESSOR POWER-ON RESET

(valid even during battery back-up mode)

■PROGRAMMABLE ALARM OUT PU T

ACTIVE IN THE BATTERY BACK-UP MODE

Figure 1. Package

SOH28 (MH)

28-pin SOIC

SNAPHAT (SH)

Battery & Crystal

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TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPT ION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logi c Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signal Na mes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. S OIC Connec tions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4. Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

RAM OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. RE AD Mode AC Wavefo rms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 6. WRITE Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Reading the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Setting the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Stopping a nd Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0

Setting the Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 7. Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 5. A larm Repeat Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 8. B ack -Up Mode Alarm Wavefo rm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Calibrating th e Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2

Watchdog Time r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Po wer-o n Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3

R eset Inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4

Initial Power-on Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9. RSTIN1 & RSTIN2 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 6. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 10.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 11.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

VCC Noise And Negative Going Transie nts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 12.Supply Voltage Protect ion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6

MAXIMU M RATING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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M48T559Y

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 8. DC and A C Measurem ent Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

Table 9. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

Table 10. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9

Figure 14.Power Down/Up Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 11. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 12. Power Down/Up T rip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 15.SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT , Package Outline. . . . . . . . 21

Table 13. SOH28 – 28-lead Plastic Small Outline, battery SNAPHA T, Package Me ch. Data. . . . . 21

Figure 16.SH – 4-pin SNAPHA T Housing for 48mAh Ba ttery & Crystal, Package Outline . . . . . . . 22

Table 14. SH – 4-pin SNAP HAT Housing for 48mAh Ba ttery & Crystal, Package M ec h. Data . . . . 22

Figure 17.SH – 4-pin SNAPHA T Housing for 120mAh B attery & Crystal, Package Outline . . . . . . 23

Table 15. SH – 4-pin SNAP HAT Housing for 120mAh B attery & Crystal, Package M ech. Data . . . 23

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 16. Orderi ng Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 17. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 18. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

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S UM MARY DESCR IPTION

The M48T559Y TIMEKEEPER® RAM is an

8 Kb x8 non-volatile static RAM and real time

clock. The monolithic chip is available in the

SNAPHAT® package to provide a highly integrat-

ed battery bac ked-up m emo ry a nd real time c lock

solution.

The 28-pin, 330mil SOIC provides sockets with

gold plated contacts at both ends for direct con-

nection to a separate SNAPHA T housing cont ain-

ing the battery and crystal. The unique design

allows the SNAPHAT battery package to be

mounted on top of the SOIC package after the

completion of the surface mount process.

Insertion of the SNAPHAT housing after reflow

prevents potential battery and crystal damage due

to the high temperatures required for device sur-

face-mounting. The SNAPHAT housing is keyed

to prevent reverse insertion.

The SOIC and battery/crystal packages are

shipped separately in plastic anti-static tubes or in

Tape & Reel form. For the 28-lead SO IC, the bat-

tery/crystal package (e.g., SNAPHAT) part num-

ber is “M4T28-BR12SH” (see Table 17., page 24).

Caution: Do not place the SNAPHAT battery/crys-

tal top in conductive foam, as this will drain the lith-

ium button-cell battery.

Figure 2. Logic Diagram Table 1. Signal Names

AI01674B

AD0-AD7

VCC

M48T559Y

RSTIN2

RSTIN1

VSS

AS1

AS0

WDI

RST

IRQ/FT

AD0 - AD7 Address/Address/Data

AS0 - AS1 Address Strobes

WWRITE Enable

RREAD Enable

EChip Enable

WDI Watchdog Input

RST Reset Output (Open Drain)

RSTIN1 Reset 1 Input

RSTIN2 Reset 2 Input

IRQ/FT Interrupt/Frequency Test Output

(Open Drain)

VCC Supply Voltage

VSS Ground

NC Not Connected Internally

DU Don’t Use; must be connected to

VCC or VSS

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M48T559Y

Figure 3. SOIC Connections

Figu re 4. Blo ck Diagram

AI01675B

AD1

IRQ/FT

AD7

AS1

AS0

AD5AD2

VSS AD3VSS AD4

AD6

WDI

RST VCC

M48T559Y

RSTIN1

RSTIN2

AD0

AI01676B

LITHIUM

CELL

OSCILLATOR AND

CLOCK CHAIN

VPFD

VCC

32,768 Hz

CRYSTAL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

8176 x 8

SRAM ARRAY

POWER

AS1

AD0-AD7

AS0

RSTIN1

RSTIN2

RST

IRQ/FT

16 x 8 BiPORT

SRAM ARRAY

VSS

DATA

TRANSCEIVER

UPPER

ADDRESS

LATCH

LOWER

ADDRESS

LATCH

WDI

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OPERATION MODES

As Figure 4., page 5 shows, the static memory ar-

ray and the quartz c ontrolled clock oscillator of the

M48T559Y are integrated on one silicon chip. The

two circuits are interconnected at the upper eight

memory locations to provide user accessible

BYTEWIDE™ clock information in the bytes with

addresses 1FF8h-1FFFh. The clock locations

contain the ye ar, month, date, day, hour, minute,

and second in 24 hour BCD format. Corrections for

28, 29 (leap year - valid until 2100), 30, and 31 day

months are made automatically. Byte 1FF8h is the

clock control register. This byte controls user ac-

cess to the clock information and also stores the

clock calibration setting.

The eight clock bytes are not the actual clock

counters themselves; they are memory locations

consisting of BiPORT™ READ/WRITE memory

cells.

The M48T559Y includes a clock control circuit

which updates the clock bytes with current infor-

mation on ce per second. The information can be

accessed by t he us er i n t he sa me m anner a s any

other location in the static memory array.

The M48T559Y also has its own Power-fail Detect

circuit. The control circuitry constantly monitors

the single 5V supply for an out of tolerance condi-

tion.

When VCC is out-of-tolerance, the c ircuit write pro-

tects the SRAM, providing a high degree of data

security in the midst of unpredictable syst em oper-

ation brought on by low VCC. As VCC falls below

the Battery Back-up Switchover Voltage (VSO), the

control circuitry connects the battery which main-

tains data and clock operation until valid power re-

turns.

Table 2. Operating Modes

No te: X = VIH or VIL; VSO = B attery Bac k-up Switchover Voltage

1. See Tabl e 12., p age 20 for de tails.

2. AD0- AD7, A S0 , AS1 active w hen E i s high and VCC > VPFD.

Mode VCC E R W AD0-AD7(2) Power

Deselect

4.5 to 5.5V

VIH X X High Z Standby

WRITE VIL VIH VIL DIN Active

READ VIL VIL VIH DOUT Active

READ VIL VIH VIH High Z Active

Deselect VSO to VPFD (min)(1) X X X High Z CMOS Standby

Deselect ≤ VSO(1) X X X High Z Battery Back-up Mode

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M48T559Y

RAM OPERATION

Four control signals, AS0, AS1, R and W, ar e use d

to access t he M48T559Y. The address latches are

loaded from the address/address/data bus in re-

sponse to rising edge signals applied to the Ad-

dress Strobe 0 (AS0) and Addres s Strobe 1 ( AS1)

signals. AS0 is used to latch the lower 8 bits of ad-

dress, and AS1 is used to latch the upper 5 bits of

address.

It is not however necessary to f ollow any particular

order. The inputs are in parallel for the two ad-

dress bytes (upper and lower) and can be latched

in any order as long as the correct strobe is used.

It is necessary to meet the set-up and hold times

given in the AC specifications with valid address

information i n o rder t o properly latch the ad dres s.

If the upper and/or lower order addresses are cor-

rect f rom a pri or cycle, it is not necessary to repeat

the address latching sequen ce.

A WRITE operation requires valid data to be

placed on the bus (AD0-AD7), followed by the ac-

tivation of the WRITE Enable (W) line. Data on the

bus will be written to the RAM, provided that the

WRITE timing specifications are met. During a

READ cycl e, the REA D Enable (R) signal is driven

active. Data from the RAM will become valid on

the bus provided that the RA M REA D acc ess tim-

ing specifications are met.

The W and R signals should never be active at the

same time. In addition, E must be active before

any control line is recognized (except for AD0-AD7

and AS0, AS1).

Figure 5. READ Mode AC Waveforms

Note: AD5-AD7 ar e “Don't care” when lat ching uppe r address.

AI01671B

AS0

AD0-AD7

tASLASH

tELRL

AS1

tAS tAH

LOW ADDRESS VALID

tAS tAH

UPPER ADDRESS VALID

tRHDZ

tRLDV

DATA OUT

VALID

tEHDZ

tRLRHtASHRL

tASLASH

tELEH

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Figure 6. WRITE Mode AC Waveforms

Note: AD5-AD7 ar e “Don't care” when lat ching uppe r address.

Table 3. AC Characteristics

Note: 1. Val i d fo r Ambient Op erat in g Te m pera ture : TA = 0 to 70°C; VCC = 4.5 to 5.5V (except where noted).

Symbol Parameter(1) Min Max Unit

tAS Address Setup Time 20 ns

tAH Address Hold Time 0 ns

tDS Data Setup Time 60 ns

tDH Data Hold Time 0 ns

tRLDV READ Enable Access Time 70 ns

tRLRH R Pulse Width Low 70 ns

tRHDZ READ Enable High to Output High Z 25 ns

tWLWH W Pulse Width Low 50 ns

tELEH E Pulse Width Low 50 ns

tASLASH AS0, AS1 Pulse Width Low 15 ns

tASHRL AS0, AS1 High to R Low 15 ns

tASHWL AS0, AS1 High to W Low 15 ns

tELRL Chip Enable Low to READ Enable Low 0 ns

tEHDZ Chip Enable High to Data Output Hi-Z 0 ns

tELWL Chip Enable Low to WRITE Enable Low 0 ns

AI01672B

AS0

AD0-AD7

tASLASH

AS1

tAS tAH

LOW ADDRESS VALID

tAS tAH

UPPER ADDRESS VALID

tWLWH

tASHWL

DATA IN VALID

tDS

tASLASH

tELWL

tDH

tEHDZ

tELEH

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M48T559Y

Data Retention Mode

Should the supply voltage decay, the RAM will au-

tomatically power-fail de select, write protect ing it-

self when VCC falls within the VPFD (max), VPFD

(min) window. All outputs become high imped-

ance, and all inputs are treated as “Don't care. ”

Note: A power failure during a WRITE cycle may

corrupt data at the currently addressed location,

but does not jeopardize the rest of the RAM's con-

tent. At voltages below VPFD (min), the user can be

assured the memory will be in a write protected

state, provided t he VCC fall time is not less than t F.

The M48T559Y may respond to transient noise

spikes on VCC that reach into the deselect window

during the time the device is sampling VCC. There-

fore, decoupling of the power supply lines is rec-

ommended.

When VCC drops below VSO, the control circuit

switches power to the internal battery which pre-

serves data and powers the clock. The internal

button c ell will mai nta in data in t he M 48T559Y f or

an accumulated period of at least 7 years when

VCC is less than VSO. As system power returns

and VCC rises above VSO, the battery is discon-

nected, and the power supply is switched to exter-

nal VCC. Write protection continues until VCC

reaches VPFD (max ) plus trec.

For more information on Battery Storage Life refer

to the App lication Note AN101 2.

C LOCK OPERATION

Reading the Clock

Updates to the TIMEKEEPER® registers should

be halted before clock data is read to prevent

reading data in transition. Because the BiPORT™

TIMEKEEPER cells in the RAM array are only

data registers and not the actual clock counters,

so updating the registers can be halted without

distu rbing the clock itself.

Updating is halted when a '1' is written to the

READ Bit, D6 in the Control register (1FF8h). As

long as a '1' remains in that position, updating is

halted.

After a halt is issued, the registers reflect the

count; that is, the day, date, and the time that were

current at the moment the halt command was is-

sued.

All of the TIMEKEEPER registers are updated si-

multaneously. A halt will not interrupt an update in

progress. Updating is within a second af ter the bit

is re se t to a '0.'

Setting the Clock

Bit D7 of the Control register (1FF8h) is the

WRITE Bit. Setting the WRITE Bit to a '1,' like the

READ Bit, halts updates to the TIMEKEEP ER re g-

isters. The user can then load them with the cor-

rect day, date, and time data in 24 hour BCD

format (see Table 4., page 10). Resetting the

WRITE Bit to a '0' then transfers the values of all

time registers (1FF9h-1FFFh) to the actual TIME-

KEEPER coun ter s a nd a l lows nor m al operation to

resume. After the WRITE Bit is reset, the next

clock update will occur in one second.

See the Application Note AN923, “TIMEKEEPER

rolling into the 21st Century” for information on

Century Rollover.

Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the

device is going to spend a significant amount of

time on the shelf, the oscillator can be turned off to

minimize current drain on the battery. The STOP

Bit is the MSB of the seconds register. Setting it to

a '1' stops the oscillator. The M48T559Y is

shipped from STMicroelectronics with the STOP

Bit set to a '1.' When res et to a '0,' the M48T 559Y

oscillator starts within one second.

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M48T559Y

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Table 4. Register Map

Keys : S = SIGN Bit

FT = FREQUENCY TEST Bit

R = READ Bit

W =WRITE Bit

ST = STOP Bit

0 = Must be set to '0'

Y = '1' or '0'

Z = '0' and is Read onl y

AF = A l arm F l ag (Read only)

BL = B at tery Low Flag (Rea d only)

WDS = Watchdog Steeri ng Bit

BMB0-BMB4 = Watchdog Multiplie r Bits

RB 0-RB1 = Watchdog R esolut ion Bit s

AFE = Ala rm Flag Enable Flag

ABE = Alarm in Bat te ry Back-Up Mod e Enable

RP T 1-RPT 4 = A l arm Repe at Mode Bits

WDF = Watchdog Fla g (Read only )

Address Data Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

1FFFh 10 Years Year Ye ar 00-99

1FFEh 0 0 0 10 M Month Month 01-12

1FFDh 0 0 10 Date Date Date 01-31

1FFCh 0 FT 0 0 0 Day Day 01-07

1FFBh 0 0 10 Hours Hours Hours 00-23

1FFAh 0 10 Minutes Minutes Minutes 00-59

1FF9h ST 10 Seconds Seconds Secon ds 00-59

1FF8h W R S Calibration Control

1FF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog

1FF6hAFEYABEYYYYYInterrupts

1FF5h RPT4 Y Al. 10 Date Alarm Date A larm Date 01-31

1FF4h RPT3 Y Al. 10 Hours Alarm Hours Alarm Hours 00-23

1FF3h RPT2 Alarm 10 Minutes Alarm Minutes Alarm Minutes 00-59

1FF2h RPT1 Alarm 10 Seconds Alarm Seconds Alarm Seconds 00-59

1FF1hYYYYYYYY Unused

1FF0h WDF AF Z BL Z Z Z Z Flags

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M48T559Y

Setting the Alarm Clock

Registers 1FF5h-1FF2h contain the alarm set-

tings. The alarm can be configured to go off at a

prescribed time on a specific month, date, hour,

minute, or second or repeat every month, day,

hour, minute, or second. It can also be pro-

grammed to go off while the M48T559Y is in the

battery back-up to serve as a system wake-up cal l.

Bits RPT1–RPT4 put the alarm in the repeat mode

of operation. Table 5., page 11 shows the possible

configurations. Codes not listed in the table default

to the once per second mode to quickly alert the

user of an incorrect alarm setting.

Note: User must transition address (or toggle chip

enable) to see Flag Bit change.

When the clock information matches the alarm

clock settings based on the m atch criteria defined

by RPT1–RPT4, the AF (Alarm Flag) is set. If AFE

(Alarm Flag Enable) is also set, the alarm condi-

tion activates the IRQ/FT pin. To disable alarm,

write '0' to the Ala rm Date Register and to RP T1-

RPT4. The Ala rm Flag and the IRQ/FT out put are

cleared by a READ to the Flags Register as shown

in Figure 7., page 11. A subseq uent READ to the

Flags Register is necessary to see that the value

of the Alarm Flag has been reset to '0.'

Note: I f an alarm con dition occurs while the Flags

er, the alarm flag will not be set until an address

other than the Flags Register (1FF0h) is latched

into the address buffer. This will insure that the

alarm flag will not be inadvertently reset while

reading the flag register. To properly chec k to see

if an alarm condition has occurred while reading

the flag register, the user is required to latch, read

or write to an alternate address and then re-read

the alarm flag.

The IRQ/FT pin can also be activated in the bat-

tery back-up mode. The IRQ/FT will go low if an

alarm occurs and both ABE (Alarm in Battery

Back-up Mode Enable) and AFE are set. The ABE

and AFE Bits are reset during power-up, therefore

an alarm generated during power-up will only set

AF. The user can read t he Flag Register at syst em

boot-up to determine if an alarm was generated

while the M48T559Y was in the deselect mode

during power-up. Figure 8., page 12 illustrat es the

back-up mode alarm timing.

Figure 7. Alarm Interrupt Reset Waveform

Table 5. Alarm Repeat Modes

RPT4 RPT3 RPT2 RPT1 Alarm Activated

1111Once per Second

1 1 1 0 Once per Minute

1100Once per Hour

1000Once per Day

0 0 0 0 Once per Month

AI01677B

AD0-AD7

ACTIVE FLAG BIT

ADDRESS 1FF0h

IRQ/FT

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Figure 8. Back-Up Mode Alarm Waveform

Ca libra t ing t he Clock

The M48T559Y is driven by a quartz controlled os-

cillator with a nominal frequency of 32,768 Hz. The

devices are tested not exceed +/–35 ppm (parts

per million) oscillator frequency error at 25oC,

which equates to about +/–1.53 minutes per

month. When the Calibration circuit is properly em-

ployed, accuracy improves to better than +1/–2

ppm at 25°C.

The oscillation rate of crystals changes with tem-

perature (see Figure 10., page 15). Therefore, the

M48T559Y design employs periodic counter cor-

rection. The calibration circuit adds or subtracts

counts from the oscillator divider circuit at the di-

vide by 256 stage, as shown in Figure

11., page 15. The number of times pulses which

are blanked (subtracted, negative calibration) or

split (added, positive calibration) depends upon

the value loaded into the five Calibration Bits found

in the Control Register. Adding counts speeds the

clock up, subtracting counts slows t he cloc k down.

The Calibration Bits occupy the five lower order

bits (D4-D0) in the Control Register (1FF8h).

These bits can be set to represent any value be-

tween 0 and 31 in bi nary f orm. Bit D5 i s a Sign Bit;

'1' indicates positive calibration, '0' indicates nega-

tive calibration. Calibration occurs within a 64

minute cycle. The first 62 minutes in the cycle

may, once per minute, have one second either

shorten ed by 12 8 o r lengthened by 256 oscillator

cycles. If a binary '1' is loaded into the register,

only the first 2 minutes in the 64 minute cycle will

be modified; if a binary 6 is loaded, the first 12 will

be affected, and so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 osc illator cycles for

every 125,829,120 actual oscillator cycles, that is

+4.068 or –2.034 ppm of adjustment per calibra-

tion step i n t he cal ibration register. Ass um ing that

the oscillator is running at exac tly 32,768 Hz, each

of the 31 increm ents in the Calibration by te would

represent +10.7 or –5.35 seconds per month

which corresponds to a total range of +5.5 or –2.75

minutes per month.

Two methods are available for ascertaining how

much calibration a given M48T559Y may require:

The first involves setting the clock, letting it run for

a month and comparing it to a known accurate ref-

erence and recording deviation over a fixed period

of time. Calibration values, including the number of

seconds lost or gained in a given period, can be

found in Application Note AN934: TIMEKEEPER

CALIBRATION. This allows the designer to give

the end user the ability to calibrate the clock as the

environment requires, even if the final product is

packaged in a non-user serviceable enclosure.

The designer could provide a simple utility that ac-

cesses the Calibration byte.

AI01678C

VCC

IRQ/FT

HIGH-Z

VPFD (max)

VPFD (min)

ABE, AFE bits in Interrupt Register

AF bit in Flags Register

HIGH-Z

VSO

trec

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M48T559Y

The second approach is better suited to a manu-

facturing environment, and involves the use of the

IRQ/FT pin. The pin will t oggle at 512Hz, when the

Stop Bit (ST, D7 of 1FF9h) is '0,' the Frequency

Test Bit (FT, D6 of 1FFCh) is '1,' the Alarm Flag

Enable Bit (AFE, D7 of 1FF6h) is '0,' and the

Watchdog Steering Bit (WDS, D7 of 1FF7h) is '1'

or the Watchdog Register (1FF7h = 0) is reset.

Any deviation from 512 Hz indicates the degree

and direction of oscillator frequency shift at the test

temperature. For example, a reading of

512.010124 Hz would indicate a +20 ppm oscilla-

tor f requency error, requi ring a –10 (XX001010) to

be loaded into the Calibration Byte for correction.

Note that setting or changing the Calibration Byte

does not affect the Frequency test output frequen-

cy. The FT Bit is cleared on power-down.

For more i nformation on cali bration, see the A ppli-

cation Note AN934, “TIMEKEEPER C a li b r a tion”.

The IRQ/FT pin is an open d ra in output which re-

quires a pull-up resistor for proper operation. A

500-10kΩ resistor is recommended in order to

control the rise time.

Watchdog Timer

The watchdog timer can be used to detect an out-

of-control microprocessor. The us er program s the

watchdog timer by setting the desired amount of

time-out into the eight-bit Watchdog Regist er (Ad-

dress 1FF7h). The five bits (BMB4-BMB0) store a

binary multiplier and the two lower order bits (RB1-

RB0) select the resolution, where 00 = 1/16 sec-

ond, 01 = 1/4 second, 10 = 1 second, an d 11 = 4

seconds. The amount of time-out is then deter-

mined to be the multiplication o f the five-bit multi-

plier value with the resolution. (For example:

writing 00001110 in the Watchdog Register = 3 x

1 or 3 seconds).

Note: Accuracy of timer is within ± the selected

resolution.

If the processor does not reset the t imer within the

specified period, the M48T559Y sets the WDF

(Watchdog Flag) and generates a watchdog inter-

rupt or a microprocessor reset. WDF is reset by

reading the Flags Register (Address 1FF0h).

The most significa nt bit of the Watchdog Regi ster

is the Watchdog Steering Bit. When set to a '0,' the

watchdog will activate the IRQ/FT pin when timed-

out. When WDS is set to a '1,' the watchdog will

output a negative pulse on the RST pin for a dura-

tion of 40ms to 200ms. The Watchdog register,

FT, AFE, and ABE bits wi l l re se t to a '0' at th e end

of a wat chdog time-out when the WDS Bit is set to

a '1.'

The watchdog timer can be reset by two methods:

– a transition (high-to-low or low-to-high) can be

applied to the Watchdog input pin (WDI); or

– the microprocessor can perform a WRITE of the

Watchdog Register. The time-out period then

starts over. The WDI pin contains a pull-down

resistor and therefore must be grounded if not

used.

The watchdog timer will be reset on each transition

(edge) seen by the WDI pin. I n order t o pe rform a

software reset of the Watchdog timer, the original

time-out period ca n be written into the Watchdog

cle.

Should the watchdog timer time-out, and the WDS

Bit is programmed to output an interrupt, a value of

00h needs to be written to the Watchdog Regi ster

in order to clear the IRQ/FT pi n. This will also dis-

able the watchdog function until it is again pro-

grammed correctly. A READ of the Flags Register

will reset the Watchdog Flag (D7; Address 1FF0h).

The watchdog function is automatically disabled

upon power-down and the Watchdog Register is

cleared. If the watchdog func tion is set to output to

the IRQ /FT pin and the frequency test function is

activated, the watchdog or alarm function prevails

and the frequency test function is denied.

Power-on Reset

The M48T559Y continuously monitors VCC. When

VCC falls to the power fail detect trip point, the RST

pulls low (open drain) and remains low on power-

up for 40ms to 200ms after VCC passes

VPFD (max). An external pull-up resistor t o VCC is

required (1KΩ resistor is recommended). The re-

set pulse remains active with VCC at VSS.

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Reset Inputs (RSTIN1 & RS T IN2)

The M48T559Y provides two independent inputs

which can generate an output reset. The duration

and function of these resets is identical to a reset

generated by a power cycle. Table 6 and Figure 9

illu strat e th e AC re set char acter istic s of this fun c-

tion. Pulses shorter than tR1 and tR2 will not gener-

ate a reset condition. RSTIN1 and RSTIN2 are

each internally pulled up to VCC throug h a 100kΩ

resistor.

Batt ery Lo w W arn in g

The M48T559Y checks its battery vol tage on pow-

er-up. The BL (Battery Low) Bit (D4 of 1FF0h) will

be set on power-up if the battery voltage is less

than 2.5V (typical).

In it ia l P o we r - on Defau l ts

Upon application of power to the device, the fol-

lowing register bits are set to a '0' state: WDS;

BMB0-BMB4; RB0 -RB1; AFE; ABE; W; R; and FT.

Figure 9. RSTIN1 & RSTIN2 Timin g Wa veform s

Table 6. Reset AC Characteristics

Note: 1. Val i d fo r Ambient Op erat in g Te m pera ture : TA = 0 to 70°C; VCC = 4.5 to 5.5V (except where noted).

2. CL = 5pF (see Figure 13., pag e 18).

Symbol Parameter(1) Min Max Unit

tR1 RSTIN1 Low to RST Low 50 200 ns

tR2 RSTIN2 Low to RST Low 20 100 ms

tR1HRZ(2) RSTIN1 High to RST Hi-Z 40 200 ms

tR2HRZ(2) RSTIN2 High to RST Hi-Z 40 200 ms

AI01679

RSTIN1

RST

RSTIN2

tR1 tR1HRZ

Hi-Z

tR2

tR2HRZ

Hi-Z

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M48T559Y

Figure 10. Crys tal Accuracy Acro ss Tem p eratur e

Figu re 11 . Cal ib rat i on W avef orm

AI02124

-80

-60

-100

-40

-20

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70

∆F= -0.038 (T - T

)

± 10%

Fppm

= 25 °C

ppm

°C

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

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VCC Noise And Negative Go ing Transients

ICC transients, including those produced by output

switching, can produce voltage fluctuations, re-

sulting in spikes on the VCC bus. These transients

can be reduced if capacitors are used to store en-

ergy which stabilizes the VCC bus. The energy

stored in the bypass capacitors will be released as

low going spikes are generated or energy will be

absorbed when overshoots occur. A ceramic by-

pass capacitor v alue of 0.1µF (as shown in Figure

12) is recomm ended in order to provide the need-

ed filtering.

In addition to t ransients that are caused by normal

SRAM operation, power cycling can generate neg-

ative voltage s pikes on VCC that drive it to values

below VSS by as much as one volt. These negative

spikes can cause data corruption in the SRAM

while in battery backup mode. To protect from

these voltage spikes, it is recommended to con-

nect a schottky diode from VCC to VSS (cathode

connected to VCC, ano de to VSS). Schottky diode

1N5817 is recommended for through hole and

MBRS120T3 is recommended for surface mount.

Figure 12. Supply Voltage Protection

AI02169

VCC

0.1µF DEVICE

VCC

VSS

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M48T559Y

MAXI MUM RA T IN G

Stressing the device ab ove t he rating l isted in t he

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indic at-

ed in the Operating sections of this specification is

not impl ied. Exposure to Absol ute Max imum Ra t-

ing conditions for extended periods may affect de-

vice reliability. Refer also to the

STMicroelectronics S URE P rogram and other rel-

evant quality documents.

Table 7. Absolute Maximum Ratings

Note: 1. For SO package, standard (S nP b) lead finish: Reflo w at pe ak t em pera ture of 225°C (total thermal budg et not to exceed 180 °C for

betw ee n 90 t o 15 0 s e c o nds).

2. For SO pac kage , Lea d-f ree ( Pb-free) l ead fin i sh: Reflow at p eak tem pera ture of 260°C (total th erm al budget not to exceed 245° C

for greater than 30 seconds).

CAUTION: Negativ e undershoots bel ow –0.3V are not allowed on any pin while i n th e Batte ry Back -up m ode.

CAUTION: Do NOT wa ve sol der SOIC to av oid damagi ng SNAP HAT so ckets .

Symbol Parameter Value Unit

TAAmbient Operating Temperature 0 to 70 °C

TSTG S torage Temperature (VCC Off, Oscillator

Off) SNAPHAT®–40 to 85 °C

SOIC 0 to 70 °C

TSLD(1,2) Lead Solder Temperature for 10 seconds 260 °C

VIO Input or Output Voltage –0.3 to 7 V

VCC Supply Voltage –0.3 to 7 V

IOOutput Current 20 mA

PDPower Dissipation 1 W

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DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Charac teristic tables are

derived from tests pe rformed unde r the Measure-

ment Condition s listed in the relevant tables. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 8. DC and AC Measureme nt Conditions

Note: O ut put High Z is def i ned as the point where data i s no longer dri ven.

Fi gure 13 . AC Testing Load Circ uit

Table 9. Capacitance

Note: 1. Effectiv e capa citan ce meas ured with po wer su pply at 5V; sampled only, n ot 100% tested.

2. At 25° C; f = 1MHz.

3. Outputs are desel ected.

Parameter M48T559Y

VCC Supply Voltage 4.5 to 5.5V

Ambient Operating Temperature 0 to 70°C

Load Capacitance (CL)100pF

Input Rise and Fall Times ≤ 5ns

Input Pulse Voltages 0 to 3V

Input and Output Timing Ref. Voltages 1.5V

AI01673

OUT

CL = 100pF

CL includes JIG capacitance

1.9kΩ

DEVICE

UNDER

TEST

1kΩ

Symbol Parameter(1,2) Min Max Unit

CIN Input Capacitance 10 pF

COUT(3) Output Capacitanc e 10 pF

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M48T559Y

Table 10. DC Characteristics

Note: 1. Val i d fo r Ambient Op erat in g Te m pera ture : TA = 0 to 70°C; VCC = 4.5 to 5.5V (except where noted).

2. Outputs Desel ected.

3. Input l eakag e curr ent on i n put RST IN1 and RS T IN2 pins.

4. AD0- AD7, A S0 , AS1 active w hen E i s high and VCC > VPFD.

5. Ne ga t i ve spi kes of –1V a l l o wed for up t o 10ns once per cy cl e .

6. For I RQ/FT pin (Open Drai n).

Sym Parameter Test Condition(1) Min Typ Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO(2) Output Leak age Curren t 0V ≤ VOUT ≤ VCC ±1 µA

ILRST(3) Input Leakage Current 0V ≤ VIN ≤ VCC 100 µA

ICC Supply Curre nt Outputs open 50 mA

ICC1 Supply Current (Standby) TTL E = VIH 10 mA

ICC2(4) Supply Current (Standby) CMOS E = VCC – 0.2V 7mA

VIL(5) Input Low Voltage –0.3 0.8 V

VIH Input High Voltage 2.2 VCC + 0.3 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

Output Low Voltage (IRQ/FT) (6) IOL = 10mA 0.4 V

VOH Output High Voltage IOL = –1mA 2.4 V

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Figure 14. Power Down /U p Mode AC Waveform s

Table 11. Power Down/U p AC Characteri stics

Note: 1. Val i d fo r Ambient Op erat in g Te m pera ture : TA = 0 to 70°C; VCC = 4.5 to 5.5V (except where noted).

2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselec t i on/wri te pr ot ectio n not occurring un til

200µs after VCC passes VPFD (min).

3. VPFD ( min) to VSS fall time of less than tFB may cause corrup tion of RA M data.

Table 12. Power Down/U p Trip Points DC Characteristic s

Note: 1. Val i d fo r Ambient Op erat in g Te m pera ture : TA = 0 to 70°C; VCC = 4.5 to 5.5V (except where noted).

2. All voltages referenced to VSS.

3. At 25° C, VCC = 0V (when usi ng SOH2 8 + M 4T 28-BR12SH SNAPHAT ® top).

Symbol Parameter(1) Min Typ Max Unit

tF(2) VPFD (max) to VPFD (min) VCC Fall Time 300 µs

tFB(3) VPFD (min) to VSS VCC Fall Time 10 µs

tPD EX at VIH before Power Down 0µs

tRVPFD (min) to VPFD (max) VCC Rise Time 10 µs

tRB VSS to VPFD (min) VCC Rise Time 1µs

trec VPFD (max) to RST High 40 200 ms

Symbol Parameter(1,2) Min Typ Max Unit

VPFD Power-fail Deselect Voltage 4.2 4.35 4.5 V

VSO Battery Back-up Switchover Voltage 3.0 V

tDR(3) Expected Data Retention Time 7 YEARS

AI01384D

VCC

INPUTS

RST

(PER CONTROL INPUT)

OUTPUTS

DON'T CARE

HIGH-Z

tFB

trec

tPD

tRB

tDR

VALID VALID

(PER CONTROL INPUT)

RECOGNIZEDRECOGNIZED

VPFD (max)

VPFD (min)

VSO

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M48T559Y

P ACKAGE ME CHANICA L INFO RMATIO N

Figure 15. SOH28 – 28-lead Plast ic Small Outline, Battery SNAPHAT, Package Outl ine

No te : Dra wi ng is not to scal e.

Table 13. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package M ech. Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 3.05 0.120

A1 0.05 0.36 0.002 0.014

A2 2.34 2.69 0.092 0.106

B 0.36 0.51 0.014 0.020

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e1.27– –0.050– –

eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

α0° 8° 0° 8°

N 28 28

CP 0.10 0.004

SOH-A

LA1 α

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Figure 16. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline

No te : Dra wi ng is not to scal e.

Table 14. SH – 4-pin S NAPHAT Housing for 48mA h Bat tery & Crystal, Package Mech. Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 9.78 0.385

A1 6.73 7.24 0.265 0.285

A2 6.48 6.99 0.255 0.275

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 14.22 14.99 0.560 0.590

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

SHTK-A

A1 A

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M48T559Y

Figure 17. SH – 4-pin S N APHAT H ousing f or 12 0mAh Battery & Crystal, Package Outline

No te : Dra wi ng is not to scal e.

Table 15. SH – 4-p in SNAPHA T Housing for 120m Ah Ba tter y & C ryst al, Package Mech. Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 10.54 0.415

A1 8.00 8.51 0.315 0.335

A2 7.24 8.00 0.285 0.315

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 17.27 18.03 0.680 0.710

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

SHTK-A

A1 A

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PART NUMBERING

Table 16. Ordering Information Scheme

Note : 1. The 2 8- pin SO IC pa ck age ( SO H28) req uire s th e SNA PH AT® b atte ry/cry s tal pac kage wh ich is order ed s epar atel y und er the p art

number “M4TXX-BR12SHX” in pl astic tu be or “M4T XX-B R12 SH XTR” in Tape & Reel form (see T abl e 17).

Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell bat-

tery.

For other options, or for more information on any aspect of this device, please contact the ST Sales Office

nearest you.

Table 17. SNAPHAT Battery Table

Example: M48T 559Y MH 6 E

Device Type

M48T

Supply Voltage and Write Protect Voltage

559Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V

Package

MH(1) = SOH28

Tem pera ture Rang e

1 = 0 to 70°C

Shipping Method

blank = Tubes (Not for New Design - Use E)

E = Lead-free Package (ECO PACK®), Tubes

F = Lead-free Package (ECO PACK®), Tape & Reel

TR = Tape & Reel (Not for New Design - Use F)

Part Number Description Package

M4T28-BR12SH Lithium Battery (48mAh) and Crystal SNAPHAT SH

M4T32-BR12SH Lithium Battery (120mAh) and Crystal SNAPHAT SH

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M48T559Y

REVISION HISTORY

Table 18. Document Revi sion History

Date Rev. # Revision Details

June 1998 1.0 First Issue

07-Feb-00 1.1

Description Paragraph changed; setting Alarm Clock paragraph changed; M4T28-BR12SH

SNAPHAT Housing for 48mAh Battery & Crystal Package added (Table 14); Power Down/

Up Mode AC Waveforms changed (Figure 14); Back-up Mode Alarm Waveforms changed

(Figure 8)

13-Aug-01 2.0 Reformatted; added temperature information (Tables 9, 10, 3, 11, 12)

20-May-02 2.1 Modify reflow time and temperature footnote (Table 7)

31-Mar-03 3.0 v2.2 template applied; data retention condition updated (Table 12)

01-Apr-04 4.0 Reformatted; update Lead-free package information (Table 7, 16)

Obsolete Product(s) - Obsolete Product(s)

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M48T559Y

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to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

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Obsolete Product(s) - Obsolete Product(s)