M-TMXL336251BL-21-DB - Agere Systems, Inc.

Hardware Design Guide, Revision 1

April 29, 2003

TMXL33625 HypermapperLite

622/155 Mbits/s SONET/SDH x DS3/E3

1 Introduction

The last issue of this data sheet was February 21, 2003. A change history (since February 21, 2003) is included in Section

12, Change History, on page 64. Red change bars have been installed on all text, figures, and tables that were added or

changed. All changes to the text are highlighted in red. Changes within figures, and the figure title itself, are highlighted in

red, if feasible.

The documentation package for the TMXL33625 HypermapperLite 622/155 Mbits/s SONET/SDH x DS3/E3 system chip

consists of the following documents:

■The Register Description and the System Design Guide. These documents are available on a password protected web-

site.

■The HypermapperLite Product Description and the HypermapperLite Hardware Design Guide (this document). These

documents are available on the public website shown below (select Mappers/MUXes).

http://www.agere.com/enterprise_metro_access/index.html

This document describes the hardware interfaces of the Agere Systems TMXL33625 HypermapperLite device. Information

relevant to the use of the device in a board design is covered. Pin descriptions, dc electrical characteristics, timing

diagrams, ac timing parameters, packaging, and operating conditions are covered.

If the reader displays this document using Acrobat ®Reader ®, clicking on any blue text will bring the reader to that refer-

ence point. Clicking on the back arrow (Go to previous View) in the toolbar of the Acrobat Reader will bring the reader back

to the starting point.

To contact Agere Systems, see the last page of this document or contact your Agere representative.

Figure 1-1. HypermapperLite Block Diagram and High-Level Interface Definition

FRM PLL IF

TMUX-A

CDR

Clock & Data

Clock/Sync

TMUX-B

CDR

Clock & Data

Clock/Sync

TMUX-C

CDR

Clock & Data

Clock/Sync

TMUX-D

CDR

Clock & Data

Clock/Sync

Miscellaneous

622/155Mb/s

High-Speed IF

STSPP

STS

STSPP

STS

STSPP

STS

STSPP

STS

622/155 Mbits/s SONET/SDH

ADM Front End

DS3/E3/DS1/E1/DS0 PDH

Tributary Termination

JTAG IF

JTAG A B C D

Mate Interconnect

MCDR

(x12)

LOPOH

24LOPOH

From/To

TMUX A,B,C,D

A B

C D

SPEMPR x12

(3-5)

A B

C D

SPEMPR x12

(0-2)

A B

C D

STS1LT x12

MPU

MPU IF

A B C D

A,B,C,D

MRXC

A B

C D

VTMPR (x12)

x28/x21

A B

C D

DS1/E1 DJA

x28/x21 (x12)

DS1XCLK,

E1XCLK

A B

C D

DS3/E3 DJA

x6 (x4)

DS3XCLK,

E3XCLK

TOAC

24 24

POAC

A B

C D

TPGM

(x4)

A B

C D

E13 MUX

(x12)

A B

C D

M13 MUX

(x12)

A B

C D

FRM (x12)

x28/x21

DS1/J1/E1

VT/TU

DS3/E3

System

Interfaces

Power & GND

pins not shown

168

(x24) DS3/E3

(x12) STS-1

(x12) NSMI

(x12) STS-1

(Total of 3 STS-1

max/partition)

032303

Note: Partitions (A, B, C, and D) are totally separate and cannot be interconnected internally. For example, a DS1 out of a VTMPR from

partition A, cannot be sent to the MRXC of partition B.

Table of Contents

Contents Page

2Agere Systems Inc.

Hardware Design Guide, Revision 1

April 29, 2003

622/155 Mbits/s SONET/SDH x DS3/E3

TMXL33625 HypermapperLite

1 Introduction .........................................................................................................................................................................1

2 Pin Information ...................................................................................................................................................................6

2.1 Ball Diagram .................................................................................................................................................................6

2.2 Pin Assignments ...........................................................................................................................................................7

2.3 Pin Matrix ....................................................................................................................................................................20

2.4 Pin Types ....................................................................................................................................................................24

2.5 Pin Definitions .............................................................................................................................................................25

3 Absolute Maximum Ratings ..............................................................................................................................................42

3.1 Handling Precautions ..................................................................................................................................................42

4 Electrical Characteristics ..................................................................................................................................................43

4.1 Recommended Operating Voltages ............................................................................................................................43

4.2 Recommended Powerup Sequence ...........................................................................................................................43

4.3 Power Consumption ....................................................................................................................................................43

4.4 ac and dc Characteristics ............................................................................................................................................44

4.4.1 LVCMOS Interface Characteristics .......................................................................................................................44

4.4.2 LVDS Interface Characteristics .............................................................................................................................46

5 Timing ...............................................................................................................................................................................47

5.1 TMUX High-Speed Interface Timing ...........................................................................................................................47

5.2 THSSYNC Characteristics ..........................................................................................................................................48

5.3 STS-3/STM-1 Mate Interconnect Timing ....................................................................................................................49

5.4 TOAC, POAC, and LOPOH Timing ............................................................................................................................50

5.5 DS3/E3/STS-1 Timing .................................................................................................................................................51

5.6 NSMI Timing ...............................................................................................................................................................52

6 Reference Clocks .............................................................................................................................................................53

7 Microprocessor Interface Timing ......................................................................................................................................57

7.1 Synchronous Write Mode ............................................................................................................................................57

7.2 Synchronous Read Mode ...........................................................................................................................................58

7.3 Asynchronous Write Mode ..........................................................................................................................................59

7.4 Asynchronous Read Mode ..........................................................................................................................................60

7.5 Accessing the Same Register Sequentially Across Multiple Partitions. ......................................................................61

8 Other Timing .....................................................................................................................................................................62

9 Hardware Design File References ....................................................................................................................................62

10 Ordering Information .......................................................................................................................................................62

11 1152-Pin PBGA Diagrams ..............................................................................................................................................63

12 Change History ...............................................................................................................................................................64

12.1 Navigating Through an Adobe Acrobat Document ...................................................................................................64

13 Glossary .........................................................................................................................................................................65

Table of Contents (continued)

Figures Page

Agere Systems Inc. 3

Hardware Design Guide, Revision 1

April 29, 2003 622/155 Mbits/s SONET/SDH x DS3/E3

TMXL33625 HypermapperLite

Figure 1-1. HypermapperLite Block Diagram and High-Level Interface Definition .................................................................1

Figure 2-1. HypermapperLite Pin-Package Diagram (Top View) ...........................................................................................6

Figure 5-1. TMUX LVDS Signal Rise/Fall Timing.................................................................................................................47

Figure 5-2. TMUX LVDS Clock and Data Timing .................................................................................................................47

Figure 5-3. THSSYNC Timing Diagram (MPU_MASTER_SLAVE = 1)................................................................................48

Figure 5-4. THSSYNC Timing Diagram (MPU_MASTER_SLAVE = 0)................................................................................48

Figure 5-5. STS-3/STM-1 Mate Rise/Fall Timing .................................................................................................................49

Figure 5-6. STS-3/STM-1 Mate Clock and Data Timing.......................................................................................................49

Figure 5-7. TOAC, POAC Timing .........................................................................................................................................50

Figure 5-8. LOPOH Timing...................................................................................................................................................50

Figure 5-9. DS3/E3 Interface Diagram in M13/E13 Block ....................................................................................................51

Figure 5-10. NSMI Clock and Data Timing (STS-1 Mode) ...................................................................................................52

Figure 7-1. Microprocessor Interface Synchronous Write Cycle (MPMODE = 1).................................................................57

Figure 7-2. Microprocessor Interface Synchronous Read Cycle (MPMODE = 1) ................................................................58

Figure 7-3. Microprocessor Interface Asynchronous Write Cycle (MPMODE = 0)...............................................................59

Figure 7-4. Microprocessor Interface Asynchronous Read Cycle (MPMODE = 0)...............................................................60

Figure 11-1. 1152-Pin PBGA Physical Dimensions..............................................................................................................63

Table of Contents (continued)

Tables Page

4Agere Systems Inc.

Hardware Design Guide, Revision 1

April 29, 2003

622/155 Mbits/s SONET/SDH x DS3/E3

TMXL33625 HypermapperLite

Table 2-1. Pin Assignments....................................................................................................................................................7

Table 2-2. Pin Matrix ............................................................................................................................................................20

Table 2-3. Pin Types ............................................................................................................................................................24

Table 2-4. TMUX Blocks, High-Speed Interface I/O.............................................................................................................25

Table 2-5. TMUX Blocks, Protection Link I/O .......................................................................................................................27

Table 2-6. TMUX Blocks, Clock and Sync I/O......................................................................................................................28

Table 2-7. STS Cross Connect (STSXC) Blocks, STS-3/STM-1 Mate Interconnect............................................................29

Table 2-8. Multirate Cross Connect (MRXC) Blocks, TOAC Input and Output Channels ....................................................30

Table 2-9. Multirate Cross Connect (MRXC) Blocks, POAC Input and Output Channels ....................................................31

Table 2-10. DS3/E3/STS-1 Out ............................................................................................................................................32

Table 2-11. DS3/E3/STS-1 In...............................................................................................................................................33

Table 2-12. NSMI/STS-1 In ..................................................................................................................................................34

Table 2-13. NSMI/STS-1 Out ...............................................................................................................................................35

Table 2-14. Reference Clocks ..............................................................................................................................................35

Table 2-15. Low-Order Path Overhead Access, Transmit Direction ....................................................................................36

Table 2-16. Low-Order Path Overhead Access, Receive Direction .....................................................................................36

Table 2-17. Clock Generator ................................................................................................................................................37

Table 2-18. Microprocessor Interface...................................................................................................................................37

Table 2-19. Boundary Scan (IEEE 1149.1) ........................................................................................................................38

Table 2-20. General-Purpose Interface ................................................................................................................................39

Table 2-21. CDR Interface....................................................................................................................................................39

Table 2-22. Analog Power and Ground Signals ...................................................................................................................40

Table 2-23. Digital Power and Ground Signals ....................................................................................................................41

Table 2-24. No Connects......................................................................................................................................................41

Table 3-1. Absolute Maximum Ratings.................................................................................................................................42

Table 3-2. ESD Tolerance ....................................................................................................................................................42

Table 4-1. Recommended Operating Conditions .................................................................................................................43

Table 4-2. Typical Power Consumption by Application ........................................................................................................43

Table 4-3. Typical Power Consumption Per Block ...............................................................................................................43

Table 4-4. LVCMOS Inputs Specifications 1 ........................................................................................................................44

Table 4-5. LVCMOS Inputs Specifications 2 ........................................................................................................................44

Table 4-6. LVCMOS Inputs Specifications 3 ........................................................................................................................44

Table 4-7. LVCMOS Outputs Specifications ........................................................................................................................45

Table 4-8. LVCMOS Bidirectionals Specifications................................................................................................................45

Table 4-9. LVDS Interface dc Characteristics ......................................................................................................................46

Table 5-1. High-Speed Interface Inputs Specifications ........................................................................................................47

Table 5-2. Protection Link Inputs Specifications...................................................................................................................47

Table 5-3. High-Speed Interface Outputs Specifications......................................................................................................48

Table 5-4. Protection Link Outputs Specifications................................................................................................................48

Table 5-5. STS-3/STM-1 Mate Interconnect Inputs Specifications.......................................................................................49

Table 5-6. STS-3/STM-1 Mate Interconnect Outputs Specifications....................................................................................49

Table 5-7. TOAC and POAC and LOPOH Input Specifications ...........................................................................................50

Table 5-8. TOAC and POAC and LOPOH Output Specifications.........................................................................................50

Table 5-9. DS3/E3 Input Specifications................................................................................................................................51

Table 5-10. STS-1 Input Specifications ................................................................................................................................51

Table 5-11. DS3/E3/STS-1 Output Specifications................................................................................................................51

Table 5-12. NSMI Input Specifications .................................................................................................................................52

Table 5-13. NSMI Output Specifications ..............................................................................................................................52

Table 6-1. High-Speed Interface Input Clocks Specifications ..............................................................................................53

Table 6-2. Protection Link Input Clock Specifications ..........................................................................................................53

Table 6-3. DS3/E3/STS-1 Input Clocks Specifications.........................................................................................................53

Table 6-4. DS1/E1 DJA Input Clocks Specifications ............................................................................................................53

Table 6-5. DS3/E3 DJA Input Clocks Specifications ............................................................................................................54

Table 6-6. LOPOH Input Clock Specifications......................................................................................................................54

Table 6-7. Microprocessor Interface Input Clocks Specifications.........................................................................................54

Tables of Contents (continued)

Tables Page

Agere Systems Inc. 5

Hardware Design Guide, Revision 1

April 29, 2003 622/155 Mbits/s SONET/SDH x DS3/E3

TMXL33625 HypermapperLite

Table 6-8. PLL Input Clock Specifications............................................................................................................................54

Table 6-9. High-Speed Interface Output Clocks Specifications............................................................................................54

Table 6-10. Protection Link Output Clocks Specifications....................................................................................................54

Table 6-11. Line Timing Interface Output Clocks Specifications ..........................................................................................54

Table 6-12. TOAC Output Clocks Specifications..................................................................................................................55

Table 6-13. POAC Output Clocks Specifications .................................................................................................................55

Table 6-14. DS3/E3/STS-1 Output Clocks Specifications ....................................................................................................56

Table 6-15. LOPOH Output Clock Specifications.................................................................................................................56

Table 6-16. PLL Output Clocks Specifications .....................................................................................................................56

Table 6-17. NSMI Input/Output Clocks Specifications..........................................................................................................56

Table 7-1. Microprocessor Interface Synchronous Write Cycle Specifications ....................................................................57

Table 7-2. Microprocessor Interface Synchronous Read Cycle Specifications ....................................................................58

Table 7-3. Microprocessor Interface Asynchronous Write Cycle Specifications ..................................................................60

Table 7-4. Microprocessor Interface Asynchronous Read Cycle Specifications ..................................................................61

Table 8-1. General-Purpose Inputs Specifications ...............................................................................................................62

Table 8-2. Miscellaneous Output Specifications...................................................................................................................62

Table 8-3. General-Purpose Output Specifications ..............................................................................................................62

Table 10-1. Ordering Information .........................................................................................................................................62

TMXL33625 HypermapperLite Hardware Design Guide, Revision 1

622/155 Mbits/s SONET/SDH x DS3/E3 April 29, 2003

66 Agere Systems Inc.

2 Pin Information

2.1 Ball Diagram

The TMXL33625 HypermapperLite is housed in a 1152-pin plastic ball grid array (PBGA), which is 45 mm2 with a

1.27 mm2 ball pitch. Figure 2-1 shows the ball assignment viewed from the top of the package.

Figure 2-1. HypermapperLite Pin-Package Diagram (Top View)

26 28

24 32

46810

14 16

234

523

731

2915 21

327

11 17913133

Hardware Design Guide, Revision 1 TMXL33625 HypermapperLite

April 29, 2003 622/155 Mbits/s SONET/SDH x DS3/E3

Agere Systems Inc. 7

2.2 Pin Assignments

Table 2-1. Pin Assignments

Signal Name Pin

MPMODE AG20

MPCLK AG21

CSN_A D15

CSN_B R31

CSN_D AL20

CSN_C Y4

ADSN AE21

RWN AJ20

DSN T28

ADDR[0] AH19

ADDR[1] AJ21

ADDR[2] AH21

ADDR[3] R29

ADDR[4] R27

ADDR[5] AF21

ADDR[6] AH20

ADDR[7] AE22

ADDR[8] T26

ADDR[9] R28

ADDR[10] AD22

ADDR[11] T27

ADDR[12] R26

ADDR[13] AJ22

ADDR[14] AC22

ADDR[15] P29

ADDR[16] AG22

ADDR[17] N24

ADDR[18] N25

ADDR[19] N29

ADDR[20] AB22

DATA[0] Y8

DATA[1] P28

DATA[2] L22

DATA[3] AA6

DATA[4] P25

DATA[5] AA8

DATA[6] M22

DATA[7] AB6

DATA[8] AA7

DATA[9] AF22

DATA[10] P27

DATA[11] P26

DATA[12] AB8

DATA[13] AB9

Signal Name Pin

DATA[14] N22

DATA[15] N26

PAR[0] AB23

PAR[1] N23

DTN AB24

HP_INTN_1 AB10

HP_INTN_2 M33

LP_INTN_1 F13

LP_INTN_2 AB11

APS_INTN_A G14

APS_INTN_B J33

APS_INTN_D AN26

APS_INTN_C AC2

DS3POSDATAIN_A[1] A14

DS3POSDATAIN_B[1] P34

DS3POSDATAIN_D[1] AP21

DS3POSDATAIN_C[1] AA1

DS3NEGDATAIN_A[1] E11

DS3NEGDATAIN_B[1] L30

DS3NEGDATAIN_D[1] AK24

DS3NEGDATAIN_C[1] AD5

DS3DATAINCLK_A[1] C11

DS3DATAINCLK_B[1] L32

DS3DATAINCLK_D[1] AM24

DS3DATAINCLK_C[1] AD3

DS3POSDATAIN_A[2] A13

DS3POSDATAIN_B[2] N34

DS3POSDATAIN_D[2] AP22

DS3POSDATAIN_C[2] AB1

DS3NEGDATAIN_A[2] A12

DS3NEGDATAIN_B[2] M34

DS3NEGDATAIN_D[2] AP23

DS3NEGDATAIN_C[2] AC1

DS3DATAINCLK_A[2] H12

DS3DATAINCLK_B[2] M27

DS3DATAINCLK_D[2] AG23

DS3DATAINCLK_C[2] AC8

DS3POSDATAIN_A[3] B11

DS3POSDATAIN_B[3] L33

DS3POSDATAIN_D[3] AN24

DS3POSDATAIN_C[3] AD2

DS3NEGDATAIN_A[3] C10

DS3NEGDATAIN_B[3] K32

DS3NEGDATAIN_D[3] AM25

DS3NEGDATAIN_C[3] AE3

DS3DATAINCLK_A[3] F11

Table 2-1. Pin Assignments (continued)

TMXL33625 HypermapperLite Hardware Design Guide, Revision 1

622/155 Mbits/s SONET/SDH x DS3/E3 April 29, 2003

88 Agere Systems Inc.

Signal Name Pin

DS3DATAINCLK_B[3] L29

DS3DATAINCLK_D[3] AJ24

DS3DATAINCLK_C[3] AD6

DS3POSDATAIN_A[4] G11

DS3POSDATAIN_B[4] L28

DS3POSDATAIN_D[4] AH24

DS3POSDATAIN_C[4] AD7

DS3NEGDATAIN_A[4] A11

DS3NEGDATAIN_B[4] L34

DS3NEGDATAIN_D[4] AP24

DS3NEGDATAIN_C[4] AD1

DS3DATAINCLK_A[4] B10

DS3DATAINCLK_B[4] K33

DS3DATAINCLK_D[4] AN25

DS3DATAINCLK_C[4] AE2

DS3POSDATAIN_A[5] D10

DS3POSDATAIN_B[5] K31

DS3POSDATAIN_D[5] AL25

DS3POSDATAIN_C[5] AE4

DS3NEGDATAIN_A[5] A10

DS3NEGDATAIN_B[5] K34

DS3NEGDATAIN_D[5] AP25

DS3NEGDATAIN_C[5] AE1

DS3DATAINCLK_A[5] C9

DS3DATAINCLK_B[5] J32

DS3DATAINCLK_D[5] AM26

DS3DATAINCLK_C[5] AF3

DS3POSDATAIN_A[6] E10

DS3POSDATAIN_B[6] K30

DS3POSDATAIN_D[6] AK25

DS3POSDATAIN_C[6] AE5

DS3NEGDATAIN_A[6] A9

DS3NEGDATAIN_B[6] J34

DS3NEGDATAIN_D[6] AP26

DS3NEGDATAIN_C[6] AF1

DS3DATAINCLK_A[6] A8

DS3DATAINCLK_B[6] H34

DS3DATAINCLK_D[6] AP27

DS3DATAINCLK_C[6] AG1

DS3POSDATAOUT_A[1] F10

DS3POSDATAOUT_B[1] K29

DS3POSDATAOUT_D[1] AJ25

DS3POSDATAOUT_C[1] AE6

DS3NEGDATAOUT_A[1] B8

DS3NEGDATAOUT_B[1] H33

DS3NEGDATAOUT_D[1] AN27

Table 2-1. Pin Assignments (continued)

Signal Name Pin

DS3NEGDATAOUT_C[1] AG2

DS3RXCLKOUT_A[1] C8

DS3RXCLKOUT_B[1] H32

DS3RXCLKOUT_D[1] AM27

DS3RXCLKOUT_C[1] AG3

DS3DATAOUTCLK_A[1] A7

DS3DATAOUTCLK_B[1] G34

DS3DATAOUTCLK_D[1] AP28

DS3DATAOUTCLK_C[1] AH1

DS3POSDATAOUT_A[2] H11

DS3POSDATAOUT_B[2] L27

DS3POSDATAOUT_D[2] AG24

DS3POSDATAOUT_C[2] AD8

DS3NEGDATAOUT_A[2] B7

DS3NEGDATAOUT_B[2] G33

DS3NEGDATAOUT_D[2] AN28

DS3NEGDATAOUT_C[2] AH2

DS3RXCLKOUT_A[2] A6

DS3RXCLKOUT_B[2] F34

DS3RXCLKOUT_D[2] AP29

DS3RXCLKOUT_C[2] AJ1

DS3DATAOUTCLK_A[2] E9

DS3DATAOUTCLK_B[2] J30

DS3DATAOUTCLK_D[2] AK26

DS3DATAOUTCLK_C[2] AF5

DS3POSDATAOUT_A[3] C7

DS3POSDATAOUT_B[3] G32

DS3POSDATAOUT_D[3] AM28

DS3POSDATAOUT_C[3] AH3

DS3NEGDATAOUT_A[3] B6

DS3NEGDATAOUT_B[3] F33

DS3NEGDATAOUT_D[3] AN29

DS3NEGDATAOUT_C[3] AJ2

DS3RXCLKOUT_A[3] E8

DS3RXCLKOUT_B[3] H30

DS3RXCLKOUT_D[3] AK27

DS3RXCLKOUT_C[3] AG5

DS3DATAOUTCLK_A[3] A5

DS3DATAOUTCLK_B[3] E34

DS3DATAOUTCLK_D[3] AP30

DS3DATAOUTCLK_C[3] AK1

DS3POSDATAOUT_A[4] A4

DS3POSDATAOUT_B[4] D34

DS3POSDATAOUT_D[4] AP31

DS3POSDATAOUT_C[4] AL1

DS3NEGDATAOUT_A[4] C6

Table 2-1. Pin Assignments (continued)

Hardware Design Guide, Revision 1 TMXL33625 HypermapperLite

April 29, 2003 622/155 Mbits/s SONET/SDH x DS3/E3

Agere Systems Inc. 9

Signal Name Pin

DS3NEGDATAOUT_B[4] F32

DS3NEGDATAOUT_D[4] AM29

DS3NEGDATAOUT_C[4] AJ3

DS3RXCLKOUT_A[4] D7

DS3RXCLKOUT_B[4] G31

DS3RXCLKOUT_D[4] AL28

DS3RXCLKOUT_C[4] AH4

DS3DATAOUTCLK_A[4] B4

DS3DATAOUTCLK_B[4] D33

DS3DATAOUTCLK_D[4] AN31

DS3DATAOUTCLK_C[4] AL2

DS3POSDATAOUT_A[5] C5

DS3POSDATAOUT_B[5] E32

DS3POSDATAOUT_D[5] AM30

DS3POSDATAOUT_C[5] AK3

DS3NEGDATAOUT_A[5] A3

DS3NEGDATAOUT_B[5] C34

DS3NEGDATAOUT_D[5] AP32

DS3NEGDATAOUT_C[5] AM1

DS3RXCLKOUT_A[5] G10

DS3RXCLKOUT_B[5] K28

DS3RXCLKOUT_D[5] AH25

DS3RXCLKOUT_C[5] AE7

DS3DATAOUTCLK_A[5] A2

DS3DATAOUTCLK_B[5] B34

DS3DATAOUTCLK_D[5] AP33

DS3DATAOUTCLK_C[5] AN1

DS3POSDATAOUT_A[6] B3

DS3POSDATAOUT_B[6] C33

DS3POSDATAOUT_D[6] AN32

DS3POSDATAOUT_C[6] AM2

DS3NEGDATAOUT_A[6] C4

DS3NEGDATAOUT_B[6] D32

DS3NEGDATAOUT_D[6] AM31

DS3NEGDATAOUT_C[6] AL3

DS3RXCLKOUT_A[6] E7

DS3RXCLKOUT_B[6] G30

DS3RXCLKOUT_D[6] AK28

DS3RXCLKOUT_C[6] AH5

DS3DATAOUTCLK_A[6] D5

DS3DATAOUTCLK_B[6] E31

DS3DATAOUTCLK_D[6] AL30

DS3DATAOUTCLK_C[6] AK4

REF10_A F4

REF10_B D29

REF10_D AJ31

Table 2-1. Pin Assignments (continued)

Signal Name Pin

REF10_C AL6

REF14_A G9

REF14_B J28

REF14_D AH26

REF14_C AF7

RESHI_A F9

RESHI_B J29

RESHI_D AJ26

RESHI_C AF6

RESLO_A G8

RESLO_B H28

RESLO_D AH27

RESLO_C AG7

RHSC_AP E4

RHSC_BP D30

RHSC_DP AK31

RHSC_CP AL5

RHSC_AN E3

RHSC_BN C30

RHSC_DN AK32

RHSC_CN AM5

CTAPRH_A F6

CTAPRH_B F29

CTAPRH_D AJ29

CTAPRH_C AJ6

RHSD_AP D3

RHSD_BP C31

RHSD_DP AL32

RHSD_CP AM4

RHSD_AN C3

RHSD_BN C32

RHSD_DN AM32

RHSD_CN AM3

THSCO_AP B2

THSCO_BP B33

THSCO_DP AN33

THSCO_CP AN2

THSCO_AN B1

THSCO_BN A33

THSCO_DN AN34

THSCO_CN AP2

CTAPTH_A F7

CTAPTH_B G29

CTAPTH_D AJ28

CTAPTH_C AH6

THSD_AP C2

Table 2-1. Pin Assignments (continued)

TMXL33625 HypermapperLite Hardware Design Guide, Revision 1

622/155 Mbits/s SONET/SDH x DS3/E3 April 29, 2003

1010 Agere Systems Inc.

Signal Name Pin

THSD_BP B31

THSD_DP AL33

THSD_CP AN4

THSD_AN C1

THSD_BN A31

THSD_DN AL34

THSD_CN AP4

THSC_AP E2

THSC_BP B30

THSC_DP AK33

THSC_CP AN5

THSC_AN E1

THSC_BN A30

THSC_DN AK34

THSC_CN AP5

RPSD_AP F3

RPSD_BP C29

RPSD_DP AJ32

RPSD_CP AM6

RPSD_AN G3

RPSD_BN C28

RPSD_DN AH32

RPSD_CN AM7

CTAPRP_A G7

CTAPRP_B G28

CTAPRP_D AH28

CTAPRP_C AH7

RPSC_AP H4

RPSC_BP D27

RPSC_DP AG31

RPSC_CP AL8

RPSC_AN G4

RPSC_BN D28

RPSC_DN AH31

RPSC_CN AL7

TPSC_AP G2

TPSC_BP B28

TPSC_DP AH33

TPSC_CP AN7

TPSC_AN G1

TPSC_BN A28

TPSC_DN AH34

TPSC_CN AP7

TPSD_AP H2

TPSD_BP B27

TPSD_DP AG33

Table 2-1. Pin Assignments (continued)

Signal Name Pin

TPSD_CP AN8

TPSD_AN H1

TPSD_BN A27

TPSD_DN AG34

TPSD_CN AP8

RLSDATA_AP[1] J1

RLSDATA_BP[1] A26

RLSDATA_DP[1] AF34

RLSDATA_CP[1] AP9

RLSDATA_AN[1] K1

RLSDATA_BN[1] A25

RLSDATA_DN[1] AE34

RLSDATA_CN[1] AP10

RLSDATA_AP[2] L1

RLSDATA_BP[2] A24

RLSDATA_DP[2] AD34

RLSDATA_CP[2] AP11

RLSDATA_AN[2] M1

RLSDATA_BN[2] A23

RLSDATA_DN[2] AC34

RLSDATA_CN[2] AP12

TLSDATA_AP[3] H7

TLSDATA_BP[3] G27

TLSDATA_DP[3] AG28

TLSDATA_CP[3] AH8

TLSDATA_AN[3] H8

TLSDATA_BN[3] H27

TLSDATA_DN[3] AG27

TLSDATA_CN[3] AG8

RLSDATA_AP[3] M2

RLSDATA_BP[3] B23

RLSDATA_DP[3] AC33

RLSDATA_CP[3] AN12

RLSDATA_AN[3] L2

RLSDATA_BN[3] B24

RLSDATA_DN[3] AD33

RLSDATA_CN[3] AN11

TLSDATA_AP[1] H3

TLSDATA_BP[1] C27

TLSDATA_DP[1] AG32

TLSDATA_CP[1] AM8

TLSDATA_AN[1] J3

TLSDATA_BN[1] C26

TLSDATA_DN[1] AF32

TLSDATA_CN[1] AM9

VDD15A_CDR2_A H5

Table 2-1. Pin Assignments (continued)

Hardware Design Guide, Revision 1 TMXL33625 HypermapperLite

April 29, 2003 622/155 Mbits/s SONET/SDH x DS3/E3

Agere Systems Inc. 11

Signal Name Pin

VDD15A_CDR2_B E27

VDD15A_CDR2_D AG30

VDD15A_CDR2_C AK8

VSSA_CDR2_A J4

VSSA_CDR2_B D26

VSSA_CDR2_D AF31

VSSA_CDR2_C AL9

TLSDATA_AP[2] J2

TLSDATA_BP[2] B26

TLSDATA_DP[2] AF33

TLSDATA_CP[2] AN9

TLSDATA_AN[2] K2

TLSDATA_BN[2] B25

TLSDATA_DN[2] AE33

TLSDATA_CN[2] AN10

CTAPTL_A H9

CTAPTL_B J27

CTAPTL_D AG26

CTAPTL_C AF8

VSSA_CDR1_A K3

VSSA_CDR1_B C25

VSSA_CDR1_D AE32

VSSA_CDR1_C AM10

VDD15A_CDR1_A L3

VDD15A_CDR1_B C24

VDD15A_CDR1_D AD32

VDD15A_CDR1_C AM11

RTOACCLK_A K4

RTOACCLK_B D25

RTOACCLK_D AE31

RTOACCLK_C AL10

RTOACDATA_A J5

RTOACDATA_B E26

RTOACDATA_D AF30

RTOACDATA_C AK9

TLSCLK_A L4

TLSCLK_B D24

TLSCLK_D AD31

TLSCLK_C AL11

RLSCLK_A H10

RLSCLK_B K27

RLSCLK_D AG25

RLSCLK_C AE8

THSSYNC_A K5

THSSYNC_B E25

THSSYNC_D AE30

Table 2-1. Pin Assignments (continued)

Signal Name Pin

THSSYNC_C AK10

BYPASS_1 H13

BYPASS_2 AN23

TSTPHASE J13

ECSEL_1 H15

ECSEL_2 AH29

ETOGGLE_1 J14

ETOGGLE_2 AF28

EXDNUP_1 K13

EXDNUP_2 D31

TSTMODE H14

TSTSFTLD J15

VDD15A_X4PLL_A K7

VDD15A_X4PLL_B G25

VDD15A_X4PLL_D AE28

VDD15A_X4PLL_C AH10

VSSA_X4PLL_A K6

VSSA_X4PLL_B F25

VSSA_X4PLL_D AE29

VSSA_X4PLL_C AJ10

RTOACSYNC_A K8

RTOACSYNC_B H25

RTOACSYNC_D AE27

RTOACSYNC_C AG10

TTOACCLK_A J6

TTOACCLK_B F26

TTOACCLKD AF29

TTOACCLK_C AJ9

TTOACSYNC_A L6

TTOACSYNC_B F24

TTOACSYNC_D AD29

TTOACSYNC_C AJ11

TTOACDATA_A L7

TTOACDATA_B G24

TTOACDATA_D AD28

TTOACDATA_C AH11

RPOACCLK_A M6

RPOACCLK_B F23

RPOACCLK_D AC29

RPOACCLK_C AJ12

RPOACDATA_A J8

RPOACDATA_B H26

RPOACDATA_D AF27

RPOACDATA_C AG9

RPOACSYNC_A M5

RPOACSYNC_B E23

Table 2-1. Pin Assignments (continued)

TMXL33625 HypermapperLite Hardware Design Guide, Revision 1

622/155 Mbits/s SONET/SDH x DS3/E3 April 29, 2003

1212 Agere Systems Inc.

Signal Name Pin

RPOACSYNC_D AC30

RPOACSYNC_C AK12

TPOACCLK_A N5

TPOACCLK_B E22

TPOACCLK_D AB30

TPOACCLK_C AK13

TPOACDATA_A N7

TPOACDATA_B G22

TPOACDATA_D AB28

TPOACDATA_C AH13

TPOACSYNC_A M3

TPOACSYNC_B C23

TPOACSYNC_D AC32

TPOACSYNC_C AM12

E1XCLK_1 W9

E1XCLK_2 F28

DS1XCLK_1 AA11

DS1XCLK_2 E33

LOSEXT_A L8

LOSEXT_B H24

LOSEXT_D AD27

LOSEXT_C AG11

RHSFSYNCN_A N2

RHSFSYNCN_B B22

RHSFSYNCN_D AB33

RHSFSYNCN_C AN13

RSTN_A N1

RSTN_B A22

RSTN_D AB34

RSTN_C AP13

PMRST N14

TCK AC21

TDI P15

TMS_1 Y6

TMS_2 AC31

TRST L14

TDO AD21

IC3STATEN M13

SCK1_1 W8

SCK1_2 AA31

SCK2_1 W7

SCK2_2 AL26

SCAN_EN N13

SCANMODE_1 L13

SCANMODE_2 AK30

IDDQ_A N3

Table 2-1. Pin Assignments (continued)

Signal Name Pin

IDDQ_B C22

IDDQ_D AB32

IDDQ_C AM13

NSMIRXDATA_A[1] P1

NSMIRXDATA_B[1] A21

NSMIRXDATA_D[1] AA34

NSMIRXDATA_C[1] AP14

NSMIRXCLK_A[1] M7

NSMIRXCLK_B[1] G23

NSMIRXCLK_D[1] AC28

NSMIRXCLK_C[1] AH12

NSMIRXSYNC_A[1] P2

NSMIRXSYNC_B[1] B21

NSMIRXSYNC_D[1] AA33

NSMIRXSYNC_C[1] AN14

RXDATAEN_A[1] P3

RXDATAEN_B[1] C21

RXDATAEN_D[1] AA32

RXDATAEN_C[1] AM14

NSMIRXDATA_A[2] P6

NSMIRXDATA_B[2] F21

NSMIRXDATA_D[2] AA29

NSMIRXDATA_C[2] AJ14

NSMIRXCLK_A[2] N6

NSMIRXCLK_B[2] F22

NSMIRXCLK_D[2] AB29

NSMIRXCLK_C[2] AJ13

NSMIRXSYNC_A[2] R1

NSMIRXSYNC_B[2] A20

NSMIRXSYNC_D[2] Y34

NSMIRXSYNC_C[2] AP15

RXDATAEN_A[2] R2

RXDATAEN_B[2] B20

RXDATAEN_D[2] Y33

RXDATAEN_C[2] AN15

NSMIRXDATA_A[3] R3

NSMIRXDATA_B[3] C20

NSMIRXDATA_D[3] Y32

NSMIRXDATA_C[3] AM15

NSMIRXCLK_A[3] M8

NSMIRXCLK_B[3] H23

NSMIRXCLK_D[3] AC27

NSMIRXCLK_C[3] AG12

NSMIRXSYNC_A[3] P5

NSMIRXSYNC_B[3] E21

NSMIRXSYNC_D[3] AA30

Table 2-1. Pin Assignments (continued)

Hardware Design Guide, Revision 1 TMXL33625 HypermapperLite

April 29, 2003 622/155 Mbits/s SONET/SDH x DS3/E3

Agere Systems Inc. 13

Signal Name Pin

NSMIRXSYNC_C[3] AK14

RXDATAEN_A[3] T1

RXDATAEN_B[3] A19

RXDATAEN_D[3] W34

RXDATAEN_C[3] AP16

NSMITXDATA_A[1] T2

NSMITXDATA_B[1] B19

NSMITXDATA_D[1] W33

NSMITXDATA_C[1] AN16

NSMITXCLK_A[1] P7

NSMITXCLK_B[1] G21

NSMITXCLK_D[1] AA28

NSMITXCLK_C[1] AH14

NSMITXSYNC_A[1] R7

NSMITXSYNC_B[1] G20

NSMITXSYNC_D[1] Y28

NSMITXSYNC_C[1] AH15

TXDATAEN_A[1] R6

TXDATAEN_B[1] F20

TXDATAEN_D[1] Y29

TXDATAEN_C[1] AJ15

NSMITXDATA_A[2] U1

NSMITXDATA_B[2] A18

NSMITXDATA_D[2] V34

NSMITXDATA_C[2] AP17

NSMITXCLK_A[2] R5

NSMITXCLK_B[2] E20

NSMITXCLK_D[2] Y30

NSMITXCLK_C[2] AK15

NSMITXSYNC_A[2] R4

NSMITXSYNC_B[2] D20

NSMITXSYNC_D[2] Y31

NSMITXSYNC_C[2] AL15

TXDATAEN_A[2] V1

TXDATAEN_B[2] A17

TXDATAEN_D[2] U34

TXDATAEN_C[2] AP18

NSMITXDATA_A[3] U2

NSMITXDATA_B[3] B18

NSMITXDATA_D[3] V33

NSMITXDATA_C[3] AN17

NSMITXCLK_A[3] P8

NSMITXCLK_B[3] H21

NSMITXCLK_D[3] AA27

NSMITXCLK_C[3] AG14

NSMITXSYNC_A[3] T3

Table 2-1. Pin Assignments (continued)

Signal Name Pin

NSMITXSYNC_B[3] C19

NSMITXSYNC_D[3] W32

NSMITXSYNC_C[3] AM16

TXDATAEN_A[3] U3

TXDATAEN_B[3] C18

TXDATAEN_D[3] V32

TXDATAEN_C[3] AM17

NC N9

NC J22

NC AB26

NC AF13

NC V2

NC B17

NC U33

NC AN18

NC T4

NC D19

NC W31

NC AL16

NC V3

NC C17

NC U32

NC AM18

MODE2_PLL F15

NC N10

NC K22

NC AB25

NC AE13

NC V4

NC D17

NC U31

NC AL18

NC U4

NC D18

NC V31

NC AL17

CG_PLLCLKOUT_A P9

CG_PLLCLKOUT_B J21

CG_PLLCLKOUT_D AA26

CG_PLLCLKOUT_C AF14

MODE0_PLL F14

VDD33A_SFPLL_A T7

VDD33A_SFPLL_B G19

VDD33A_SFPLL_D W28

VDD33A_SFPLL_C AH16

CLKIN_PLL G16

Table 2-1. Pin Assignments (continued)

TMXL33625 HypermapperLite Hardware Design Guide, Revision 1

622/155 Mbits/s SONET/SDH x DS3/E3 April 29, 2003

1414 Agere Systems Inc.

Signal Name Pin

VSSA_SFPLL_A U5

VSSA_SFPLL_B E18

VSSA_SFPLL_D V30

VSSA_SFPLL_C AK17

MODE1_PLL AD13

NC R8

NC H20

NC Y27

NC AG15

NC T6

NC F19

NC W29

NC AJ16

NC V5

NC E17

NC U30

NC AK18

NC T8

NC H19

NC W27

NC AG16

NC U6

NC F18

NC V29

NC AJ17

NC V6

NC F17

NC U29

NC AJ18

NC R9

NC J20

NC Y26

NC AF15

NC U7

NC G18

NC V28

NC AH17

NC P10

NC K21

NC AA25

NC AE14

NC N11

NC L21

NC AA24

NC AD14

NC R10

Table 2-1. Pin Assignments (continued)

Signal Name Pin

NC K20

NC Y25

NC AE15

NC AF20

NC AG19

NC AF19

NC AC13

NC AB13

NC P11

NC L20

NC Y24

NC AC14

NC T10

NC K19

NC W25

NC AE16

NC U10

NC K18

NC V25

NC AE17

NC R11

NC L19

NC AA23

NC AD15

NC T11

NC M21

NC W24

NC AD16

NC N12

NC M20

NC AA22

NC AA13

NC P12

NC N21

NC Y23

NC AB14

NC R12

NC P22

NC Y22

NC AC15

NC T12

NC M19

NC W23

NC Y14

NC P13

NC N20

Table 2-1. Pin Assignments (continued)

Hardware Design Guide, Revision 1 TMXL33625 HypermapperLite

April 29, 2003 622/155 Mbits/s SONET/SDH x DS3/E3

Agere Systems Inc. 15

Signal Name Pin

NC Y21

NC AC16

NC R13

NC P21

NC AA19

NC AB15

NC U12

NC M18

NC V23

NC AC17

NC P14

NC R21

NC Y20

NC AA14

NC R14

NC P20

NC W22

NC AB16

NC T13

NC N19

NC W21

NC AA15

NC T14

NC P19

NC W20

NC AA16

NC R15

NC R20

NC Y19

NC Y15

NC T15

NC R19

NC W19

NC Y16

LOPOHCLKIN_A T16

LOPOHCLKIN_B T19

LOPOHCLKIN_D AA20

LOPOHCLKIN_C W16

LOPOHDATAIN_A R16

LOPOHDATAIN_B T20

LOPOHDATAIN_D AA21

LOPOHDATAIN_C W15

LOPOHVALIDIN_A P16

LOPOHVALIDIN_B T21

LOPOHVALIDIN_D AB19

LOPOHVALIDIN_C W14

Table 2-1. Pin Assignments (continued)

Signal Name Pin

LOPOHCLKOUT_A N16

LOPOHCLKOUT_B T22

LOPOHCLKOUT_D AC19

LOPOHCLKOUT_C W13

LOPOHDATAOUT_A M16

LOPOHDATAOUT_B T23

LOPOHDATAOUT_D AB20

LOPOHDATAOUT_C W12

LOPOHVALIDOUT_A N15

LOPOHVALIDOUT_B R22

LOPOHVALIDOUT_D AB21

LOPOHVALIDOUT_C Y13

VDD15A_DS3PLL_A M15

VDD15A_DS3PLL_B R23

VDD15A_DS3PLL_D AC20

VDD15A_DS3PLL_C Y12

DS3XCLK P23

VSSA_DS3PLL_A L15

VSSA_DS3PLL_B R24

VSSA_DS3PLL_D AD20

VSSA_DS3PLL_C Y11

VDD15A_E3PLL_A K15

VDD15A_E3PLL_B R25

VDD15A_E3PLL_D AE20

VDD15A_E3PLL_C Y10

E3XCLK P24

VSSA_E3PLL_A K16

VSSA_E3PLL_B T25

VSSA_E3PLL_D AE19

VSSA_E3PLL_C W10

VDD15 A15

VDD15 A16

VDD15 AA9

VDD15 AA18

VDD15 AB7

VDD15 AB12

VDD15 AB17

VDD15 AB27

VDD15 AC7

VDD15 AC12

VDD15 AC18

VDD15 AC26

VDD15 AD30

VDD15 AF18

VDD15 AG4

VDD15 AG29

Table 2-1. Pin Assignments (continued)

TMXL33625 HypermapperLite Hardware Design Guide, Revision 1

622/155 Mbits/s SONET/SDH x DS3/E3 April 29, 2003

1616 Agere Systems Inc.

Signal Name Pin

VDD15 AH22

VDD15 AH23

VDD15 AJ5

VDD15 AJ8

VDD15 AJ19

VDD15 AJ30

VDD15 AK2

VDD15 AK6

VDD15 AK11

VDD15 AK16

VDD15 AK29

VDD15 AL4

VDD15 AL14

VDD15 AM19

VDD15 AN19

VDD15 AN20

VDD15 AN30

VDD15 AP19

VDD15 AP20

VDD15 B5

VDD15 B12

VDD15 B15

VDD15 B16

VDD15 C16

VDD15 D8

VDD15 D21

VDD15 E6

VDD15 E19

VDD15 E24

VDD15 E29

VDD15 F5

VDD15 F16

VDD15 F27

VDD15 F30

VDD15 G12

VDD15 G13

VDD15 G15

VDD15 H6

VDD15 H16

VDD15 H31

VDD15 J16

VDD15 J17

VDD15 L5

VDD15 M14

VDD15 M17

VDD15 M28

Table 2-1. Pin Assignments (continued)

Signal Name Pin

VDD15 N18

VDD15 N28

VDD15 P4

VDD15 P17

VDD15 R17

VDD15 R33

VDD15 R34

VDD15 T5

VDD15 T17

VDD15 T29

VDD15 T32

VDD15 T33

VDD15 T34

VDD15 U13

VDD15 U19

VDD15 U20

VDD15 U21

VDD15 U23

VDD15 U26

VDD15 V9

VDD15 V12

VDD15 V14

VDD15 V15

VDD15 V16

VDD15 V22

VDD15 W1

VDD15 W2

VDD15 W3

VDD15 W6

VDD15 W18

VDD15 W30

VDD15 Y1

VDD15 Y2

VDD15 Y7

VDD15 Y9

VDD15 Y18

VDD33 AA5

VDD33 AA10

VDD33 AA12

VDD33 AB5

VDD33 AB18

VDD33 AB31

VDD33 AC5

VDD33 AC6

VDD33 AD17

VDD33 AD18

Table 2-1. Pin Assignments (continued)

Hardware Design Guide, Revision 1 TMXL33625 HypermapperLite

April 29, 2003 622/155 Mbits/s SONET/SDH x DS3/E3

Agere Systems Inc. 17

Signal Name Pin

VDD33 AE18

VDD33 AE26

VDD33 AF2

VDD33 AF4

VDD33 AF10

VDD33 AF11

VDD33 AF17

VDD33 AF26

VDD33 AG6

VDD33 AG17

VDD33 AH18

VDD33 AH30

VDD33 AJ23

VDD33 AJ27

VDD33 AK5

VDD33 AK7

VDD33 AK19

VDD33 AK22

VDD33 AK23

VDD33 AL13

VDD33 AL19

VDD33 AL21

VDD33 AL27

VDD33 AL31

VDD33 B9

VDD33 D4

VDD33 D9

VDD33 D14

VDD33 D16

VDD33 D22

VDD33 E5

VDD33 E12

VDD33 E13

VDD33 E16

VDD33 E28

VDD33 E30

VDD33 F8

VDD33 F12

VDD33 G5

VDD33 G17

VDD33 H18

VDD33 H29

VDD33 J18

VDD33 J25

VDD33 J26

VDD33 J31

Table 2-1. Pin Assignments (continued)

Signal Name Pin

VDD33 K9

VDD33 K14

VDD33 K17

VDD33 L9

VDD33 L17

VDD33 L18

VDD33 M29

VDD33 M30

VDD33 N4

VDD33 N17

VDD33 N30

VDD33 P31

VDD33 R18

VDD33 T30

VDD33 T31

VDD33 U8

VDD33 U9

VDD33 U11

VDD33 U15

VDD33 U17

VDD33 U18

VDD33 U22

VDD33 U24

VDD33 U25

VDD33 U28

VDD33 V7

VDD33 V10

VDD33 V11

VDD33 V13

VDD33 V17

VDD33 V18

VDD33 V20

VDD33 V24

VDD33 V26

VDD33 V27

VDD33 W4

VDD33 W5

VDD33 Y17

VSS A29

VSS A32

VSS AA2

VSS AA3

VSS AA4

VSS AA17

VSS AB2

VSS AB3

Table 2-1. Pin Assignments (continued)

TMXL33625 HypermapperLite Hardware Design Guide, Revision 1

622/155 Mbits/s SONET/SDH x DS3/E3 April 29, 2003

1818 Agere Systems Inc.

Signal Name Pin

VSS AB4

VSS AC3

VSS AC4

VSS AC9

VSS AC10

VSS AC11

VSS AC23

VSS AC24

VSS AC25

VSS AD4

VSS AD9

VSS AD10

VSS AD11

VSS AD12

VSS AD19

VSS AD23

VSS AD24

VSS AD25

VSS AD26

VSS AE9

VSS AE10

VSS AE11

VSS AE12

VSS AE23

VSS AE24

VSS AE25

VSS AF9

VSS AF12

VSS AF16

VSS AF23

VSS AF24

VSS AF25

VSS AG13

VSS AG18

VSS AH9

VSS AJ4

VSS AJ7

VSS AJ33

VSS AJ34

VSS AK20

VSS AK21

VSS AL12

VSS AL22

VSS AL23

VSS AL24

VSS AL29

Table 2-1. Pin Assignments (continued)

Signal Name Pin

VSS AM20

VSS AM21

VSS AM22

VSS AM23

VSS AM33

VSS AM34

VSS AN3

VSS AN6

VSS AN21

VSS AN22

VSS AP3

VSS AP6

VSS B13

VSS B14

VSS B29

VSS B32

VSS C12

VSS C13

VSS C14

VSS C15

VSS D1

VSS D2

VSS D6

VSS D11

VSS D12

VSS D13

VSS D23

VSS E14

VSS E15

VSS F1

VSS F2

VSS F31

VSS G6

VSS G26

VSS H17

VSS H22

VSS J7

VSS J9

VSS J10

VSS J11

VSS J12

VSS J19

VSS J23

VSS J24

VSS K10

VSS K11

Table 2-1. Pin Assignments (continued)

Hardware Design Guide, Revision 1 TMXL33625 HypermapperLite

April 29, 2003 622/155 Mbits/s SONET/SDH x DS3/E3

Agere Systems Inc. 19

Signal Name Pin

VSS K12

VSS K23

VSS K24

VSS K25

VSS K26

VSS L10

VSS L11

VSS L12

VSS L16

VSS L23

VSS L24

VSS L25

VSS L26

VSS L31

VSS M4

VSS M9

VSS M10

VSS M11

VSS M12

VSS M23

VSS M24

VSS M25

VSS M26

VSS M31

Table 2-1. Pin Assignments (continued)

Signal Name Pin

VSS M32

VSS N8

VSS N27

VSS N31

VSS N32

VSS N33

VSS P18

VSS P30

VSS P32

VSS P33

VSS R30

VSS R32

VSS T9

VSS T18

VSS T24

VSS U14

VSS U16

VSS U27

VSS V8

VSS V19

VSS V21

VSS W11

VSS W17

VSS W26

VSS Y3

VSS Y5

Table 2-1. Pin Assignments (continued)

TMXL33625 HypermapperLite

622/155 Mbits/s SONET/SDH x DS3/E3

Hardware Design Guide, Revision 1

April 29, 2003

20 Agere Systems Inc.

2.3 Pin Matrix

Table 2-2. Pin Matrix

123456789

A — DS3DATAOUTCLK_A[5] DS3NEGDATAOUT_A[5] DS3POSDATAOUT_A[4] DS3DATAOUTCLK_A[3] DS3RXCLKOUT_A[2] DS3DATAOUTCLK_A[1] DS3DATAINCLK_A[6] DS3NEGDATAIN_A[6]

B THSCO_AN THSCO_AP DS3POSDATAOUT_A[6] DS3DATAOUTCLK_A[4] VDD15 DS3NEGDATAOUT_A[3] DS3NEGDATAOUT_A[2] DS3NEGDATAOUT_A[1] VDD33

C THSD_AN THSD_AP RHSD_AN DS3NEGDATAOUT_A[6] DS3POSDATAOUT_A[5] DS3NEGDATAOUT_A[4] DS3POSDATAOUT_A[3] DS3RXCLKOUT_A[1] DS3DATAINCLK_A[5]

D VSS VSS RHSD_AP VDD33 DS3DATAOUTCLK_A[6] VSS DS3RXCLKOUT_A[4] VDD15 VDD33

E THSC_AN THSC_AP RHSC_AN RHSC_AP VDD33 VDD15 DS3RXCLKOUT_A[6] DS3RXCLKOUT_A[3] DS3DATAOUTCLK_A[2]

F VSS VSS RPSD_AP REF10_A VDD15 CTAPRH_A CTAPTH_A VDD33 RESHI_A

G TPSC_AN TPSC_AP RPSD_AN RPSC_AN VDD33 VSS CTAPRP_A RESLO_A REF14_A

H TPSD_AN TPSD_AP TLSDATA_AP[1] RPSC_AP VDD15A_CDR2_A VDD15 TLSDATA_AP[3] TLSDATA_AN[3] CTAPTL_A

J RLSDATA_AP[1] TLSDATA_AP[2] TLSDATA_AN[1] VSSA_CDR2_A RTOACDATA_A TTOACCLK_A VSS RPOACDATA_A VSS

K RLSDATA_AN[1] TLSDATA_AN[2] VSSA_CDR1_A RTOACCLK_A THSSYNC_A VSSA_X4PLL_A VDD15A_X4PLL_A RTOACSYNC_A VDD33

L RLSDATA_AP[2] RLSDATA_AN[3] VDD15A_CDR1_A TLSCLK_A VDD15 TTOACSYNC_A TTOACDATA_A LOSEXT_A VDD33

M RLSDATA_AN[2] RLSDATA_AP[3] TPOACSYNC_A VSS RPOACSYNC_A RPOACCLK_A NSMIRXCLK_A[1] NSMIRXCLK_A[3] VSS

N RSTN_A RHSFSYNCN_A IDDQ_A VDD33 TPOACCLK_A NSMIRXCLK_A[2] TPOACDATA_A VSS NC

P NSMIRXDATA_A[1] NSMIRXSYNC_A[1] RXDATAEN_A[1] VDD15 NSMIRXSYNC_A[3] NSMIRXDATA_A[2] NSMITXCLK_A[1] NSMITXCLK_A[3] CG_PLLCLKOUT_A

R NSMIRXSYNC_A[2] RXDATAEN_A[2] NSMIRXDATA_A[3] NSMITXSYNC_A[2] NSMITXCLK_A[2] TXDATAEN_A[1] NSMITXSYNC_A[1] NC NC

T RXDATAEN_A[3] NSMITXDATA_A[1] NSMITXSYNC_A[3] NC VDD15 NC VDD33A_SFPLL_A NC VSS

U NSMITXDATA_A[2] NSMITXDATA_A[3] TXDATAEN_A[3] NC VSSA_SFPLL_A NC NC VDD33 VDD33

VTXDATAEN_A[2]NCNCNCNCNCVDD33VSSVDD15

W VDD15 VDD15 VDD15 VDD33 VDD33 VDD15 SCK2_1 SCK1_1 E1XCLK_1

Y VDD15 VDD15 VSS CSN_C VSS TMS_1 VDD15 DATA[0] VDD15

AA DS3POSDATAIN_C[1] VSS VSS VSS VDD33 DATA[3] DATA[8] DATA[5] VDD15

AB DS3POSDATAIN_C[2] VSS VSS VSS VDD33 DATA[7] VDD15 DATA[12] DATA[13]

AC DS3NEGDATAIN_C[2] APS_INTN_C VSS VSS VDD33 VDD33 VDD15 DS3DATAINCLK_C[2] VSS

AD DS3NEGDATAIN_C[4] DS3POSDATAIN_C[3] DS3DATAINCLK_C[1] VSS DS3NEGDATAIN_C[1] DS3DATAINCLK_C[3] DS3POSDATAIN_C[4] DS3POSDATAOUT_C[2] VSS

AE DS3NEGDATAIN_C[5] DS3DATAINCLK_C[4] DS3NEGDATAIN_C[3] DS3POSDATAIN_C[5] DS3POSDATAIN_C[6] DS3POSDATAOUT_C[1] DS3RXCLKOUT_C[5] RLSCLK_C VSS

AF DS3NEGDATAIN_C[6] VDD33 DS3DATAINCLK_C[5] VDD33 DS3DATAOUTCLK_C[2] RESHI_C REF14_C CTAPTL_C VSS

AG DS3DATAINCLK_C[6] DS3NEGDATAOUT_C[1] DS3RXCLKOUT_C[1] VDD15 DS3RXCLKOUT_C[3] VDD33 RESLO_C TLSDATA_CN[3] RPOACDATA_C

AH DS3DATAOUTCLK_C[1] DS3NEGDATAOUT_C[2] DS3POSDATAOUT_C[3] DS3RXCLKOUT_C[4] DS3RXCLKOUT_C[6] CTAPTH_C CTAPRP_C TLSDATA_CP[3] VSS

AJ DS3RXCLKOUT_C[2] DS3NEGDATAOUT_C[3] DS3NEGDATAOUT_C[4] VSS VDD15 CTAPRH_C VSS VDD15 TTOACCLK_C

AK DS3DATAOUTCLK_C[3] VDD15 DS3POSDATAOUT_C[5] DS3DATAOUTCLK_C[6] VDD33 VDD15 VDD33 VDD15A_CDR2_C RTOACDATA_C

AL DS3POSDATAOUT_C[4] DS3DATAOUTCLK_C[4] DS3NEGDATAOUT_C[6] VDD15 RHSC_CP REF10_C RPSC_CN RPSC_CP VSSA_CDR2_C

AM DS3NEGDATAOUT_C[5] DS3POSDATAOUT_C[6] RHSD_CN RHSD_CP RHSC_CN RPSD_CP RPSD_CN TLSDATA_CP[1] TLSDATA_CN[1]

AN DS3DATAOUTCLK_C[5] THSCO_CP VSS THSD_CP THSC_CP VSS TPSC_CP TPSD_CP TLSDATA_CP[2]

AP — THSCO_CN VSS THSD_CN THSC_CN VSS TPSC_CN TPSD_CN RLSDATA_CP[1]

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Table 2-2. Pin Matrix (continued)

10 11 12 13 14 15 16 17 18

A DS3NEGDATAIN_A[5] DS3NEGDATAIN_A[4] DS3NEGDATAIN_A[2] DS3POSDATAIN_A[2] DS3POSDATAIN_A[1] VDD15 VDD15 TXDATAEN_B[2] NSMITXDATA_B[2]

B DS3DATAINCLK_A[4] DS3POSDATAIN_A[3] VDD15 VSS VSS VDD15 VDD15 NC NSMITXDATA_B[3]

C DS3NEGDATAIN_A[3] DS3DATAINCLK_A[1] VSS VSS VSS VSS VDD15 NC TXDATAEN_B[3]

D DS3POSDATAIN_A[5] VSS VSS VSS VDD33 CSN_A VDD33 NC NC

E DS3POSDATAIN_A[6] DS3NEGDATAIN_A[1] VDD33 VDD33 VSS VSS VDD33 NC VSSA_SFPLL_B

F DS3POSDATAOUT_A[1] DS3DATAINCLK_A[3] VDD33 LP_INTN_1 MODE0_PLL MODE2_PLL VDD15 NC NC

G DS3RXCLKOUT_A[5] DS3POSDATAIN_A[4] VDD15 VDD15 APS_INTN_A VDD15 CLKIN_PLL VDD33 NC

H RLSCLK_A DS3POSDATAOUT_A[2] DS3DATAINCLK_A[2] BYPASS_1 TSTMODE ECSEL_1 VDD15 VSS VDD33

J VSS VSS VSS TSTPHASE ETOGGLE_1 TSTSFTLD VDD15 VDD15 VDD33

K VSS VSS VSS EXDNUP_1 VDD33 VDD15A_E3PLL_A VSSA_E3PLL_A VDD33 NC

L VSS VSS VSS SCANMODE_1 TRST VSSA_DS3PLL_A VSS VDD33 VDD33

M VSS VSS VSS IC3STATEN VDD15 VDD15A_DS3PLL_A LOPOHDATAOUT_A VDD15 NC

N NC NC NC SCAN_EN PMRST LOPOHVALIDOUT_A LOPOHCLKOUT_A VDD33 VDD15

PNCNCNCNCNCTDILOPOHVALIDIN_AVDD15VSS

RNCNCNCNCNCNCLOPOHDATAIN_AVDD15VDD33

TNCNCNCNCNCNCLOPOHCLKIN_AVDD15VSS

U NC VDD33 NC VDD15 VSS VDD33 VSS VDD33 VDD33

V VDD33 VDD33 VDD15 VDD33 VDD15 VDD15 VDD15 VDD33 VDD33

W VSSA_E3PLL_C VSS LOPOHDATAOUT_C LOPOHCLKOUT_C LOPOHVALIDIN_C LOPOHDATAIN_C LOPOHCLKIN_C VSS VDD15

Y VDD15A_E3PLL_C VSSA_DS3PLL_C VDD15A_DS3PLL_C LOPOHVALIDOUT_C NC NC NC VDD33 VDD15

AA VDD33 DS1XCLK_1 VDD33 NC NC NC NC VSS VDD15

AB HP_INTN_1 LP_INTN_2 VDD15 NC NC NC NC VDD15 VDD33

ACVSSVSSVDD15NCNCNCNCNCVDD15

AD VSS VSS VSS MODE1_PLL NC NC NC VDD33 VDD33

AEVSSVSSVSSNCNCNCNCNCVDD33

AF VDD33 VDD33 VSS NC CG_PLLCLKOUT_C NC VSS VDD33 VDD15

AG RTOACSYNC_C LOSEXT_C NSMIRXCLK_C[3] VSS NSMITXCLK_C[3] NC NC VDD33 VSS

AH VDD15A_X4PLL_C TTOACDATA_C NSMIRXCLK_C[1] TPOACDATA_C NSMITXCLK_C[1] NSMITXSYNC_C[1] VDD33A_SFPLL_C NC VDD33

AJ VSSA_X4PLL_C TTOACSYNC_C RPOACCLK_C NSMIRXCLK_C[2] NSMIRXDATA_C[2] TXDATAEN_C[1] NC NC NC

AK THSSYNC_C VDD15 RPOACSYNC_C TPOACCLK_C NSMIRXSYNC_C[3] NSMITXCLK_C[2] VDD15 VSSA_SFPLL_C NC

AL RTOACCLK_C TLSCLK_C VSS VDD33 VDD15 NSMITXSYNC_C[2] NC NC NC

AM VSSA_CDR1_C VDD15A_CDR1_C TPOACSYNC_C IDDQ_C RXDATAEN_C[1] NSMIRXDATA_C[3] NSMITXSYNC_C[3] TXDATAEN_C[3] NC

AN TLSDATA_CN[2] RLSDATA_CN[3] RLSDATA_CP[3] RHSFSYNCN_C NSMIRXSYNC_C[1] RXDATAEN_C[2] NSMITXDATA_C[1] NSMITXDATA_C[3] NC

AP RLSDATA_CN[1] RLSDATA_CP[2] RLSDATA_CN[2] RSTN_C NSMIRXDATA_C[1] NSMIRXSYNC_C[2] RXDATAEN_C[3] NSMITXDATA_C[2] TXDATAEN_C(2)

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Table 2-2. Pin Matrix (continued)

19 20 21 22 23 24 25 26 27

A RXDATAEN_B[3] NSMIRXSYNC_B[2] NSMIRXDATA_B[1] RSTN_B RLSDATA_BN[2] RLSDATA_BP[2] RLSDATA_BN[1] RLSDATA_BP[1] TPSD_BN

B NSMITXDATA_B[1] RXDATAEN_B[2] NSMIRXSYNC_B[1] RHSFSYNCN_B RLSDATA_BP[3] RLSDATA_BN[3] TLSDATA_BN[2] TLSDATA_BP[2] TPSD_BP

C NSMITXSYNC_B[3] NSMIRXDATA_B[3] RXDATAEN_B[1] IDDQ_B TPOACSYNC_B VDD15A_CDR1_B VSSA_CDR1_B TLSDATA_BN[1] TLSDATA_BP[1]

D NC NSMITXSYNC_B[2] VDD15 VDD33 VSS TLSCLK_B RTOACCLK_B VSSA_CDR2_B RPSC_BP

E VDD15 NSMITXCLK_B[2] NSMIRXSYNC_B[3] TPOACCLK_B RPOACSYNC_B VDD15 THSSYNC_B RTOACDATA_B VDD15A_CDR2_B

F NC TXDATAEN_B[1] NSMIRXDATA_B[2] NSMIRXCLK_B[2] RPOACCLK_B TTOACSYNC_B VSSA_X4PLL_B TTOACCLK_B VDD15

G VDD33A_SFPLL_B NSMITXSYNC_B[1] NSMITXCLK_B[1] TPOACDATA_B NSMIRXCLK_B[1] TTOACDATA_B VDD15A_X4PLL_B VSS TLSDATA_BP[3]

H NC NC NSMITXCLK_B[3] VSS NSMIRXCLK_B[3] LOSEXT_B RTOACSYNC_B RPOACDATA_B TLSDATA_BN[3]

J VSS NC NC NC VSS VSS VDD33 VDD33 CTAPTL_B

K NC NC NC NC VSS VSS VSS VSS RLSCLK_B

L NC NC NC DATA[2] VSS VSS VSS VSS DS3POSDATAOUT_B[2]

M NC NC NC DATA[6] VSS VSS VSS VSS DS3DATAINCLK_B[2]

N NC NC NC DATA[14] PAR[1] ADDR[17] ADDR[18] DATA[15] VSS

P NC NC NC NC DS3XCLK E3XCLK DATA[4] DATA[11] DATA[10]

R NC NC NC LOPOHVALIDOUT_B VDD15A_DS3PLL_B VSSA_DS3PLL_B VDD15A_E3PLL_B ADDR[12] ADDR[4]

T LOPOHCLKIN_B LOPOHDATAIN_B LOPOHVALIDIN_B LOPOHCLKOUT_B LOPOHDATAOUT_B VSS VSSA_E3PLL_B ADDR[8] ADDR[11]

U VDD15 VDD15 VDD15 VDD33 VDD15 VDD33 VDD33 VDD15 VSS

V VSS VDD33 VSS VDD15 NC VDD33 NC VDD33 VDD33

WNCNCNCNCNCNC NC VSS NC

YNCNCNCNCNCNC NC NC NC

AA NC LOPOHCLKIN_D LOPOHDATAIN_D NC NC NC NC CG_PLLCLKOUT_D NSMITXCLK_D[3]

AB LOPOHVALIDIN_D LOPOHDATAOUT_D LOPOHVALIDOUT_D ADDR[20] PAR[0] DTN NC NC VDD15

AC LOPOHCLKOUT_D VDD15A_DS3PLL_D TCK ADDR[14] VSS VSS VSS VDD15 NSMIRXCLK_D[3]

AD VSS VSSA_DS3PLL_D TDO ADDR[10] VSS VSS VSS VSS LOSEXT_D

AE VSSA_E3PLL_D VDD15A_E3PLL_D ADSN ADDR[7] VSS VSS VSS VDD33 RTOACSYNC_D

AF NC NC ADDR[5] DATA[9] VSS VSS VSS VDD33 RPOACDATA_D

AG NC MPMODE MPCLK ADDR[16] DS3DATAINCLK_D[2] DS3POSDATAOUT_D[2] RLSCLK_D CTAPTL_D TLSDATA_DN[3]

AH ADDR[0] ADDR[6] ADDR[2] VDD15 VDD15 DS3POSDATAIN_D[4] DS3RXCLKOUT_D[5] REF14_D RESLO_D

AJ VDD15 RWN ADDR[1] ADDR[13] VDD33 DS3DATAINCLK_D[3] DS3POSDATAOUT_D[1] RESHI_D VDD33

AK VDD33 VSS VSS VDD33 VDD33 DS3NEGDATAIN_D[1] DS3POSDATAIN_D[6] DS3DATAOUTCLK_D[2] DS3RXCLKOUT_D[3]

AL VDD33 CSN_D VDD33 VSS VSS VSS DS3POSDATAIN_D[5] SCK2_2 VDD33

AM VDD15 VSS VSS VSS VSS DS3DATAINCLK_D[1] DS3NEGDATAIN_D[3] DS3DATAINCLK_D[5] DS3RXCLKOUT_D[1]

AN VDD15 VDD15 VSS VSS BYPASS_2 DS3POSDATAIN_D[3] DS3DATAINCLK_D[4] APS_INTN_D DS3NEGDATAOUT_D[1]

AP VDD15 VDD15 DS3POSDATAIN_D[1] DS3POSDATAIN_D[2] DS3NEGDATAIN_D[2] DS3NEGDATAIN_D[4] DS3NEGDATAIN_D[5] DS3NEGDATAIN_D[6] DS3DATAINCLK_D[6]

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Table 2-2. Pin Matrix (continued)

28 29 30 31 32 33 34

A TPSC_BN VSS THSC_BN THSD_BN VSS THSCO_BN —

B TPSC_BP VSS THSC_BP THSD_BP VSS THSCO_BP DS3DATAOUTCLK_B[5]

C RPSD_BN RPSD_BP RHSC_BN RHSD_BP RHSD_BN DS3POSDATAOUT_B[6] DS3NEGDATAOUT_B[5]

D RPSC_BN REF10_B RHSC_BP EXDNUP_2 DS3NEGDATAOUT_B[6] DS3DATAOUTCLK_B[4] DS3POSDATAOUT_B[4]

E VDD33 VDD15 VDD33 DS3DATAOUTCLK_B[6] DS3POSDATAOUT_B[5] DS1XCLK_2 DS3DATAOUTCLK_B[3]

F E1XCLK_2 CTAPRH_B VDD15 VSS DS3NEGDATAOUT_B[4] DS3NEGDATAOUT_B[3] DS3RXCLKOUT_B[2]

G CTAPRP_B CTAPTH_B DS3RXCLKOUT_B[6] DS3RXCLKOUT_B[4] DS3POSDATAOUT_B[3] DS3NEGDATAOUT_B[2] DS3DATAOUTCLK_B[1]

H RESLO_B VDD33 DS3RXCLKOUT_B[3] VDD15 DS3RXCLKOUT_B[1] DS3NEGDATAOUT_B[1] DS3DATAINCLK_B[6]

J REF14_B RESHI_B DS3DATAOUTCLK_B[2] VDD33 DS3DATAINCLK_B[5] APS_INTN_B DS3NEGDATAIN_B[6]

K DS3RXCLKOUT_B[5] DS3POSDATAOUT_B[1] DS3POSDATAIN_B[6] DS3POSDATAIN_B[5] DS3NEGDATAIN_B[3] DS3DATAINCLK_B[4] DS3NEGDATAIN_B[5]

L DS3POSDATAIN_B[4] DS3DATAINCLK_B[3] DS3NEGDATAIN_B[1] VSS DS3DATAINCLK_B[1] DS3POSDATAIN_B[3] DS3NEGDATAIN_B[4]

M VDD15 VDD33 VDD33 VSS VSS HP_INTN_2 DS3NEGDATAIN_B[2]

N VDD15 ADDR[19] VDD33 VSS VSS VSS DS3POSDATAIN_B[2]

P DATA[1] ADDR[15] VSS VDD33 VSS VSS DS3POSDATAIN_B[1]

R ADDR[9] ADDR[3] VSS CSN_B VSS VDD15 VDD15

T DSN VDD15 VDD33 VDD33 VDD15 VDD15 VDD15

U VDD33 NC NC NC NC NC TXDATAEN_D[2]

V NC NC VSSA_SFPLL_D NC TXDATAEN_D[3] NSMITXDATA_D[3] NSMITXDATA_D[2]

W VDD33A_SFPLL_D NC VDD15 NC NSMITXSYNC_D[3] NSMITXDATA_D[1] RXDATAEN_D[3]

Y NSMITXSYNC_D[1] TXDATAEN_D[1] NSMITXCLK_D[2] NSMITXSYNC_D[2] NSMIRXDATA_D[3] RXDATAEN_D[2] NSMIRXSYNC_D[2]

AA NSMITXCLK_D[1] NSMIRXDATA_D[2] NSMIRXSYNC_D[3] SCK1_2 RXDATAEN_D[1] NSMIRXSYNC_D[1] NSMIRXDATA_D[1]

AB TPOACDATA_D NSMIRXCLK_D[2] TPOACCLK_D VDD33 IDDQ_D RHSFSYNCN_D RSTN_D

AC NSMIRXCLK_D[1] RPOACCLK_D RPOACSYNC_D TMS_2 TPOACSYNC_D RLSDATA_DP[3] RLSDATA_DN[2]

AD TTOACDATA_D TTOACSYNC_D VDD15 TLSCLK_D VDD15A_CDR1_D RLSDATA_DN[3] RLSDATA_DP[2]

AE VDD15A_X4PLL_D VSSA_X4PLL_D THSSYNC_D RTOACCLK_D VSSA_CDR1_D TLSDATA_DN[2] RLSDATA_DN[1]

AF ETOGGLE_2 TTOACCLK_D RTOACDATA_D VSSA_CDR2_D TLSDATA_DN[1] TLSDATA_DP[2] RLSDATA_DP[1]

AG TLSDATA_DP[3] VDD15 VDD15A_CDR2_D RPSC_DP TLSDATA_DP[1] TPSD_DP TPSD_DN

AH CTAPRP_D ECSEL_2 VDD33 RPSC_DN RPSD_DN TPSC_DP TPSC_DN

AJ CTAPTH_D CTAPRH_D VDD15 REF10_D RPSD_DP VSS VSS

AK DS3RXCLKOUT_D[6] VDD15 SCANMODE_2 RHSC_DP RHSC_DN THSC_DP THSC_DN

AL DS3RXCLKOUT_D[4] VSS DS3DATAOUTCLK_D[6] VDD33 RHSD_DP THSD_DP THSD_DN

AM DS3POSDATAOUT_D[3] DS3NEGDATAOUT_D[4] DS3POSDATAOUT_D[5] DS3NEGDATAOUT_D[6] RHSD_DN VSS VSS

AN DS3NEGDATAOUT_D[2] DS3NEGDATAOUT_D[3] VDD15 DS3DATAOUTCLK_D[4] DS3POSDATAOUT_D[6] THSCO_DP THSCO_DN

AP DS3DATAOUTCLK_D[1] DS3RXCLKOUT_D[2] DS3DATAOUTCLK_D[3] DS3POSDATAOUT_D[4] DS3NEGDATAOUT_D[5] DS3DATAOUTCLK_D[5] —

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2.4 Pin Types

Table 2-3 describes each type of input, output, and I/O pin used in the HypermapperLite.

Table 2-3. Pin Types

Type Label Description

ILVCMOS Input, LVTTL Switching Thresholds.

I pd LVCMOS Input, LVTTL Switching Thresholds with Internal 50 kΩ

ΩΩ

Ω Pull-Down Resistor.

I pd 1 LVCMOS Input, LVTTL Switching Thresholds with Internal 25 kΩ

ΩΩ

Ω Pull-Down Resistor.

I pd 2 LVCMOS Input, LVTTL Switching Thresholds with Internal 12.5 kΩ

ΩΩ

Ω Pull-Down Resistor.

I pu LVCMOS Input, LVTTL Switching Thresholds with Internal 50 kΩ

Ω Ω

Ω Pull-Up Resistor.

I pu 1 LVCMOS Input, LVTTL Switching Thresholds with Internal 25 kΩ

Ω Ω

Ω Pull-Up Resistor.

I pu 2 LVCMOS Input, LVTTL Switching Thresholds with Internal 12.5 kΩ

ΩΩ

Ω Pull-Up Resistor.

OLVCMOS Output.

O od Open-Drain Output.

LIN LVDS Inputs.

LOUT LVDS Outputs.

I/O Bidirectional Pin. LVCMOS input with LVTTL switching thresholds and LVCMOS output.

I/O pd Bidirectional Pin. LVCMOS input with LVTTL switching thresholds with internal 50 kΩ pull-down resistor

and LVCMOS output.

—Power, Ground, Analog Inputs for External Resistors, Capacitors, Voltage References, etc.

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2.5 Pin Definitions

This section describes the function of each of the device pins. All LVDS input buffers have built-in 100 Ω terminating

resistor with a center tap pin available for external capacitor connection. All unused LVDS inputs may be left unconnected.

Pin functionality is descriptive information. The actual functionality is dependent upon the device configuration via the

registers.

Table 2-4. TMUX Blocks, High-Speed Interface I/O

Symbol Pin Type Name/Description

RHSD_AP D3 LIN Receive High-Speed Data. 622/155 Mbits/s input data; also, input to internal clock

and data recovery (CDR). CDR may be bypassed in 155 Mbits/s mode. The internal

CDR must be used in 622 Mbits/s mode.

RHSD_BP C31

RHSD_CP AM4

RHSD_DP AL32

RHSD_AN C3

RHSD_BN C32

RHSD_CN AM3

RHSD_DN AM32

RHSC_AP E4 LIN Receive High-Speed Clock. 155 MHz input clock for 155 Mbits/s data if CDR is by-

passed. Not used in 622 Mbits/s mode.

RHSC_BP D30

RHSC_CP AL5

RHSC_DP AK31

RHSC_AN E3

RHSC_BN C30

RHSC_CN AM5

RHSC_DN AK32

CTAPRH_A F6 — Center Tap RH. LVDS buffer terminator center tap for RHSDP/N and RHSCP/N. An op-

tional 0.1 µF capacitor, connected between CTAP pin and ground, will improve the com-

mon-mode rejection of the LVDS input buffers.

CTAPRH_B F29

CTAPRH_C AJ6

CTAPRH_D AJ29

LOSEXT_A L8 I pu External Loss of Signal Input. Active level is programmable by register

TMUX_LOSEXT_LEVEL, defaults to active-low. This pin can be part of the high-priority

interrupt when active. Usually connected to optical transceiver to indicate loss of signal.

LOSEXT_B H24

LOSEXT_C AG11

LOSEXT_D AD27

THSD_AP C2 LOUT Transmit High-Speed Data. 622/155 Mbits/s output data. The frame location in slave

mode is determined by THSSYNC and transmit high-speed control parameter register

(TMUX_TFRAMEOFFSETA). In master mode, the frame timing is arbitrary.

THSD_BP B31

THSD_CP AN4

THSD_DP AL33

THSD_AN C1

THSD_BN A31

THSD_CN AP4

THSD_DN AL34

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THSCO_AP B2 LOUT Transmit High-Speed Clock Output. 622/155 MHz transmit output clock associated

with THSDP/N.

THSCO_BP B33

THSCO_CP AN2

THSCO_DP AN33

THSCO_AN B1

THSCO_BN A33

THSCO_CN AP2

THSCO_DN AN34

RESHI_A F9 — Resistor. A 100 Ω, 1% resistor is required between the RESHI_X and RESLO_X pins

as a reference for the LVDS input buffer termination.

RESHI_B J29

RESHI_C AF6

RESHI_D AJ26

RESLO_A G8

RESLO_B H28

RESLO_C AG7

RESLO_D AH27

REF10_A*F4 I Reference 1.0 V. External 1 V reference voltage pin. (Optional.)

REF10_B*D29

REF10_C*AL6

REF10_D*AJ31

REF14_A*G9 I Reference 1.4 V. External 1.4 V reference voltage pin. (Optional.)

REF14_B*J28

REF14_C*AF7

REF14_D*AH26

* Optional: selected by MPU/top-level register. External reference voltage can be sourced from a low-impedance resistor (less than 1 kΩ) divider circuit

decoupled with a 0.1 µF capacitor.

Table 2-4. TMUX Blocks, High-Speed Interface I/O (continued)

Symbol Pin Type Name/Description

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Table 2-5. TMUX Blocks, Protection Link I/O

Symbol Pin Type Name/Description

RPSD_AP F3 LIN Receive Protection High-Speed Data. 622/155 Mbits/s protection input data; also input

to internal protection CDR. CDR may be bypassed in 155 Mbits/s mode. The internal

CDR must be used in 622 Mbits/s mode.

RPSD_BP C29

RPSD_CP AM6

RPSD_DP AJ32

RPSD_AN G3

RPSD_BN C28

RPSD_CN AM7

RPSD_DN AH32

RPSC_AP H4 LIN Receive Protection High-Speed Clock. 155 MHz input clock for 155 Mbits/s data if pro-

tection CDR is bypassed. Not used in 622 Mbits/s mode.

RPSC_BP D27

RPSC_CP AL8

RPSC_DP AG31

RPSC_AN G4

RPSC_BN D28

RPSC_CN AL7

RPSC_DN AH31

CTAPRP_A G7 — Center Tap RP. LVDS buffer terminator center tap for RPSDP/N and RPSCP/N. An op-

tional 0.1 µF capacitor, connected between the CTAP pin and ground, will improve the

common-mode rejection of the LVDS input buffers.

CTAPRP_B G28

CTAPRP_C AH7

CTAPRP_D AH28

TPSD_AP H2 LOUT Transmit Protection High-Speed Data. 622/155 Mbits/s protection output data.

TPSD_BP B27

TPSD_CP AN8

TPSD_DP AG33

TPSD_AN H1

TPSD_BN A27

TPSD_CN AP8

TPSD_DN AG34

TPSC_AP G2 LOUT Transmit Protection High-Speed Clock. 622/155 MHz transmit output clock associated

with TPSDP/N.

TPSC_BP B28

TPSC_CP AN7

TPSC_DP AH33

TPSC_AN G1

TPSC_BN A28

TPSC_CN AP7

TPSC_DN AH34

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Table 2-6. TMUX Blocks, Clock and Sync I/O

Symbol Pin Type Name/Description

THSC_AP E2 LIN Transmit High-Speed Clock. 622/155 MHz input clock for the transmit 622/155 Mbits/s

data; also used as a reference clock for all CDRs. There are five CDR circuits per parti-

tion (A—D). The high-speed data and protection high-speed data have CDRs that oper-

ate at 155 MHz or 622 MHz. The mate inputs have three CDRs that operate at 155 MHz.

The clock on this pin is also internally routed to the DS1/E1 framers and is used as an

internal master clock.

THSC_BP B30

THSC_CP AN5

THSC_DP AK33

THSC_AN E1

THSC_BN A30

THSC_CN AP5

THSC_DN AK34

CTAPTH_A F7 — Center Tap TH. LVDS buffer terminator center tap for THSCP/N. An optional 0.1 µF ca-

pacitor, connected between the CTAP pin and ground, will improve the common-mode re-

jection of the LVDS input buffers.

CTAPTH_B G29

CTAPTH_C AH6

CTAPTH_D AJ28

RHSFSYNCN_A N2 O Receive High-Speed Frame Sync. This output indicates the start of the frame in the

high-speed data input. Only present when a valid frame signal is detected on the

RHSDP/N inputs. It is an active-low pulse width almost equal to one E1 clock period or

approximately 500 ns.

RHSFSYNCN_B B22

RHSFSYNCN_C AN13

RHSFSYNCN_D AB33

RLSCLK_A H10 O Receive Low-Speed Clock. 19.44 MHz receive output clock divided down from

RHSCP/N. May be used as a system timing reference.

RLSCLK_B K27

RLSCLK_C AE8

RLSCLK_D AG25

TLSCLK_A L4 O Transmit Low-Speed Clock. 19.44 MHz transmit output clock divided down from

THSCP/N.

TLSCLK_B D24

TLSCLK_C AL11

TLSCLK_D AD31

THSSYNC_A K5 I/O pd Transmit High-Speed Frame Sync. 2 kHz/8 kHz composite frame sync signal that iden-

tifies the locations of the J0, J1-1, J1-2, J1-3 . . . J1-12, and V1-1 bytes. This signal is used to

align transmit frames before multiplexing.

Note: J0, J1-1, J1-2, and J1-3 . . . J1-12 occur every 125 µs. V1-1 occurs every 500 µs.

If the register MPU_MASTER_SLAVE = 1, THSSYNC is an output; otherwise,

THSSYNC is an input.

The positive 8 kHz and 2 kHz pulses are synchronized to TLSCLK. The rising edge is

referenced for frame location. For master/slave configuration, the THSSYNC of Hyper-

mapperLite partitions (A, B, C, and D; up to four) must be connected together. The mas-

ter can be one of the HypermapperLite partitions (A, B, C, or D), and it sources the frame

sync pulse to other HypermapperLite partitions. All HypermapperLite partitions (A, B, C,

and D) can also be configured as slaves and receive frame sync from the external sys-

tem frame sync.

THSSYNC_B E25

THSSYNC_C AK10

THSSYNC_D AE30

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Table 2-7. STS Cross Connect (STSXC) Blocks, STS-3/STM-1 Mate Interconnect

Symbol Pin Type Name/Description

RLSDATA_AP[3:1] M2, L1, J1 LOUT Receive Low-Speed Data. These pins are only used in 622 Mbits/s

applications. They are used only on the master partition (A, B, C, or D).

Connect these pins to the high-speed data inputs (RHSDP/N) of the

slave partitions.

This 155 Mbits/s signal uses a SONET structure. The overheads sup-

ported are the A1/A2 and B2 bytes and line RDI. The data is scrambled.

Data from the RHSD is routed via the STSXC.

RLSDATA_BP[3:1] B23, A24, A26

RLSDATA_CP[3:1] AN12, AP11, AP9

RLSDATA_DP[3:1] AC33, AD34, AF34

RLSDATA_AN[3:1] L2, M1, K1

RLSDATA_BN[3:1] B24, A23, A25

RLSDATA_CN[3:1] AN11, AP12, AP10

RLSDATA_DN[3:1] AD33, AC34, AE34

TLSDATA_AP[3:1] H7, J2, H3 LIN Transmit Low-Speed Data. These pins are only used in 622 Mbits/s ap-

plications. They are used only on the master partition (A, B, C, or D). Con-

nect these pins to the high-speed data outputs (THSDP/N) of the slave

partitions. This 155 Mbits/s input receives data from the slave high-speed

outputs.

These inputs have built-in clock and data recovery (CDR). The frame lo-

cation expects a fixed relationship to the high-speed transmit frame sync

(THSSYNC).

TLSDATA_BP[3:1] G27, B26, C27

TLSDATA_CP[3:1] AH8, AN9, AM8

TLSDATA_DP[3:1] AG28, AF33, AG32

TLSDATA_AN[3:1] H8, K2, J3

TLSDATA_BN[3:1] H27, B25, C26

TLSDATA_CN[3:1] AG8, AN10, AM9

TLSDATA_DN[3:1] AG27, AE33, AF32

CTAPTL_A H9 — Center Tap TL. LVDS buffer terminator center tap for TLSDATAP/N. An

optional 0.1 µF capacitor, connected between the CTAP pin and ground,

will improve the common-mode rejection of the LVDS input buffers.

CTAPTL_B J27

CTAPTL_C AF8

CTAPTL_D AG26

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Table 2-8. Multirate Cross Connect (MRXC) Blocks, TOAC Input and Output Channels

Symbol Pin Type Name/Description

RTOACCLK_A K4 O Receive Transport Overhead Access Channel Clock. The frequency of this clock is

determined by the TOAC provisioning registers.

RTOACCLK_B D25

RTOACCLK_C AL10

RTOACCLK_D AE31

RTOACDATA_A J5 O Receive Transport Overhead Access Channel Data. 622/155 Mbits/s transport

overhead bytes are output on this pin. The content is determined by the TOAC

provisioning registers.

RTOACDATA_B E26

RTOACDATA_C AK9

RTOACDATA_D AF30

RTOACSYNC_A K8 O Receive Transport Overhead Access Channel Sync. Active-high 8 kHz frame sync. It

is active during the clock period of the first bit of each frame.

RTOACSYNC_B H25

RTOACSYNC_C AG10

RTOACSYNC_D AE27

TTOACCLK_A J6 O Transmit Transport Overhead Access Channel Clock. The frequency of this clock is

determined by the TOAC provisioning registers.

TTOACCLK_B F26

TTOACCLK_C AJ9

TTOACCLK_D AF29

TTOACDATA_A L7 I pd Transmit Transport Overhead Access Channel Data. Input for the transport overhead

bytes.

TTOACDATA_B G24

TTOACDATA_C AH11

TTOACDATA_D AD28

TTOACSYNC_A L6 O Transmit Transport Overhead Access Channel Sync. Active-high 8 kHz frame sync.

It is active during the clock period of the first bit of each frame.

TTOACSYNC_B F24

TTOACSYNC_C AJ11

TTOACSYNC_D AD29

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Table 2-9. Multirate Cross Connect (MRXC) Blocks, POAC Input and Output Channels

Symbol Pin Type Name/Description

RPOACCLK_A M6 O Receive Path Overhead Access Channel Clock. Output for the path overhead bytes.

This is a 3-state output pin controlled by register provisioning.

RPOACCLK_B F23

RPOACCLK_C AJ12

RPOACCLK_D AC29

RPOACDATA_A J8 O Receive Path Overhead Access Channel Data. Output for the path overhead bytes.

This pin can be 3-stated.

RPOACDATA_B H26

RPOACDATA_C AG9

RPOACDATA_D AF27

RPOACSYNC_A M5 O Receive Path Overhead Access Channel Sync. Output for POAC channel. Active-

high during the first bit of each frame. This pin can be individually 3-stated.

RPOACSYNC_B E23

RPOACSYNC_C AK12

RPOACSYNC_D AC30

TPOACCLK_A N5 O Transmit Path Overhead Access Channel Clock. Serial access channel clock output

for the path overhead bytes. This pin can be individually 3-stated.

TPOACCLK_B E22

TPOACCLK_C AK13

TPOACCLK_D AB30

TPOACDATA_A N7 I pd Transmit Path Overhead Access Channel Data. Serial access channel data input for

the path overhead bytes.

TPOACDATA_B G22

TPOACDATA_C AH13

TPOACDATA_D AB28

TPOACSYNC_A M3 O Transmit Path Overhead Access Channel Sync. Sync output for POAC channel. Ac-

tive-high during the first bit of each frame. This pin can be individually 3-stated.

TPOACSYNC_B C23

TPOACSYNC_C AM12

TPOACSYNC_D AC32

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Table 2-10. DS3/E3/STS-1 Out

Symbol Pin Type Name/Description

DS3POSDATAOUT_A[6:1] B3, C5, A4, C7, H11,

F10

ODS3/E3/STS-1 Positive Data Output. Either contains the

positive-rail of the B3ZS/HDB3 encoded output data, or

single-rail NRZ data.

DS3POSDATAOUT_B[6:1] C33, E32, D34, G32,

L27, K29

DS3POSDATAOUT_C[6:1] AM2, AK3, AL1, AH3,

AD8, AE6

DS3POSDATAOUT_D[6:1] AN32, AM30, AP31,

AM28, AG24, AJ25

DS3NEGDATAOUT_A[6:1] C4, A3, C6, B6, B7, B8 O DS3/E3/STS-1 Negative Data Output. Negative-rail B3ZS/

HDB3 encoded output data. Not used in single-rail mode

(held low in this case).

DS3NEGDATAOUT_B[6:1] D32, C34, F32, F33,

G33, H33

DS3NEGDATAOUT_C[6:1] AL3, AM1, AJ3, AJ2,

AH2, AG2

DS3NEGDATAOUT_D[6:1] AM31, AP32, AM29,

AN29, AN28, AN27

DS3DATAOUTCLK_A[6:1] D5, A2, B4, A5, E9, A7 I pd DS3/E3/STS-1 Data Output Clock. 44.736 MHz,

34.368 MHz, or 51.84 MHz clock input.

This clock is required for M13, E13, or STS1LT applications

and is typically connected to a crystal oscillator or clocking

chip.

For DS3/E3 to SONET/SDH mapping applications, the DS3/

E3 DJA is used, and this clock is therefore not required.

DS3XCLK/E3XCLK is needed for DS3/E3 DJA in this case.

For STS-1 to SONET mapping applications, the TMUX can

be used to supply the STS-1 rate DATAOUT clock and there-

fore this clock is not needed.

DS3DATAOUTCLK_B[6:1] E31, B34, D33, E34,

J30, G34

DS3DATAOUTCLK_C[6:1] AK4, AN1, AL2, AK1,

AF5, AH1

DS3DATAOUTCLK_D[6:1] AL30, AP33, AN31,

AP30, AK26, AP28

DS3RXCLKOUT_A[6:1] E7, G10, D7, E8, A6,

ODS3/E3/STS-1 Receive Clock Output. 44.736 MHz

DS3, 34.368 MHz E3, and 51.84 MHz STS-1 clock out to ex-

ternal circuit.

DS3RXCLKOUT_B[6:1] G30, K28, G31, H30,

F34, H32

DS3RXCLKOUT_C[6:1] AH5, AE7, AH4, AG5,

AJ1, AG3

DS3RXCLKOUT_D[6:1] AK28, AH25, AL28,

AK27, AP29, AM27

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Table 2-11. DS3/E3/STS-1 In

Symbol Pin Type Name/Description

DS3POSDATAIN_A[6:1] E10, D10, G11, B11, A13, A14 I pd DS3/E3/STS-1 Positive Data Input. Either contains the

positive rail of the B3ZS/HDB3 encoded input data or sin-

gle-rail NRZ data.

DS3POSDATAIN_B[6:1] K30, K31, L28, L33, N34, P34

DS3POSDATAIN_C[6:1] AE5, AE4, AD7, AD2, AB1,

AA1

DS3POSDATAIN_D[6:1] AK25, AL25, AH24, AN24,

AP22, AP21

DS3NEGDATAIN_A[6:1] A9, A10, A11, C10, A12, E11 I pd DS3/E3/STS-1 Negative Data Input. Either contains the

negative rail of the B3ZS/HDB3 encoded input data or, in

single-rail mode, this input may be used to count bipolar

violations.

DS3NEGDATAIN_B[6:1] J34, K34, L34, K32, M34, L30

DS3NEGDATAIN_C[6:1] AF1, AE1, AD1, AE3, AC1,

AD5

DS3NEGDATAIN_D[6:1] AP26, AP25, AP24, AM25,

AP23, AK24

DS3DATAINCLK_A[6:1] A8, C9, B10, F11, H12, C11 I pd DS3/E3/STS-1 Data Input Clock. 44.736 MHz,

34.368 MHz, or 51.84 MHz clock for the DS3/E3/STS-1

positive and negative data inputs.

DS3DATAINCLK_B[6:1] H34, J32, K33, L29, M27, L32

DS3DATAINCLK_C[6:1] AG1, AF3, AE2, AD6, AC8,

AD3

DS3DATAINCLK_D[6:1] AP27, AM26, AN25, AJ24,

AG23, AM24

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Table 2-12. NSMI/STS-1 In

Symbol Pin Type Name/Description

NSMIRXDATA_A[3:1] R3, P6, P1 I pd Network Serial Multiplex Interface (NSMI) Receive* Data.

Used in the following applications:

■STS-1 rate clear-channel receive data to SPEMPR.

■DS3/E3 rate clear-channel receive data to M13/E13.

Additionally, it could be used as a SONET compliant STS-1 input

signal to STS1LT from external LIU.

* The transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. Low-speed inputs, e.g., NSMIRXDATA, on

the transmit path are labeled receive. Low-speed outputs, e.g., NSMITXDATA on the receive path are labeled transmit.

NSMIRXDATA_B[3:1] C20, F21, A21

NSMIRXDATA_C[3:1] AM15, AJ14, AP14

NSMIRXDATA_D[3:1] Y32, AA29, AA34

NSMIRXCLK_A[3:1] M8, N6, M7 I/O pd NSMI Receive Clock. Used in the following applications:

■Output (51.84 MHz) for the STS-1 rate clear-channel applica-

tion.

■Output (44.736 MHz/34.368 MHz) for the DS3/E3 application.

Additionally, it could be used as an input clock for SONET compli-

ant STS-1 to STS1LT from external LIU.

NSMIRXCLK_B[3:1] H23, F22, G23

NSMIRXCLK_C[3:1] AG12, AJ13, AH12

NSMIRXCLK_D[3:1] AC27, AB29, AC28

NSMIRXSYNC_A[3:1] P5, R1, P2 I/O pd NSMI Receive Frame Sync. Used in the following applications:

■Output receive control frame sync signal for M13/E13.

■Output receive control frame sync signal for SPEMPR.

Additionally, it could be used to carry STS-1 input transmit clock

for STS1LTs.

NSMIRXSYNC_B[3:1] E21, A20, B21

NSMIRXSYNC_C[3:1] AK14, AP15, AN14

NSMIRXSYNC_D[3:1] AA30, Y34, AA33

RXDATAEN_A[3:1] T1, R2, P3 O NSMI Receive Data Enable. This is used for an 8-pin NSMI mode

receive clock. More information will be published in a separate op-

erational guide.

RXDATAEN_B[3:1] A19, B20, C21

RXDATAEN_C[3:1] AP16, AN15, AM14

RXDATAEN_D[3:1] W34, Y33, AA32

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Table 2-13. NSMI/STS-1 Out

Symbol Pin Type Name/Description

NSMITXDATA_A[3:1] U2, U1, T2 O NSMI Transmit Data. NSMI outputs or STS-1 Tx data outputs

from STS1LTs. NSMI output data from either the SPEMPR or

M13/E13 block.

NSMITXDATA_B[3:1] B18, A18, B19

NSMITXDATA_C[3:1] AN17, AP17, AN16

NSMITXDATA_D[3:1] V33, V34, W33

NSMITXCLK_A[3:1] P8, R5, P7 O NSMI Transmit Clock Output or STS-1 Tx Clock Outputs from

STS1LTs. Output clock at 51.84 MHz for the STS-1 rate clear-

channel application, or a (44.736 MHz/34.368 MHz) output clock

for the DS3/E3 application.

NSMITXCLK_B[3:1] H21, E20, G21

NSMITXCLK_C[3:1] AG14, AK15, AH14

NSMITXCLK_D[3:1] AA27, Y30, AA28

NSMITXSYNC_A[3:1] T3, R4, R7 O Transmit System Frame Sync Output. Output transmit control

frame sync signal from M13/E13 or SPEMPR.

NSMITXSYNC_B[3:1] C19, D20, G20

NSMITXSYNC_C[3:1] AM16, AL15, AH15

NSMITXSYNC_D[3:1] W32, Y31, Y28

TXDATAEN_A[3:1] U3, V1, R6 O Transmit Data Enable for NSMI Mode. This is used for an 8-pin

NSMI mode transmit control frame sync. More information will be

published in a separate operational guide.

TXDATAEN_B[3:1] C18, A17, F20

TXDATAEN_C[3:1] AM17, AP18, AJ15

TXDATAEN_D[3:1] V32, U34, Y29

Note: The transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. Low-speed inputs, e.g., NSMIRXDATA,

on the transmit path are labeled receive. Low-speed outputs, e.g., NSMITXDATA on the receive path are labeled transmit.

Table 2-14. Reference Clocks

Symbol Pin Type Name/Description

E1XCLK_1 W9 I pd 1 E1 X Clock. This clock signal is used for three purposes as follows:

■To generate E1 AIS (all 1s).

■As a reference to the E1 DJA.

■As a clock source for the E1 test pattern generator and test pattern monitor.

This input may be provided by a 2.048 MHz, a 32.768 MHz, or a 65.536 MHz ± 50 ppm

free-running crystal oscillator, or clocking chip. E1XCLK_1 and E1XCLK_2 should be

tied together.

Note: For the E1 DJA, an input of 32.768 MHz or 65.536 MHz must be used.

E1XCLK_2 F28

DS1XCLK_1 AA11 I pd 1 DS1 X Clock. This clock signal is used for three purposes as follows:

■To generate DS1 AIS (all 1s).

■As a reference to the DS1 DJA.

■As a clock source for the DS1 test pattern generator and test pattern monitor.

This input may be provided by a 1.544 MHz, a 24.704 MHz, or a 49.408 MHz ± 32 ppm

free-running crystal oscillator, or clocking chip. DS1XCLK_1 and DS1XCLK_2 should

be tied together.

Note: For the DS1 DJA, an input of 24.704 MHz or 49.408 MHz must be used.

DS1XCLK_2 E33

DS3XCLK P23 I pd 2 DS3 X Clock. A 44.736 MHz ± 20 ppm clock input for DS3 DJA and TPG. This input

may be provided by a 44.736 MHz ± 20 ppm free-running crystal oscillator, or clocking

chip.

E3XCLK P24 I pd 2 E3 X Clock. A 34.368 MHz ± 20 ppm clock input for E3 DJA and TPG. This input may

be provided by a 34.368 MHz ± 20 ppm free-running crystal oscillator, or clocking chip.

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Table 2-15. Low-Order Path Overhead Access, Transmit Direction

Symbol Pin Type Name/Description

LOPOHCLKIN_A T16 I pd Low-Order Path Overhead Clock. 19.44 MHz clock supplied from external cir-

cuits that provides the low-order path overhead data.

LOPOHCLKIN_B T19

LOPOHCLKIN_C W16

LOPOHCLKIN_D AA20

LOPOHDATAIN_A R16 I pd Low-Order Path Overhead Data. The following parts of the low-order (VT) over-

head are presented at these pins: communication channel bits (O bits), V5, J2,

Z6/N2, Z7, and K4 byte.

LOPOHDATAIN_B T20

LOPOHDATAIN_C W15

LOPOHDATAIN_D AA21

LOPOHVALIDIN_A P16 I pd Low-Order Path Overhead Data Input Valid. This signal is a mask that indicates

the location of the overhead bytes in the LOPOHDATAIN.

LOPOHVALIDIN_B T21

LOPOHVALIDIN_C W14

LOPOHVALIDIN_D AB19

Table 2-16. Low-Order Path Overhead Access, Receive Direction

Symbol Pin Type Name/Description

LOPOHCLKOUT_A N16 O Low-Order Path Overhead Clock. 19.44 MHz clock supplied to external circuits

that receive the low-order path overhead data.

LOPOHCLKOUT_B T22

LOPOHCLKOUT_C W13

LOPOHCLKOUT_D AC19

LOPOHDATAOUT_A M16 O Low-Order Path Overhead Data. (Line and path REI and RDI, O bits, V5, J2,

Z6/N2, and Z7/K4 byte.)

LOPOHDATAOUT_B T23

LOPOHDATAOUT_C W12

LOPOHDATAOUT_D AB20

LOPOHVALIDOUT_A N15 O Low-Order Path Overhead Data Output Valid. This signal is a mask that indi-

cates the location of the overhead bytes in the LOPOHDATAOUT.

LOPOHVALIDOUT_B R22

LOPOHVALIDOUT_C Y13

LOPOHVALIDOUT_D AB21

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Table 2-17. Clock Generator

Symbol Pin Type Name/Description

CLKIN_PLL G16 I pd 2 On-Chip PLL Reference Input. The clock generator can be used to derive a

clock of the appropriate frequency (DS1/E1) synchronized to CLKIN_PLL.

CG_PLLCLKOUT_A P9 O PLL Test Mode Output. PLL clock (1.544 MHz, 2.048 MHz) selected by

device register.

CG_PLLCLKOUT_B J21

CG_PLLCLKOUT_C AF14

CG_PLLCLKOUT_D AA26

MODE[2:0]_PLL F15, AD13,

F14

I pd 2 PLL Input Clock Mode Select Bits. The settings of these mode select pins

must correspond to the frequency of CLKIN_PLL as shown below.

MODE[2:0]_PLL CLKIN_PLL MODE[2:0]_PLL CLKIN_PLL

000 Reserved 100 16.384 MHz

001 51.840 MHz 101 8.192 MHz

010 26.624 MHz 110 4.096 MHz

011 19.440 MHz 111 2.048 MHz

Table 2-18. Microprocessor Interface

Symbol Pin Type Name/Description

MPCLK AG21 I Microprocessor Clock. This clock is required to properly sample address,

data, and control signals from the microprocessor in both asynchronous and

synchronous modes of operation.

MPMODE AG20 I Microprocessor Mode. If the microprocessor interface is synchronous,

MPMODE should be set to 1. If the microprocessor interface is asynchronous,

MPMODE should be set to 0.

CSN_A D15 I pu Chip Select. Active-low, high-order address signals. Chip select must be set

low at the beginning of any read or write access and returned high at the end

of the cycle. There are four chip selects in the HypermapperLite to determine

which partition is being addressed (A, B, C, or D). Only one of these can be

active-low at any time.

CSN_B R31

CSN_C Y4

CSN_D AL20

ADSN AE21 I Address Strobe. Active-low address strobe that indicates the beginning of a

read or write access. It is a one MPCLK cycle-wide pulse for synchronous

mode. In asynchronous mode, it is active for the entire read/write cycle.

Address bus signals, ADDR[20:0], are available to the HypermapperLite when

ADSN is low. The address bus should remain valid for the duration of ADSN.

RWN AJ20 I Read/Write. RWN is set high during a read cycle, or set low during a write

cycle.

DSN T28 I Data Strobe. For a read cycle, the contents of the internal register will be out-

put on DATA [15:0]; and for a write cycle, the DATA [15:0] will be clocked into

the internal register. To initiate the start of the read/write operation, DSN must

be low during the entire read/write cycle. This signal should only be used for

asynchronous mode.

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ADDR[20:0] AB22, N29, N25,

N24, AG22, P29,

AC22, AJ22, R26,

T27, AD22, R28,

T26, AE22, AH20,

AF21, R27, R29,

AH21, AJ21, AH19

IAddress [20:0]. ADDR[20] is the most significant bit and ADDR[0] is the least

significant bit for addressing all the internal registers during microprocessor

access cycles. All addresses are 21-bit word addresses; hence, in a typical

application ADDR[0] of the TMXL33625 device would be connected to

address bit 1 of a byte addressable system address bus.

Note: The HypermapperLite is little endian, i.e., the least significant byte is

stored in the lowest address and the most significant byte is stored in the

highest address. Care must be exercised when connecting to micropro-

cessors that use big-endian byte ordering.

DATA[15:0] N26, N22, AB9, AB8,

P26, P27, AF22,

AA7, AB6, M22,

AA8, P25, AA6, L22,

P28, Y8

I/O Data [15:0]. 16-bit data bus input for write operations and output for read

operations. DATA[15] is the MSB, and DATA[0] is the LSB.

PAR[1:0] N23, AB23 I/O Data Parity. Byte-wide parity bits for data. PAR[1] is the parity for DATA[15:8],

and PAR[0] is the parity for DATA[7:0]

DTN AB24 O Data Transfer Acknowledge. The delay associated with DTN going low de-

pends on the HypermapperLite block being accessed. In asynchronous mode,

when ADSN or DSN is deasserted, the deassertion will drive the DTN signal

high. When inactive, CSN will drive DTN to be 3-stated. The microprocessor

should wait after DTN is deasserted before starting the next operation.

HP_INTN_1 AB10 O od High-Priority and Low-Priority Interrupts. Active-low. Each of the functional

blocks contain their individual low-priority interrupts. High-priority interrupts are

generated by TMUX, STS1LT, and E13 blocks. Each interrupt is individually

maskable. Requires an external 5 kΩ pull-up resistor. HP_INTN_1 and

HP_INTN_2 should be connected; LP_INTN_1 and LP_INTN_2 should be con-

nected.

HP_INTN_2 M33

LP_INTN_1 F13

LP_INTN_2 AB11

APS_INTN_A G14 O od Automatic Protection Switch Interrupts. Active-low. See the TMUX and

STS1LT sections in the Register Description document for specific interrupts.

Each interrupt is individually maskable. Requires an external 5 kΩ pull-up re-

sistor.

APS_INTN_B J33

APS_INTN_C AC2

APS_INTN_D AN26

Table 2-19. Boundary Scan (IEEE 1149.1)

Symbol Pin Type Name/Description

TCK AC21 I Test Clock. This signal provides timing for boundary-scan test operations.

TDI P15 I pu 2 Test Data In. Boundary-scan test data input signal, sampled on the rising edge of TCK.

TMS_1 Y6 I pu 1 Test Mode Select. Controls boundary-scan test operations. TMS is sampled on the ris-

ing edge of TCK. TMS_1 and TMS_2 should be connected.

TMS_2 AC31

TRST L14 I pu 2 Test Reset (Active-Low). This signal provides an asynchronous reset for the boundary-

scan TAP controller.

TDO AD21 O Test Data Out. Boundary-scan test data output signal is updated on the falling edge of

TCK. The TDO output will be high-impedance, except when transmitting test data.

Table 2-18. Microprocessor Interface (continued)

Symbol Pin Type Name/Description

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Table 2-20. General-Purpose Interface

Symbol Pin Type Name/Description

RSTN_A N1 I pu Global Hardware Reset. Active-low. Initializes all internal registers to their default

state. This is an asynchronous reset, which occurs on the falling edge, but RSTN

should be held low for at least 1 µs. RSTN should be held low until both power sup-

plies (1.5 V and 3.3 V) are stabilized upon powerup.

RSTN_B A22

RSTN_C AP13

RSTN_D AB34

PMRST N14 I/O pd Performance Monitor Reset. Resets error counters. When enabled as an input, it

is a 1s square wave that forces an update of PM counters upon the rising edge.

When the PMRST is generated internally from the MPU clock, this pin is an output.

IC3STATEN M13 I pu 2 Output Enable. When high, output buffers will operate normally. When low, all out-

puts will be forced to a high-impedance state. IC3STATEN should be held low until

both power supplies (1.5 V and 3.3 V) are stabilized upon powerup.

SCK1_1 W8 I pd 1 Scan Clock 1. Reserved. Do not connect.

SCK1_2 AA31

SCK2_1 W7 I pd 1 Scan Clock 2. Reserved. Do not connect.

SCK2_2 AL26

SCAN_EN N13 I pd 2 Scan Enable. Reserved. Do not connect.

SCANMODE_1 L13 I pd 1 Serial Scan Input for Testing. Reserved. Do not connect.

SCANMODE_2 AK30

IDDQ_A N3 I IDDQ Input. This pin must be externally pulled down with a 1 kΩ resistor.

IDDQ_B C22

IDDQ_C AM13

IDDQ_D AB32

Table 2-21. CDR Interface

Symbol Pin Type Name/Description

BYPASS_1 H13 I pd 1 High-Speed CDR Bypass. Reserved. Do not connect.

BYPASS_2 AN23

TSTPHASE J13 I pd 2 Test Phase. Reserved. Do not connect.

ECSEL_1 H15 I pd 1 External Clock Select. Reserved. Do not connect.

ECSEL_2 AH29

ETOGGLE_1 J14 I pd 1 External Toggle. Reserved. Do not connect.

ETOGGLE_2 AF28

EXDNUP_1 K13 I pd 1 External Down Up. Reserved. Do not connect.

EXDNUP_2 D31

TSTMODE H14 I pd 2 Test Mode. Reserved. Do not connect.

TSTSFTLD J15 I pd 2 Test Shift Load. Reserved. Do not connect.

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Table 2-22. Analog Power and Ground Signals

Symbol Pin Type Name/Description

VSSA_CDR1_A K3 — CDR1 Ground. Isolated ground for the internal CDR1.

VSSA_CDR1_B C25

VSSA_CDR1_C AM10

VSSA_CDR1_D AE32

VSSA_CDR2_A J4 — CDR2 Ground. Isolated ground for the internal CDR2.

VSSA_CDR2_B D26

VSSA_CDR2_C AL9

VSSA_CDR2_D AF31

VSSA_X4PLL_A K6 — X4PLL Ground. Isolated ground for the internal X4PLL.

VSSA_X4PLL_B F25

VSSA_X4PLL_C AJ10

VSSA_X4PLL_D AE29

VSSA_SFPLL_A U5 — SFPLL Ground. Isolated ground for the internal SFPLL.

VSSA_SFPLL_B E18

VSSA_SFPLL_C AK17

VSSA_SFPLL_D V30

VSSA_DS3PLL_A L15 — DS3PLL Ground. Isolated ground for the internal DS3PLL.

VSSA_DS3PLL_B R24

VSSA_DS3PLL_C Y11

VSSA_DS3PLL_D AD20

VSSA_E3PLL_A K16 — E3PLL Ground. Isolated ground for the internal E3PLL.

VSSA_E3PLL_B T25

VSSA_E3PLL_C W10

VSSA_E3PLL_D AE19

VDD15A_CDR1_A L3 — CDR1 Power. 1.5 V power supply for the internal CDR1, which is used by

the high-speed receive CDR, the protection receive CDR, and the three

CDRs accociated with the mate interconnect ports. Good engineering prac-

tice needs to be applied; refer to the System Design Guide.

VDD15A_CDR1_B C24

VDD15A_CDR1_C AM11

VDD15A_CDR1_D AD32

VDD15A_CDR2_A H5 — CDR2 Power. 1.5 V power supply for the internal CDR2, which is used by

the high-speed receive CDR, the protection receive CDR, and the three

CDRs accociated with the mate interconnect ports. Good engineering prac-

tice needs to be applied; refer to the System Design Guide.

VDD15A_CDR2_B E27

VDD15A_CDR2_C AK8

VDD15A_CDR2_D AG30

VDD15A_X4PLL_A K7 — X4PLL Power. 1.5 V power supply for the internal X4PLL, which is used for

the transmit protection 1 + 1 port. Good engineering practice needs to be

applied; refer to the System Design Guide.

VDD15A_X4PLL_B G25

VDD15A_X4PLL_C AH10

VDD15A_X4PLL_D AE28

VDD15A_DS3PLL_A M15 — DS3PLL Power. 1.5 V power supply for the internal DS3PLL, which is used

by the DS3DJA. Good engineering practice needs to be applied; refer to the

System Design Guide.

VDD15A_DS3PLL_B R23

VDD15A_DS3PLL_C Y12

VDD15A_DS3PLL_D AC20

VDD15A_E3PLL_A K15 — E3PLL Power. 1.5 V power supply for the internal E3PLL, which is used by

the E3DJA. Good engineering practice needs to be applied; refer to the Sys-

tem Design Guide.

VDD15A_E3PLL_B R25

VDD15A_E3PLL_C Y10

VDD15A_E3PLL_D AE20

VDD33A_SFPLL_A T7 — SFPLL Power. 3.3 V power supply for the internal SFPLL, which is used by

the CG block. Good engineering practice needs to be applied; refer to the

System Design Guide.

VDD33A_SFPLL_B G19

VDD33A_SFPLL_C AH16

VDD33A_SFPLL_D W28

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Table 2-23. Digital Power and Ground Signals

Pin Symbol Type Name/Description

A15, A16, AA9, AA18, AB7, AB12, AB17, AB27, AC7, AC12, AC18,

AC26, AD30, AF18, AG4, AG29, AH22, AH23, AJ5, AJ8, AJ19,

AJ30, AK2, AK6, AK11, AK16, AK29, AL4, AL14, AM19, AN19,

AN20, AN30, AP19, AP20, B5, B12, B15, B16, C16, D8, D21, E6,

E19, E24, E29, F5, F16, F27, F30, G12, G13, G15, H6, H16, H31,

J16, J17, L5, M14, M17, M28, N18, N28, P4, P17, R17, R33, R34,

T5, T17, T29, T32, T33, T34, U13, U19, U20, U21, U23, U26, V9,

V12, V14, V15, V16, V22, W1, W2, W3, W6, W18, W30, Y1, Y2,

Y7, Y9, Y18

VDD15 — Common power signals for 1.5 V VDD.

AA5, AA10, AA12, AB5, AB18, AB31, AC5, AC6, AD17, AD18,

AE18, AE26, AF2, AF4, AF10, AF11, AF17, AF26, AG6, AG17,

AH18, AH30, AJ23, AJ27, AK5, AK7, AK19, AK22, AK23, AL13,

AL19, AL21, AL27, AL31, B9, D4, D9, D14, D16, D22, E5, E12,

E13, E16, E28, E30, F8, F12, G5, G17, H18, H29, J18, J25, J26,

J31, K9, K14, K17, L9, L17, L18, M29, M30, N4, N17, N30, P31,

R18, T30, T31, U8, U9, U11, U15, U17, U18, U22, U24, U25, U28,

V7, V10, V11, V13, V17, V18, V20, V24, V26, V27, W4, W5, Y17

VDD33 — Common power signals for 3.3 V VDD.

A29, A32, AA2, AA3, AA4, AA17, AB2, AB3, AB4, AC3, AC4, AC9,

AC10, AC11, AC23, AC24, AC25, AD4, AD9, AD10, AD11, AD12,

AD19, AD23, AD24, AD25, AD26, AE9, AE10, AE11, AE12, AE23,

AE24, AE25, AF9, AF12, AF16, AF23, AF24, AF25, AG13, AG18,

AH9, AJ4, AJ7, AJ33, AJ34, AK20, AK21, AL12, AL22, AL23,

AL24, AL29, AM20, AM21, AM22, AM23, AM33, AM34, AN3, AN6,

AN21, AN22, AP3, AP6, B13, B14, B29, B32, C12, C13, C14, C15,

D1, D2, D6, D11, D12, D13, D23, E14, E15, F1, F2, F31, G6, G26,

H17, H22, J7, J9, J10, J11, J12, J19, J23, J24, K10, K11, K12, K23,

K24, K25, K26, L10, L11, L12, L16, L23, L24, L25, L26, L31, M4,

M9, M10, M11, M12, M23, M24, M25, M26, M31, M32, N8, N27,

N31, N32, N33, P18, P30, P32, P33, R30, R32, T9, T18, T24, U14,

U16, U27, V8, V19, V21, W11, W17, W26, Y3, Y5

VSS — Common ground signals.

Table 2-24. No Connects

Symbol Pin Type Name/Description

No Connect T15, R15, T14, T13, R14, P14, U12, R13, P13, T12, R12, P12, N12, T11,

R11, U10, T10, P11, R19, R20, P19, N19, P20, R21, M18, P21, N20, M19,

P22, N21, M20, M21, L19, K18, K19, L20, Y16, Y15, AA16, AA15, AB16,

AA14, AC17, AB15, AC16, Y14, AC15, AB14, AA13, AD16, AD15, AE17,

AE16, AC14, W19, Y19, W20, W21, W22, Y20, V23, AA19, Y21, W23, Y22,

Y23, AA22, W24, AA23, V25, W25, Y24, R10, N11, P10, U7, R9, V6, U6,

T8, V5, T6, R8, U4, V4, N10, V3, T4, V2, N9, K20, L21, K21, G18, J20, F17,

F18, H19, E17, F19, H20, D18, D17, K22, C17, D19, B17, J22, AE15,

AD14, AE14, AH17, AF15, AJ18, AJ17, AG16, AK18, AJ16, AG15, AL17,

AL18, AE13, AM18, AL16, AN18, AF13, Y25, AA24, AA25, V28, Y26, U29,

V29, W27, U30, W29, Y27, V31, U31, AB25, U32, W31, U33, AB26, AF19,

AC13, AB13, AG19, AF20.

NC No Connects. These

pins are not used in the

HypemapperLite.

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3 Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute

stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those

given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can

adversely affect device reliability.

3.1 Handling Precautions

Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be

taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations. Agere

employs both a human-body model (HBM) and a charged-device model (CDM) qualification requirement in order to

determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit

parameters used in each of the models, as defined by JEDEC’s JESD22-A114 (HBM) and JESD22-C101 (CDM)

standards.

Table 3-1. Absolute Maximum Ratings

Parameter Min Max Unit

Supply Voltage (VDD33) –0.5 4.2 V

Supply Voltage (VDD15) –0.3 2.0 V

Input Voltage:

LVCMOS

LVDS

–0.3

5.25

VDD33 + 0.3

Power Dissipation — — mW

Storage Temperature Range –65 125 °C

Table 3-2. ESD Tolerance

Device Minimum Threshold

HBM CDM

TMXL33625 2000 V 500 V

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4 Electrical Characteristics

4.1 Recommended Operating Voltages

The following table lists the voltages, along with the tolerances, required for proper operation of the TMXL33625 device.

Internal reference voltage is used if bit LVDS_REF_SEL = 1, or else external voltage is used.

4.2 Recommended Powerup Sequence

The HypermapperLite device requires dual power supplies, a 3.3 V supply for the I/O, and a 1.5 V supply for the core.

During powerup, RSTN should be held low (holding the device in reset) and IC3STATEN should be held low (3-stating all

output buffers). After the 3.3 V and 1.5 V supplies are stable, MPCLK (which affects the device reset) should be applied and

must be present for at least two clock cycles before RSTN and IC3STATEN are released. It is then recommended that

IC3STATEN be released concurrent with, or after, the release of RSTN. There are no constraints as to which supply (3.3 V

or 1.5 V) must come up first, nor does it matter how long it takes the second supply to come up after the first supply.

4.3 Power Consumption

The thermal resistance (ΘJA) between junction and ambient with zero airflow is 7.1 °C/Watt.

The power consumption of the device is application dependent since it is not possible to use all the device features simul-

taneously. The nominal measured values for power per block are shown in Table 4-3.

Typical power by block refers to all instances being used.

Table 4-1. Recommended Operating Conditions

Parameter Symbol Min Typ Max Unit

3.3 V Power Supply VDD33 3.14 3.3 3.47 V

1.5 V Power Supply VDD15 1.4 1.5 1.6 V

Ground VSS —0.0 — V

1.0 V: LVDS Reference* REF10 — 1.0 — V

1.4 V: LVDS Reference* REF14 — 1.4 — V

Ambient Temperature TA–40 — 85 °C

Table 4-2. Typical Power Consumption by Application

Application Conditions Typ Unit

TBD — — —

Table 4-3. Typical Power Consumption Per Block

Block Maximum Instance Typical, Per Single Instance Unit

TMUX 4 0.120 W

STSPP 4 0.020 W

STSXC 4 0.200 W

MRXC 4 0.050 W

SPEMPR 24 0.009 W

STS1LT 12 0.028 W

VTMPR 12 0.015 W

E13 12 0.013 W

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4.4 ac and dc Characteristics

4.4.1 LVCMOS Interface Characteristics

The following table applies to pins with the designations I, Ipd, and Ipu.

* Excludes current due to pull-up or pull-down resistors.

The following table applies to pins with the designations Ipd 1 and Ipu 1.

* Excludes current due to pull-up or pull-down resistors.

The following table applies to pins with the designations Ipd 2 and Ipu 2.

* Excludes current due to pull-up or pull-down resistors.

M13 12 0.013 W

TPG/TPM 4 TBD W

FRM 12 0.195 W

DS1DJA 12 0.026 W

DS3DJA 4 0.050 W

MPU 4 0.420 W

CDR/PLL 4 0.150 W

LVDS I/O 60 0.020 W

NSMI I/O 12 0.032 W

DS3 I/O 24 0.050 W

Table 4-4. LVCMOS Inputs Specifications 1

Parameter Symbol Conditions Min Typ Max Unit

Input Leakage Current IIVSS < VIN < VDD33 — — 1.0* µA

High-input Voltage VIH —2.0——V

Low-input Voltage VIL —V

SS —0.8 V

Input Capacitance CI———1.5pF

Table 4-5. LVCMOS Inputs Specifications 2

Parameter Symbol Conditions Min Typ Max Unit

Input Leakage Current IIVSS < VIN < VDD33 —— 2.0* µA

High-input Voltage VIH —2.0——V

Low-input Voltage VIL —V

SS —0.8 V

Input Capacitance CI———1.5 pF

Table 4-6. LVCMOS Inputs Specifications 3

Parameter Symbol Conditions Min Typ Max Unit

Input Leakage Current IIVSS < VIN < VDD33 —— 4.0* µA

High-input Voltage VIH —2.0——V

Low-input Voltage VIL —V

SS —0.8 V

Input Capacitance CI———1.5 pF

Table 4-3. Typical Power Consumption Per Block (continued)

Block Maximum Instance Typical, Per Single Instance Unit

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* Output current is 10 mA max for NSMITXCLK[3:1].

† Output leakage current of 20 µA for HP_INTN_1, HP_INTN_2, LP_INTN_1, and LP_INTN_2. Output leakage current of 40 µA for DTN.

‡Output capacitance of 6 pF for HP_INTN_1, HP_INTN_2, LP_INTN_1, and LP_INTN_2. Output capacitance of 12 pF for DTN.

* Output current is 10 mA max for NSMIRXCLK[3:1].

† Output leakage current of 44 µA for DATA[15:1], PAR[1:0], and PMRST.

‡Biput capacitance of 20 pF for DATA[15:1], PAR[1:0], and PMRST.

Table 4-7. LVCMOS Outputs Specifications

Parameter Symbol Conditions Min Typ Max Unit

Output Voltage Low VOL IOL = max VSS —0.5V

Output Voltage High VOH IOL = max VDD – 0.5 — VDD V

Output Current Low IOL ———6*mA

Output Current High IOH ———–6*mA

Output Capacitance CO——3

‡—pF

HIZ Output Leakage Current IOZ ———10

†µA

Table 4-8. LVCMOS Bidirectionals Specifications

Parameter Symbol Conditions Min Typ Max Unit

Leakage Current ILVSS < VIN < VDD33 ——11

† µA

High-input Voltage VIH —2.0—V

DD33 + 0.3 V

Low-input Voltage VIL —V

SS —0.8V

Biput Capacitance CIB ——5.0

‡—pF

Output Voltage Low VOL IOL = –6 mA — — 0.5 V

Output Voltage High VOH IOH = 6 mA 2.4 — — V

Output Current Low IOL ———6mA

Output Current High IOH ———–6*mA

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4.4.2 LVDS Interface Characteristics

3.3 V ± 5% VDD, –40 °C to +125 °C junction temperature.

* The buffer will not produce output transitions when input is open-circuited. When the true and complement inputs are floating, the input buffer will not

oscillate.

Table 4-9. LVDS Interface dc Characteristics

Parameter Symbol Test Conditions Min Typ Max Unit

Input Buffer Parameters

Input Voltage Range

High (VIA or VIB)

Low (VIA or VIB)

VIH

VIL

|VGPD| < 925 mV, dc—1 MHz

—

2.4

—

Input Differential Threshold VIDTH dc— 450 MHz –100 — 100 mV

Input Differential Hysteresis VHYST (+VIDTH) – (–VIDTH)———*mV

Receiver Differential Input

Impedance

RIN With build-in termination, center-tapped 80 100 120 Ω

Output Buffer Parameters

Output Voltage:

High (VOA or VOB)

Low (VOA or VOB)

VOH

VOL

RLOAD = 100 Ω ± 1%

—

0.925

—

1.475

—

Output Differential Voltage |VOD|R

LOAD = 100 Ω ± 1% 0.25 — 0.45 V

Output Offset Voltage VOS RLOAD = 100 Ω ± 1% 1.125 — 1.275 V

Output Impedance, Single Ended ROVCM = 1.0 V and 1.4 V 80 100 120 Ω

RO Mismatch Between A and B ∆ROVCM = 1.0 V and 1.4 V — — 10 %

Change in Differential Voltage

Between Complementary States

|∆VOD|R

LOAD = 100 Ω ± 1% — — 25 mV

Change in Output Offset Voltage

Between Complementary States

∆VOS RLOAD = 100 Ω ± 1% — — 25 mV

Output Current ISA, ISB Driver shorted to VSS ——24mA

Output Current ISAB Drivers shorted together — — 12 mA

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5 Timing

5.1 TMUX High-Speed Interface Timing

Figure 5-1. TMUX LVDS Signal Rise/Fall Timing

Figure 5-2. TMUX LVDS Clock and Data Timing

Table 5-1. High-Speed Interface Inputs Specifications

Name Reference Edge

Rising/Falling

Max Rise

Time (ns)

Max Fall

Time (ns)

Min Setup

(ns)

Min Hold

(ns)

RHSDP/N (622 MHz)*Asynchronous — 0.5 0.5 — —

RHSDP/N (155 MHz)*Asynchronous — 0.5 0.5 — —

RHSDP/N (155 MHz) RHSCP/N R/F 1.0 1.0 2 0

THSSYNC†THSCP/N (155.52 MHz) R 1.0 1.0 2 1.5

THSSYNC†THSCP/N (622.08 MHz) R 1.0 1.0 1.7 1.5

* Input serial data stream should have minimum eye opening of 0.4 UIp-p, and no more than 60 consecutive bits that have no transitional edge within

one minute. It must meet 100 ps maximum phase variation limit over a 200 ns interval; this translates to a frequency change of 500 ppm.

† When MPU_MASTER_SLAVE = 0, then refer to Figure 5-4.

Table 5-2. Protection Link Inputs Specifications

Name Reference Edge

Rising/Falling

Max Rise

Time (ns)

Max Fall

Time (ns)

Min Setup

(ns)

Min Hold

(ns)

RPSDP/N (622 MHz)*Asynchronous — 0.5 0.5 — —

RPSDP/N (155 MHz)*Asynchronous — 0.5 0.5 — —

RPSDP/N (155 MHz) RPSCP/N R 1.0 1.0 2 0

* Input serial data stream should have minimum eye opening of 0.4 UIp-p, and no more than 60 consecutive bits that have no transitional edge within

one minute. It must meet 100 ps maximum phase variation limit over a 200 ns interval; this translates to a frequency change of 500 ppm.

80%

20%

THSCOP/N

RHSCP/N

tSU tH

tPD

50%

RHSDP/N

THSDP/N

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5.2 THSSYNC Characteristics

THSSYNC is an 8 kHz composite frame sync pulse for STS-3 or STS-12. THSSYNC contains J0, J1, and V1-1 information

as shown in Figure 5-3. The time delay from any rising edge of a J0 (8 kHz) to the rising edge of the next J0 is 125 µs. The

time delay between any two V1-1 (2 kHz) pulses is 500 µs. This is true whether in STS-3 or in STS-12 mode.

When MPU_MASTER_SLAVE = 1, then THSSYNC is according to Figure 5-3.

Figure 5-3. THSSYNC Timing Diagram (MPU_MASTER_SLAVE = 1)

When MPU_MASTER_SLAVE = 0, then THSSYNC (supplied from an external source) can be according to Figure 5-4.

Figure 5-4. THSSYNC Timing Diagram (MPU_MASTER_SLAVE = 0)

Table 5-3. High-Speed Interface Outputs Specifications

Name Reference Propagation Delay

Min (ns) Max (ns)

THSDP/N (622.08 MHz or 155.52 MHz) THSCOP/N 0.3 0.8

THSSYNC (MPU_MASTER_SLAVE = 1) TLSCLK –0.5 0.2

Table 5-4. Protection Link Outputs Specifications

Name Reference Propagation Delay

Min (ns) Max (ns)

TPSDP/N (622.08 MHz or 155.52 MHz) TPSCP/N 0.3 0.8

STS-3

1-1

1-2

1-3

1-1

1-2

1-3

FIRST FRAME

50 ns

SECOND FRAME THIRD FRAME FOURTH FRAME

STS-12

1-2

1-3

1-1

1-2

1-3

1-1

1-2

1-3

1-1

1-2

1-3

1-1

1-2

1-3

1-5

1-7

1-9

1-11

1-4

1-6

1-8

1-10

1-12

50 ns

1-1

1-2

1-3

1-5

1-7

1-9

1-11

1-4

1-6

1-8

1-10

1-12

1-1

1-2

1-3

1-5

1-7

1-9

1-11

1-4

1-6

1-8

1-10

1-12

1-1

1-2

1-3

1-5

1-7

1-9

1-11

1-4

1-6

1-8

1-10

1-12

12.5 ns

FIRST FRAME SECOND FRAME THIRD FRAME FOURTH FRAME

STS-3 J0

FIRST FRAME

50 ns

STS-12

50 ns

125

J0 J0 J0

SECOND FRAME THIRD FRAME FOURTH FRAME

FIRST FRAME

J0 J0 J0 J0

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When supplied externally, the 8 kHz THSSYNC may have a 50/50 duty cycle since the signal will only be sampled on the

rising edge.

However, if the system needs to synchronize VTs, generated from different HypermapperLites or other external devices,

then THSSYNC needs to look like the waveform representation in Figure 5-3, i.e., THSSYNC must be composed of both the

8 kHz and the 2 kHz sync components (J0 + J1-1—J1-12 + V1-1); V1-2 and V1-3 are not needed.

5.3 STS-3/STM-1 Mate Interconnect Timing

Figure 5-5. STS-3/STM-1 Mate Rise/Fall Timing

Figure 5-6. STS-3/STM-1 Mate Clock and Data Timing

Table 5-5. STS-3/STM-1 Mate Interconnect Inputs Specifications

Name Reference Edge

Rising/Falling

Max Rise Time

(ns)

Max Fall Time

(ns)

Min Setup (ns) Min Hold

(ns)

TLSDATAP/N[3:1] Asynchronous —————

Table 5-6. STS-3/STM-1 Mate Interconnect Outputs Specifications

Name Reference Edge

Rising/Falling

Propagation Delay

Min (ns) Max (ns)

RLSDATAP/N[3:1] Asynchronous — — —

80%

20%

CLOCK

tSU tH

tPD

50%

TLSDATAP/N

RLSDATAP/N

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5.4 TOAC, POAC, and LOPOH Timing

The relationships between data, clock, and sync signals are specific to the TOAC and POAC operation mode selected.

This is explained in detail in the TOAC/POAC chapter of the System Design Guide.

Figure 5-7. TOAC, POAC Timing

Note: For all modes, SYNC signals are high during the clock period of the first bit of each frame.

Figure 5-8. LOPOH Timing

Table 5-7. TOAC and POAC and LOPOH Input Specifications

Name Reference Edge

Rising/Falling

Max Rise

Time (ns)

Max Fall

Time (ns)

Min Setup

(ns)

Min Hold

(ns)

TTOACDATA TTOACCLK (output) R 10 10 3.50

TPOACDATA TPOACCLK (output) R 10 10 3.50

LOPOHDATAIN and

LOPOHVALIDIN

LOPOHCLKIN F 8 8 5 5

* Preliminary estimate, additional simulation underway.

Table 5-8. TOAC and POAC and LOPOH Output Specifications

Name Reference Edge

Rising/Falling

Propagation Delay

Min (ns) Max (ns)

RTOACDATA, RTOACSYNC RTOACCLK R 0 3.5

TTOACSYNC TTOACCLK R 0 3.5

RPOACDATA, RPOACSYNC RPOACCLK R 0 3.5

TPOACSYNC TPOACCLK R 0 3.5

TPOACCLK

tPD

W68 W+

TTOACCLK

TPOACDATA

TTOACDATA

RPOACDATA

RTOACDATA

RPOACCLK

RTOACCLK

W68 W+

LOPOHCLKIN

LOPOHDATAIN

LOPOHDATAOUT

tPD

LOPOHCLKOUT

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5.5 DS3/E3/STS-1 Timing

Figure 5-9 shows a simplified representation of the DS3/E3/STS-1 I/O.

Figure 5-9. DS3/E3 Interface Diagram in M13/E13 Block

LOPOHDATAOUT and LOPOHVALIDOUT LOPOHCLKOUT R 0 5

Table 5-9. DS3/E3 Input Specifications

Name Reference Edge

Rising/Falling

Max Rise

Time (ns)

Max Fall

Time (ns)

Min Setup

(ns)

Min Hold

(ns)

DS3POSDATAIN[6:1]

DS3NEGDATAIN[6:1]

DS3DATAINCLKR/F 5533

Table 5-10. STS-1 Input Specifications

Name Reference Edge

Rising/Falling

Max Rise

Time (ns)

Max Fall

Time (ns)

Min Setup

(ns)

Min Hold

(ns)

DS3POSDATAIN[6:1]

DS3NEGDATAIN[6:1]

DS3DATAINCLK F 5 5 3 3

Table 5-11. DS3/E3/STS-1 Output Specifications

Name Reference Edge

Rising/Falling

Propagation Delay

Min (ns) Max (ns)

DS3POSDATAOUT[6:1]

DS3NEGDATAOUT[6:1]

DS3RXCLKOUT R/F 0 3

Table 5-8. TOAC and POAC and LOPOH Output Specifications

Name Reference Edge

Rising/Falling

Propagation Delay

Min (ns) Max (ns)

M13/E13 BLOCK

DEMUX MUX

CLK

CLK D

DS3DATAINCLK

DS3POSDATAIN

DS3NEGDATAIN DS3DATAOUTCLK

DS3POSDATAOUT

DS3NEGDATAOUT

DS3RXCLKOUT

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5.6 NSMI Timing

For clock and data timing diagrams, related to other NSMI modes, refer to the appropriate System Design Guide section.

Figure 5-10. NSMI Clock and Data Timing (STS-1 Mode)

Table 5-12. NSMI Input Specifications

Name Reference Edge

Rising/Falling

Max Rise

Time (ns)

Max Fall

Time (ns)

Min Setup

(ns)

Min Hold

(ns)

NSMIRXDATA[3:1] NSMIRXCLK R 3.5 3.5 5 0

NSMIRXSYNC[3:1] NSMIRXCLK R 3.5 3.5 5 0

Table 5-13. NSMI Output Specifications

Name Reference Edge

Rising/Falling

Propagation Delay

Min (ns) Max (ns)

NSMITXDATA[3:1] NSMITXCLK R 0.5 8.75

NSMITXSYNC[3:1] NSMITXCLK R 0.5 8.75

RXDATAEN[3:1] NSMIRXCLK R 0.5 8.75

TXDATAEN[3:1] NSMITXCLK R 0.5 8.75

NSMIRXSYNC[3:1] NSMIRXCLK R 0.5 8.75

160,7;&/.

tPD

W68 W+

NSMIRXCLK

NSMIRXDATA

NSMITXDATA

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6 Reference Clocks

Table 6-1. High-Speed Interface Input Clocks Specifications

Clock Name Period

(ns)

Frequency Accuracy

(ppm)

Jitter Rise

(ns)

Fall

(ns)

Min/

Max

Duty Cycle

RHSCP/N 6.43 155.52 MHz 20 — 0.4 0.4 Nominal 50% ± 5%

THSCP/N 6.43 155.52 MHz 20 0.01 UIp-p or 64 psp-p or

0.001 UIrms (12 kHz—5 MHz)

0.4 0.4 Nominal 50% ± 5%

THSCP/N 1.6 622.08 MHz 20 0.04 UIp-p or 64 psp-p

(12 kHz—5 MHz)

—— — 50% ± 5%

Table 6-2. Protection Link Input Clock Specifications

Clock Name Period

(ns)

Frequency Accuracy

(ppm)

Jitter Rise

(ns)

Fall

(ns)

Min/Max Duty Cycle

RPSCP/N 6.43 155.52 MHz 20 — 0.4 0.4 Nominal 50% ± 5%

Table 6-3. DS3/E3/STS-1 Input Clocks Specifications

Clock Name Period

(ns)

Frequency Accuracy

(ppm)

Jitter Rise

(ns)

Fall

(ns)

Min/

Max

Duty Cycle

DS3DATAOUTCLK[6:1] (DS3) 22.353 44.736 MHz 20 0.05 UIp-p or

1.12 nsp-p

(10 kHz—400 kHz)

5 5 Max 50% ± 10%

DS3DATAINCLK[6:1] (DS3) 22.353 44.736 MHz 20 — 3.5 2.5 Max 50% ± 5%

DS3DATAOUTCLK[6:1] (E3) 29.090 34.368 MHz 20 0.03 UIp-p or

0.87 nsp-p

(100 kHz—800 kHz)

5 5 Max 50% ± 10%

DS3DATAINCLK [6:1] (E3) 29.090 34.368 MHz 20 — 3.5 2.5 Max 50% ± 5%

DS3DATAOUTCLK[6:1] (STS-1) 19.290 51.840 MHz 20 0.01 UIp-p or

0.19 nsp-p or

0.001 UIrms

(12 kHz—400 kHz)

5 5 Max 50% ± 10%

DS3DATAINCLK[6:1] (STS-1) 19.290 51.840 MHz 20 — 3.5 2.5 Max 50% ± 5%

Table 6-4. DS1/E1 DJA Input Clocks Specifications

Clock Name Period

(ns)

Frequency Accuracy

(ppm)

Jitter Rise

(ns)

Fall

(ns)

Min/Max Duty Cycle

E1XCLK 15.25 65.536 MHz 50 0.1 UIp-p or 1.5 nsp-p

(20 kHz—100 kHz)

3.5 3.5 Max 50% ± 10%

DS1XCLK 20.20 49.408 MHz 32 0.1 UIp-p or 2.0 nsp-p

(10 kHz—40 kHz)

3.5 3.5 Max 50% ± 10%

E1XCLK 30.52 32.768 MHz 50 0.1 UIp-p or 3.0 nsp-p

(20 kHz—100 kHz)

3.5 3.5 Max 50% ± 10%

DS1XCLK 40.40 24.704 MHz 32 0.1 UIp-p or 4.0 nsp-p

(10 kHz—40 kHz)

3.5 3.5 Max 50% ± 10%

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Table 6-5. DS3/E3 DJA Input Clocks Specifications

Clock Name Period

(ns)

Frequency Accuracy

(ppm)

Jitter Rise

(ns)

Fall

(ns)

Min/Max Duty Cycle

DS3XCLK 22.35 44.736 MHz 20 0.01 UIp-p or 0.22 nsp-p

(10 kHz—400 kHz)

3.5 3.5 Max 50% ± 5%

E3XCLK 29.09 34.368 MHz 20 0.01 UIp-p or 0.29 nsp-p

(100 kHz—800 kHz)

3.5 3.5 Max 50% ± 5%

Table 6-6. LOPOH Input Clock Specifications

Clock Name Period

(ns)

Frequency Accuracy

(ppm)

Jitter Rise

(ns)

Fall

(ns)

Min/Max Duty Cycle

LOPOHCLKIN 51.44 19.44 MHz — — 8 8 Max 50% ± 5%

Table 6-7. Microprocessor Interface Input Clocks Specifications

Clock Name Period

(ns)

Frequency Accuracy

(ppm)

Jitter Rise

(ns)

Fall

(ns)

Min/Max Duty Cycle

MPCLK (min)*62.50 16 MHz — — 4 4 Min 50% ± 10%

MPCLK (max) 15.15 66 MHz — — 4 4 Max 50% ± 10%

* If DTN is used, then the maximum frequency for MPCLK is determined by the processor’s setup specification for DTN. MPU maximum bus operating

frequency = 1/(MPU DTN setup time + tDTNVPD). For example, an 8 ns setup time would limit MPCLK to 50 MHz for reliable DTN detection.

Table 6-8. PLL Input Clock Specifications

Clock Name Period

(ns)

Frequency Accuracy

(ppm)

Jitter Rise

(ns)

Fall

(ns)

Min/Max Duty Cycle

CLKIN_PLL 19.20 51.84 MHz 20 GR-499 and G.823 — — — 50% ± 10%

Table 6-9. High-Speed Interface Output Clocks Specifications

Clock Name Period

(ns)

Frequency Accuracy

(ppm)

Jitter Rise

(ns)

Fall

(ns)

Min/Max Duty Cycle

THSCOP/N 6.43 155.52 MHz 20 0.1 UIp-p — — — 50% ± 5%

THSCOP/N 1.6 622 MHz 20 0.1 UIp-p — — — 50% ± 5%

Table 6-10. Protection Link Output Clocks Specifications

Clock Name Period

(ns)

Frequency Accuracy

(ppm)

Jitter Rise

(ns)

Fall

(ns)

Min/Max Duty Cycle

TPSCP/N 6.43 155.52 MHz 20 — — — — 50% ± 5%

TPSCP/N 1.60 622.08 MHz 20 — — — — 50% ± 5%

Table 6-11. Line Timing Interface Output Clocks Specifications

Clock Name Period

(ns)

Frequency Accuracy

(ppm)

Jitter Rise

(ns)

Fall

(ns)

Min/Max Duty Cycle

RLSCLK 51.44 19.44 MHz 20 — 1.5 1.5 Nominal 50% ± 5%

TLSCLK 51.44 19.44 MHz 20 — 1.5 1.5 Nominal 50% ± 5%

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Table 6-12. TOAC Output Clocks Specifications

Clock Name Period

(ns)

Frequency Accuracy

(ppm)

Jitter Rise

(ns)

Fall

(ns)

Min/Max Duty Cycle

RTOACCLK (STS1LT; mode1) 5.2 (µs) 192 kHz — — 1.5 1.5 Nominal 50% ± 10%

RTOACCLK (STS1LT; mode2) 1.73 (µs) 576 kHz — — 1.5 1.5 Nominal 50% ± 10%

RTOACCLK (STS1LT; mode3) 578 1.728 MHz — — 1.5 1.5 Nominal 50% ± 10%

RTOACCLK

(TMUX; STS-12 D1-3 mode)

5.2 (µs) 192 kHz — — 1.5 1.5 Nominal 37% ± 10%*

RTOACCLK

(TMUX; STS-12 D4-12 mode)

1.73 (µs) 576 kHz — — 1.5 1.5 Nominal 53% ± 10%*

RTOACCLK

(TMUX; STS-12 full access)

48.22 20.736 MHz — — 1.5 1.5 Nominal 33% ± 10%*

RTOACCLK

(TMUX; STS-3 D1-3 mode)

5.2 (µs) 192 kHz — — 1.5 1.5 Nominal 58% ± 10%*

RTOACCLK

(TMUX; STS-3 D4-12 mode)

1.73 (µs) 576 kHz — — 1.5 1.5 Nominal 52% ± 10%*

RTOACCLK

(TMUX; STS-3 full access)

192.9 5.184 MHz — — 1.5 1.5 Nominal 33% ± 10%*

TTOACCLK (STS1LT; mode1) 5.2 (µs) 192 kHz — — 1.5 1.5 Nominal 50% ± 10%

TTOACCLK (STS1LT; mode2) 1.73 (µs) 576 kHz — — 1.5 1.5 Nominal 50% ± 10%

TTOACCLK (STS1LT; mode3) 578 1.728 MHz — — 1.5 1.5 Nominal 50% ± 10%

TTOACCLK

(TMUX; STS-12 D1-3 mode)

5.2 (µs) 192 kHz — — 1.5 1.5 Nominal 37% ± 10%*

TTOACCLK

(TMUX; STS-12 D4-12 mode)

1.73 (µs) 576 kHz — — 1.5 1.5 Nominal 53% ± 10%*

TTOACCLK

(TMUX; STS-12 full access)

48.22 20.736 MHz — — 1.5 1.5 Nominal 33% ± 10%*

TTOACCLK

(TMUX-STS-3 D1-3 mode)

5.2 (µs) 192 kHz — — 1.5 1.5 Nominal 58% ± 10%*

TTOACCLK

(TMUX-STS-3 D4-12 mode)

1.73 (µs) 576 kHz — — 1.5 1.5 Nominal 52% ± 10%*

TTOACCLK

(TMUX-STS-3 full access)

192.9 5.184 MHz — — 1.5 1.5 Nominal 33% ± 10%*

Table 6-13. POAC Output Clocks Specifications

Clock Name Period Frequency Accuracy

(ppm)

Jitter Rise

(ns)

Fall

(ns)

Min/Max Duty Cycle

RPOACCLK (TMUX) 1.73 µs 576 kHz — — 1.5 1.5 Nominal 50% ± 10%

RPOACCLK (STS1LT) 1.73 µs 576 kHz — — 1.5 1.5 Nominal 50% ± 10%

RPOACCLK (SPEMPR) 1.73 µs 576 kHz — — 1.5 1.5 Nominal 50% ± 10%

TPOACCLK (TMUX) 1.73 µs 576 kHz — — 1.5 1.5 Nominal 50% ± 10%

TPOACCLK (STS1LT) 1.73 µs 576 kHz — — 1.5 1.5 Nominal 50% ± 10%

TPOACCLK (SPEMPR) 1.73 µs 576 kHz — — 1.5 1.5 Nominal 50% ± 10%

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Table 6-14. DS3/E3/STS-1 Output Clocks Specifications

Clock Name Period (ns) Frequency Accuracy

(ppm)

Jitter Rise

(ns)

Fall

(ns)

Min/Max Duty Cycle

DS3RXCLKOUT [6:1] (DS3) 22.353 44.736 MHz 20 GR-253 1.5 1.5 Nominal 50% ± 5%

DS3RXCLKOUT [6:1] (E3) 29.090 34.368 MHz 20 G.783 1.5 1.5 Nominal 50% ± 5%

DS3RXCLKOUT [6:1] (STS-1) 19.290 51.840 MHz 20 GR-253 1.5 1.5 Nominal 50% ± 5%

Table 6-15. LOPOH Output Clock Specifications

Clock Name Period (ns) Frequency Accuracy (ppm) Jitter Rise (ns) Fall (ns) Min/Max Duty Cycle

LOPOHCLKOUT 51.44 19.44 MHz 20 — 1.5 1.5 Nominal 50% ± 5%

Table 6-16. PLL Output Clocks Specifications

Clock Name Period (ns) Frequency Accuracy (ppm) Jitter Rise

(ns)

Fall

(ns)

Min/Max Duty Cycle

CG_PLLCLKOUT 647.66 1.544 MHz 32 GR-499 — — — 50% ± 5%

CG_PLLCLKOUT 488.28 2.048 MHz 50 G.823 — — — 50% ± 5%

Table 6-17. NSMI Input/Output Clocks Specifications

Clock Name Period (ns) Frequency Accuracy

(ppm)

Jitter Rise

(ns)

Fall

(ns)

Min/Max Duty Cycle

NSMIRXCLK (STS1LT) 19.29 51.840 MHz 20 — 3.5 3.5 Max 50% ± 5%

NSMIRXCLK (M13) 22.35 44.736 MHz 20 — 1.5 1.5 Nominal 50% ± 5%

NSMIRXCLK (E13) 29.09 34.368 MHz 20 — 1.5 1.5 Nominal 50% ± 5%

NSMIRXCLK (SPEMPR) 19.29 51.840 MHz 20 — 3.5 3.5 Max 50% ± 5%

NSMITXCLK (STS1LT) 19.29 51.84 MHz 20 — 1.5 1.5 Nominal 50% ± 5%

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7 Microprocessor Interface Timing

7.1 Synchronous Write Mode

The synchronous microprocessor interface mode is selected when MPMODE = 1. In this mode, MPCLK used for the

HypermapperLite is the same as the microprocessor clock. Interface timing for the synchronous mode write cycle is given

in Figure 7-1 and in Table 7-1, and for the read cycle in Figure 7-2 and in Table 7-2.

Notes:

MPCLK Input clock to HypermapperLite MPU block.

ADDR [20:0] The address will be available throughout the entire cycle.

CSN (Input) Chip select is an active-low signal.

ADSN (Input) Address strobe is active-low. ADSN must be one MPCLK clock period wide.

RWN (Input) The read (H) write (L) signal is always high except during a write cycle.

DATA[15:0] Data will be available during cycle T1.

DTN (Output) Data transfer acknowledge is active-low for one clock and then driven high before entering a high-impedance state. (This is done with an

I/O pad using the input as feedback to qualify the 3-state term.) DTN will become 3-stated when CSN is high. Typically, DTN is active for

four or five MPCLK cycles after ADSN is low.

Figure 7-1. Microprocessor Interface Synchronous Write Cycle (MPMODE = 1)

* If DTN is used, then the maximum frequency for MPCLK is determined by the processor’s setup specification for DTN. MPU maximum bus operating

frequency = 1/(MPU DTN setup time + tDTNVPD). For example, a 8 ns setup time would limit MPCLK to 50 MHz for reliable DTN detection.

† DTN fall is variable, depending on the block selected for access and in some cases the state of the SONET frame. This interval is typically in the

100 ns to 200 ns range, but can be several hundred ns. In lab measurements, it has never exceeded 1000 ns.

Table 7-1. Microprocessor Interface Synchronous Write Cycle Specifications

Symbol Parameter Setup (Min) Hold (Min) Delay (Min) Delay (Max) Unit

MPCLK MPCLK 16 MHz Min—66* MHz Max Frequency. — — — — ns

tWS ADSN, RWN, DATA (write) Valid to MPCLK. 6.7 — — — ns

tAPD MPCLK to ADDR, RWN, DATA, CSN (write) Invalid. — 0 — — ns

tCSNVS CSN Valid to MPCLK. 6 — — — ns

tADDRVS ADDR Valid to MPCLK. 3.5 — — — ns

tAIPD MPCLK to ADSN Invalid. — 0 — — ns

tDTNVPD MPCLK to DTN Valid. — — 2.5 12 ns

tDTNIPD MPCLK to DTN Invalid. — — 2.5 12 ns

TADSNVDTF ADSN Valid to DTN Falling. — — — —†ns

MPCLK

ADDR[20:0]

CSN

ADSN

RWN

DATA[15:0]

DTN

(INPUT)

tWS

tDTNVPD

tADDRVS

tCSNVS

tWS

T0T1T2T3Tn – 2 Tn – 1 Tn

tAIPD

tAPD

tDTNIPD

HIGH ZHIGH Z

tADSNVDTF

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7.2 Synchronous Read Mode

Notes:

MPCLK Input clock to HypermapperLite MPU block.

ADDR [20:0] The address will be available throughout the entire cycle, and must be stable before ADSN turns high.

CSN (Input) Chip select is an active-low signal.

ADSN (Input) Address strobe is active-low. ADSN must be one MPCLK clock period wide.

RWN (Input) The read (H) write (L) signal is always high during the read cycle.

DTN (Output) Data transfer acknowledge on the host bus interface is initiated on T6. This signal is active for one clock, and then driven high before

entering a high-impedance state. (This is done with an I/O pad using the input as feedback to qualify the 3-state term.) DTN will become

3-stated when CSN is high. Typically, DTN is active four or five MPCLK cycles after ADSN is low.

DATA [15:0] Read data is stable in Tn – 1.

Figure 7-2. Microprocessor Interface Synchronous Read Cycle (MPMODE = 1)

* If DTN is used, then the maximum frequency for MPCLK is determined by the processor’s setup specification for DTN. MPU maximum bus operating

frequency = 1/(MPU DTN setup time + tDNVPD). For example, an 8 ns setup time would limit MPCLK to 50 MHz for reliable DTN detection.

† DTN fall is variable, depending on the block selected for access and in some cases the state of the SONET frame. This interval is typically in the

100 ns to 200 ns range, but can be several hundred ns. In lab measurements, it has never exceeded 1000 ns.

Table 7-2. Microprocessor Interface Synchronous Read Cycle Specifications

Symbol Parameter Setup

(Min)

Hold

(Min)

Delay

(Min)

Delay

(Max)

Unit

MPCLK MPCLK 16 MHz Min—66* MHz Max Frequency.————ns

tAVS ADDR Valid to MPCLK. 3.5 — — — ns

tAPD MPCLK to ADDR Invalid. — 0 — — ns

tCSNSU CSN Active to MPCLK. 6 — — — ns

tADSNSU ADSN Valid to MPCLK. 6 — — — ns

tSNIPD MPCLK to ADSN Inactive. — 0 — — ns

tDNVPD MPCLK to DTN Valid. — — 2.5 12 ns

tDNIPD MPCLK to DTN Invalid. — — 2.5 12 ns

tDAIPD MPCLK to DATA 3-state. — — 3.5 15 ns

tADSNVDTF ADSN Valid to DTN Falling. — — — —†ns

MPCLK

ADDR[20:0]

CSN

ADSN

RWN

tADSNSU tSNIPD

tCSNSU

tAVS

T0T1T2Tn – 4 Tn – 3 Tn – 2 Tn – 1 Tn

DTN

DATA[15:0]

(OUTPUT)

tDAIPD

tDNVPD

tDNIPD

tADSNVDTF

HIGH ZHIGH Z

tAPD

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7.3 Asynchronous Write Mode

The asynchronous microprocessor interface mode is selected when MPMODE = 0. Interface timing for the asynchronous

mode write cycle is given in Figure 7-3 and in Tab l e 7- 3, and for the read cycle in Figure 7-4 and in Ta b le 7-4. Although this

is an asynchronous interface, an MPCLK is still required. This clock can be different (asynchronous) from the MPU clock.

Internal to the chip, RWN, ADSN, and DSN will be sampled by MPCLK.

Notes:

ADDR [20:0] Address is asynchronously passed from the host bus to the internal bus. The address will be available throughout the entire cycle. ADDR

must be held constant while ADSN and DSN are valid (low).

CSN (Input) Chip select is an active-low signal. CSN must be held low (active) until ADSN and DSN are deasserted.

ADSN (Input) Address strobe is active-low. ADSN must be stable the entire period. ADSN and CSN may be connected and driven from the same

source.

DSN (Input) Data strobe is active-low.

DATA [15:0] Write data is asynchronously passed from the host bus to the internal bus. Data will be available throughout the entire cycle. DATA must

be held constant while DSN is valid (low).

RWN (Input) The read/write signal should be high for a read cycle and low for a write cycle. It should always be held high, except during a write cycle.

RWN must be held low (write) until DSN is deasserted (high).

DTN (Output) Data transfer acknowledge (active-low). DTN is driven out of 3-state to inactive-high on the assertion of CSN. When the internal transac-

tion is complete, DTN goes active-low. DTN is then driven high again when either ADSN or DSN is deasserted. DTN will become 3-stated

when CSN is high. DTN fall is variable, depending on the block selected for access and in some cases the state of the SONET frame.

This interval is typically in the 100 ns to 200 ns range, but can be several hundred ns. In lab measurements, it has never exceeded 1000

ns.

Figure 7-3. Microprocessor Interface Asynchronous Write Cycle (MPMODE = 0)

ADDR[20:0]

CSN

ADSN

DSN

RWN

DATA[15:0]

DTN

(INPUT)

tAVADSF

tDVDSF

tCSFDTR

tDSFDTF

tADSRDTR tCSRDT3

tDSRDI

tDSRRWR

tDSNRAI

tADSRAI

tAICSR

tRWFDSF

tAVDSF

HIGH Z HIGH Z

tCSFDSF

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7.4 Asynchronous Read Mode

Notes:

ADDR [20:0] Address is asynchronously passed from the host bus to the internal bus. The address will be available throughout the entire cycle.

CSN (Input) Chip select is an active-low signal.

ADSN (Input) Address strobe is active-low.

DSN (Input) Data strobe is active-low.

RWN (Input) The read (H) write (L) signal is always high during a read cycle.

DTN (Output) Data transfer acknowledge (active-low). DTN is driven out of 3-state to inactive-high on the assertion of CSN. When the internal transac-

tion is complete, DTN goes active-low. DTN is then driven high again when either ADSN or DSN is deasserted. DTN will become 3-stated

when CSN is high.

DATA [15:0] 16-bit data bus.

Figure 7-4. Microprocessor Interface Asynchronous Read Cycle (MPMODE = 0)

Table 7-3. Microprocessor Interface Asynchronous Write Cycle Specifications

Symbol Parameter Setup

(Min)

Hold

(Min)

Delay

(Min)

Delay

(Max)

Unit

tCSFDSF CSN Fall Setup and Hold to DSN Fall. 0 — — — ns

tAICSR ADDR Invalid to CSN Rise. — 0 — — ns

tAVADSF ADDR Valid Setup and Hold to ADSN Fall. 1.0 — — — ns

tADSRAI ADSN Rise to ADDR Invalid. — 1.42 — — ns

tAVDSF ADDR Valid Setup and Hold to DSN Fall. 0 — — — ns

tDSNRAI DSN Rise to ADDR Invalid. — 0 — — ns

tRWFDSF RWN Fall Setup and Hold to DSN Fall. 0 — — — ns

tDSRRWR DSN Rise to RWN Rise. ————ns

tDVDSF DATA Valid Setup and Hold to DSN Fall. 0 — — — ns

tDSRDI DSN Rise to DATA Invalid. — 0 — — ns

tCSFDTR CSN Fall to DTN Rise. — — 5.2 16.0 ns

tDSFDTF DSN Fall to DTN Fall. ————ns

tADSRDTR ADSN or DSN Rise to DTN Rise. — — 2.9 13.3 ns

tCSRDT3 CSN Rise to DTN 3-State. — — 2.9 13 ns

ADDR[20:0]

CSN

ADSN

DSN

DTN

DATA[15:0]

ADSRD3

CSRDT3

ADSRDTR

CSFDSF

RWN

AVADSF

AVDSF

AICSR

ADSRAI

DSNRAI

DTVDV

DSFDTF

CSFDTR

HIGH Z

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7.5 Accessing the Same Register Sequentially Across Multiple Partitions.

Each partition (A, B, C, and D) must be accessed (read or write) independently (treated as individual subsections of the

overall device). The address bus may be held stable but each access (for each partition) must be accompanied by the

assertion of both an address strobe and chip select.

Table 7-4. Microprocessor Interface Asynchronous Read Cycle Specifications

Symbol Parameter Setup

(Min)

Hold

(Min)

Delay

(Min)

Delay

(Max)

Unit

tCSFDSF CSN Fall Setup and Hold to DSN Fall. 0 —*

* CSN must be held low (active) until ADSN and DSN are deasserted.

——ns

tAICSR ADDR Invalid to CSN Rise. — 0 — — ns

tAVADSF ADDR Valid Setup and Hold to ADSN Fall. 1.0 —†

† ADDR must be held constant while ADSN and DSN are valid (low).

——ns

tADSRAI ADSN Rise to ADDR Invalid. — 1.42 — — ns

tAVDSF ADDR Valid Setup and Hold to DSN Fall. 0 ———ns

tDSNRAI DSN Rise to ADDR Invalid. — 0 — — ns

tCSFDTR CSN Fall to DTN Rise. — — 5.2 16.0 ns

tDSFDTF DSN Fall to DTN Fall. — — — —‡

‡ DTN fall is variable, depending on the block selected for access and in some cases, the state of the SONET frame. This interval is typically in the

100 ns to 200 ns range, but can be several hundred ns. In lab measurements, it has never exceeded 1000 ns.

tADSRDTR ADSN or DSN Rise to DTN Rise. — — 2.9 13.3 ns

tCSRDT3 CSN Rise to DTN 3-State. — — 2.9 13.0 ns

tDTVDV DTN Valid to DATA Valid. — — — 0 ns

tADSRD3 ADSN Rise to DATA 3-State. — — 2.9 14 + MPCLK§

§ DATA[15:0] is enabled by a retimed version of the ADSN.

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8 Other Timing

This interface may be used as either synchronous or asynchronous mode.

9 Hardware Design File References

(IBIS, Spice, BSDL, etc.) Available upon request.

10 Ordering Information

Table 8-1. General-Purpose Inputs Specifications

Name Reference Edge

Rising/Falling

Rise Time

(ns)

Fall Time

(ns)

Setup

(ns)

Hold

(ns)

RSTN Async — — — — —

PMRST Async — — — — —

TDI and TMS TCLK R 5 5 19.5 6.4

Table 8-2. Miscellaneous Output Specifications

Name Reference Edge

Rising/Falling

Propagation Delay

Min (ns) Max (ns)

RHSFSYNCN Asynchronous — — —

Table 8-3. General-Purpose Output Specifications

Name Reference Edge

Rising/Falling

Propagation Delay

Min (ns) Max (ns)

TDO TCLK F 12.5 45

Table 10-1. Ordering Information

Device Package Comcode

M-TMXL336251BL-2-DB 1152-pin PBGA 700046355

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11 1152-Pin PBGA Diagrams

Figure 11-1. 1152-Pin PBGA Physical Dimensions

0.61

1.17

1.27

0.75

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6464 Agere Systems Inc.

12 Change History

Changes that were made to this document (since February 21, 2003) are listed in the table below.

12.1 Navigating Through an Adobe Acrobat Document

If the reader displays this document in Adobe Acrobat Reader, clicking on any blue entry in the text will bring the reader to

that reference point. Clicking on the back arrow in Acrobat Reader, will bring the reader back to the starting point.

For example, clicking on page 24 (in Table 12-1), will bring the reader to page 24 of this document, which is the first change.

Clicking on the back arrow in Acrobat Reader will bring the reader back to this page.

Table 12-1. Document Changes

Page Page Page Page Page Page Page

page 24 page 35 page 37 page 38 page 39 page 45 page 61

page 62 ————— —

Hardware Design Guide, Revision 1 TMXL33625 HypermapperLite

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Agere Systems Inc. 65

13 Glossary

AIS Alarm indication signal

AMI Alternate mark inversion

APS Automatic protection switch

ASM Associated signaling mode

BER Bit error rate

BOM Bit-oriented message

BPV Bipolar violation

B8ZS Binary 8 zero code suppression

CCI Common channel signaling

CDR Clock and data recovery

CHI Concentrated highway interface

CMI Coded mark inversion

CRC Cyclic redundancy check

CRV Coding rule violation

DACS Digital access cross connects

DJA Digital jitter attenuation

ESF Extended superframe

EXZ Excessive zeros

FCS Frame check sequence

FDL Facility data link

FEAC Far-end alarm and control

FEBE Far-end block error

HDB3 High-density bipolar of order three

HDLC High-level data link control

LIU Line interface unit

LOC Loss of clock

LOF Loss of frame

LOS Loss of signal

LOPOH Low-order path overhead

OOF Out of frame

MCDR Mate clock and data recovery

MRXC Multirate cross connect

NSMI Network serial multiplexed interface

PBGA Pin ball grid array

POAC Path overhead access channel

PRBS Pseudorandom bit sequence

PRM Performance report message

QRSS Quasirandom signal source

RAI Remote alarm indicator

RDI Remote defect indication

RPOAC Receive path overhead access channel

REI Remote error indication

SDH Synchronous digital hierarchy

SEF Severely errored frame

SONET Synchronous optical network

TCM Tandem connection monitoring

TOAC Transport overhead access channels

UPSR Unidirectional path switch ring

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

Agere, Agere Systems, and the Agere logo are trademarks of Agere Systems Inc.

April 29, 2003

DS03-054MPIC-1 (Replaces DS03-054MPIC)

For additional information, contact your Agere Systems Account Manager or the following:

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