Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 OPAx836 Very-Low-Power, Rail-to-Rail Out, Negative Rail In, Voltage-Feedback Operational Amplifiers 1 Features * 1 * * * * * * * * * * * * * * * Low Power: - Supply Voltage: 2.5 V to 5.5 V - Quiescent Current: 1 mA (Typical) - Power Down Mode: 0.5 A (Typical) Bandwidth: 205 MHz Slew Rate: 560 V/s Rise Time: 3 ns (2 VSTEP) Settling Time (0.1%): 22 ns (2 VSTEP) Overdrive Recovery Time: 60 ns SNR: 0.00013% (-117.6 dBc) at 1 kHz (1 VRMS) THD: 0.00003% (-130 dBc) at 1 kHz (1 VRMS) HD2/HD3: -85 dBc/-105 dBc at 1 MHz (2 VPP) Input Voltage Noise: 4.6 nV/Hz (f = 100 kHz) Input Offset Voltage: 65 V (400-V Maximum) CMRR: 116 dB Output Current Drive: 50 mA RRO: Rail-to-Rail Output Input Voltage Range: -0.2 V to +3.9 V (5-V Supply) Operating Temperature Range: -40C to +125C 2 Applications * * * * * * Low-Power Signal Conditioning Audio ADC Input Buffers Low-Power SAR and ADC Drivers Portable Systems Low-Power Systems High-Density Systems For battery-powered, portable applications where power is of key importance, the low-power consumption and high-frequency performance of the OPA836 and OPA2836 devices offer performanceversus-power capability that is not attainable in other devices. Coupled with a power-savings mode to reduce current to < 1.5 A, these devices offer an attractive solution for high-frequency amplifiers in battery-powered applications. The OPA836 RUN package option includes integrated gain-setting resistors for the smallest possible footprint on a printed-circuit board (approximately 2.00 mm x 2.00 mm). By adding circuit traces on the PCB, gains of +1, -1, -1.33, +2, +2.33, -3, +4, -4, +5, -5.33, +6.33, -7, +8 and inverting attenuations of -0.1429, -0.1875, -0.25, -0.33, -0.75 can be achieved. See Table 3 and Table 4 for details. The OPA836 and OPA2836 devices are characterized for operation over the extended industrial temperature range of -40C to +125C. Device Information(1) PART NUMBER OPA836 OPA2836 BODY SIZE (NOM) 2.90 mm x 1.60 mm WQFN (10) 2.00 mm x 2.00 mm SOIC (8) 4.90 mm x 3.91 mm VSSOP (10) 3.00 mm x 3.00 mm UQFN (10) 2.00 mm x 2.00 mm WQFN (10) 2.00 mm x 2.00 mm (1) For all available packages, see the package option addendum at the end of the data sheet. Harmonic Distortion vs Frequency -40 VS = 2.7 V, -50 G = 1, VOUT = 1 Vpp, -60 R = 0 W, 3 Description F Harmonic Distortion - dBc The OPA836 and OPA2836 devices (OPAx836) are single- and dual-channel, ultra-low power, rail-to-rail output, negative-rail input, voltage-feedback (VFB) operational amplifiers designed to operate over a power-supply range of 2.5 V to 5.5 V with a single supply, or 1.25 V to 2.75 V with a dual supply. Consuming only 1 mA per channel and a unity-gain bandwidth of 205 MHz, these amplifiers set an industry-leading power-to-performance ratio for railto-rail amplifiers. PACKAGE SOT-23 (6) -70 RL = 1 kW -80 -90 HD2 -100 -110 HD3 -120 -130 -140 10k 100k 1M 10M f - Frequency - Hz 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... OPA836-Related Devices ...................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 8 1 1 1 2 4 4 6 Absolute Maximum Ratings ...................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 6 Thermal Information: OPA836 .................................. 6 Thermal Information: OPA2836 ................................ 7 Electrical Characteristics: VS = 2.7 V........................ 7 Electrical Characteristics: VS = 5 V........................... 9 Typical Characteristics ............................................ 12 Detailed Description ............................................ 24 8.1 Overview ................................................................. 24 8.2 Functional Block Diagrams ..................................... 24 8.3 Feature Description................................................. 24 8.4 Device Functional Modes........................................ 27 9 Application and Implementation ........................ 30 9.1 Application Information............................................ 30 9.2 Typical Applications ................................................ 36 10 Power Supply Recommendations ..................... 40 11 Layout................................................................... 40 11.1 Layout Guidelines ................................................. 40 11.2 Layout Example .................................................... 41 12 Device and Documentation Support ................. 42 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Device Support .................................................... Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 42 42 42 42 42 42 42 13 Mechanical, Packaging, and Orderable Information ........................................................... 43 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (September 2016) to Revision I Page * Changed text in sections throughout the data sheet to be more clear and concise .............................................................. 1 * Changed "RG = (open)" to "RG = open".......................................................................................................................... 32 * Changed "gain tracking is superior to using" to "gain drift is superior to the drift with"........................................................ 33 * Changed "results in degraded harmonic distortion" to "increases the harmonic distortion" ............................................... 37 * Deleted "A 10- series resistor can be inserted between the capacitor and the noninverting pin to isolate the capacitance." ........................................................................................................................................................................ 38 Changes from Revision G (October 2015) to Revision H Page * Changed "Type" column header to "I/O" on Pin Functions table .......................................................................................... 5 * Reformatted header rows in Thermal Information: OPA836 and Thermal Information: OPA2836 tables ............................ 6 * Reformatted Thermal Information table note ......................................................................................................................... 6 * Reformatted Thermal Information table note ......................................................................................................................... 7 * Deleted the word "linear" from Output section parameters in Electrical Characteristics VS = 2.7 V table ............................ 7 * Deleted the word "linear" from Output section parameters in Electrical Characteristics VS = 5 V table ............................... 9 * Reformatted Development Support subsection ................................................................................................................... 42 * Reformatted Related Documentation section ...................................................................................................................... 42 * Added Receiving Notification of Documentation Updates section ...................................................................................... 42 Changes from Revision E (September 2013) to Revision F Page * Changed Features section ..................................................................................................................................................... 1 * Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 2 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 OPA836, OPA2836 www.ti.com SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 * Changed Device Comparison Table....................................................................................................................................... 4 * Changed Pin Functions table ................................................................................................................................................. 5 * Changed Open Loop Gain vs Frequency graph................................................................................................................... 15 * Changed Input Referred Noise vs Frequency graph ........................................................................................................... 15 * Changed Open Loop Gain vs Frequency graph ................................................................................................................. 21 * Changed Input Referred Noise vs Frequency graph............................................................................................................ 21 Changes from Revision D (October 2011) to Revision E Page * Added OPA2836 RMC package to document........................................................................................................................ 1 * Added RMC pin definitions to Pin Functions table ................................................................................................................. 5 * Deleted Packaging/Ordering Information table, leaving only note to POA............................................................................. 6 * Added OPA2836 RMC package to Thermal Information table............................................................................................... 7 Changes from Revision C (September 2011) to Revision D Page * Removed Product Preview from OPA835IRUNT and OPA835IRUNR .................................................................................. 4 * Removed Product Preview from OPA836IRUNT and OPA836IRUNR .................................................................................. 6 * Changed typical value for resistor temperature coefficien parameter from TBD to < 10 ....................................................... 9 * Changed "quiescent operating current" parameter to "quiescent operating current per amplifier" ........................................ 9 * Changed resistor temperature coefficient typical value from TBD to < 10........................................................................... 11 * Changed "quiescent operating current" to "quiescent operating current per amplifier" ....................................................... 11 Changes from Revision B (May 2011) to Revision C Page * Added the "The OPA836 RUN package..." text to the Description ........................................................................................ 1 * Removed Product Preview from all devices except OPA835IRUNT and OPA835IRUNR .................................................... 4 * Removed Product Preview from all devices except OPA836IRUNT and OPA836IRUNR .................................................... 6 * Changed typical value for channel to channel crosstalk (OPA2836) parameter from TBD to -120 dB................................. 8 * Changed the common-mode rejection ratio minimum value from 94 dB to 91 dB................................................................. 8 * Added Gain Setting Resistors (OPA836IRUN ONLY) parameter in Electrical Characteristics table ..................................... 9 * Changed the quiescent operating current (TA = 25C) minimum value from 0.8 mA to 0.7 mA ............................................ 9 * Changed the minimum value for power supply rejection (PSRR) parameter from 95 dB to 91 dB ..................................... 9 * Changed the power-down pin bias current test condition from PD = 0.7 V to PD = 0.5 V .................................................... 9 * Changed the power-down quiescent current test condition from PD = 0.7 V to PD = 0.5 V ................................................. 9 * Changed typical value for channel to channel crosstalk (OPA2836) parameter from TBD to -120 dB............................... 10 * Changed the Common-mode rejection ratio Min value From: 97 dB To: 94 dB .................................................................. 11 * Added GAIN SETTING RESISTORS (OPA836I RUN ONLY) parameter to Electrical Characteristics table ...................... 11 * Changed the quiescent operating current (TA = 25C) minimum value from 0.9 mA to 0.8 mA .......................................... 11 * Changed the power supply rejection (PSRR) minimum value from: 97 dB to 94 dB ......................................................... 11 * Changed the Power-down quiescent current CONDITIONS From: PD = 0.7 V To: PD = 0.5 V ......................................... 11 * Changed the Power-down quiescent current Conditions From: PD = 0.7 V To: PD = 0.5 V............................................... 11 * Added Figure Crosstalk vs Frequency ................................................................................................................................. 16 * Added Crosstalk vs Frequency figure................................................................................................................................... 22 * Added section Single Ended to Differential Amplifier ........................................................................................................... 31 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 3 OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 Changes from Revision A (March 2011) to Revision B * 4 www.ti.com Page Changed OPA836 from product preview to production data.................................................................................................. 1 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 OPA836, OPA2836 www.ti.com SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 5 OPA836-Related Devices BW (AV = 1) (MHz) SLEW RATE (V/s) Iq (+5 V) (mA) INPUT NOISE (nV/Hz) RAIL-TO-RAIL IN/OUT DUALS OPA836 205 560 1 4.6 -VS/Out OPA2836 OPA835 30 110 0.25 9.3 -VS/Out OPA2835 OPA365 50 25 5 4.5 In/Out OPA2365 THS4281 95 35 0.75 12.5 In/Out LMH6618 140 45 1.25 10 In/Out LMH6619 OPA830 310 600 3.9 9.5 -VS/Out OPA2830 DEVICE For a complete selection of TI High Speed Amplifiers, visit ti.com. 6 Pin Configuration and Functions OPA836 DBV Package 6-Pin SOT-23 Top View OPA2836 D Package 8-Pin SOIC Top View VOUT 1 6 VS+ VS- 2 5 PD VIN+ 3 + 4 VIN- VOUT1 1 VIN1- 2 VIN1+ 3 VS- 4 OPA836 RUN Package 10-Pin WQFN Top View 1 10 9 FB1 8 FB2 1.6k VIN- - + 2 VOUT1 1 VIN1- 2 VIN1+ 3 VS- 4 PD1 5 1.2k VIN+ 3 7 FB3 6 FB4 400 PD 4 5 + VS+ 7 VOUT2 6 VIN2- 5 VIN2+ OPA2836 DGS Package 10-Pin VSSOP Top View VS+ VOUT + 8 10 + + VS+ 9 VOUT2 8 VIN2- 7 VIN2+ 6 PD2 VS- Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 5 OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 www.ti.com OPA2836 RUN, RMC Packages 10-Pin WQFN, UQFN Top View VS+ VOUT1 1 VIN1- 2 VIN1+ 3 PD1 4 10 9 VOUT2 8 VIN2- 7 VIN2+ 6 PD2 + - - + 5 VS- Pin Functions PIN OPA836 NAME SOT-23 OPA2836 WQFN SOIC VSSOP I/O DESCRIPTION WQFN, UQFN FB1 9 I/O Connection to top of 2.4-k internal gain setting resistors FB2 8 I/O Connection to junction of 1.8-k and 2.4-k internal gain setting resistors I/O Connection to junction of 600- and 1.8-k internal gain setting resistors I/O Connection to bottom of 600- internal gain setting resistors -- FB3 7 FB4 6 PD 5 4 -- -- PD1 -- -- I Amplifier Power Down, low = low-power mode, high = normal operation (PIN MUST BE DRIVEN) 5 4 I Amplifier 1 Power Down, low = low-power mode, high = normal operation (PIN MUST BE DRIVEN) 6 6 I Amplifier 2 Power Down, low = low-power mode, high = normal operation (PIN MUST BE DRIVEN) -- -- I Amplifier noninverting input I Amplifier inverting input -- PD2 VIN+ 3 3 VIN- 4 2 VIN1+ 3 3 3 I Amplifier 1 noninverting input VIN1- 2 2 2 I Amplifier 1 inverting input 5 7 7 I Amplifier 2 noninverting input VIN2+ -- -- 1 1 VIN2- VOUT VOUT1 6 8 8 I Amplifier 2 inverting input -- -- -- O Amplifier output 1 1 1 O Amplifier 1 output 7 9 9 O Amplifier 2 output -- -- VS+ 6 10 8 10 10 POW Positive power supply input VS- 2 5 4 4 5 POW Negative power supply input VOUT2 6 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 OPA836, OPA2836 www.ti.com SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT 5.5 V VS+ + 0.7 V VS- to VS+ Supply voltage VI Input voltage VID Differential input voltage 1 V II Continuous input current 0.85 mA IO Continuous output current 60 mA VS- - 0.7 See Thermal Information: OPA836 and Thermal Information: OPA2836 Continuous power dissipation TJ Maximum junction temperature 150 C TA Operating free-air temperature -40 125 C Tstg Storage temperature -65 150 C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 6000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) 1000 Machine model 200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX VS+ Single supply voltage 2.5 5 5.5 UNIT V TA Ambient temperature -40 25 125 C 7.4 Thermal Information: OPA836 OPA836 THERMAL METRIC (1) DBV (SOT23-6) RUN (WQFN10) 6 PINS 10 PINS UNIT RJA Junction-to-ambient thermal resistance 194 145.8 C/W RJC(top) Junction-to-case (top) thermal resistance 129.2 75.1 C/W RJB Junction-to-board thermal resistance 39.4 38.9 C/W JT Junction-to-top characterization parameter 25.6 13.5 C/W JB Junction-to-board characterization parameter 38.9 104.5 C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953). Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 7 OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 www.ti.com 7.5 Thermal Information: OPA2836 OPA2836 THERMAL METRIC (1) D (SOIC-8) (DGS) VSSOP, MSOP-10 (RUN) WQFN-10 RMC (UQFN-10) 8 PINS 10 PINS 10 PINS 10 PINS UNIT RJA Junction-to-ambient thermal resistance 150.1 206 145.8 143.2 C/W RJCtop Junction-to-case (top) thermal resistance 83.8 75.3 75.1 49.0 C/W RJB Junction-to-board thermal resistance 68.4 96.2 38.9 61.9 C/W JT Junction-to-top characterization parameter 33.0 12.9 13.5 3.3 C/W JB Junction-to-board characterization parameter 67.9 94.6 104.5 61.9 C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953). 7.6 Electrical Characteristics: VS = 2.7 V at VS+ = +2.7 V, VS- = 0 V, VOUT = 1 VPP, RF = 0 , RL = 2 k, G = 1 V/V, input and output referenced to mid-supply, VIN_CM = mid-supply - 0.5 V. TA = 25C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) MHz C AC PERFORMANCE VOUT = 100 mVPP, G = 1 200 VOUT = 100 mVPP, G = 2 100 VOUT = 100 mVPP, G = 5 26 VOUT = 100 mVPP, G = 10 11 Gain-bandwidth product VOUT = 100 mVPP, G = 10 110 MHz C Large-signal bandwidth VOUT = 1 VPP, G = 2 60 MHz C Bandwidth for 0.1-dB flatness VOUT = 1 VPP, G = 2 25 MHz C Slew rate, rise VOUT = 1 VSTEP, G = 2 260 V/s C Slew rate, fall VOUT = 1 VSTEP, G = 2 240 V/s C Rise time VOUT = 1 VSTEP, G = 2 4 ns C Fall time VOUT = 1 VSTEP, G = 2 4.5 ns C Settling time to 1%, rise VOUT = 1 VSTEP, G = 2 15 ns C Settling time to 1%, fall VOUT = 1 VSTEP, G = 2 15 ns C Settling time to 0.1%, rise VOUT = 1 VSTEP, G = 2 30 ns C Settling time to 0.1%, fall VOUT = 1 VSTEP, G = 2 25 ns C Settling time to 0.01%, rise VOUT = 1 VSTEP, G = 2 50 ns C Settling time to 0.01%, fall VOUT = 1 VSTEP, G = 2 45 ns C Overshoot/Undershoot VOUT = 1 VSTEP, G = 2 5%/3% Small-signal bandwidth Second-order harmonic distortion Third-order harmonic distortion f = 10 kHz, VIN_CM = mid-supply - 0.5 V -133 f = 100 kHz, VIN_CM = mid-supply - 0.5 V -120 f = 1 MHz, VIN_CM = mid-supply - 0.5 V -84 f = 10 kHz, VIN_CM = mid-supply - 0.5 V -137 f = 100 kHz, VIN_CM = mid-supply - 0.5 V -130 f = 1 MHz, VIN_CM = mid-supply - 0.5 V -105 C C dBc C C C dBc C C Second-order intermodulation distortion f = 1 MHz, 200-kHz Tone Spacing, VOUT Envelope = 1 VPP VIN_CM = mid-supply - 0.5 V -90 dBc C Third-order intermodulation distortion f = 1 MHz, 200-kHz Tone Spacing, VOUT Envelope = 1 VPP VIN_CM = mid-supply - 0.5 V -90 dBc C Input voltage noise f = 100 KHz Voltage noise 1/f corner frequency Input current noise (1) 8 f = 1 MHz 4.6 nV/Hz C 215 Hz C 0.75 pA/Hz C Test levels (all values set by characterization and simulation): (A) 100% tested at 25C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information. Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 OPA836, OPA2836 www.ti.com SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 Electrical Characteristics: VS = 2.7 V (continued) at VS+ = +2.7 V, VS- = 0 V, VOUT = 1 VPP, RF = 0 , RL = 2 k, G = 1 V/V, input and output referenced to mid-supply, VIN_CM = mid-supply - 0.5 V. TA = 25C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) AC PERFORMANCE (continued) Current noise 1/f corner frequency 31.7 kHz C 55/60 ns C f = 100 kHz 0.02 C f = 10 kHz -120 dB C dB A Overdrive recovery time, over/under Overdrive = 0.5 V Closed-loop output impedance Channel-to-channel crosstalk (OPA2836) DC PERFORMANCE Open-loop voltage gain (AOL) Input referred offset voltage 100 125 TA = 25C -400 65 TA = 0C to 70C -680 680 TA = -40C to 85C -760 760 TA = -40C to 125C -1060 1060 TA = 0C to 70C Input offset voltage drift (2) Input bias current (3) -6.2 1 6.2 -6 1 6 TA = -40C to 125C -6.6 1.1 6.6 TA = 25C 300 650 1000 TA = 0C to 70C 190 1400 TA = -40C to 85C 120 1500 TA = -40C to 125C 120 1800 TA = -40C to 85C TA = 0C to 70C Input bias current drift (2) Input offset current Input offset current drift (2) 400 -2 0.33 2 TA = -40C to 85C -1.9 0.32 1.9 TA = -40C to 125C -2.1 0.37 2.1 TA = 25C -180 30 180 TA = 0C to 70C -200 30 200 TA = -40C to 85C -215 30 215 TA = -40C to 125C -240 30 240 TA = 0C to 70C -460 77 460 TA = -40C to 85C -575 95 575 TA = -40C to 125C -600 100 600 TA = 25C, < 3-dB degradation in CMRR limit -0.2 TA = -40C to 125C, < 3-dB degradation in CMRR limit -0.2 A V V/C B B A nA nA/C B B A nA B pA/C B 0 V A 0 V B INPUT Common-mode input range low Common-mode input range high Input operating voltage range TA = 25C, < 3-dB degradation in CMRR limit 1.5 1.6 V A TA = -40C to 125C, < 3-dB degradation in CMRR limit 1.5 1.6 V B -0.3 to 1.75 V C TA = 25C, < 6-dB degradation in THD Common-mode rejection ratio 91 Input impedance common-mode Input impedance differential mode (2) (3) dB A 200 || 1.2 114 k || pF C 200 || 1 k || pF C Input Offset Voltage Drift, Input Bias Current Drift, and Input Offset Current Drift are average values calculated by taking data at the end points, computing the difference, and dividing by the temperature range. Current is considered positive out of the pin. Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 9 OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 www.ti.com Electrical Characteristics: VS = 2.7 V (continued) at VS+ = +2.7 V, VS- = 0 V, VOUT = 1 VPP, RF = 0 , RL = 2 k, G = 1 V/V, input and output referenced to mid-supply, VIN_CM = mid-supply - 0.5 V. TA = 25C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN UNIT TEST LEVEL (1) 0.2 V A 0.2 V B A TYP MAX TA = 25C, G = 5 0.15 TA = -40C to 125C, G = 5 0.15 OUTPUT Output voltage low Output voltage high Output saturation voltage, high/low Output current drive TA = 25C, G = 5 2.45 2.5 V TA = -40C to 125C, G = 5 2.45 2.5 V B 80/40 mV C TA = 25C, G = 5 TA = 25C 40 45 mA A TA = -40C to 125C 40 45 mA B GAIN SETTING RESISTORS (OPA836IRUN ONLY) Resistor FB1 to FB2 DC resistance 1584 1600 1616 A Resistor FB2 to FB3 DC resistance 1188 1200 1212 A Resistor FB3 to FB4 DC resistance 396 400 404 A Resistor tolerance DC resistance -1% Resistor temperature coefficient DC resistance 1% <10 A PPM C POWER SUPPLY Specified operating voltage Quiescent operating current per amplifier 2.5 TA = 25C 0.7 TA = -40C to 125C 0.6 Power supply rejection (PSRR) 91 0.95 5.5 V B 1.15 mA A 1.4 mA B dB A V A V A 108 POWER DOWN Enable voltage threshold Specified "on" above VS- + 2.1 V Disable voltage threshold Specified "off" below VS- + 0.7 V 2.1 Power-down pin bias current PD = 0.5 V 20 500 nA A Power-down quiescent current PD = 0. 5 V 0.5 1.5 A A Turnon time delay Time from PD = high to VOUT = 90% of final value 200 ns C Turnoff time delay Time from PD = low to VOUT = 10% of original value 25 ns C 0.7 7.7 Electrical Characteristics: VS = 5 V at VS+ = +5 V, VS- = 0 V, VOUT = 2 VPP, RF = 0 , RL = 1 k, G = 1 V/V, input and output referenced to mid-supply. TA = 25C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) MHz C AC PERFORMANCE Small-signal bandwidth VOUT = 100 mVPP, G = 1 205 VOUT = 100 mVPP, G = 2 100 VOUT = 100 mVPP, G = 5 28 VOUT = 100 mVPP, G = 10 11.8 Gain-bandwidth product VOUT = 100 mVPP, G = 10 118 MHz C Large-signal bandwidth VOUT = 2 VPP, G = 2 87 MHz C Bandwidth for 0.1-dB flatness VOUT = 2 VPP, G = 2 29 MHz C Slew rate, rise VOUT = 2-V Step, G = 2 560 V/s C Slew rate, fall VOUT = 2-V Step, G = 2 580 V/s C Rise time VOUT = 2-V Step, G = 2 3 ns C Fall time VOUT = 2-V Step, G = 2 3 ns C (1) 10 Test levels (all values set by characterization and simulation): (A) 100% tested at 25C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information. Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 OPA836, OPA2836 www.ti.com SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 Electrical Characteristics: VS = 5 V (continued) at VS+ = +5 V, VS- = 0 V, VOUT = 2 VPP, RF = 0 , RL = 1 k, G = 1 V/V, input and output referenced to mid-supply. TA = 25C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) AC PERFORMANCE (continued) Settling time to 1%, rise VOUT = 2-V Step, G = 2 22 ns C Settling time to 1%, fall VOUT = 2-V Step, G = 2 22 ns C Settling time to 0.1%, rise VOUT = 2-V Step, G = 2 30 ns C Settling time to 0.1%, fall VOUT = 2-V Step, G = 2 30 ns C Settling time to 0.01%, rise VOUT = 2-V Step, G = 2 40 ns C Settling time to 0.01%, fall VOUT = 2-V Step, G = 2 45 ns C Overshoot/Undershoot VOUT = 2-V Step, G = 2 7.5%/5% Second-order harmonic distortion Third-order harmonic distortion f = 10 kHz -133 f = 100 kHz -120 f = 1 MHz -85 f = 10 kHz -140 f = 100 kHz -130 f = 1 MHz -105 C dBc C dBc C Second-order intermodulation distortion f = 1 MHz, 200 kHz Tone Spacing, VOUT Envelope = 2 VPP -79 dBc C Third-order intermodulation distortion f = 1 MHz, 200 kHz Tone Spacing, VOUT Envelope = 2 VPP -91 dBc C Signal-to-noise ratio, SNR f = 1 kHz, VOUT = 1 VRMS, 22 kHz bandwidth Total harmonic distortion, THD f = 1 kHz, VOUT = 1 VRMS Input voltage noise f = 100 KHz 0.00013% -117.6 0.00003% -130 Voltage noise 1/f corner frequency Input current noise dBc f > 1 MHz Current noise 1/f corner frequency dBc C C 4.6 nV/Hz C 215 Hz C 0.75 pA/Hz C 31.7 kHz C 55/60 ns C Overdrive recovery time, over/under Overdrive = 0.5 V Closed-loop output impedance f = 100 kHz 0.02 C Channel to channel crosstalk (OPA2836) f = 10 kHz -120 dB C dB A DC PERFORMANCE Open-loop voltage gain (AOL) Input referred offset voltage Input offset voltage drift (2) Input bias current (3) Input bias current drift (2) (2) (3) 100 122 TA = 25C -400 65 TA = 0C to 70C -685 685 TA = -40C to 85C -765 765 TA = -40C to 125C -1080 1080 400 TA = 0C to 70C -6.3 1.05 6.3 TA = -40C to 85C -6.1 1 6.1 TA = -40C to 125C -6.8 1.1 6.8 TA = 25C 300 650 1000 TA = 0C to 70C 190 1400 TA = -40C to 85C 120 1550 TA = -40C to 125C 120 1850 TA = 0C to 70C 0.34 TA = -40C to 85C 0.34 2 TA = -40C to 125C 0.38 2.3 A V V/C B B A nA B 2 nA/C B Input Offset Voltage Drift, Input Bias Current Drift, and Input Offset Current Drift are average values calculated by taking data at the end points, computing the difference, and dividing by the temperature range. Current is considered positive out of the pin. Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 11 OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 www.ti.com Electrical Characteristics: VS = 5 V (continued) at VS+ = +5 V, VS- = 0 V, VOUT = 2 VPP, RF = 0 , RL = 1 k, G = 1 V/V, input and output referenced to mid-supply. TA = 25C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX TA = 25C 30 180 TA = 0C to 70C 30 200 TA = -40C to 85C 30 215 TA = -40C to 125C 30 250 UNIT TEST LEVEL (1) DC PERFORMANCE (continued) Input offset current TA = 0C to 70C Input offset current drift (2) 80 480 TA = -40C to 85C 100 600 TA = -40C to 125C 110 660 TA = 25C, < 3-dB degradation in CMRR limit -0.2 TA = -40C to 125C, < 3-dB degradation in CMRR limit -0.2 A nA B pA/C B 0 V A 0 V B INPUT Common-mode input range low Common-mode input range high Input linear operating voltage range TA = 25C, < 3-dB degradation in CMRR limit 3.8 3.9 V A TA = -40C to 125C, < 3-dB degradation in CMRR limit 3.8 3.9 V B -0.3 to 4.05 V C TA = 25C, < 6-dB degradation in THD Common-mode rejection ratio 94 Input impedance common mode Input impedance differential mode dB A 200 || 1.2 116 k || pF C 200 || 1 k || pF C OUTPUT Output voltage low Output voltage high Output saturation voltage, high/low Output current drive TA = 25C, G = 5 0.15 0.2 V A TA = -40C to 125C, G = 5 0.15 0.2 V B A TA = 25C, G = 5 4.75 4.8 V TA = -40C to 125C, G = 5 4.75 4.8 V B 100/50 mV C TA = 25C, G = 5 TA = 25C 40 50 mA A TA = -40C to 125C 40 50 mA B GAIN SETTING RESISTORS (OPA836IRUN ONLY) Resistor FB1 to FB2 DC resistance 1584 1600 1616 A Resistor FB2 to FB3 DC resistance 1188 1200 1212 A Resistor FB3 to FB4 DC resistance 396 400 404 A Resistor tolerance DC resistance -1 Resistor temperature coefficient DC resistance PPM C 5.5 V B 1.2 mA A 1.5 mA B dB A V A V A 1% <10 A POWER SUPPLY Specified operating voltage Quiescent operating current per amplifier 2.5 TA = 25C TA = -40C to 125C Power supply rejection (PSRR) 0.8 1.0 0.65 94 108 POWER DOWN Enable voltage threshold Specified "on" above VS-+ 2.1 V Disable voltage threshold Specified "off" below VS-+ 0.7 V Power-down pin bias current PD = 0.5 V 20 500 nA A Power-down quiescent current PD = 0.5 V 0.5 1.5 A A Turnon time delay Time from PD = high to VOUT = 90% of final value 170 ns C Turnoff time delay Time from PD = low to VOUT = 10% of original value 35 ns C 12 Submit Documentation Feedback 2.1 0.7 Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 OPA836, OPA2836 www.ti.com SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 7.8 Typical Characteristics 7.8.1 Typical Characteristics: VS = 2.7 V Table 1. Table of Graphs FIGURE TITLE FIGURE LOCATION Small Signal Frequency Response Figure 1 Large Signal Frequency Response Figure 2 Noninverting Pulse Response Figure 3 Inverting Pulse Response Figure 4 Slew Rate vs Output Voltage Step Output Overdrive Recovery Figure 5 Figure 6 Harmonic Distortion vs Frequency Figure 7 Harmonic Distortion vs Load Resistance Figure 8 Harmonic Distortion vs Output Voltage Figure 9 Harmonic Distortion vs Gain Figure 10 Output Voltage Swing vs Load Resistance Figure 11 Output Saturation Voltage vs Load Current Figure 12 Output Impedance vs Frequency Figure 13 Frequency Response With Capacitive Load Figure 14 Series Output Resistor vs Capacitive Load Figure 17 Input Referred Noise vs Frequency Figure 16 Open Loop Gain vs Frequency Figure 15 Common Mode/Power Supply Rejection Ratios vs Frequency Figure 18 Crosstalk vs Frequency Figure 19 Power Down Response Figure 20 Input Offset Voltage Figure 23 Input Offset Voltage vs Free-Air Temperature Figure 21 Input Offset Voltage Drift Figure 48 Input Offset Current Figure 24 Input Offset Current vs Free-Air Temperature Input Offset Current Drift Figure 25 Figure 26 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 13 OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 www.ti.com at VS+ = +2.7 V, VS- = 0 V, VOUT = 1 Vpp, RF = 0 , RL = 2 k, G = 1 V/V, input and output referenced to midsupply, VIN_CM = mid-supply - 0.5 V. TA = 25C, unless otherwise noted. 21 21 VS = 2.7 V, VOUT = 100 mVpp, G = 10 18 RL = 1 kW G=5 12 RL = 1 kW 15 9 6 G=2 3 G=5 12 Gain Magnitude - dB Gain Magnitude - dB 15 VS = 2.7 V, VOUT = 1 Vpp, G = 10 18 9 6 G=2 3 G=1 0 0 G=1 -3 -3 G = -1 -6 -6 -9 100k -9 100k 1M 10M f - Frequency - Hz 100M 1G G = -1 3 VS = 2.7 V, G = 1, RF = 0 W VO - Output Voltage - V 1G VOUT = 1.5 Vpp 1.5 RL = 1 kW VOUT = 2 Vpp 2 1.5 1 VOUT = 0.5 Vpp 0.5 VOUT = 0.5 Vpp 1 0.5 0 0 0 500 t - Time - ns 0 1000 500 t - Time - ns 1000 Figure 4. Inverting Pulse Response Figure 3. Noninverting Pulse Response 300 0.75 3.75 VS = 2.7 V, G = 5, RF = 1 kW, VS = 2.7 V, G = 2, 250 RF = 1 kW RL = 1 kW Falling VI - Input Voltage - V 0.5 200 Rising 150 100 VIN 3.25 VOUT 2.75 RL = 1 kW 2.25 1.75 0.25 1.25 0.75 0.25 VO - Output Voltage - V VO - Output Voltage - V 100M VS = 2.7 V, G = -1, RF = 1 kW 2.5 2 RL = 1 kW Slew Rate - V/ms 10M f - Frequency - Hz Figure 2. Large Signal Frequency Response Figure 1. Small Signal Frequency Response 2.5 1M 0 -0.25 50 -0.75 0 0.5 0.6 0.7 0.8 Output Voltage Step -V 0.9 Figure 5. Slew Rate vs Output Voltage Step 14 1 -0.25 0 500 1000 t - Time - ns 1500 -1.25 2000 Figure 6. Output Overdrive Recovery Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 OPA836, OPA2836 www.ti.com SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 at VS+ = +2.7 V, VS- = 0 V, VOUT = 1 Vpp, RF = 0 , RL = 2 k, G = 1 V/V, input and output referenced to midsupply, VIN_CM = mid-supply - 0.5 V. TA = 25C, unless otherwise noted. -40 -70 VS = 2.7 V, -50 G = 1, VOUT = 1 Vpp, -60 R = 0 W, -75 Harmonic Distortion - dBc Harmonic Distortion - dBc F RL = 1 kW -70 -80 -90 HD2 -100 -110 -80 HD2 -85 -90 -95 -100 HD3 -120 HD3 -105 -130 -140 10k -110 100 f - Frequency - Hz 1k RLOAD - Load Resistance - W Figure 7. Harmonic Distortion vs Frequency Figure 8. Harmonic Distortion vs Load Resistance 100k 10M 1M -30 -40 -50 RL = 1 kW VS = 2.7 V, G = 1, f = 1 MHz, VOUT = 1 Vpp, -65 -70 -60 -70 HD2 -80 -90 HD2 RL = 1 kW -75 -80 -85 -90 -95 HD3 -100 -100 HD3 -105 -110 0 1 VO - Output Voltage - Vpp -110 2 1 2 3 4 5 6 Gain - V/V 7 8 9 10 Figure 10. Harmonic Distortion vs Gain Figure 9. Harmonic Distortion vs Output Voltage 1 3 VS = 2.7 V, G = 5, 2.5 RF = 1 kW VS = 2.7 V, G = 5, RF = 1 kW VOUT = High VSAT - Saturation Voltage - V VO - Output Voltage - V 10k -60 VS = 2.7 V, G = 1, f = 1 MHz, RF = 0 W, Harmonic Distortion - dBc Harmonic Distortion - dBc VS = 2.7 V, G = 1, f = 1 MHz, RF = 0 W VOUT = 1 Vpp 2 1.5 1 0.1 VOUT = High VOUT = Low 0.01 0.5 VOUT = Low 0 10 100 1k 10k 0.001 0.1 RL - Load Resistance - W Figure 11. Output Voltage Swing vs Load Resistance 1 10 IL - Load Current - mA 100 Figure 12. Output Saturation Voltage vs Load Current Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 15 OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 www.ti.com at VS+ = +2.7 V, VS- = 0 V, VOUT = 1 Vpp, RF = 0 , RL = 2 k, G = 1 V/V, input and output referenced to midsupply, VIN_CM = mid-supply - 0.5 V. TA = 25C, unless otherwise noted. 3 VS = 2.7 V, G=1 100 VS = 2.7 V, G = 1, R F = 0W CL = 10 pF RO = 49.9 W Gain Magnitude - dB ZO - Output Impedance - W RL = 1 kW, CL = 22 pF 0 10 1 RO = 40.2 W CL = 56 pF RO = 24.9 W CL = 100 pF -3 RO = 16.9 W CL = 220 pF RO = 10 W CL = 560 pF -6 0.1 RO = 5 W CL = 2.2 pF 0.01 10k 100k 1M 10M f - Frequency - Hz 100M 1G 100 -90 80 -135 60 -180 40 -225 20 -270 0 -315 40 1 10 100 1k 10k 100k 100M 1G Voltage Noise Current Noise 10 1 -360 -405 1M 10M 100M 0.1 1G 1 Frequency (Hz) 10 100 C001 1K 10K 100K Frequency (Hz) 1M 10M VS = 2.7 V VS = 2.7 V Figure 16. Input Referred Noise vs Frequency Figure 15. Open Loop Gain vs Frequency 100 0 VS = 2.7 V, G = 1, RF = 0 W, VS = 2.7 V PSRR -10 RL = 1 kW -20 CMRR/PSRR - dB RO - Output Resistor - W 10M f - Frequency - Hz 100 VN, IN (nV/Hz, pA/Hz) -45 Phase () 0 120 Magnitude (dB) 140 Open Loop Gain Magnitude Open Loop Gain Phase 1M Figure 14. Frequency Response With Capacitive Load Figure 13. Output Impedance vs Frequency 20 RO = 0 W -9 100k 10 CMRR -30 -40 -50 -60 -70 1 1 10 100 CLOAD - Capacitive Load - pF 1000 Figure 17. Series Output Resistor vs Capacitive Load 16 -80 100k 1M 10M f - Frequency - Hz 100M Figure 18. Common Mode/Power Supply Rejection Ratios vs Frequency Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 OPA836, OPA2836 www.ti.com SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 at VS+ = +2.7 V, VS- = 0 V, VOUT = 1 Vpp, RF = 0 , RL = 2 k, G = 1 V/V, input and output referenced to midsupply, VIN_CM = mid-supply - 0.5 V. TA = 25C, unless otherwise noted. 3 -80 VS = 2.7 V, G = 2, RF = 1 kW, VPD 2.5 RL = 1 kW 2 -100 VOUT /VPD Crosstalk (dB) -90 -110 VOUT 1.5 1 -120 0.5 -130 -140 20 100 1k 10k 100k Frequency (Hz) 1M 10M 0 100M 0 500 t - Time - ns Figure 20. Power Down Response Figure 19. Crosstalk vs Frequency 400 8 300 7 200 6 100 5 Count VOS - Offset Voltage - mV 1000 0 0C to 70C -40C to 85C -40C to 125C 4 -100 3 -200 2 -300 1 0 -400 -40 -20 0 20 40 60 80 100 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOS - Drift - mV/C 120 TA - Free-Air Temperature - C Figure 22. Input Offset Voltage Drift Figure 21. Input Offset Voltage vs Free-Air Temperature 1800 3000 1687 2666 1600 1532 2500 1400 1200 964 1507 Count 1500 1268 1000 1000 768 800 600 365 400 311 233 200 34 3 2 0 0 0 0 0 0 58 29 29 9 10 4 13 Figure 23. Input Offset Voltage IOS - Offset Current - nA Figure 24. Input Offset Current Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 >36.6 <136.6 <122.94 <95.62 <109.28 <68.3 <81.96 <-0 <13.66 <-27.32 <-68.3 <-54.64 <-40.98 <-95.62 <-81.96 0 <-136.6 <694.3 >694.3 <624.87 <486.01 <555.44 <277.72 <347.15 <416.58 <138.86 <208.29 <0 <69.43 <-138.86 <-69.43 <-347.15 <-277.72 <-208.29 <-486.01 <-416.58 <-694.3 <-624.87 <-555.44 IOS - Offset Current - nA 125 80 20 8 7 11 15 28 40 <-122.94 <-109.28 207 0 0 0 0 0 0 7 30 0 <-13.66 500 <27.32 <40.98 <54.64 Count 2000 17 OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 www.ti.com at VS+ = +2.7 V, VS- = 0 V, VOUT = 1 Vpp, RF = 0 , RL = 2 k, G = 1 V/V, input and output referenced to midsupply, VIN_CM = mid-supply - 0.5 V. TA = 25C, unless otherwise noted. 14 150 12 10 0 8 6 -50 4 -100 -150 -40 2 0 -20 0 20 40 60 80 100 120 TA - Free-Air Temperature - C Figure 25. Input Offset Current vs Free-Air Temperature 18 0C to 70C -40C to 85C -40C to 125C 50 Count IOS - Offset Current - nA 100 -400-350-300-250-200-150-100 -50 0 50 100 150 200 250 300 350 400 IOS - Drift - pA/C Figure 26. Input Offset Current Drift Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 OPA836, OPA2836 www.ti.com SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 7.8.2 Typical Performance Graphs: VS = 5 V Table 2. Table of Graphs FIGURE TITLE FIGURE LOCATION Small Signal Frequency Response Figure 27 Large Signal Frequency Response Figure 28 Noninverting Pulse Response Figure 29 Inverting Pulse Response Figure 30 Slew Rate vs Output Voltage Step Output Overdrive Recovery Figure 31 Figure 32 Harmonic Distortion vs Frequency Figure 33 Harmonic Distortion vs Load Resistance Figure 34 Harmonic Distortion vs Output Voltage Figure 35 Harmonic Distortion vs Gain Figure 36 Output Voltage Swing vs Load Resistance Figure 37 Output Saturation Voltage vs Load Current Figure 38 Output Impedance vs Frequency Figure 39 Frequency Response With Capacitive Load Figure 40 Series Output Resistor vs Capacitive Load Figure 43 Input Referred Noise vs Frequency Figure 41 Open Loop Gain vs Frequency Figure 42 Common Mode/Power Supply Rejection Ratios vs Frequency Figure 44 Crosstalk vs Frequency Figure 45 Power Down Response Figure 46 Input Offset Voltage Figure 49 Input Offset Voltage vs Free-Air Temperature Figure 47 Input Offset Voltage Drift Figure 48 Input Offset Current Figure 50 Input Offset Current vs Free-Air Temperature Input Offset Current Drift Figure 51 Figure 52 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 19 OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 www.ti.com at VS+ = +5 V, VS- = 0 V, VOUT = 2 VPP, RF = 0 , RL = 1 k, G = 1 V/V, input and output referenced to midsupply unless otherwise noted. TA = 25C, unless otherwise noted. 21 21 VS = 5 V, VOUT = 100 mVpp, G = 10 18 RL = 1 kW 15 G=2 3 0 G=5 12 Gain Magnitude - dB Gain Magnitude - dB 9 6 RL = 1 kW 15 G=5 12 VS = 5 V, VOUT = 2 Vpp, G = 10 18 9 6 G=2 3 0 G=1 -3 -3 G=1 -6 -6 G = -1 G = -1 -9 100k 1M 10M f - Frequency - Hz 100M -9 100k 1G Figure 27. Small Signal Frequency Response 5 100M 1G 5 VS = 5 V, 4.5 G = 1, RF = 1 kW 4 R = 1 kW 4 3 VO - Output Voltage - V 3.5 VOUT = 4 Vpp L VOUT = 4 Vpp VS = 5 V, G = 1, RF = 0 W 2.5 RL = 1 kW 2 1.5 3.5 3 2.5 VOUT = 0.5 Vpp 2 1.5 1 1 0.5 0.5 VOUT = 0.5 Vpp 0 0 500 t - Time - ns 1000 0 Figure 29. Noninverting Pulse Response 1000 Figure 30. Inverting Pulse Response 1.25 700 600 500 t - Time - ns VS = 5 V, G = 2, RF = 1 kW RL = 1 kW 6.25 VIN VS = 5 V, G = 5, 1 RF = 1 kW, RL = 1 kW Falling Rising 5.75 5.25 VOUT 4.75 4.25 VI - Input Voltage - V 500 400 300 0.75 3.75 3.25 2.75 0.5 2.25 1.75 0.25 1.25 200 0.75 0 0 -0.25 -0.25 1 2 Output Voltage Step -V 3 Figure 31. Slew Rate vs Output Voltage Step 20 0.25 0 100 VO - Output Voltage - V 0 Slew Rate - V/ms 10M f - Frequency - Hz Figure 28. Large Signal Frequency Response 4.5 VO - Output Voltage - V 1M 4 0 500 1000 t - Time - ns 1500 -0.75 -1.25 2000 Figure 32. Output Overdrive Recovery Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 OPA836, OPA2836 www.ti.com SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 at VS+ = +5 V, VS- = 0 V, VOUT = 2 VPP, RF = 0 , RL = 1 k, G = 1 V/V, input and output referenced to midsupply unless otherwise noted. TA = 25C, unless otherwise noted. -40 -70 VS = 5 V, -50 G = 1, VOUT = 2 Vpp, -60 R = 0 W, -80 -90 HD2 -100 -110 -80 Harmonic Distortion - dBc Harmonic Distortion - dBc F RL = 1 kW -70 VS = 5 V, G = 1, f = 1 MHz, RF = 0 W VOUT = 2 Vpp -75 HD3 HD2 -85 -90 -95 -100 -120 HD3 -105 -130 -140 10k 1M 100k -110 100 10M 1k RLOAD - Load Resistance - W f - Frequency - Hz Figure 33. Harmonic Distortion vs Frequency Figure 34. Harmonic Distortion vs Load Resistance -60 -70 VS = 5 V, G = 1, f = 1 MHz, RF = 0 W, -80 VS = 5 V, G = 1, f = 1 MHz, VOUT = 2 Vpp, -65 -70 RL = 1 kW Harmonic Distortion - dBc -75 Harmonic Distortion - dBc 10k HD2 -85 -90 -95 -100 HD3 RL = 1 kW -75 HD2 -80 -85 -90 -95 HD3 -100 -105 -105 -110 0 1 2 VO - Output Voltage - Vpp 3 -110 4 1 Figure 35. Harmonic Distortion vs Output Voltage 5 3 4 5 6 Gain - V/V 7 8 9 10 Figure 36. Harmonic Distortion vs Gain 1 VS = 5 V, G = 2, RF = 1 kW VS = 5 V, G = 5, RF = 1 kW VOUT = High VSAT - Saturation Voltage - V 4 VO - Output Voltage - V 2 3 2 1 VOUT = High 0.1 VOUT = Low VOUT = Low 0 10 100 1k 10k 0.01 0.1 RL - Load Resistance - W Figure 37. Output Voltage Swing vs Load Resistance 1 10 IL - Load Current - mA 100 Figure 38. Output Saturation Voltage vs Load Current Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 21 OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 www.ti.com at VS+ = +5 V, VS- = 0 V, VOUT = 2 VPP, RF = 0 , RL = 1 k, G = 1 V/V, input and output referenced to midsupply unless otherwise noted. TA = 25C, unless otherwise noted. VS = 5 V, G = 1, RF = 0 W CL = 10 pF RO = 49.9 W RL = 1 kW CL = 2.2 pF 0 10 Gain Magnitude - dB ZO - Output Impedance - W 3 VS = 5 V, G=1 100 1 0.1 RO = 0 W CL = 56 pF RO = 24.9 W CL = 100 pF -3 RO = 16.9 W CL = 220 pF RO = 10 W -6 CL = 560 pF RO = 5 W CL = 22 pF RO = 40.2 W -9 0.01 0.01 0.1 1 10 100 1000 1M 100k 10M f - Frequency - Hz f - Frequency - MHz Figure 39. Output Impedance vs Frequency -90 80 -135 60 -180 40 -225 20 -270 0 -315 Open Loop Gain Magnitude Open Loop Gain Phase 1 10 100 1k 10k 100k Voltage Noise Current Noise VN, IN (nV/Hz, pA/Hz) 100 100 Phase () -45 Magnitude (dB) 0 120 40 10 1 -360 -405 1M 10M 100M 0.1 1G Frequency (Hz) 1 10 100 C002 1K 10K 100K Frequency (Hz) 1M 10M VS = 5.0 V VS = 5.0 V Figure 42. Input Referred Noise vs Frequency Figure 41. Open Loop Gain vs Frequency 0 100 VS = 5 V VS = 5 V, G = 1, RF = 0 W, PSRR -10 RL = 1 kW -20 CMRR/PSRR - dB RO - Output Resistor - W 1G Figure 40. Frequency Response With Capacitive Load 140 20 100M 10 CMRR -30 -40 -50 -60 -70 1 1 10 100 CLOAD - Capacitive Load - pF 1000 Figure 43. Series Output Resistor vs Capacitive Load 22 -80 100k 1M 10M f - Frequency - Hz 100M Figure 44. Common-Mode/Power Supply Rejection Ratios vs Frequency Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 OPA836, OPA2836 www.ti.com SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 at VS+ = +5 V, VS- = 0 V, VOUT = 2 VPP, RF = 0 , RL = 1 k, G = 1 V/V, input and output referenced to midsupply unless otherwise noted. TA = 25C, unless otherwise noted. 5 4.5 VS = 5 V, G = 2, RF = 1 kW 4 RL = 1 kW VPD -90 3.5 -100 3 VOUT VOUT /VPD Crosstalk (dB) -80 -110 2.5 2 -120 1.5 1 -130 0.5 -140 20 100 1k 10k 100k Frequency (Hz) 1M 10M 0 100M 0 500 t - Time - ns Figure 45. Crosstalk vs Frequency Figure 46. Power Down Response 400 9 300 8 0C to 70C -40C to 85C -40C to 125C 7 200 6 100 Count VOS - Offset Voltage - mV 1000 0 5 4 -100 3 -200 2 -300 1 -400 -40 0 -20 0 20 40 60 80 100 120 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOS - Drift - mV/C TA - Free-Air Temperature - C Figure 47. Input Offset Voltage vs Free-Air Temperature Figure 48. Input Offset Voltage Drift 3000 1800 1641 2707 1600 1525 2500 1400 1200 Count 1511 1500 1269 1000 947 1000 788 800 600 369 400 261 500 200 58 28 30 10 8 5 13 Figure 49. Input Offset Voltage <136.5 IOS - Offset Current - nA Figure 50. Input Offset Current Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 >136.5 <109.2 <122.85 <81.9 <95.55 <0 <13.65 <27.3 <-27.3 <-13.65 <-40.95 <-109.2 <-95.55 <-81.9 <-68.25 <-54.6 <-136.5 0 <-122.85 >693 <485.1 VOS - Offset Voltage - mV <554.4 <623.7 <693 <277.2 <346.5 <415.8 <138.6 <207.9 <-69.3 <0 <69.3 <-138.6 <-277.2 <-207.9 <-415.8 <-346.5 <-554.4 <-485.1 <-693 <-623.7 0 129 89 20 8 8 9 14 32 43 31 1 2 0 0 0 0 0 0 <68.25 289 193 0 0 0 0 0 0 7 25 <40.95 <54.6 Count 2000 23 OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 www.ti.com 150 12 100 10 50 8 Count IOS - Offset Current - nA at VS+ = +5 V, VS- = 0 V, VOUT = 2 VPP, RF = 0 , RL = 1 k, G = 1 V/V, input and output referenced to midsupply unless otherwise noted. TA = 25C, unless otherwise noted. 0 6 -50 4 -100 2 -150 -40 0C to 70C -40C to 85C -40C to 125C 0 -20 0 20 40 60 80 100 120 -400-350-300-250-200-150-100 -50 0 Figure 51. Input Offset Current vs Free-Air Temperature 24 50 100 150 200 250 300 350 400 IOS - Drift - pA/C TA - Free-Air Temperature - C Figure 52. Input Offset Current Drift Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 OPA836, OPA2836 www.ti.com SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 8 Detailed Description 8.1 Overview The OPAx836 family of bipolar-input operational amplifiers offers excellent bandwidth of 205 MHz with ultra-low THD of 0.00003% at 1 kHz. The OPAx836 device can swing to within 200 mV of the supply rails while driving a 1-k load. The input common-mode of the amplifier can swing to 200 mV below the negative supply rail. This level of performance is achieved at 1 mA of quiescent current per amplifier channel. 8.2 Functional Block Diagrams VSIG VS+ VREF VIN RG OPA 836 VOUT GVSIG VREF VS- VREF RF Figure 53. Noninverting Amplifier VSIG VREF VS+ VREF RG OPA 836 VIN VS- VOUT GVSIG VREF RF Figure 54. Inverting Amplifier 8.3 Feature Description 8.3.1 Input Common-Mode Voltage Range When the primary design goal is a linear amplifier with high CMRR, it is important to not violate the input common-mode voltage range (VICR) of an operational amplifier. The common-mode input range specifications in the table data use CMRR to set the limit. The limits are selected to ensure CMRR will not degrade more than 3 dB below the CMRR limit if the input voltage is kept within the specified range. The limits cover all process variations and most parts will be better than specified. The typical specifications are from 0.2 V below the negative rail to 1.1 V below the positive rail. Assuming the operational amplifier is in linear operation, the voltage difference between the input pins is small (ideally 0 V) and input common-mode voltage is analyzed at either input pin with the other input pin assumed to be at the same potential. The voltage at VIN+ is simple to evaluate. In noninverting configuration, Figure 53, the input signal, VIN, must not violate the VICR. In inverting configuration, Figure 54, the reference voltage, VREF, must be within the VICR. The input voltage limits have fixed headroom to the power rails and track the power supply voltages. For one 5-V supply, the linear input voltage ranges from -0.2 V to 3.9 V and from -0.2 V to 1.6 V for a 2.7-V supply. The delta headroom from each power supply rail is the same in either case: -0.2 V and 1.1 V. Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 25 OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 www.ti.com Feature Description (continued) 8.3.2 Output Voltage Range The OPA836 and OPA2836 devices are rail-to-rail output (RRO) operational amplifiers. Rail-to-rail output typically means the output voltage swings within a couple hundred millivolts of the supply rails. There are different ways to specify this: one is with the output still in linear operation and another is with the output saturated. Saturated output voltages are closer to the power supply rails than linear outputs, but the signal is not a linear representation of the input. Linear output is a better representation of how well a device performs when used as a linear amplifier. Saturation and linear operation limits are affected by the output current, where higher currents lead to more loss in the output transistors. Figure 11 and Figure 37 show saturated voltage-swing limits versus output load resistance and Figure 12 and Figure 38 show the output saturation voltage versus load current. Given a light load, the output voltage limits have nearly constant headroom to the power rails and track the power supply voltages. For example, with a 2-k load and single 5-V supply, the linear output voltage ranges from 0.15 V to 4.8 V, and ranges from 0.15 V to 2.5 V for a 2.7-V supply. The delta from each power supply rail is the same in either case: 0.15 V and 0.2 V. With devices like the OPA836 and OPA2836, where the input range is lower than the output range, typically the input will limit the available signal swing only in noninverting gain of 1. Signal swing in noninverting configurations in gains > +1 and inverting configurations in any gain is typically limited by the output voltage limits of the operational amplifier. 8.3.3 Power-Down Operation The OPA836 and OPA2836 devices include a power-down mode. Under logic control, the amplifiers can switch from normal operation to a standby current of < 1.5 A. When the PD pin is connected high, the amplifier is active. Connecting PD pin low disables the amplifier and places the output in a high-impedance state. When the amplifier is configured as a unity-gain buffer, the output stage is in a high dc-impedance state. To protect the input stage of the amplifier, the devices use internal, back-to-back ESD diodes between the inverting and noninverting input pins. This configuration creates a parallel low-impedance path from the amplifier output to the noninverting pin when the differential voltage between the pins exceeds a diode voltage drop. When the op amp is configured in other gains, the feedback (RF) and gain (RG) resistor network forms a parallel load. The PD pin must be actively driven high or low and must not be left floating. If the power-down mode is not used, PD must be tied to the positive supply rail. PD logic states are TTL with reference to the negative supply rail and VS-. When the operational amplifier is powered from single-supply and ground and driven from logic devices with similar VDD, voltages to the operational amplifier do not require any special consideration. When the operational amplifier is powered from a split supply, with VS- below ground, an open-collector type of interface with pullup resistor is more appropriate. Pullup resistor values must be lower than 100 k. Additionally, the drive logic must be negated due to the inverting action of an open-collector gate. 8.3.4 Low-Power Applications and the Effects of Resistor Values on Bandwidth The OPA836 and OPA2836 devices are designed for the nominal value of RF to be 1 k in gains other than +1. This gives excellent distortion performance, maximum bandwidth, best flatness, and best pulse response, but it also loads the amplifier. For example; in gain of 2 with RF = RG = 1 k, RG to ground, and VOUT = 4 V, 2 mA of current will flow through the feedback path to ground. In gain of +1, RG is open and no current will flow to ground. In low-power applications, it is desirable to reduce the current in the feedback by increasing the gain-setting resistors values. Using larger value gain resistors has two primary side effects (other than lower power) due to their interaction with parasitic circuit capacitance: * * Lowers the bandwidth Lowers the phase margin - This causes peaking in the frequency response - This also causes overshoot and ringing in the pulse response Figure 55 shows the small-signal frequency response on OPA836EVM for noninverting gain of 2 with RF and RG equal to 1 k, 10 k, and 100 k. The test was done with RL = 1 k. Due to loading effects of RL, lower RL values may reduce the peaking, but higher values will not have a significant effect. 26 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 OPA836, OPA2836 www.ti.com SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 Feature Description (continued) 24 Gain Magnitude - dB VS = 5 V, 21 V OUT = 100 mVpp, 18 G = 2, RL = 1 kW 15 RF = 100 kW 12 RF = 10 kW RF = 10 kW CF = 1 pF RF = 100 kW CF = 1 pF 9 6 RF = 1 kW 3 0 -3 -6 -9 0 1 10 f - Frequency - MHz 100 1000 Figure 55. Frequency Response With Various Gain-Setting Resistor Values As expected, larger value gain resistors cause lower bandwidth and peaking in the response (peaking in the frequency response is synonymous with overshoot and ringing in the pulse response). Adding 1-pF capacitors in parallel with RF helps compensate the phase margin and restores flat frequency response. Figure 56 shows the test circuit. VIN RG VOUT OPA 836 1 kW RF CF Figure 56. G = 2 Test Circuit for Various Gain-Setting Resistor Values 8.3.5 Driving Capacitive Loads The OPA836 and OPA2836 devices can drive up to a nominal capacitive load of 2.2 pF on the output with no special consideration. When driving capacitive loads greater than 2.2 pF, TI recommends using a small resister (RO) in series with the output as close to the device as possible. Without RO, capacitance on the output interacts with the output impedance of the amplifier causing phase shift in the loop gain of the amplifier that will reduce the phase margin. This will cause peaking in the frequency response and overshoot and ringing in the pulse response. Interaction with other parasitic elements may lead to instability or oscillation. Inserting RO will isolate the phase shift from the feedback path and restore the phase margin; however, RO can limit the bandwidth slightly. Figure 57 shows the test circuit and Figure 43 shows the recommended values of RO versus capacitive loads, CL. See Figure 40 for the frequency response with various values. RO VIN VOUT OPA836 CL 1 kW Figure 57. RO versus CL Test Circuit Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 27 OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 www.ti.com 8.4 Device Functional Modes 8.4.1 Split-Supply Operation (1.25 V to 2.75 V) To facilitate testing with common lab equipment, the OPA836 EVM (see OPA835DBV, OPA836DBV EVM, SLOU314) is built to allow for split-supply operation. This configuration eases lab testing because the mid-point between the power rails is ground, and most signal generators, network analyzers, oscilloscopes, spectrum analyzers and other lab equipment have inputs and outputs with a ground reference. Figure 58 shows a simple noninverting configuration analogous to Figure 53 with 2.5-V supply and VREF equal to ground. The input and output will swing symmetrically around ground. For ease of use, split supplies are preferred in systems where signals swing around ground. +2.5 V VSIG RG VOUT OPA 836 Load -2.5 V RF Figure 58. Split-Supply Operation 8.4.2 Single-Supply Operation (2.5 V to 5.5 V) Often, newer systems use a single power supply to improve efficiency and reduce the cost of the power supply. The OPA836 and OPA2836 devices are designed for use with a single supply with no change in performance compared to a split supply, as long as the input and output are biased within the linear operation of the device. To change the circuit from split supply to single supply, level shift of all voltages by half the difference between the power supply rails. For example, changing from 2.5-V split supply to 5-V single supply is shown in Figure 59. 5V VSIG RG VOUT OPA 836 Load RF 2.5 V Figure 59. Single-Supply Concept A practical circuit will have an amplifier or other circuit providing the bias voltage for the input, and the output of this amplifier stage provides the bias for the next stage. Figure 60 shows a typical noninverting amplifiercircuit. With 5-V single-supply, a mid-supply reference generator is needed to bias the negative side through RG. To cancel the voltage offset that would otherwise be caused by the input bias currents, R1 is selected to be equal to RF in parallel with RG. For example, if gain of 2 is required and RF = 1 k, select RG = 1 k to set the gain and R1 = 499 for bias-current cancellation. The value for C depends on the reference; TI recommends a value of at least 0.1 F to limit noise. 28 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 OPA836, OPA2836 www.ti.com SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 Device Functional Modes (continued) Signal and bias from previous stage VSIG 2.5 V 5V R1 RO OPA 836 5V RG 2.5 V REF VOUT GVSIG 2.5 V C RF Signal and bias to next stage Figure 60. Noninverting Single Supply With Reference Figure 61 shows a similar noninverting single-supply scenario with the reference generator replaced by the Thevenin equivalent using resistors and the positive supply. RG' and RG" form a resistor divider from the 5-V supply and are used to bias the negative side with their parallel sum equal to the equivalent RG to set the gain. To cancel the voltage offset that would otherwise be caused by the input bias currents, R1 is selected to be equal to RF in parallel with RG' in parallel with RG" (R1= RF || RG' || RG"). For example, if gain of 2 is required and RF = 1 k, selecting RG' = RG" = 2 k gives equivalent parallel sum of 1 k, sets the gain to 2, and references the input to mid supply (2.5 V). R1 is then set to 499 for bias-current cancellation. The resistor divider costs less than the 2.5 V reference in Figure 60 but may increase the current from the 5-V supply. Signal and bias from previous stage VSIG 2.5 V 5V R1 5V RO OPA 836 RG' VOUT GVSIG 2.5 V RG" RF Signal and bias to next stage Figure 61. Noninverting Single Supply With Resistors Figure 62 shows a typical inverting amplifier situation. With 5-V single supply, a mid-supply reference generator is needed to bias the positive side through R1. To cancel the voltage offset that would otherwise be caused by the input bias currents, R1 is selected to be equal to RF in parallel with RG. For example if gain of -2 is required and RF = 1 k, select RG = 499 to set the gain and R1 = 332 for bias-current cancellation. The value for C is dependent on the reference, but TI recommends a value of at least 0.1 F to limit noise into the operational amplifier. Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 29 OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 www.ti.com Device Functional Modes (continued) 5V 5V R1 2.5 V REF RO VOUT OPA 836 C GVSIG 2.5 V RG Signal and bias to next stage RF VSIG 2.5 V Signal and bias from previous stage Figure 62. Inverting Single Supply With Reference Figure 63 shows a similar inverting single-supply scenario with the reference generator replaced by the Thevenin equivalent using resistors and the positive supply. R1 and R2 form a resistor divider from the 5-V supply and are used to bias the positive side. To cancel the voltage offset that would otherwise be caused by the input bias currents, set the parallel sum of R1 and R2 equal to the parallel sum of RF and RG. C must be added to limit coupling of noise into the positive input. For example if gain of -2 is required and RF = 1 k, select RG = 499 to set the gain. R1 = R2 = 665 for mid-supply voltage bias and for operational amplifier input bias-current cancellation. A good value for C is 0.1 F. The resistor divider costs less than the 2.5-V reference in Figure 62 but may increase the current from the 5-V supply. 5V 5V R1 RO R2 C OPA 836 VOUT GVSIG 2.5 V RG VSIG RF Signal and bias to next stage 2.5 V Signal and bias from previous stage Figure 63. Inverting Single Supply With Resistors 30 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 OPA836, OPA2836 www.ti.com SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Noninverting Amplifier The OPA836 and OPA2836 devices can be used as noninverting amplifiers with signal input to the noninverting input, VIN+ . A basic block diagram of the circuit is shown in Figure 53. If VIN = VREF + VSIG, then the output of the amplifier may be calculated according to Equation 1. ae RF o V = VSIG c 1 + / + VREF OUT RG o e (1) RF RG , and V The signal gain of the circuit is set by REF provides a reference around which the input and output signals swing. Output signals are in-phase with the input signals. G= 1 + The OPA836 and OPA2836 devices are designed for the nominal value of RF to be 1 k in gains other than +1. This gives excellent distortion performance, maximum bandwidth, best flatness, and best pulse response. RF = 1 k must be used as a default unless other design goals require changing to other values. All test circuits used to collect data for this data sheet had RF = 1 k for all gains other than +1. Gain of +1 is a special case where RF is shorted and RG is left open. 9.1.2 Inverting Amplifier The OPA836 and OPA2836 devices can be used as inverting amplifiers with signal input to the inverting input, VIN- , through the gain setting resistor RG. A basic block diagram of the circuit is shown in Figure 54. If VIN = VREF + VSIG, then the output of the amplifier may be calculated according to Equation 2. ae -R VOUT = VSIG c F e RG o / + VREF o (2) G= -RF RG , and V The signal gain of the circuit is set by REF provides a reference point around which the input and output signals swing. Output signals are 180 out-of-phase with the input signals. The nominal value of RF must be 1 k for inverting gains. 9.1.3 Instrumentation Amplifier Figure 64 is an instrumentation amplifier that combines the high input impedance of the differential-to-differential amplifier circuit and the common-mode rejection of the differential-to-single-ended amplifier circuit. This circuit is often used in applications where high input impedance is required (such as taps from a differential line) or in cases where the signal source has a high output impedance. If VIN+ = VCM + VSIG+ and VIN- = VCM + VSIG- , then the output of the amplifier may be calculated according to Equation 3. VOUT = (VIN+ - VIN- ) ae 2RF1 o ae RF2 o c1 + / c / + VREF RG1 o e RG2 o e (3) Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 31 OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 www.ti.com Application Information (continued) ae 2R F1 o ae R F2 o G = c1 + / c / R G 1 o e R G2 o e The signal gain of the circuit is set by . VCM is rejected, and VREF provides a level shift around which the output signal swings. The single-ended output signal is in-phase with the differential input signal. VIN1/2 OPA2836 VSIG- RF2 VCM RG2 RF1 RG1 RG2 VOUT OPA 836 RF1 G[(VSIG+)-(VSIG-)] VSIG+ RF2 VCM 1/2 OPA2836 VREF VREF VIN+ Figure 64. Instrumentation Amplifier Integrated solutions are available, but the OPA836 device provides a much lower-power, high-frequency solution. For best CMRR performance, resistors must be matched. A good guideline to follow is CMRR the resistor tolerance; so, 0.1% tolerance will provide approximately 60-dB CMRR. 9.1.4 Attenuators The noninverting circuit of Figure 53 has minimum gain of 1. To implement attenuation, a resistor divider can be placed in series with the positive input, and the amplifier set for gain of 1 by shorting VOUT to VIN- and removing RG. Because the operational amplifier input is high impedance, the resistor divider sets the attenuation. The inverting circuit of Figure 54 can be used as an attenuator by making RG larger than RF. The attenuation is the resistor ratio. For example, a 10:1 attenuator can be implemented with RF = 1 k and RG = 10 k. 9.1.5 Single-Ended-to-Differential Amplifier Figure 65 shows an amplifier circuit that is used to convert single-ended signals to differential, and provides gain and level shifting. This circuit can be used for converting signals to differential in applications like line drivers for Cat5 cabling or driving differential-input SAR and ADCs. With VIN = VREF + VSIG , the output of the amplifier may be calculated according to Equation 4. VOUT+ = G x VIN + VREF and VOUT- = -G x VIN + VREF Where: G = 1 + RF RG (4) The differential-signal gain of the circuit is 2 x G, and VREF provides a reference around which the output signal swings. The differential output signal is in-phase with the single-ended input signal. G x V SIG RO VOUT+ VREF VSIG VREF R1 VIN 1/2 OPA2836 + 2R 2R VREF VREF -G x V SIG RO VOUT+ RG RF VREF 1/2 OPA2836 R Figure 65. Single Ended to Differential Amplifier 32 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 OPA836, OPA2836 www.ti.com SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 Application Information (continued) Line termination on the output can be accomplished with resistors RO. The differential impedance seen from the line will be 2 x RO. For example, if 100- Cat5 cable is used with double termination, the amplifier is typically set for a differential gain of 2 V/V (6 dB) with RF = 0 (short), RG = open, 2R = 1 k, R1 = 0 , R = 499 to balance the input bias currents, and RO = 49.9 for output line termination. This configuration is shown in Figure 66. For driving a differential-input ADC the situation is similar, but the output resistors, RO are selected with a capacitor across the ADC input for optimum filtering and settling-time performance. VSIG 49.9 VOUT+ VREF VSIG VREF RG 1 k 1/2 OPA2836 VIN + RF 1 k VREF -VSIG 49.9 VOUT- VREF 1/2 OPA2836 + 499 Figure 66. Cat5 Line Driver With Gain = 2 V/V (6 dB) 9.1.6 Differential-to-Signal-Ended Amplifier Figure 67 shows a differential amplifier that is used to convert differential signals to single-ended and provides gain (or attenuation) and level shifting. This circuit can be used in applications like a line receiver for converting a differential signal from a Cat5 cable to a single-ended signal. If VIN+ = VCM + VSIG+ and VIN- = VCM + VSIG- , then the output of the amplifier may be calculated according to Equation 5. aeR o VOUT = (VIN+ - VIN - ) c F / + VREF e RG o (5) G= RF RG , V The signal gain of the circuit is CM is rejected, and VREF provides a level shift around which the output signal swings. The single ended output signal is in-phase with the differential input signal. VSIG- RF VCM VINVIN+ VSIG+ VCM RG VOUT OPA836 RG G[(VSIG+)-(VSIG-)] RF VREF VREF Figure 67. Differential to Single-Ended Amplifier Line termination can be accomplished by adding a shunt resistor across the VIN+ and VIN- inputs. The differential impedance is the shunt resistance in parallel with the input impedance of the amplifier circuit, which is usually much higher. For low gain and low line impedance, the resistor value to add is approximately the impedance of the line. For example if 100- Cat5 cable is used with a gain of 1 amplifier and RF = RG = 1 k, adding a 100- shunt across the input will give a differential impedance of 98 , which is adequate for most applications. Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 33 OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 www.ti.com Application Information (continued) For best CMRR performance, resistors must be matched. Assuming CMRR the resistor tolerance, a 0.1% tolerance will provide about 60-dB CMRR. 9.1.7 Differential-to-Differential Amplifier Figure 68 shows a differential amplifier that is used to amplify differential signals. This circuit has high input impedance and is used in differential line driver applications where the signal source is a high-impedance driver (for example, a differential DAC) that must drive a line. If VIN = VCM + VSIG , then the output of the amplifier may be calculated according to Equation 6. ae 2RF o V = VIN c 1 + / + VCM OUT RG o e G= 1 + (6) 2RF RG , and V passes with unity gain. The amplifier in essence The signal gain of the circuit is set by CM combines two noninverting amplifiers into one differential amplifier that shares the RG resistor, which makes RG effectively half its value when calculating the gain. The output signals are in-phase with the input signals. VIN1/2 OPA2836 VSIG- VOUTGVSIGVCM VCM RF RG RF VSIG+ GVSIG+ VCM VCM 1/2 OPA2836 VOUT+ VIN+ Figure 68. Differential to Differential Amplifier 9.1.8 Gain Setting With OPA836 RUN Integrated Resistors The OPA836 RUN package option includes integrated gain-setting resistors for smallest possible footprint on a printed circuit board ( 2.00 mm x 2.00 mm). By adding circuit traces on the PCB, gains of +1, -1, -1.33, +2, +2.33, -3, +4, -4, +5, -5.33, +6.33, -7, +8 and inverting attenuations of -0.1429, -0.1875, -0.25, -0.33, -0.75 can be achieved. Figure 69 shows a simplified view of how the OPA836IRUN integrated gain-setting network is implemented. Table 3 lists the required pin connections for various noninverting and inverting gains (reference Figure 53 and Figure 54). Table 4 shows the required pin connections for various attenuations using the inverting-amplifier architecture (reference Figure 54). Due to ESD protection devices being used on all pins, the absolute maximum and minimum input-voltage range, VS- - 0.7 V to VS+ + 0.7 V, applies to the gain-setting resistors, so attenuation of large input voltages requires external resistors to implement. The gain-setting resistors are laser trimmed to 1% tolerance with nominal values of 1.6 k, 1.2 k, and 400 . The gain-setting resistors have excellent temperature coefficients, and gain drift is superior to the drift with external gain-setting resistors. The 500- and 1.5-pF capacitor in parallel with the 1.6-k gain-setting resistor provide compensation for best stability and pulse response. 34 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 OPA836, OPA2836 www.ti.com SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 Application Information (continued) FB1 FB2 FB3 9 8 7 1.6 k 500 1.2 k FB4 6 400 1.5 pF Figure 69. OPA836IRUN Gain-Setting Network Table 3. Gain Settings NONINVERTING GAIN (Figure 53) INVERTING GAIN (Figure 54) SHORT PINS 1 V/V (0 dB) -- 1 to 9 SHORT PINS SHORT PINS SHORT PINS -- 2 V/V (6.02 dB) -1 V/V (0 dB) 1 to 9 2 to 8 6 to GND -- 2.33 V/V (7.36 dB) -1.33 V/V (2.5 dB) 1 to 9 2 to 8 7 to GND -- 4 V/V (12.04 dB) -3 V/V (9.54 dB) 1 to 8 2 to 7 6 to GND -- 5 V/V (13.98 dB) -4 V/V (12.04 dB) 1 to 9 2 to 7 or 8 7 to 8 6 to GND 6.33 V/V (16.03 dB) -5.33 V/V (14.54 dB) 1 to 9 2 to 6 or 8 6 to 8 7 to GND 8 V/V (18.06 dB) -7 V/V (16.90 dB) 1 to 9 2 to 7 6 to GND -- Table 4. Attenuator Settings INVERTING GAIN (Figure 54) SHORT PINS SHORT PINS SHORT PINS SHORT PINS -0.75 V/V (-2.5 dB) 1 to 7 2 to 8 9 to GND -- -0.333 V/V (-9.54 dB) 1 to 6 2 to 7 8 to GND -- -0.25 V/V (-12.04 dB) 1 to 6 2 to 7 or 8 7 to 8 9 to GND -0.1875 V/V (-14.54 dB) 1 to 7 2 to 6 or 8 6 to 8 9 to GND -0.1429 V/V (-16.90 dB) 1 to 6 2 to 7 9 to GND -- 9.1.9 Pulse Application With Single-Supply For pulsed applications, where the signal is at ground and pulses to a positive or negative voltage, the circuit bias-voltage considerations differ from those in an application with a signal that swings symmetrical about a reference point. Figure 70 shows a circuit where the signal is at ground (0 V) and pulses to a positive value. Signal and bias from previous stage VSIG 0V 5V R1 RO VOUT OPA836 GVSIG RG 0V RF Signal and bias to next stage Figure 70. Noninverting Single Supply With Pulse Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 35 OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 www.ti.com If the input signal pulses negative from ground, an inverting amplifier is more appropriate as shown in Figure 71. A key consideration in noninverting and inverting cases is that the input and output voltages are kept within the limits of the amplifier. Because the VICR of the OPA836 device includes the negative supply rail, the OPA836 operational amplifier is well-suited to this application. 5V R1 OPA 836 RO VOUT GVSIG RG Signal and bias from previous stage 0V VSIG 0V RF Signal and bias to next stage Figure 71. Inverting Single Supply With Pulse 9.1.10 ADC Driver Performance The OPA836 device provides excellent performance when driving high-performance delta-sigma () and successive-approximation-register (SAR) ADCs in low-power audio and industrial applications. To show achievable performance, the OPA836 device is tested as the drive amplifier for the ADS8326. The ADS8326 is a 16-bit, micro power, SAR ADC with pseudodifferential inputs and sample rates up to 250 kSPS. The device offers excellent noise and distortion performance in a small 8-pin SOIC or VSSOP (MSOP) package. Low power and small size make the ADS8326 and OPA836 devices an ideal solution for portable and batteryoperated systems, remote data-acquisition modules, simultaneous multichannel systems, and isolated data acquisition. With the circuit shown in Figure 72 to test the performance, Figure 73 shows the FFT plot with a 10-kHz input signal . The tabulated AC analysis is in Table 5. 2.7 V VSIG VSIG 0V 2.7V 2k 1k 1.35 V 5V VS+ VIN 2.5 V 100 OPA836 2k VS- 2.2 nF +In VDD REF ADS 8326 -In 1k 1k Figure 72. OPA836 and ADS8326 Test Circuit 36 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 OPA836, OPA2836 www.ti.com SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 0 -20 AIN - dBc -40 -60 -80 -100 -120 -140 0 20 40 60 80 f - Frequency - Hz 100 120 Figure 73. ADS8326 and OPA836 10-kHz FFT Table 5. AC Analysis TONE (Hz) SIGNAL (dBFS) SNR (dBc) THD (dBc) SINAD (dBc) SFDR (dBc) 10k -0.85 83.3 -86.6 81.65 88.9 9.2 Typical Applications 9.2.1 Audio Frequency Performance The OPA836 and OPA2836 devices provide excellent audio performance with low quiescent power. To show performance in the audio band, an audio analyzer from Audio Precision (2700 series) tests THD+N and FFT at 1 VRMS output voltage. Figure 74 shows the circuit used for the audio-frequency performance test. VIN From AP +2.5 V VOUT To AP 100 pF OPA 836 10 W -2.5 V The 100-pF capacitor to ground on the input helped to decouple noise pick up in the lab and improved noise performance. Figure 74. OPA836 Audio Precision Analyzer Test Circuit Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 37 OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 www.ti.com Typical Applications (continued) 9.2.1.1 Design Requirements Design a low distortion, single-ended input to single-ended output audio amplifier using the OPA836 device. The 2700-series audio analyzer from Audio Precision is used as the signal source and also as the measurement system. Table 6. Design Requirements CONFIGURATION INPUT EXCITATION PERFORMANCE TARGET RLoad OPA836 Unity Gain Config. 1 KHz Tone Frequency >110 dBc SFDR 300 and 100 k 9.2.1.2 Detailed Design Procedure The OPA836 device is tested in this application in a unity-gain buffer configuration. A buffer configuration is selected for maximum loop gain of the amplifier circuit. At higher closed-loop gains, the loop gain of the circuit reduces, which increases the harmonic distortion. The relationship between distortion and closed-loop gain at a fixed input frequency is shown in Figure 36 in Typical Performance Graphs: VS = 5 V. The test was performed under using resistive loads of 300 and 100 K. Figure 34 shows the distortion performance of the amplifier versus the resistive load. Output loading, output swing, and closed-loop gain play a key role in determining the distortion performance of the amplifier. NOTE The 100-pF capacitor to ground on the input helped to decouple noise pickup in the lab and improved noise performance. The Audio Precision was configured as a single-ended output in this application circuit. In applications where a differential output is available, the OPA836 device can be configured as a differential-to-single-ended amplifier as shown in Figure 67. Power-supply bypassing is critical to reject noise from the power supplies. A 2.2-F supply decoupling capacitor must be placed within 2 inches of the device and can be shared with other operational amplifiers on the same board. A 0.1-F supply decoupling capacitor must be placed as close to the supply pins as possible, preferably within 0.1 inch. For a split supply, a capacitor is required for both supplies. A 0.1-F capacitor placed directly between the supplies is also beneficial for improving system noise performance. If the output load is heavy, such as 16 to 32 , performance of the amplifier could begin to degrade. To drive such heavy loads, both channels of the OPA2836 device can be paralleled with their outputs isolated with 1- resistors to reduce the loading effects. 38 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 OPA836, OPA2836 www.ti.com SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 9.2.1.3 Application Curves Figure 75 shows the THD+N performance with 100-k and 300- loads, and with A-weighting and with no weighting. Both loads show similar performance. With no weighting, the THD+N performance is dominated by the noise for both loads. A-weighting provides filtering that improves the noise, revealing the increased distortion with RL = 300 . Figure 76 and Figure 77 show the FFT output with a 1-kHz tone and 100-k and 300- loads. To show relative performance of the device versus the test set, one channel has the OPA836 device in-line between the generator output and the analyzer. The other channel is in "Gen Mon" loopback mode, which internally connects the signal generator to the analyzer input. With 100-k load, Figure 76, the curves are indistinguishable from each other except for noise, which means the OPA836 device cannot be directly measured. With 300- load, as shown in Figure 77, the main difference between the curves is that the OPA836 device shows slightly higher even-order harmonics, but the performance of the test set masks the odd-order harmonics. 0 VS = 5 V, VOUT = 1 VRMS, G = 1, RF = 0 W, BW = 80 kHz -95 -100 No weighting RL = 300 W, VS = 5 V, VOUT = 1 VRMS, G = 1, RF = 0 W -10 -20 -30 -40 FFT - dBV THD+N - Total Harmonic Distortion + Noise - dBv -90 RL = 100 kW -105 -50 -60 -70 -80 -110 A-weighting RL = 300 W, -90 -100 RL = 100 kW Gen Mon - 100k -110 -115 -120 RL = 100k -130 -120 10 -140 100 1k f - Frequency - Hz 10k 100k Figure 75. OPA836 1 VRMS 20-Hz to 80-kHz THD+N 0 2k 4k 6k 8k 10k 12k f - Frequency - Hz 14 16k 18k 20k Figure 76. OPA836 and AP Gen Mon 10-kHz FFT Plot; VOUT = 1 VRMS, RL = 100 k 0 VS = 5 V, VOUT = 1 VRMS, G = 1, RF = 0 W -10 -20 -30 -40 FFT - dBV -50 -60 -70 -80 -90 Gen Mon - 300 -100 -110 RL = 300 -120 -130 -140 0 2k 4k 6k 8k 10k 12k f - Frequency - Hz 14 16k 18k 20k Figure 77. OPA836 and AP Gen Mon 10-kHz FFT Plot; VOUT = 1 VRMS, RL = 300 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 39 OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 www.ti.com 9.2.2 Active Filters The OPA836 and OPA2836 devices are good choices for active filters. Figure 78 and Figure 79 show MFB and Sallen-Key circuits designed using the WEBENCH(R) Filter Designer to implement second-order low-pass Butterworth filter circuits. Figure 80 shows the frequency response. Other MFB and Sallen-Key filter circuits offer similar performance. The main difference is the MFB is an inverting amplifier in the pass-band and the Sallen-Key is noninverting. The primary advantage for each is the Sallen-Key in unity gain has no resistor gain-error term, and thus no sensitivity to gain error, while the MFB has better attenuation properties beyond the bandwidth of the operational amplifier. 1.24 kW 330 pF 1.24 kW 2.80 kW OPA 836 2.2 nF Figure 78. MFB 100-kHz Second-Order Low-Pass Butterworth Filter Circuit 2.2 nF 562 W 6.19 kW 330 pF OPA836 Figure 79. Sallen-Key 100-kHz Second-Order Low-Pass Butterworth Filter Circuit 9.2.2.1 Application Curve VS = 5 V, VOUT = 100 mVpp Gain Magnitude - dB 0 MFB -10 -20 Sallen-Key -30 -40 1k 10k 100k 1M f - Frequency - Hz Figure 80. MFB and Sallen-Key Second Order Low-Pass Butterworth Filter Response 40 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 OPA836, OPA2836 www.ti.com SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 10 Power Supply Recommendations The OPAx836 devices are intended to work in a supply range of 2.7 V to 5 V. Supply-voltage tolerances are supported with the specified operating range of 2.5 V (7% on a 2.7-V supply) and 5.5 V (10% on a 5-V supply). Good power-supply bypassing is required. Minimize the distance (< 0.1 inch) from the power-supply pins to high frequency, 0.1-F decoupling capacitors. A larger capacitor (2.2 F is typical) is used along with a high frequency, 0.1-F supply decoupling capacitor at the device supply pins. For single-supply operation, only the positive supply has these capacitors. When a split supply is used, use these capacitors for each supply to ground. If necessary, place the larger capacitors farther from the device and share these capacitors among several devices in the same area of the PCB. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) reduces second harmonic distortion. 11 Layout 11.1 Layout Guidelines The OPA835DBV, OPA836DBV EVM (SLOU314) can be used as a reference when designing the circuit board. TI recommends following the EVM layout of the external components near the amplifier, ground-plane construction, and power routing. General guidelines are listed as follows: 1. Signal routing must be direct and as short as possible into and out of the operational amplifier. 2. The feedback path must be short and direct avoiding vias if possible especially with G = +1. 3. Ground or power planes must be removed from directly under the negative input and output pins of the amplifier. 4. TI recommends placing a series output resistor as close to the output pin as possible. See Series Output Resistor vs Capacitive Load (Figure 17) for recommended values for the expected capacitive load. 5. A 2.2-F power-supply decoupling capacitor must be placed within two inches of the device and can be shared with other operational amplifiers. For spit supply, a capacitor is required for both supplies. 6. A 0.1-F power-supply decoupling capacitor must be placed as close to the power supply pins as possible, preferably within 0.1 inch. For split supply, a capacitor is required for both supplies. 7. The PD pin uses TTL logic levels. If the pin is not used, it must be tied to the positive supply to enable the amplifier. If the pin is used, it must be actively driven. A bypass capacitor is not necessary, but is used for robustness in noisy environments. Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 41 OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 www.ti.com 11.2 Layout Example Figure 81. Top Layer Figure 82. Bottom Layer 42 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 OPA836, OPA2836 www.ti.com SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 12 Device and Documentation Support 12.1 Device Support 12.1.1 Development Support WEBENCH(R) Filter Designer 12.1.2 Related Documentation For related documentation see the following: OPA835DBV, OPA836DBV EVM (SLOU314). 12.2 Related Links Table 7 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 7. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY OPA836 Click here Click here Click here Click here Click here OPA2836 Click here Click here Click here Click here Click here 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.5 Trademarks E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.7 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 43 OPA836, OPA2836 SLOS712I - JANUARY 2011 - REVISED OCTOBER 2016 www.ti.com 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 44 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: OPA836 OPA2836 PACKAGE OPTION ADDENDUM www.ti.com 4-Dec-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) OPA2836ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2836 OPA2836IDGS ACTIVE VSSOP DGS 10 80 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 2836 OPA2836IDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 2836 OPA2836IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2836 OPA2836IRMCR ACTIVE UQFN RMC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2836 OPA2836IRMCT ACTIVE UQFN RMC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2836 OPA2836IRUNR ACTIVE QFN RUN 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2836 OPA2836IRUNT ACTIVE QFN RUN 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2836 OPA836IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 QTL OPA836IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 QTL OPA836IRUNR ACTIVE QFN RUN 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 836 OPA836IRUNT ACTIVE QFN RUN 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 836 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 4-Dec-2017 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF OPA2836 : * Automotive: OPA2836-Q1 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 30-Mar-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device OPA2836IDGSR Package Package Pins Type Drawing VSSOP DGS SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA2836IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA2836IRMCR UQFN RMC 10 3000 180.0 9.5 2.3 2.3 1.1 2.0 8.0 Q2 OPA2836IRMCT UQFN RMC 10 250 180.0 9.5 2.3 2.3 1.1 2.0 8.0 Q2 OPA2836IRUNR QFN RUN 10 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 OPA2836IRUNT QFN RUN 10 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 OPA836IDBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 OPA836IDBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 OPA836IRUNR QFN RUN 10 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 OPA836IRUNT QFN RUN 10 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Mar-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA2836IDGSR VSSOP DGS 10 2500 366.0 364.0 50.0 OPA2836IDR SOIC D 8 2500 340.5 338.1 20.6 OPA2836IRMCR UQFN RMC 10 3000 205.0 200.0 30.0 OPA2836IRMCT UQFN RMC 10 250 205.0 200.0 30.0 OPA2836IRUNR QFN RUN 10 3000 210.0 185.0 35.0 OPA2836IRUNT QFN RUN 10 250 210.0 185.0 35.0 OPA836IDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 OPA836IDBVT SOT-23 DBV 6 250 180.0 180.0 18.0 OPA836IRUNR QFN RUN 10 3000 210.0 185.0 35.0 OPA836IRUNT QFN RUN 10 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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