HLX6228 HLX6228 128K x 8 STATIC RAM--Low Power SOI The 128K x 8 Radiation Hardened Static RAM is a high performance 131,072 word x 8-bit static random access memory with industry-standard functionality. It is fabricated with Honeywell's radiation hardened technology, and is designed for use in low voltage systems operating in radiation environments. The RAM operates over the full military temperature range and requires only a single 3.3 V 0.3V power supply. The RAM is compatible with JEDEC standard low voltage CMOS I/O. Power consumption is typically less than 9 mW/MHz in operation, and less than 2 mW when deselected. The RAM read operation is fully asynchronous, with an associated typical access time of 32 ns at 3.3 V. Honeywell's enhanced SOI RICMOSTMIV (Radiation Insensitive CMOS) technology is radiation hardened through the use of advanced and proprietary design, layout and process hardening techniques. The RICMOSTM IV low power process is a SIMOX CMOS technology with a 150 A gate oxide and a minimum drawn feature size of 0.7 m (0.55 m effective gate length--Leff). Additional features include tungsten via plugs, Honeywell's proprietary SHARP planarization process and a lightly doped drain (LDD) structure for improved short channel reliability. A 7 transistor (7T) memory cell is used for superior single event upset hardening, while three layer metal power bussing and the low collection volume SIMOX substrate provide improved dose rate hardening. FEATURES RADIATION * Fabricated with RICMOSTM IV Silicon on Insulator (SOI) 0.7 m (Leff = 0.55 m) OTHER * Read/Write Cycle Times o 32 ns (-55 to 125C) * Total Dose Hardness through 1x10 rad(SiO2) * Typical Operating Power <9 mW/MHz * Neutron Hardness through 1x10 * * JEDEC Standard Low Voltage CMOS Compatible I/O Dynamic and Static Transient Upset Hardness 9 through 1x10 rad(Si)/s * Single 3.3 V 0.3 V Power Supply * Asynchronous Operation * Packaging Options o 32-Lead Flat Pack (0.820 in. x 0.600 in.) o 40-Lead Flat Pack (0.775 in. x 0.710 in.) 6 14 cm- 2 * Dose Rate Survivability through <1x10 rad(Si)/s * Soft Error Rate of <1x10 Geosynchronous Orbit * No Latchup 11 www.honeywell.com -10 upsets/bit-day in 1 HLX6228 FUNCTIONAL DIAGRAM SIGNAL DEFINITIONS A: 0-16 Address input pins which select a particular eight-bit word within the memory array. DQ: 0-7 Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write operation. NCS Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all input buffers except CE. This part must be Read and Write controlled using the NCS pin: it requires that NCS returns to a high state for at least 5ns whenever there is an address change. This 5ns pulse to high provides the part with a defined pre-charge pulse duration to ensure that the new address is latched. The part must be controlled in this fashion to meet the timing specifications defined. NWE Negative write enable, when at a low level activates a write operation and holds the data output drivers in a high impedance state. When at a high level NWE allows normal read operation. NOE Negative output enable, when at a high level holds the data output drivers in a high impedance state. When at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must be connected to VSS. CE Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers except the NCS input buffer. If this signal is not used it must be connected to VDD. TRUTH TABLE 2 NCS CE NWE NOE MODE DQ L H H L Read Data Out L H L X Write Data In H X XX XX Deselected High Z X L XX XX Disabled High Z Notes: X: VI=VIH or VIL XX: VSSVIVDD NOE=H: High Z output state maintained for NCS=X, CE=X, NWE=X www.honeywell.com HLX6228 RADIATION CHARACTERISTICS Total Ionizing Radiation Dose The SRAM will meet all stated functional and electrical specifications over the entire operating temperature range after the specified total ionizing radiation dose. All electrical and timing performance parameters will remain within specifications after rebound at VDD = 3.6 V and T =125C extrapolated to ten years of operation. Total dose hardness is assured by wafer level testing of process monitor transistors and RAM product using 10 KeV X-ray and Co60 radiation sources. Transistor gate threshold shift correlations have been made between 10 5 KeV X-rays applied at a dose rate of 1x10 rad(Si)/min at T = 25C and gamma rays (Cobalt 60 source) to ensure that wafer level X-ray testing is consistent with standard military radiation test environments. The SRAM will meet any functional or electrical specification after exposure to a radiation pulse up to the transient dose rate survivability specification, when applied under recommended operating conditions. Note that the current conducted during the pulse by the RAM inputs, outputs, and power supply may significantly exceed the normal operating levels. The application design must accommodate these effects. Neutron Radiation The SRAM will meet any functional or timing specification after exposure to the specified neutron fluence under recommended operating or storage conditions. This assumes equivalent neutron energy of 1 MeV. Soft Error Rate Transient Pulse Ionizing Radiation The SRAM is capable of writing, reading, and retaining stored data during and after exposure to a transient ionizing radiation pulse, up to the specified transient dose rate upset specification, when applied under recommended operating conditions. To ensure validity of all specified performance parameters before, during, and after radiation (timing degradation during transient pulse radiation (timing degradation during transient pulse radiation is 10%), it is suggested that stiffening capacitance be placed on or near the package VDD and VSS, with a maximum inductance between the package (chip) and stiffening capacitance of 0.7 nH per part. If there are no operate-through or valid stored data requirements, typical circuit board mounted de-coupling capacitors are recommended. The SRAM is capable of meeting the specified Soft Error Rate (SER), under recommended operating conditions. This hardness level is defined by the Adams 90% worst case cosmic ray environment for geosynchronous orbits. Latchup The SRAM will not latch up due to any of the above radiation exposure conditions when applied under recommended operating conditions. Fabrication with the SIMOX substrate material provides oxide isolation between adjacent PMOS and NMOS transistors and eliminates any potential SCR latchup structures. Sufficient transistor body tie connections to the p- and nchannel substrates are made to ensure no source/drain snapback occurs. RADIATION HARDNESS RATINGS (1) Parameter Limits (2) Units Total Dose 1x10 rad(Si) Transient Dose Rate Upset 9 1x10 rad(Si)/s Pulse width 20ns, X-ray, TA = 125 C Transient Dose Rate Survivability 1x10 11 rad(Si)/s Pulse width 20 ns, X-ray, TA=25C -10 upsets/bit-day 6 Soft Error Rate (SER) <1x10 Neutron Fluence 1x10 14 N/cm 2 Test Conditions TA=25C, O TA=25C, Adams 90% worst case environment 1 MeV equivalent energy, Unbiased, TA=25C (1) Device will not latch up due to any of the specified radiation exposure conditions. (2) Specifications apply to operating conditions (unless otherwise specified) of: VDD=3.0 V to 3.6 V, TA=-55C to 125C. www.honeywell.com 3 HLX6228 ABSOLUTE MAXIMUM RATINGS (1) Rating Symbol VDD VPIN TSTORE TSOLDER PD IOUT VPROT Parameter Supply Voltage Range (2) Voltage on Any Pin (2) Storage Temperature (Zero Bias) Soldering Temperature (5 seconds) Maximum Package Power Dissipation (3) DC or Average Output Current ESD Input Protection Voltage (4) JC Thermal Resistance (Jct-toCase) TJ Junction Temperature Min -0.5 -0.5 -65 Max 6.5 VDD +0.5 150 270 2.5 25 2000 32 FP 40 FP 2 2 175 Units V V C C W mA V C / W C / W C (1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability. (2) Voltage referenced to VSS. (3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this specification. (4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab. RECOMMENDED OPERATING CONDITIONS Symbol VDD Parameter Supply Voltage (referenced to VSS) Min 3.0 Description Typ 3.3 Max 3.6 Units V TA Ambient Temperature -55 25 125 C VPIN VDD Ramp Time Voltage on Any Pin (referenced to VSS) -0.3 VDD+0.3 V 50 ms Supply Voltage Ramp Time CAPACITANCE (1) Symbol CI Parameter Input Capacitance CO Output Capacitance Typical Worst Case Min Max 7 Units pF Test Conditions VI=VDD or VSS, f=1 MHz 9 pF VIO=VDD or VSS, f=1 MHz (1) This parameter is tested during initial design characterization only. DATA RETENTION CHARACTERISTICS Symbol Parameter VDR Data Retention Voltage IDR Data Retention Current Typical (1) Worst Case (2) Min Max Units 2.5 700 Test Conditions V NCS=VDR, VI=VDR or VSS A NCS=VDD=VDR, VI=VDD or VSS (1) Typical operating conditions: TA= 25C, pre-radiation. (2) Worst case operating conditions: TA= -55C to +125C, post total dose at 25C. 4 www.honeywell.com HLX6228 DC ELECTRICAL CHARACTERISTICS Symbol Parameter Typical (1) Worst Case (2) Min Max Units Test Conditions IDDSB1 Static Supply Current 700 A VIH=VDD, IO=0 VIL=VSS, Inputs Stable IDDSBMF Standby Supply Current - Deselected 700 A NCS=VDD, CE=VSS, IO=0, f=40 MHZ 3.2 mA f=1 MHz, IO=0, CE=VIH=VDD NCS=VIL=VSS (3) 2.2 mA F=1 MHz, IO=0, CE=VIH=VDD NCS=VIL=VSS (3) IDDOPW IDDOPR Dynamic Supply Current - Selected (Write) Dynamic Supply Current - Selected (Read) II Input Leakage Current -5 5 A VSS <VI <VDD IOZ Output Leakage Current -10 10 A VSS <VI<VDD, Output = high Z VIL Low-Level Input Voltage 0.27xVDD V March Pattern, VDD = 3.0V VIH High-Level Input Voltage V March Pattern, VDD = 3.6V VOL Low-Level Output Voltage V VDD=3.0V, IOL = 8 mA VOH High-Level Output Voltage V VDD=3.0V, IOL = -4 mA .725xVDD 0.4 2.7 (1) Typical operating conditions: VDD=3.3 V, TA=25C, pre-radiation. (2) Worst case operating conditions: VDD=3.0 V to 3.6 V, -55C to +125C, post total dose at 25C. (3) All inputs switching. DC average current. SIGNAL INTEGRITY AND SIGNAL CONNECTIONS It is important that input signal transitions (between VIL and VIH levels) that produce asynchronous behavior (i.e., Address, Read/Write, Chip Select/Enable) have good signal integrity (free of noise, glitches, ringing or discontinuities from impedance mismatch reflections or driver changes) and have rising and falling edges of 10ns. Input signal transitions with poor signal integrity, slow state changes (>10ns) or where the driver changes between VIL and VIH levels, when the chip is enabled and selected, can interfere with intended read or write operations. Note: Some examples of "driver change" include changing from a floating or weakly driven (e.g., weak pull-up or pull-down) input state to an active driver defined input state or changing between devices driving the signal input. In addition, input signals should not be left floating unless the chip is disabled or deselected. TESTER EQUIVALENT LOAD CIRCUIT www.honeywell.com 5 HLX6228 READ CYCLE AC TIMING CHARACTERISTICS (1, 2) Worst Case (3) Symbol Parameter Typical (2) -55 to 125 C Min Max 32 Units TAVAVR Address Read Cycle Time ns TAVQV Address Access Time TAXQX Address Change to Output Invalid Time TSLQV Chip Select Access Time TSLQX Chip Select Output Enable Time TSHQZ Chip Select Output Disable Time 10 ns TEHQV Chip Enable Access Time 35 ns TEHQX Chip Enable Output Enable Time TELQZ Chip Enable Output Disable Time 13 ns TGLQV Output Enable Access Time 12 ns TGLQX Output Enable Output Enable Time TGHQZ Output Enable Output Disable Time 32 3 ns ns 35 5 ns ns 5 ns 0 ns 9 ns (1) Key Note: This part must be Read controlled using the NCS pin: it requires that NCS returns to a high state for at least 5ns whenever there is an address change. This 5ns pulse to high provides the part with a defined pre-charge pulse duration to ensure that the new address is latched. The part must be controlled in this fashion to meet the timing specifications defined. (2) Test conditions: Control inputs driven with logic level signals, input and output timing reference levels shown in the Tester AC Timing Characteristics table and Tester Load Circuit Diagram. (3) Typical operating conditions: VDD=3.3 V, TA=25C, pre-radiation. (4) Worst case operating conditions: VDD=3.0 V to 3.6 V, TA= -55C to 125C, post total dose at 25C. 6 www.honeywell.com HLX6228 WRITE CYCLE AC TIMING CHARACTERISTICS (1, 2) Worst Case (4) Symbol Parameter Typical (3) -55 to 125 C Min Max Units TAVAVW Write Cycle Time (5) 30 ns TWLWH Write Enable Write Pulse Width 25 ns TSLWH Chip Select to End of Write Time 25 ns TDVWH Data Valid to End of Write Time 20 ns TAVWH Address Valid to End of Write Time 25 ns TWHDX Data Hold Time after End of Write Time 0 ns TAVWL Address Valid Setup to Start of Write Time 0 ns TWHAX Address Valid Hold after End of Write Time 0 ns TWLQZ Write Enable to Output Disable Time 0 TWHQX Write Disable to Output Enable Time 5 ns TWHWL Write Disable to Write Enable Pulse Width (6) 5 ns TEHWH Chip Enable to End of Write Time 25 ns 12 ns (1) Key Note: This part must be Write controlled using the NCS pin: it requires that NCS returns to a high state for at least 5ns whenever there is an address change. This 5ns pulse to high provides the part with a defined pre-charge pulse duration to ensure that the new address is latched. The part must be controlled in this fashion to meet the timing specifications defined. (2) Test conditions: Control inputs driven with logic level signals, input and output timing reference levels shown in the Tester AC Timing Characteristics table and Tester Load Circuit Diagram. (3) Typical operating conditions: VDD=3.3 V, TA=25C, pre-radiation. (4) Worst case operating conditions: VDD=3.0 V to 3.6 V, -55 to 125C, post total dose at 25C. (5) TAVAVW = TWLWH + TWHWL (6) Guaranteed but not tested. www.honeywell.com 7 HLX6228 DYNAMIC ELECTRICAL CHARACTERISTICS Read Cycle The RAM is asynchronous in operation, allowing the read cycle to be controlled only by chip select (NCS) (refer to Read Cycle timing diagram). To perform a valid read operation, both chip select and output enable (NOE) must be low and chip enable and write enable (NWE) must be high. The output drivers can be controlled independently by the NOE signal. To control a read cycle with NCS, all addresses and CE must be valid prior to or coincident with the enabling NCS edge transition delayed. Read control with NCS requires that NCS returns to a high state for at least 5ns whenever there is an address change. This 5ns pulse to high provides the part with a defined pre-charge pulse duration to ensure that the new address is latched. The device must be controlled in this fashion to meet the timing specifications herein. The data output will not become valid until TSLQV time following return of NCS to a low state. Data outputs will enter a high impedance state TSHQZ time following a disabling NCS edge transition. Write Cycle The write operation is synchronous with respect to the address bits, and control is governed by only chip select (NCS) (refer to Write Cycle timing diagrams). To perform a write operation, both NWE and NCS must be low, and CE must be high. This part must be Write controlled using the NCS pin; it requires that NCS returns to a high state for at least 5ns whenever there is an address change. This 5ns pulse to high provides the part with a defined pre-charge pulse duration to ensure that the new address is latched. The part must be controlled in this fashion to meet the timing specifications defined. Both CE and NCS fully disable the RAM decode logic and input buffers for power savings. To write data into the RAM, NWE and NCS must be held low and CE must be held high for at least TWLWH/TSLSH/TEHEL time. Any amount of edge skew between the signals can be tolerated, and any one of the control signals can initiate or terminate the write operation. For consecutive write operations, write pulses must be separated by the minimum specified TWHWL/TSHSL/TELEH time. Address inputs must be valid at least TAVWL/TAVSL/TAVEH time before the enabling NWE/NCS/CE edge transition, and must remain valid during the entire write time. A valid data overlap of write pulse width time of TDVWH/TDVSH/TDVEL, and an address valid to end of write time of TAVWH/TAVSH/TAVEL also must be provided for during the write operation. Hold times for address inputs and data inputs with respect to the disabling NWE/NCS/CE edge transition must be a minimum of TWHAX/TSHAX/TELAX time and TWHDX/TSHDX/TELDX time, respectively. The minimum write cycle time is TAVAV. TESTER AC TIMING CHARACTERISTICS * Input rise and fall times <1 ns/V 8 www.honeywell.com HLX6228 QUALITY AND RADIATION HARDNESS ASSURANCE Honeywell maintains a high level of product integrity through process control, utilizing statistical process control, a complete "Total Quality Assurance System," a computer data base process performance tracking system and a radiation-hardness assurance strategy. The radiation hardness assurance strategy starts with a technology that is resistant to the effects of radiation. Radiation hardness is assured on every wafer by irradiating test structures as well as SRAM product, and then monitoring key parameters which are sensitive to ionizing radiation. Conventional MIL-STD-883 TM 5005 Group E testing, which includes total dose exposure with Cobalt 60, may also be performed as required. This Total Quality approach ensures our customers of a reliable product by engineering in reliability, starting with process development and continuing through product qualification and screening. SCREENING LEVELS Honeywell offers several levels of device screening to meet your system needs. "Engineering Devices" are available with limited performance and screening for breadboarding and/or evaluation testing. Hi-Rel Level B and S devices undergo additional screening per the requirements of MILSTD-883. DYNAMIC BURN-IN DIAGRAM* R = 1.5k ohms RELIABILITY Honeywell understands the stringent reliability requirements for space and defense systems and has extensive experience in reliability testing on programs of this nature. This experience is derived from comprehensive testing of VLSI processes. Reliability attributes of the RICMOSTM process were characterized by testing specially designed irradiated and nonirradiated test structures from which specific failure mechanisms were evaluated. These specific mechanisms included, but were not limited to, hot carriers, electromigration and time dependent dielectric breakdown. This data was then used to make changes to the design models and process to ensure more reliable products. In addition, the reliability of the RICMOSTM process and product in a military environment was monitored by testing irradiated and non-irradiated circuits in accelerated dynamic life test conditions. Packages are qualified for product use after undergoing Groups B & D testing as outlined in MIL-STD-883, TM 5005, Class S. The product is qualified by following a screening and testing flow to meet the customer's requirements. Quality conformance testing is performed as an option on all production lots to ensure the ongoing reliability of the product. STATIC BURN-IN DIAGRAM* R = 1.5k ohms *40-Lead FP Burn-in diagram has similar connections and is available on request. www.honeywell.com 9 HLX6228 PACKAGING The 128K x 8 SRAM is offered in a custom 32-lead or 40- lead flat pack (FP). The packages are constructed of multilayer ceramic (Al2O3) and feature internal power and ground planes. Ceramic chip capacitors can be mounted to the package by the user to maximize supply noise decoupling and increase board packing density. These capacitors attach directly to the internal package power and ground planes. This design minimizes resistance and inductance of the bond wire and package. All NC (no connect) pins should be connected to VSS to prevent charge build up in the radiation environment. 32-LEAD FLAT PACK PINOUT 40-LEAD FLAT PACK PINOUT 32-LEAD FLAT PACK (22018533-001) All dimensions are in inches A B C D e E E2 E3 F L Q S U V W X Y Z [1] [2] [3] [4] 10 0.135 +/- 0.015 0.017 +/- 0.002 0.004 to 0.009 0.820 +/- 0.008 0.050 +/- 0.005 [1] 0.600 +/- 0.008 0.500 +/- 0.008 0.050 ref 0.750 +/- 0.005 [2] 0.290 min [3] 0.026 to 0.045 0.035 +/- 0.010 0.080 ref 0.380 ref 0.050 ref 0.075 ref 0.010 ref 0.100 ref BSC - Basic lead spacing between centers Where lead is brazed to package Parts are delivered with leads unformed Lid connected to VSS www.honeywell.com HLX6228 40-LEAD FLAT PACK (22019370-001) www.honeywell.com 11 HLX6228 ORDERING INFORMATION (1) (1) Orders may be faxed to 763-954-2257. Please contact our Customer Service Department at 763-954-2474 for further information. (2) Engineering Device description: Parameters are tested from -55 to 125C, 24 hr burn-in, no radiation guaranteed. FIND OUT MORE For more information on Honeywell's Magnetic Sensors visit us online at www.honeywellmicroelectronics.com or contact us at 800-323-8295 (763-954-2474 internationally). The application circuits herein constitute typical usage and interface of Honeywell product. Honeywell does not warranty or assume liability of customerdesigned circuits derived from this description or depiction. Honeywell reserves the right to make changes to improve reliability, function or design. Honeywell does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Honeywell 12001 Highway 55 Plymouth, MN 55441 Tel: 800-323-8295 12 www.honeywellmicroelectronics.com/ Form ADS-14207 Rev August 2013 (c)2013 Honeywell International Inc. www.honeywell.com