HLX6228-SR - Honeywell - Microelectronics & Precision Sensors

HLX6228

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HLX6228

128K x 8 STATIC RAM—Low Power SOI

The 128K x 8 Radiation Hardened Static RAM is a high

performance 131,072 word x 8-bit static random access

memory with industry-standard functionality. It is fabricated

with Honeywell’s radiation hardened technology, and is

designed f or use in low vol tage system s operating in radi ation

environments. The RAM operates over the full military

temperature range and requires only a single 3.3 V ± 0.3V

power supply. The RAM is compatible with JEDEC standard

low voltage CMOS I/O. Power consumption is typically less

than 9 mW/MHz in operation, and less than 2 mW when

deselected. The RAM read operation is fully asynchronous,

with an associated typical access time of 32 ns at 3.3 V.

Honeywell’s enhanced SOI RICMOS™IV (Radiation

Insensitive CMOS) technology is radiation hardened through

the use of advanced and proprietary design, layout and process hardening techniques. The RICMOS™ IV low power

process is a SIMOX CMOS technology with a 150 Å gate oxide and a minimum drawn feature size of 0.7 µm (0.55 µm

effective gate length—Leff). Additional features include tungsten via plugs, Honeywell’s proprietary SHARP planarization

process and a light ly dope d drain (LD D) struc ture for improved s hort chan nel rel iability. A 7 transis tor (7 T) m em ory cell is

used for superior single event upset hardening, while three layer metal power bussing and the low collection volume

SIMOX substrate provide improved dose rate hardening.

FEATURES

RADIATION

• Fabricated with RICMOS™ IV Silicon on Insulator

(SOI) 0.7 µm (Leff = 0.55 µm)

• Total Dose Hardness through 1x106 rad(SiO2)

• Neutron Hardness through 1x1014 cm-2

• Dynamic and Static Transient Upset Hardness

through 1x109 rad(Si)/s

• Dose Rate Survivability through <1x1011 rad(Si)/s

• Soft Error Rate of <1x10-10 upsets/bit-day in

Geosynchronous Orbit

• No Latchup

OTHER

• Read/Write Cycle Times

o ≤ 32 ns (-55 to 125°C)

• Typical Operating Power <9 mW/MHz

• JEDEC Standard Low Voltage

CMOS Compatible I/O

• Single 3.3 V ± 0.3 V Power Sup ply

• Asynchronous Operation

• Packaging Options

o 32-Lead Fl at Pack (0.820 in. x 0.600 in.)

o 40-Lead Flat Pack (0.775 in. x 0.710 in.)

HLX6228

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FUNCTIONAL DIAGRAM

SIGNAL DEFINITIONS

A: 0-16 Address input pins which select a particular eight-bit word within the memory array.

DQ: 0-7 Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write

operation.

NCS Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS

forc es the SR AM t o a precharge co ndi tio n, h ol ds the data outp ut drivers in a high impedanc e s tat e a nd disables

all input buf f er s exc ept CE. T his part m ust be Read an d Write controlled us ing t he NCS pin: i t requir es that NCS

returns to a high state for at least 5ns whenever there is an address change. This 5ns pulse to high provides the

part with a defined pre-charge pulse duration to ensure that the new address is latched. The part must be

controlled in this fashion to meet the timing specifications defined.

NWE Negative write enable, when at a low level activates a write operation and holds the data output drivers in a high

impedance state. When at a high level NWE allows normal read operation.

NOE N egat i ve out put e nab le, wh en at a h igh l e vel hol ds the data o utpu t dri vers in a h igh impedance s tate. When a t a

low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must be

connected to VSS.

CE Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a

precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers

except the NCS input buffer. If this signal is not used it must be connected to VDD.

TRUTH TABLE

NCS CE NWE NOE MODE DQ

L H H L Read Data Out

L H L X Write Data In

H X XX XX Deselected High Z

X L XX XX Disabled High Z

Notes:

X: VI=VIH or VIL

XX: VSS≤VI≤VDD

NOE=H: High Z output stat e

maintained for NCS=X,

CE=X, NWE= X

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RADIATION CHARACTERIST ICS

Total Ionizing Radiation Dos e

The SRAM will meet all stated functional and electrical

specifications over the entire operating temperature

range af ter the spec ified total io nizing radiati on dose. All

electrical a nd tim ing per form anc e param eters will r emain

within specific ations af ter rebound at VD D = 3.6 V an d T

=125°C extrapolated to ten years of operation. Total

dose hardness is assured by wafer level testing of

process monitor transistors and RAM product using 10

KeV X-ray and Co60 radiation sources. Transistor gate

threshold s hift correlat ions have been made betwee n 10

KeV X-r a ys applied at a do s e r ate of 1x 105 r ad(Si)/min at

T = 25°C and gamm a rays (Cobalt 60 source) to ensure

that wafer level X-ray testing is consistent with standard

military radiation test environments.

Transient Pulse Ionizing Radi ation

The SRAM is capable of writing, reading, and retaining

stored data during and after exposure to a transient

ionizing radiation pulse, up to the specified transient

dose rate upset specification, when applied under

recom m ended o perat ing c o ndit io ns . T o ens ur e va lid it y of

all specif ie d perform anc e par ameters bef or e, dur ing, and

after radiation (timing degradation during transient pulse

radiation (timing degradation during transient pulse

radiation is ≤10%), it is suggested that stiffening

capacita nce be placed on or ne ar the p ackage VDD and

VSS, with a maximum inductance between the package

(chip) and stiffening capacitance of 0.7 nH per part. If

there are no operate-through or valid stored data

requirements, typical circuit board mounted de-coupling

capacitors are recommended.

The SRAM will meet any functional or electrical

specif icatio n af ter exposure to a r ad iat ion pulse up to the

transient dose rate survivability specification, when

applied under recommended operating conditions. Note

that the current conducted during the pulse by the RAM

inputs, outputs, and power supply may significantly

exceed the normal operating levels. The application

design must accommodate these effects.

Neutron Radiation

The SRAM will meet any functional or timing

specification after exposure to the specified neutron

fluence under recommended operating or storage

conditio ns. T his ass um es equiva lent n eutro n energ y of 1

MeV.

Soft Error Rate

The SRAM is capable of meeting the specified Soft Error

Rate (SER), under recommended operating conditions.

This hardness level is defined by the Adams 90% worst

case cosm ic ra y environm ent f or geosynchro nous orbit s.

Latchup

The SRAM will not latch up due to any of the above

radiation exposure conditions when applied under

recommended operating conditions. Fabrication with the

SIMOX substrate material provides oxide isolation

between adjacent PMOS and NMOS transistors and

eliminates any potential SCR latchup structures.

Suffic ient trans istor bod y tie conn ectio ns to the p- and n-

channel substrates are made to ensure no source/drain

snapback occurs.

RADIATION HARDNESS RATINGS (1)

Parameter Limits (2) Units Test Conditions

Total Dose ≥1x106 rad(Si) TA=25°C,

Transient Dose Rate Upset ≥1x109 rad(Si)/s Pulse width ≤20ns, X-ray, TA = 125OC

Transient Dose Rate Survivability ≥1x1011 rad(Si)/s Pulse width ≤20 ns, X-ray, TA=25°C

Soft Error Rate (SER) <1x10-10 upsets/bit-day TA=25°C, Ad ams 90% worst case environment

Neutron Fluence ≥1x1014 N/cm2 1 MeV equivalent energy, Unbiased, TA=25°C

(1) Device will not latch up due to any of the specified radiation exposure conditions.

(2) Specifications apply to operating conditions (unless otherwise specified) of: VDD=3.0 V to 3.6 V, TA=-55°C to 125°C.

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ABSOLUTE MAXIMUM RATINGS (1)

Symbol

Parameter

Rating

Units

Min

Max

VDD Sup ply Voltage Range (2) -0.5 6.5 V

VPIN Voltage on Any Pin (2) -0.5 VDD +0.5 V

TSTORE Storage Temperature (Zero Bias) -65 150 °C

TSOLDER Soldering Temperature (5 seconds) 270 °C

PD Maximum Package Power Dissipation (3) 2.5 W

IOUT DC or Average Output Current 25 mA

VPROT ESD Input Protection Voltage (4) 2000 V

ΘJC Thermal Resistance (Jct-toCase) 32 FP 2 °C / W

40 FP 2 °C / W

TJ Junction Temperature 175 °C

(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these

levels is not implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.

(2) Voltage referenced to VSS.

(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this

specification.

(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.

RECOMMENDED O PERATING CONDITIONS

Symbol

Parameter

Description

Units

Min

Typ

Max

VDD Supply Voltage (referenced to VSS) 3.0 3.3 3.6 V

TA Ambient Temperature -55 25 125 °C

VPIN Voltage on Any Pin (referenced to VSS) -0.3 VDD+0.3 V

VDD Ramp

Time

Supply Voltage Ramp Time 50 ms

CAPACITANC E (1)

Symbol

Parameter

Typical

Worst Case

Units

Test Conditions

Min Max

CI Input Capacitance 7 pF VI=VDD or VSS, f=1 MHz

CO Output Cap acita nc e 9 pF VIO=VDD or VSS, f=1 MHz

(1) This parameter is tested during initial design characterization only.

DATA RETENTIO N CHARACTERISTICS

Symbol

Parameter

Typical (1)

Worst Case (2)

Units

Test Conditions

Min Max

VDR Data Retention Voltage 2.5 V NCS=VDR, VI=VDR or VSS

IDR Data Retention Current 700 μA NCS=VDD=VDR, VI=VDD or VSS

(1) Typical operating conditions: TA= 25°C, pre-radiation.

(2) Worst case operating conditions: TA= -55°C to +125°C, post total dose at 25°C.

HLX6228

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DC ELECTRICAL CHARACTERISTICS

Symbol

Parameter

Typical

(1)

Worst Case (2)

Units

Test Conditions

Min Max

IDDSB1 Static Supply Current 700 µA VIH=VDD, IO=0

VIL=VSS, Inputs Stable

IDDSBMF Standby Supply Current –

Deselected 700 µA NCS=VDD, CE=VSS, IO=0,

f=40 MHZ

IDDOPW Dynamic Supply Current – Selected

(Write) 3.2 mA f=1 MHz, IO=0, CE=VIH=VDD

NCS=VIL=VSS (3)

IDDOPR Dynamic Supply Current – Selected

(Read) 2.2 mA F=1 MHz, IO=0, CE=VIH=VDD

NCS=VIL=VSS (3)

II Input Leakage Current -5 5 μA VSS <VI <VDD

IOZ Output Leakage Current -10 10 μA VSS <VI<VDD, Output = high

Z

VIL Low-Level Input Voltage 0.27xVDD V March Pattern, VDD = 3.0V

VIH High-Level Input Voltage .725xVDD V March Pattern, VDD = 3.6V

VOL Low-Level Output Voltage 0.4 V VDD=3.0V, IOL = 8 mA

VOH High-Level Output Voltage 2.7 V VDD=3.0V, IOL = -4 mA

(1) Typical operating conditions: VDD=3.3 V, TA=25°C, pre-radiation.

(2) Worst case operating conditions: VDD=3.0 V to 3.6 V, -55°C to +125°C, post total dose at 25°C.

(3) All inputs switchi ng. DC av er age curre nt.

SIGNAL INTEGRITY AND SIGNAL CONNECTIONS

It is important that input signal transitions (between VIL

and VIH levels) that produce asynchronous behavior

(i.e., Address, Read/Write, Chip Select/Enable) have

good signal integrity (free of noise, glitches, ringing or

discontinuities from impedance mismatch reflections or

driver changes) and have rising and falling edges of

≤10ns. Input signal transitions with poor signal integrity,

slow state chan ges (>10ns) or where the driv er changes

between VIL and VIH levels, when the chip is enabled

and selected, can interfere with intended read or write

operations. Note: Some examples of “driver change”

include changing from a floating or weakly driven (e.g.,

weak pul l-up or pull-do wn) input sta te to an ac tive driver

defined input state or changing between devices driving

the signal input.

In addition, input signals should not be left floating

unless the chip is disabled or deselected.

TESTER EQUIVALENT LOAD CIRCUIT

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READ CYCLE AC TIMI NG CHARACTERISTICS (1, 2)

Symbol

Parameter

Typical (2)

Worst Case (3)

Units

-55 to 125° C

Min Max

TAVAVR Address Read Cycle Time 32 ns

TAVQV Address Access Time 32 ns

TAXQX Address Change to Output Invalid Time 3 ns

TSLQV Chip Select Access Time 35 ns

TSLQX Chip Select Output Enable Time 5 ns

TSHQZ Chip Select Output Disable Time 10 ns

TEHQV Chip Enable Access Time 35 ns

TEHQX Chip Enable Output Enable Time 5 ns

TELQZ Chip Enable Output Disable Time 13 ns

TGLQV Output Enable Acces s Time 12 ns

TGLQX Output Enable Output Enable Time 0 ns

TGHQZ Output Enable Output Disable Time 9 ns

(1) Key Note: This part must be Read controlled using the NCS pin: it requires that NCS returns to a high state for at least 5ns

whenever there is an address change. This 5ns pulse to high provides the part with a defined pre-charge pulse duration to ensure

that the new address is latched. The part must be controlled in this fashion to meet the timing specifications defined.

(2) Test conditio ns: Control inputs driven with logic level signals, input and output timing reference levels shown in the Tester AC

Timing Characteristics table and Tester Load Circuit Diagram.

(3) Typical operating conditions: VDD=3.3 V, TA=25°C, pre-radiation.

(4) Worst case operating conditions: VDD=3.0 V to 3.6 V, TA= -55°C to 125°C, post total dose at 25°C.

HLX6228

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WRITE CYCLE AC TIMING CHAR ACTERISTICS (1, 2)

Symbol

Parameter

Typical (3)

Worst Case (4)

Units

-55 to 125° C

Min Max

TAVAVW Write Cycle Time (5) 30 ns

TWLWH Write Enable Write Pulse Width 25 ns

TSLWH Chip Select to End of Write Time 25 ns

TDVWH Data Valid to End of Write Time 20 ns

TAVWH Address Valid to End of W r ite Tim e 25 ns

TWHDX Data Hold Time after End of Write Time 0 ns

TAVWL Address Valid Setup to Start of Write Time 0 ns

TWHAX Address Valid Hold after End of Write Time 0 ns

TWLQZ Write Enable to Output Disable Time 0 12 ns

TWHQX Write Disable to Output Enable Time 5 ns

TWHWL Write Disable to Write Enable Pulse Width (6) 5 ns

TEHWH Chip Enable to End of Write Time 25 ns

(1) Key Note: This part must be Write controlled using the NCS pin: it requires that NCS returns to a high state for at least 5ns

whenever there is an address change. This 5ns pulse to high provides the part with a defined pre-charge pulse duration to ensure

that the new address is latched. The part must be controlled in this fashion to meet the timing specifications defined.

(2) Test conditio ns: Control inputs driven with logic level signals, input and output timing reference levels shown in the Tester AC

Timing Characteristics table and Tester Load Circuit Diagram. (3) Typical operating conditions: VDD=3.3 V, TA=25°C, pre-radiation.

(4) Worst case operating conditions: VDD=3.0 V to 3.6 V, -55 to 125°C, post total dose at 25°C.

(5) TAVAVW = TWLWH + TWHWL

(6) Guaranteed but not t est ed.

HLX6228

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DYNAMIC ELECTRICAL CHARACTERISTICS

Read Cycle

The RAM is asynchronous in operation, allowing the

read cycle to be controlled only by chip select (NCS)

(refer to Read Cycle t iming di agram). T o perform a valid

read operation, both chip select and output enable

(NOE) must be low and chip enable and write enable

(NWE) must be high. The output drivers can be

controlled independently by the NOE signal.

To control a read cycle with NCS, all addresses and CE

must be valid prior to or coincident with the enabling

NCS edge transition delayed. Read control with NCS

requires th at NCS returns to a high s tate for at least 5ns

whenever there is an addr ess change. This 5ns pulse to

high provides the part with a defined pre-charge pulse

duration to ensure that the new address is latched. The

device must be controlled in this fashion to meet the

timing specifications herein. The data output will not

become valid until TSLQV time following return of NCS

to a low state. Data outputs will enter a high impedance

state TSHQZ time following a disabling NCS edge

transition.

Write Cycle

The write operation is synchronous with respect to the

address bits, and control is governed by only chip select

(NCS) (r efer to W rite C ycle timing diagram s ). To perform

a write operation, bot h NWE and NCS mus t be low, and

CE must be high. This part must be Write controlled

using the NC S pin; it requ ires that NC S returns to a high

state for at least 5ns whenever there is an address

change. This 5ns pulse to high provides the part with a

defined pre-char ge pulse duratio n to e ns ur e th at th e n e w

address is latched. The part must be controlled in this

fashion to meet the timing specifications defined. Both

CE and NCS fully disable the RAM decode logic and

input buffers for power savings.

To write data into the RA M, NWE and N CS must be he ld

low and CE must be held high for at least

TW LW H/TSLSH/TEHEL t im e. Any amount of edge skew

between th e s ignals c an be tolerat ed, a nd any one of the

control signals can initiate or terminate the write

operatio n. For consecutive wri te operations, write puls es

must be separated by the minimum specified

TWHWL/TSHSL/TELEH time. Address inputs must be

valid at least TAVWL/TAVSL/TAVEH time before the

enabling NWE/NCS/CE edge transition, and must

remain valid during the entire write time. A valid data

overlap of write pulse width time of

TDVW H/TDVSH/T DVEL, and an address valid to end of

write time of TAVWH/TAVSH/TAVEL also must be

provided for during the write operation. Hold times for

address inputs and data inputs with respect to the

disabling NWE/NCS/CE edge transition must be a

minimum of TWHAX/TSHAX/TELAX time and

TWHDX/TSHDX/TELDX time, respectively. The

minimum write cycle time is TAVAV.

TESTER AC TIMING CHARACTERISTICS

* Input rise and fall times <1 ns/V

HLX6228

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QUALITY AND RADIATION HARDNESS

ASSURANCE

Honeywell maintains a high level of product integrity

through process control, utilizing statistical process

control, a complete “Total Quality Assurance System,” a

computer data base process performance tracking

system and a radiation-hardness assurance strategy.

The radiation hardness assurance strategy starts with a

technology that is resistant to the effects of radiation.

Radiation hardness is assured on every wafer by

irradiating test structures as well as SRAM product, and

then monitoring key parameters which are sensitive to

ionizing radiation. Conventional MIL-STD-883 TM 5005

Group E testin g, whic h includes total dose ex posure with

Cobalt 60, may also be performed as required. This

Total Quality approach ensures our customers of a

reliable product b y engineering in reliability, starting with

process development and continuing through product

qualification and screening.

SCREENING LEVELS

Honeywell offers several levels of device screening to

meet your system needs. “Engineering Devices” are

available with limited performance and screening for

breadboarding and/or evaluation testing. Hi-Rel Level B

and S devices undergo additional screening per the

requirements of MILSTD-883.

RELIABILITY

Honeywell understands the stringent reliability

requirements for space and defense systems and has

extensive experience in reliability testing on program s of

this nature. This experience is derived from

comprehensive testing of VLSI processes. Reliability

attributes of the RICMOSTM process were characterized

by testing specially designed irradiated and non-

irradiated test structures from which specific failure

mechanisms were evaluated. These specific

mechanisms included, but were not limited to, hot

carriers, electromigration and time dependent dielectric

breakdown. This data was then used to make changes

to the design models and process to ensure more

reliable products.

In addition, the reliability of the RICMOSTM process and

product in a military environment was monitored by

testing irradiated and non-irradiated circuits in

accelerated dynamic life test conditions. Packages are

qualified for product use after undergoing Gro ups B & D

testing as outlined in MIL-STD-883, TM 5005, Class S.

The product is qualified by following a screening and

testing flow to meet the customer’s requirements. Quality

conformance testing is performed as an option on all

production lots to ensure the ongoing reliability of the

product.

DYNAMIC BURN-IN DIAGRAM* STATIC BURN-IN DIAGRAM*

*40-Lead FP Burn-in diagram has similar connections and is available on request.

R = 1.5k ohms

HLX6228

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PACKAGING

The 128K x 8 SRAM is offered in a custom 32-lead or

40- lead f lat pack ( FP). T he pack ages ar e cons tructed of

multilayer ceramic (Al2O3) and feature internal power and

ground p lanes. C eram ic chip capac itors can be m ounted

to the package by the user to maximize supply noise

decoupling and increase board packing density. These

capacitors attach directly to the internal package power

and ground planes. This design minimizes resistance

and inductance of the bond wire and package. All NC

(no connect) pins should be connected to VSS to

prevent charge build up in the radiation environment.

32-LEAD FLAT PACK PINOUT 40-LEAD FLAT PACK PINOUT

32-LEAD FLAT PACK (22018533-001)

A

0.135 +/- 0.015

B 0.017 +/- 0.002

C

0.004 to 0.009

D 0.820 +/- 0.008

e

0.050 +/- 0.005 [1]

E 0.600 +/- 0.008

E2

0.500 +/- 0.008

E3 0.050 ref

F

0.750 +/- 0.005 [2]

L 0.290 min [3]

Q

0.026 to 0.045

S 0.035 +/- 0.010

U

0.080 ref

V 0.380 ref

W

0.050 ref

X 0.075 ref

Y 0.010 ref

Z

0.100 ref

[1] BSC – Basic lead spacing between centers

[2] Where lead is brazed to package

[3] Parts are delivered with leads unformed

[4] Lid connected to VSS

All dimensions are in inches

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40-LEAD FLAT PACK (22019370-001)

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ORDERING I NFORMATION (1)

(1) Orders may be faxed to 763-954-2257. Please contact our Customer Service Department at 763-954-2474 for fur ther i nf orm atio n.

(2) Engineering Device description: Parameters are tested from -55 to 125°C, 24 hr burn-in, no radiation guaranteed.

FIND OUT MORE

For more information on Honeywell’s Magnetic Sensors visit us online at www.honeywellmicroelectronics.com or

contact us at 800-323-8295 (763-954-2474 inter nat ion ally).

The application circuits herein constitute typical usage and interface of Honeywell product. Honeywell does not warranty or ass um e liabil ity of custom er-

designed circuits derived f rom t his descript i on or depiction.

Honeywell reserves the right to make changes to improve reliability, function or design. Honeywell does not assume any liability arising out of the

applicat i on or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the ri ghts of others.

Honeywell

12001 Highway 55

Plymouth, MN 55441

Tel: 800-323-8295

www.honeywellmicroelectronics.com/

Form ADS-14207 Rev -

August 2013