RD
QS
20
DELAY
23
GND 11
VCC
REF 15
RT 17
CT 18
SYNC 19
CSA− 9
CSA+ 8
SS 4
CSAO 7
CEA− 13
VEA− 16
VEA+ 14
22
24
3
2
1
RAMPCEA+
12 CEAOVEAO
10
PULL
PGND
PUSH
SRC
BUCK
V+
DELAY
DELAY
T
Q
Q
REF
&
UVLO
SS
INHBT
UV
OSC
500 kHz
MAX
6 5
21
Current Sense
Amplifier
ILIM Comparator
+3 V
Current Error
Amplifier
PWM Comparator0.7 V
Flying
Driver
Push/Pull
Drivers
OSC
UVLO
Voltage Error
Amplifier
+
UC2827-1, UC2827-2
UC3827-1, UC3827-2
www.ti.com
SLUS365D –APRIL 1999–REVISED APRIL 2011
BUCK CURRENT/VOLTAGE FED PUSH-PULL
PWM CONTROLLERS
Check for Samples: UC2827-1, UC2827-2,UC3827-1, UC3827-2
1FEATURES DESCRIPTION
•Ideal for Multiple Output and/or High The UC3827 family of controller devices provides an
Voltage Output Voltage Converters integrated control solution for cascaded buck and
•Up to 500 kHz Operation push-pull converters. These converters are known as
•High Voltage, High Current Floating current fed or voltage fed push-pull converters and
Driver for Buck Converter Stage are ideally suited for multiple output and/or high
voltage output applications. In both current fed and
•UC3827-1 Current Fed Controller has voltage fed modes, the push-pull switches are driven
Push-Pull Drivers with Overlapping at 50% nominal duty cycles and at one half the
Conduction Periods switching frequency of the buck stage. In the current
•UC3827-2 Voltage Fed Controller has fed mode, the two switches are driven with a
Push-Pull Drivers with Nonoverlapping specified over-lap period to prevent ringing and
Conduction Periods voltage stress on the devices. In the voltage fed
mode, the two switches are driven with a specified
•Average Current Mode, Peak Current gap time between the switches to prevent shorting
Mode or Voltage Mode with Input the transformer across the energy storage capacitor
Voltage Feedforward Control for Buck and to prohibit excessive currents flowing through the
Power Stage devices.
•Wide Bandwidth, Low Offset, The converter's output voltage is regulated by pulse
Differential Current Sense Amplifier width modulation of the buck switch. The UC3827
•Precise Short Circuit Current Control contains complete protection and PWM control
functions for the buck converter. Easy control of the
floating switch is accomplished by the floating drive
circuitry. The gate drive waveform is level shifted to
support an input voltage up to 72 VDC.
BLOCK DIAGRAM
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright ©1999–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
UC2827-1, UC2827-2
UC3827-1, UC3827-2
SLUS365D –APRIL 1999–REVISED APRIL 2011
www.ti.com
DESCRIPTION (CONTINUED)
The UC3827 can be set up in traditional voltage mode control using input voltage feedforward technique or in
current mode control. Using current mode control prevents potential core saturation of the push-pull transformer
due to mismatches in timing and in component tolerances. With average current mode control, precise control of
the inductor current feeding the push-pull stage is possible without the noise sensitivity associated with peak
current mode control. The UC3827 average current mode loop can also be connected in parallel with the voltage
regulation loop to assist only in fault conditions.
Other valuable features of the UC3827 include bidirectional synchronization capability, user programmable
overlap time (UC3827-1), user programmable gap time (UC3827-2), a high bandwidth differential current sense
amplifier, and soft start circuitry.
ORDERING INFORMATION(1)
PACKAGES
TA= TJPUSH-PULL TOPOLOGY SOIC-24 PDIP-24 PLCC-28
Current Fed UC2827DW-1 UC2827N-1 -
-40°C to 85°CVoltage Fed UC2827DW-2 UC2827N-2 -
Current Fed UC3827DW-1 UC3827N-1 UC3827Q-1
0°C to 70°CVoltage Fed UC3827DW-2 UC3827N-2 -
(1) The DW and Q packages are also available taped and reeled. Add a TR suffix to the device type (i.e., UC2827DWTR-1).
THERMAL INFORMATION UC2827-1, UC2827-1,
UC2827-2, UC2827-2,
UC3827-1, UC3827-1,
THERMAL METRIC UNITS
UC3827-2 UC3827-2
N J
24 PINS 24 PINS
θJA Junction-to-ambient thermal resistance(1) 60 70 to 80 °C/W
θJCtop Junction-to-case (top) thermal resistance(2) 30 28
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
THERMAL INFORMATION UC2827-1, UC2827-1,
UC2827-2, UC2827-2,
UC3827-1, UC3827-1,
THERMAL METRIC UNITS
UC3827-2 UC3827-2
DW (1)QLCC
28 PINS 28 PINS
θJA Junction-to-ambient thermal resistance(2) 71 to 83 40 to 65 °C/W
θJCtop Junction-to-case (top) thermal resistance(3) 24 30
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
2Copyright ©1999–2011, Texas Instruments Incorporated
UC2827-1, UC2827-2
UC3827-1, UC3827-2
www.ti.com
SLUS365D –APRIL 1999–REVISED APRIL 2011
ABSOLUTE MAXIMUM RATINGS(1)
UC2827-1
UC2827-2 UNITS
UC3827-1
UC3827-2
Supply voltage, VCC 20
CEAO, CEA+, CEA-, CSAO, CSA+, CSA-, CT, DELAY, PUSH, PULL, –0.3 to 5
RAMP, RT, SS, SYNC, VEA+, VEAO, V
Input voltage range V+ and BUCK 90
SRC 90-VCC
I/O continuous ±250 mA
BUCK driver I/O peak ±1 A
I/O continuous ±200 mA
PUSH/PULL driver I/O peak ±0.8 A
Storage temperature –65 to 150
Junction temperature –55 to 150 °C
Lead temperature (soldering, 10 sec) 300
(1) Voltages are referenced to ground. Currents are positive into, negative out of the specified terminal. Consult Packaging section of
databook for thermal limitations and considerations of packages.
ELECTRICAL CHARACTERISTICS
Unless otherwise spsecified, VVCC = 15 V, VV+ = 14.3 V, CCT = 340 pF, RRT = 10 kΩ, RDELAY = 24.3 kΩ, VSRC = VGND = VBUCK=
VPUSH = VPULL outputs no load, TJ= TA
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VCC UVLO, Turn-on 8.3 8.8 9.5 V
Hysteresis 0.9 1.2 1.5 V
IVCC Supply current start VVCC = 8 V 1000 µA
IVCC Supply current run 32 45 mA
IV+ buck high 0.2 1 2 mA
VOLTAGE ERROR AMPLIFIER
IB 0.5 3 µA
VIO 10 mV
AVOL 80 95 dB
GBW(1) Gain bandwidth 1 4 MHz
VOL Low-level output voltage IVEAO = 0 µA (No load) 0.3 0.5 V
VOH High-level output voltage IVEAO = 0 µA (No load) 2.85 3 3.20 V
CURRENT SENSE AMPLIFIER
IB –1–5µA
VIO 5 mV
AVOL 80 110 dB
GBW (1) Gain bandwidth 15 29 MHz
VOL Low-level output voltage ICEAO = 0 µA (No load) 0.25 0.5 V
VOH High-level output voltage ICEAO = 0 µA (No load) 3 3.3 V
CMRR Common mode range(1) -0.3 2 V
(1) Ensured by design. Not production tested.
Copyright ©1999–2011, Texas Instruments Incorporated 3
UC2827-1, UC2827-2
UC3827-1, UC3827-2
SLUS365D –APRIL 1999–REVISED APRIL 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise spsecified, VVCC = 15 V, VV+ = 14.3 V, CCT = 340 pF, RRT = 10 kΩ, RDELAY = 24.3 kΩ, VSRC = VGND = VBUCK=
VPUSH = VPULL outputs no load, TJ= TA
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT ERROR AMPLIFIER
IB –1–5µA
VIO 10 mV
AVOL 80 110 dB
GBW(2) Gain bandwidth At 100 kHz, Measure Gain 2 4.5 MHz
VOL ICEAO = 0 µA (No Load) 0.25 0.5 V
VOH ICEAO = 0 µA (No Load) 3.3 3.5 V
CMRR Common mode range(2) -0.3 5 V
OSCILLATOR SECTION
fOSC Frequency 180 220 250 kHz
ICT(dsch) CT discharge current 3.5V at CT when CT removed 5 mA
PWM COMPARATOR
DMAX Minimum duty cycle 200 kHz 0%
DMAX Maximum duty cycle 200 kHz 85% 91% 95%
BUCK OUTPUT STAGE
tRISE Rise time 1 nF Load(3) 40 100 ns
tFALL Fall tIme 1 nF, Load 30 80 ns
IBUCK =–15 mA , V+ –BUCK(4) 1.5 2.5 V
VOH High-level output voltage IBUCK = –150 mA, V+ –BUCK (4) 2 2.5 V
IBUCK = 15 mA(5) 0.2 0.4 V
VOL Low-level output voltage IBUCK = 150 mA (5) 0.7 1.2 V
PUSH/PULL OUTPUT STAGES
tRISE Rise time 1 nF load 50 100 ns
tFALL Fall tIme 1 nF load 35 100 ns
Overlap time UCx827-1 1 nF loads(6) 100 250 400 ns
Nonoverlapping time (7) UCx827-2 100 250 500 ns
IPUSH/PULL =–10 mA, VCC –PUSH 2 3 V
(8)
VOH High-level output voltage IPUSH/PULL =–100 mA, VCC –2.5 3 V
PUSH(8)
IPUSH/PULL = 10 mA(8) 0.2 0.8 V
VOL Low-level output voltage IPUSH/PULL = 100 mA(8) 0.6 1.2 V
REFERENCE
Reference voltage 4.8 5 5.2 V
ISC Shor-circuit current VREF = 0V –35 –50 –65 mA
Line regulation 0.5V <VVCC <20 V 5 20 mV
Load regulation 0 mA <IIO <10 mA 8 20 mV
SOFT START
VOL Low-level output voltage saturation VVCC = 7 V 250 500 mV
ISS Soft-start current –5–12 –25 µA
(2) Ensured by design. Not production tested.
(3) Measure the rise time from when BUCK crosses 1 V until it crosses 9 V.
(4) To force BUCK high, force VCSAO=2.5 V, VCEAO = 2.5 V, a 25-kΩpulldown resistor from RAMP to ground, and VCT = 0.5 V.
(5) To force BUCK low, force VCSAO = 2.5 V, VCEAO = 2.5 V, a 10-kΩpulldown resistor from RAMP to ground, and VCT = 3.5 V.
(6) The overlap time is measured from the point at which the rising edge of PUSH/PULL crosses 5 V until the falling edge of PULL/PUSH
crosses 5V.
(7) The non-overlap time is measured from the point at which the falling edge of PUSH/PULL crosses 5 V until the rising edge of
PULL/PUSH crosses 5 V.
(8) To toggle PUSH or PULL into a desired state, pulse CT from 0.5 V to 3.5 V. PUSH and PULL toggle on the rising edge of CT.
4Copyright ©1999–2011, Texas Instruments Incorporated
fOSC +0.77
RRT CCT (Hz)
tDELAY +RDELAY
200W 10*9(s)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V+
BUCK
SRC
SS
RAMP
CEAO
CSAO
CSA+
CSA−
VEAO
GND
CEA+
PUSH
VCC
PULL
PGND
DELAY
SYNC
CT
RT
VEA−
REF
VEA+
CEA−
N, J OR DW PACKAGES
(TOP VIEW)
3 2 1
13 14
5
6
7
8
9
10
11
PGND
NC
NC
DELAY
SYNC
CT
RT
SS
RAMP
CEAO
CSAO
CSA+
CSA−
VEAO
4
15 16 17 18
CEA+
CEA−
VEA+
REF
NC
VEA−
SRC
BUCK
NC
V+
Q PACKAGE
(TOP VIEW)
28 27 2625
24
23
22
21
20
19
12
GND
PUSH
VCC
PULL
NC − No internal connection
(1)
(2)
UC2827-1, UC2827-2
UC3827-1, UC3827-2
www.ti.com
SLUS365D –APRIL 1999–REVISED APRIL 2011
PLCC-28 (Q PACKAGE)
CONNECTION DIAGRAMS (TOP VIEW)
DIL-24 (N or J, DW PACKAGES)
(TOP VIEW)
Terminal Functions
TERMINAL I/O DESCRIPTION
N or
NAME Q
DW
Output of the buck PWM controller. The BUCK output is a floating driver, optimized for controlling the
BUCK 2 3 O gate of an N-channel MOSFET. The peak sink and source currents are 1 A. VCC undervoltage faults
disables BUCK to an off condition (low).
CEA+ 12 13 I Non-inverting input of the current error amplifier.
CEA- 13 14 I Inverting input of the current error amplifier
Output of the current error amplifier and the inverting input of the PWM comparator of the buck
CEAO 6 7 O converter.
CSA+ 8 9 I Noninverting input of the current sense amplifier.
CSA–9 10 I Inverting input of the current sense amplifier.
Output of the current sense amplifier and the noninverting input of the current limit comparator. When
the signal level on this pin exceeds the 3V threshold of the current limit comparator, the buck gate drive
CSAO 7 8 O pulse is terminated. This feature is useful to implement cycle-by-cycle current limiting for the buck
converter.
Provides for the timing capacitor which is connected between CT and GND. The oscillator frequency is
set by CT and a resistor RT, connected between pin RT and GND. The CT discharge current is
CT 18 20 I approximately 40 x the bias current through the resistor connected to RT. A practical maximum value for
the discharge current is 20 mA. The frequency of the oscillator is given by equation(1)
A resistor to GND programs the overlap time of the PUSH and PULL outputs of the UC3827-1 and the
DELAY 20 22 I dead time of the PUSH and PULL outputs of the UC3827-2. The minimum value of the resistor, RDELAY,
is 18 kΩ. The delay or overlap time is given by equation(2)
Ground reference for all sensitive setup components not related to driving the outputs. They include all
GND 11 12 - timing, voltage sense, current sense, and bypass components.
Ground connection for the PUSH and PULL outputs. PGND must be connected to GND at a single point
PGND 21 25 - on the printed circuit board. This is imperative to prevent large, high frequency switching currents
flowing through the ground metalization inside the device.
Ground referenced output to drive an N-channel MOSFET. The PULL and the PUSH outputs are driving
PULL 22 26 O the two switches of the push-pull converter with complementary signals at close to a 50% duty cycle.
Any undervoltage faults will disable PULL to an off condition (low).
Copyright ©1999–2011, Texas Instruments Incorporated 5
IRT +2.5 V
RRT
(3)
UC2827-1, UC2827-2
UC3827-1, UC3827-2
SLUS365D –APRIL 1999–REVISED APRIL 2011
www.ti.com
Terminal Functions (continued)
TERMINAL I/O DESCRIPTION
N or
NAME Q
DW
Ground referenced output to drive an N-channel MOSFET. The PULL and the PUSH outputs are driving
PUSH 24 28 O the two switches of the push-pull converter with complementary signals at close to a 50% duty cycle.
Any undervoltage faults disables PUSH to an off condition (low).
The RAMP voltage, after a 700 mV internal level shift, is fed to the noninverting input of the buck PWM
comparator. A resistor to VIN and a capacitor to GND provide an input voltage feedforward signal for the
buck controller in voltage mode control. In peak current mode control, the RAMP pin receives the
RAMP 5 6 I current signal of the buck converter. In an average current mode setup, the RAMP pin has a linearly
increasing ramp signal. This waveform may be generated either by connecting RAMP directly to CT, or
by connecting both a resistor from VCC to RAMP and a capacitor from RAMP to GND.
The output of the +5V on board reference. Bypass this pin with a capacitor to GND. The reference is off
REF 15 16 O when the chip is in undervoltage lockout mode.o
A resistor to GND programs the charge current of the timing capacitor connected to CT. The charge
current approximately equals that shown in equation(3). The charge current should be less than 500 µA
RT 17 19 I to keep CT's discharge peak current less than 20 mA, which is CT's maximum practical discharge value.
The discharge time, which sets the maximum duty cycle, is set internally and is influenced by the charge
current.
The source connection for the floating buck switch. The voltage on the SRC pin can exceed VCC but
SRC 3 4 I must be lower than 90 V–VVCC. Also, during turn-off transients of the buck switch, the voltage at SRC
can go to –2V.
5Soft-start pin requires a capacitor to GND. During soft-start the output of the voltage error amplifier is
SS 4 5 O clamped to the soft-start capacitor voltage which is slowly charged by an internal current source. In
UVLO, SS is held low.
A bidirectional pin for the oscillator., used to synchronize several chips to the fastest oscillator. Its input
synchronization threshold is 1.4 V. The SYNC voltage is 3.6 V when the oscillator capacitor, CT, is
SYNC 19 21 I discharged. Otherwise it is 0 V. If the recommended synchronization circuit is not used, a 1 kΩor lower
value resistor from SYNC to GND may be needed to increase the fall time of the signal at SYNC.
A voltage source connected to this pin supplies the power for the UC3827. It is recommended to bypass
VCC 23 27 I this pin to both GND and PGND ground connections with good quality high frequency capacitors
VEA+ 14 15 I Non-inverting input of the voltage error amplifier
VEA- 16 18 I Inverting input of the voltage error amplifier
VEAO 10 11 O Output of the voltage error amplifier
Supply voltage for the buck output. The floating driver of the UC3827 uses the bootstrap technique
which requires a reservoir capacitor to store the required energy for the on time of the buck switch. A
V+ 1 1 I diode must be connected from VCC to V+ to charge the reservoir capacitor. This diode must be able to
withstand VIN. The reservoir capacitor must be connected between V+ and SRC.
6Copyright ©1999–2011, Texas Instruments Incorporated
+
–
RT
CT
SYNC
S
R
VREF
2.5 V
OSCILLATOR
VREF
10 kW
1.4 V
2.5 V
2.9 V
0.5 V
RT
CT
VDG−99086
IRT +2.5 V
RRT
UC2827-1, UC2827-2
UC3827-1, UC3827-2
www.ti.com
SLUS365D –APRIL 1999–REVISED APRIL 2011
APPLICATION INFORMATION
Figure 1. Oscillator Block With External Connections
CIRCUIT BLOCK DESCRIPTION
PWM Oscillator
The oscillator block diagram with external connections is shown in Equation 1. A resistor (RT) connected to pin
RT sets the linear charge current:
(1)
The timing capacitor (CCT) is linearly charged with the charge current forcing the OSC pin to charge to a 3.4 V
threshold. After exceeding this threshold, the RS flip-flop is set driving CLKSYN high and RDEAD low which
discharges CCT. CT continues to discharge until it reaches a 0.5 V threshold and resets the RS flip-flop which
repeats the charging sequence as shown in Figure 2
As shown in Figure 3, several oscillators are synchronized to the highest free running frequency by connecting
100 pF capacitors in series with each CLKSYN pin and connecting the other side of the capacitors together
forming the CLKSYN bus. The CLKSYN bus is then pulled down to ground with a resistance of approximately
10k. Referring to Figure 1, the synchronization threshold is 1.4 V. The oscillator blanks any synchronization pulse
that occurs when OSC is below 2.5 V. This allows units, once they discharge below 2.5 V, to continue through
the current discharge and subsequent charge cycles whether or not other units on the CLKSYN bus are still
synchronizing. This requires the frequency of all free running oscillators to be within 17% of each other to assure
synchronization.
Copyright ©1999–2011, Texas Instruments Incorporated 7
OSC
CLKSYN
OUT
THRESHOLD
Charging
VAO Current
Command Discharging
Threshold
2.9 V
0.5 V
3.6 V
1.4 V
8.5 V
0 V VDG−99087
UC2827-1, UC2827-2
UC3827-1, UC3827-2
SLUS365D –APRIL 1999–REVISED APRIL 2011
www.ti.com
Figure 2. Oscillator and PWM Output Waveform
Figure 3. Oscillator Synchronization Connection Diagram
REVISION HISTORY
REVISION DATE OF CHANGE DESCRIPTION
Improved CMRR of CSA from ( 0 - 2 V) to ( -0.3 - 2 V)
SLUS365A 8/2005 Improved CMRR of CEA from ( 0 - 5 V) to ( -0.3 - 5 V)
SLUS365D 4/2011 Updated the Thermal Information Section
8Copyright ©1999–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 23-Jul-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UC2827DW-1 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
UC2827DW-1G4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
UC2827DW-2 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
UC2827DW-2G4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
UC2827DWTR-1 ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
UC2827DWTR-1G4 ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
UC2827N-1 ACTIVE PDIP N 24 15 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Purchase Samples
UC2827N-1G4 ACTIVE PDIP N 24 15 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Purchase Samples
UC3827DW-1 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
UC3827DW-1G4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
UC3827DW-2 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
UC3827DW-2G4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
UC3827N-1 ACTIVE PDIP N 24 15 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
UC3827N-1G4 ACTIVE PDIP N 24 15 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
UC3827N-2 ACTIVE PDIP N 24 15 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
UC3827N-2G4 ACTIVE PDIP N 24 15 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 23-Jul-2010
Addendum-Page 2
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC3827-1 :
•Military: UC1827-1
NOTE: Qualified Version Definitions:
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UC2827DWTR-1 SOIC DW 24 2000 330.0 24.4 10.85 15.8 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UC2827DWTR-1 SOIC DW 24 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MPDI006B – SEPTEMBER 2001 – REVISED APRIL 2002
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
N (R–PDIP–T24) PLASTIC DUAL–IN–LINE
0.020 (0,51) MIN
0.021 (0,53)
0.015 (0,38)
0.100 (2,54)
1
24
0.070 (1,78) MAX 12
13
1.222 (31,04) MAX
0.125 (3,18) MIN
0’–15’
0.010 (0,25) NOM
0.425 (10,80) MAX
Seating Plane
0.200 (5,08) MAX
0.360 (9,14) MAX
0.010 (0,25)
4040051–3/D 09/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS–010
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