© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 10 1Publication Order Number:
NCP2890/D
NCP2890, NCV2890
1.0 Watt Audio Power
Amplifier
The NCP2890 is an audio power amplifier designed for portable
communication device applications such as mobile phone
applications. The NCP2890 is capable of delivering 1.0 W of
continuous average power to an 8.0 BTL load from a 5.0 V power
supply, and 320 mW to a 4.0 BTL load from a 2.6 V power supply.
The NCP2890 provides high quality audio while requiring few
external components and minimal power consumption. It features a
low−power consumption shutdown mode, which is achieved by
driving the SHUTDOWN pin with logic low.
The NCP2890 contains circuitry to prevent from “pop and click”
noise that would otherwise occur during turn−on and turn−off
transitions.
For maximum flexibility, the NCP2890 provides an externally
controlled gain (with resistors), as well as an externally controlled
turn−on time (with the bypass capacitor).
Due to its excellent PSRR, it can be directly connected to the
battery, saving the use of an LDO.
This device is available in a 9−Pin Flip−Chip CSP (standard
Tin−Lead and Lead−Free versions) and a Micro8t package.
Features
•1.0 W to an 8.0 BTL Load from a 5.0 V Power Supply
•Excellent PSRR: Direct Connection to the Battery
•“Pop and Click” Noise Protection Circuit
•Ultra Low Current Shutdown Mode
•2.2 V−5.5 V Operation
•External Gain Configuration Capability
•External Turn−on Time Configuration Capability
•Up to 1.0 nF Capacitive Load Driving Capability
•Thermal Overload Protection Circuitry
•AEC−Q100 Qualified Part Available
•Pb−Free Packages are Available
•NCV Prefix for Automotive and Other Applications Requiring Site
and Control Changes
Typical Applications
•Portable Electronic Devices
•PDAs
•Wireless Phones
9−Pin Flip−Chip CSP
FC SUFFIX
CASE 499E
PIN CONNECTIONS
XXX = Specific Device Code,
A, R = Assembly Location
Y = Year
WW, W = W ork Week
G= Pb−Free Package
MARKING
DIAGRAMS
A3
B3
C3
A2
B2
C2
A1
B1
C1
INM OUTA INP
VM_P VM Vp
BYPASS OUTB SHUTDOWN
8
7
6
5
1
2
3
4
Micro8
DM SUFFIX
CASE 846A
S
HUTDOWN
BYPASS
INP
INM
OUTB
VM
Vp
OUTA
1
8
9−Pin Flip−Chip CSP
Micro8
(Top View)
(Top View)
1
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
ORDERING INFORMATION
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XXX
AYWWG
A1
A3
C
1
XXX
RYWG
G
1
8
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Figure 1. Typical Audio Amplifier Application Circuit with Single Ended Input
+
−
+
−
Vp
INM
Vp
Vp
300 k
300 k
8
OUTA
OUTB
R1
20 k
R2
20 k
INP
BYPASS
20 k
1 F
390 nF
VMVM_P
SHUTDOWN
CONTROL
Cbypass
20 k
1 FCs
SHUTDOWN
Rf
Ri
Ci
AUDIO
INPUT
VIH
VIL
Figure 2. Typical Audio Amplifier Application Circuit with a Differential Input
+
−
+
−
Vp
INM
Vp
Vp
300 k
300 k
8
OUTA
OUTB
R1
20 k
R2
20 k
INP
BYPASS
20 k
1 F
390 nF
VMVM_P
SHUTDOWN
CONTROL
Cbypass
20 k
1 FCs
SHUTDOWN
Rf
Ri
Ci
AUDIO
INPUT
VIH
VIL
20 k
390 nF
Ri
Ci
+
−
20 kRf
This device contains 671 active transistors and 1899 MOS gates.
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PIN DESCRIPTION
9−Pin Flip−Chip
CSP Micro8 Type Symbol Description
A1 4 I INM Negative input of the first amplifier, receives the audio input signal. Connected to
the feedback resistor Rf and to the input resistor Rin.
A2 5 O OUTA Negative output of the NCP2890. Connected to the load and to the feedback
resistor Rf.
A3 3 I INP Positive input of the first amplifier , receives the common mode voltage.
B1 NA I VM_P Power Analog Ground.
B2 7 I VM Core Analog Ground.
B3 6 I VpPositive analog supply of the cell. Range: 2.2 V−5.5 V.
C1 2 I BYPASS Bypass capacitor pin which provides the common mode voltage (Vp/2).
C2 8 O OUTB Positive output of the NCP2890. Connected to the load.
C3 1 I SHUTDOWN The device enters in shutdown mode when a low level is applied on this pin.
MAXIMUM RATINGS (Note 1)
Rating Symbol Value Unit
Supply Voltage Vp6.0 V
Operating Supply Voltage Op Vp 2.2 to 5.5 V
2.0 V = Functional Only −
Input Voltage Vin −0.3 to Vcc +0.3 V
Max Output Current Iout 500 mA
Power Dissipation (Note 2) Pd Internally Limited −
Operating Ambient Temperature TA−40 to +85 °C
Max Junction Temperature TJ150 °C
Storage Temperature Range Tstg −65 to +150 °C
Thermal Resistance Junction−to−Air Micro8
9−Pin Flip−Chip CSP RJA 230
(Note 3) °C/W
ESD Protection Human Body Model (HBM) (Note 4)
Machine Model (MM) (Note 5) − 8000
>250 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may af fect
device reliability.
1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = +25°C.
2. The thermal shutdown set to 160°C (typical) avoids irreversible damage on the device due to power dissipation. For further information see
page 10.
3. For the 9−Pin Flip−Chip CSP package, the RJA is highly dependent of the PCB Heatsink area. For example, RJA can equal 195°C/W with
50 mm2 total area and also 135°C/W with 500 mm2. For further information see page 10. The bumps have the same thermal resistance and
all need to be connected to optimize the power dissipation.
4. Human Body Model, 100 pF discharge through a 1.5 k resistor following specification JESD22/A114.
5. Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
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ELECTRICAL CHARACTERISTICS Limits apply for TA between −40°C to +85°C (Unless otherwise noted).
Characteristic Symbol Conditions Min
(Note 6) Typ Max
(Note 6) Unit
Supply Quiescent Current Idd Vp = 2.6 V, No Load
Vp = 5.0 V, No Load −
−1.5
1.7 4 mA
Vp = 2.6 V, 8
Vp = 5.0 V, 8
−
−1.7
1.9 5.5
Common Mode Voltage Vcm − − Vp/2 − V
Shutdown Current ISD − − 10 600 nA
Shutdown Voltage High VSDIH − 1.2 − − V
Shutdown Voltage Low VSDIL − − − 0.4 V
Turning On Time (Note 8) TWU Cby = 1 F − 285 − ms
Output Swing Vloadpeak Vp = 2.6 V, RL = 8.0
Vp = 5.0 V, RL = 8.0 (Note 7) 2.0
4.0 2.12
4.15 −
−V
Rms Output Power POVp = 2.6 V, RL = 4.0
THD + N < 0.1%
Vp = 2.6 V, RL = 8.0
THD + N < 0.1%
Vp = 5.0 V, RL = 8.0
THD + N < 0.1%
−
−
0.36
0.28
1.08
−
−
W
Maximum Power Dissipation (Note 8) PDmax Vp = 5.0 V, RL = 8.0 − − 0.65 W
Output Offset Voltage VOS Vp = 2.6 V
Vp = 5.0 V −30 30 mV
Signal−to−Noise Ratio SNR Vp = 2.6 V, G = 2.0
10 Hz < F < 20 kHz
Vp = 5.0 V, G = 10
10 Hz < F < 20 kHz
−
−
84
77
−
−
dB
Positive Supply Rejection Ratio PSRR V+ G = 2.0, RL = 8.0
Vpripple_pp = 200 mV
Cby = 1.0 F
Input Terminated with 10
F = 217 Hz
Vp = 5.0 V
Vp = 3.0 V
Vp = 2.6 V
F = 1.0 kHz
Vp = 5.0 V
Vp = 3.0 V
Vp = 2.6 V
−
−
−
−
−
−
−64
−72
−73
−64
−74
−75
−
−
−
−
−
−
dB
Efficiency Vp = 2.6 V, Porms = 320 mW
Vp = 5.0 V, Porms = 1.0 W −
−48
63 −
−%
Thermal Shutdown Temperature (Note 9) Tsd 140 160 180 °C
Total Harmonic Distortion THD Vp = 2.6, F = 1.0 kHz
RL = 4.0 AV = 2.0
PO = 0.32 W
Vp = 5.0 V, F = 1.0 kHz
RL = 8.0 AV = 2.0
PO = 1.0 W
−
−
−
−
−
−
−
0.04
−
−
0.02
−
−
−
−
−
−
−
%
6. Min/Max limits are guaranteed by design, test or statistical analysis.
7. This parameter is not tested in production for 9−Pin Flip−Chip CSP package in case of a 5.0 V power supply.
8. See page 11 for a theoretical approach of this parameter .
9. For this parameter, the Min/Max values are given for information.
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TYPICAL PERFORMANCE CHARACTERISTICS
Figure 1. THD + N versus Frequency
10 100 1000 10,000 100,000
1
0.001
0.1
THD + N (%)
FREQUENCY (Hz) Figure 2. THD + N versus Frequency
10 100 1000 10,000 100,00
0
1
0.001
0.1
THD + N (%)
FREQUENCY (Hz)
Vp = 5 V
RL = 8
Pout = 250 mW
AV = 2
Vp = 3.3 V
RL = 8
Pout = 150 mW
AV = 2
Figure 3. THD + N versus Frequency
10 100 1000 10,000 100,000
1
0.001
0.1
THD + N (%)
FREQUENCY (Hz) Figure 4. THD + N versus Frequency
10 100 1000 10,000 100,00
0
1
0.001
0.1
THD + N (%)
FREQUENCY (Hz)
Vp = 3 V
RL = 8
Pout = 250 mW
AV = 2
Vp = 2.6 V
RL = 8
Pout = 100 mW
AV = 2
Figure 5. THD + N versus Frequency
10 100 1000 10,000 100,000
1
0.001
0.1
THD + N (%)
FREQUENCY (Hz) Figure 6. THD + N versus Power Out
0 200 400 1000 140
0
10
0.001
0.1
THD + N (%)
Pout, POWER OUT (mW)
Vp = 2.6 V
RL = 4
Pout = 100 mW
AV = 2
Vp = 5 V
RL = 8
1 kHz
AV = 2
1
600 800 1200
0.01 0.01
0.01 0.01
0.01 0.01
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TYPICAL PERFORMANCE CHARACTERISTICS
Figure 7. THD + N versus Power Out
0 100
10
0.001
0.1
THD + N (%)
Pout, POWER OUT (mW) Figure 8. THD + N versus Power Out
0 100 200 300
10
0.001
0.1
THD + N (%)
Pout, POWER OUT (mW)
Vp = 3.3 V
RL = 8
1 kHz
AV = 2
Vp = 3 V
RL = 8
1 kHz
AV = 2
Figure 9. THD + N versus Power Out
0 100 200 300 400
10
0.001
0.1
THD + N (%)
Pout, POWER OUT (mW) Figure 10. THD + N versus Power Out
0 100 200 300 50
0
10
0.01
0.1
THD + N (%)
Pout, POWER OUT (mW)
Vp = 2.6 V
RL = 8
1 kHz
AV = 2
Vp = 2.6 V
RL = 4
1 kHz
AV = 2
Figure 11. Output Power versus Power Supply
2.0 3.5 4.0 4.5 5.0
1700
100
700
OUTPUT POWER (mW)
POWER SUPPLY (V)
1
200 300 400 500 600
1
400 50
0
11
300
500
1100
1500
0.01 0.01
0.01
400
Figure 12. P
SRR
@ V
p
= 5 V
10 100 1000 10,000 100,00
0
−30
−70
−50
PSRR (dB)
FREQUENCY (Hz)
−65
−60
−55
−45
−40
−35 Vp = 5 V
RL = 8
Rin = 10
AV = 2
Vripple = 200 mVpk−pk
Cbypass = 1 F
THD+N = 10%
THD+N = 1%
f = 1 kHz
RL = 8
900
1300
3.02.5
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TYPICAL PERFORMANCE CHARACTERISTICS
10 100
−25
−55
PSRR (dB)
FREQUENCY (Hz)
10 100 1000
−10
−100
−90
PSRR (dB)
FREQUENCY (Hz) 10 100 1000 10,000 100,00
0
−30
−80
−75
PSRR (dB)
FREQUENCY (Hz)
10 100 1000 10,000 100,00
0
−25
−70
−50
PSRR (dB)
FREQUENCY (Hz)
−35
1000 10,000 100,00
0
−50
10,000 100,000
−55
−65
−60
−55
−45
−40
−35
Vp = 3 V
RL = 8
Rin = 10
AV = 4
Vripple = 200 mVpk−pk
Cbypass = 1 F
−65
−60
−50
−45
−40
Vp = 5 V
RL = 8
Rin = 10
AV = 4
Vripple = 200 mVpk−pk
Cbypass = 1 F
−80
−70
−60
−30
−40
Vp = 5 V
RL = 8
Rin = Float
AV = 4
Vripple = 200 mVpk−pk
Cbypass = 1 F
−70
−65
−60
−50
−45
−40
−35 Vp = 3 V
RL = 8
Rin = 10
AV = 2
Vripple = 200 mVpk−pk
Cbypass = 1 F
10 100 1000
−20
−90
PSRR (dB)
FREQUENCY (Hz)
−50
10,000 100,000
−80
−70
−60
−30
−40
Vp = 3 V
RL = 8
Rin = Float
AV = 2
Vripple = 200 mVpk−pk
Cbypass = 1 F
−100
−30
−20
−30
Figure 13. PSRR @ Vp = 5 V
10 100 10,000 100,000
−20
−100
−90
PSRR (dB)
FREQUENCY (Hz)
−50
1000
−80
−70
−60
−30
−40
Vp = 5 V
RL = 8
Rin = Float
AV = 2
Vripple = 200 mVpk−pk
Cbypass = 1 F
Figure 14. PSRR @ Vp = 5 V
Figure 15. PSRR @ Vp = 5 V Figure 16. PSRR @ Vp = 3 V
Figure 17. PSRR @ Vp = 3 V Figure 18. PSRR @ Vp = 3 V
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TYPICAL PERFORMANCE CHARACTERISTICS
10 100
−30
−75
−55
PSRR (dB)
FREQUENCY (Hz)
10 100 1000
−20
−100
−90
PSRR (dB)
FREQUENCY (Hz) 10 100 1000 10,000 100,00
0
−30
−80
−75
PSRR (dB)
FREQUENCY (Hz)
10 100 1000 10,000 100,00
0
−30
−70
−50
PSRR (dB)
FREQUENCY (Hz)
−35
1000 10,000 100,00
0
−50
10,000 100,000
−55
−65
−60
−55
−45
−40
−35 Vp = 5 V
RL = 8
Rin = 10
AV = 2
Vripple = 200 mVpk−pk
−70
−65
−60
−50
−45
−40
Vp = 3.3 V
RL = 8
Rin = 10
AV = 2
Vripple = 200 mVpk−pk
Cbypass = 1 F
−80
−70
−60
−30
−40
Vp = 3.3 V
RL = 8
Rin = Float
AV = 2
Vripple = 200 mVpk−pk
Cbypass = 1 F
−70
−65
−60
−50
−45
−40
−35 Vp = 2.6 V
RL = 8
Rin = 10
AV = 2
Vripple = 200 mVpk−pk
Cbypass = 1 F
10 100 1000
−20
−90
PSRR (dB)
FREQUENCY (Hz)
−50
10,000 100,000
−80
−70
−60
−30
−40
Vp = 2.6 V
RL = 8
Rin = Float
AV = 2
Vripple = 200 mVpk−pk
Cbypass = 1 F
−100
1 F
2.2 F
Figure 19. PSRR @ Vp = 3 V
10 100 1000 10,000 100,000
−100
−90
PSRR (dB)
FREQUENCY (Hz)
−80
−70
−60
−50
−40
−30
−20 Vp = 3 V
RL = 8
Rin = Float
AV = 4
Vripple = 200 mVpk−pk
Cbypass = 1 F
−10
Figure 20. PSRR @ Vp = 3.3 V
Figure 21. PSRR @ Vp = 3.3 V Figure 22. PSRR @ Vp = 2.6 V
Figure 23. PSRR @ Vp = 2.6 V Figure 24. PSRR versus Cbypass @ Vp = 5 V
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TYPICAL PERFORMANCE CHARACTERISTICS
DC OUTPUT VOLT AGE (V)
DC OUTPUT VOLTAGE (V) −2.5 −1.5 −1 0.5 2.
5
0
−80
−60
PSRR (dB)
DC OUTPUT VOLTAGE (V)
−20
−2 −0.5 0 1 1.5 2
−70
−50
−30
−40
−10 Vp = 2.6 V
RL = 8
F = 217 Hz
AV = 2
Vripple = 200 mVpk−pk
Cbypass = 1 F
−5 −3 −2 1
5
0
−80
−60
PSRR (dB)
−20
−4 −1 0 2 3 4
−70
−50
−30
−40
−10 Vp = 5 V
RL = 8
F = 217 Hz
AV = 2
Vripple = 200 mVpk−pk
Cbypass = 1 F
−2.5 −1.5 −1 0.5 2.5
0
−90
−60
PSRR (dB)
−20
−2 −0.5 0 1 1.5 2
−70
−50
−30
−40
−10 Vp = 3 V
RL = 8
F = 217 Hz
AV = 2
Vripple = 200 mVpk−pk
Cbypass = 1 F
−80
Figure 25. PSRR versus Cbypass @ Vp = 3 V
10 100 1000 10,000 100,000
−30
−80
−75
PSRR (dB)
FREQUENCY (Hz)
−55
−70
−65
−60
−50
−45
−40
−35 Vp = 3 V
RL = 8
Rin = 10
AV = 2
Vripple = 200 mVpk−pk
1 F
2.2 F
Figure 26. PSRR @ DC Output Voltage
Figure 27. PSRR @ DC Output Voltage Figure 28. PSRR @ DC Output Voltage
Figure 29. Turning On T ime − V
p
= 5 V Figure 30. Turning Off T ime − V
p
= 5 V
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TYPICAL PERFORMANCE CHARACTERISTICS
Figure 31. Power Dissipation versus Output
Power
0 0.2
0.7
0
0.1
P
D
, POWER DISSIPA TION (W)
Pout, OUTPUT POWER (W) Figure 32. Power Dissipation versus Output
Power
0 0.1 0.2 0.3
0.3
0
0.1
PD, POWER DISSIPATION (W)
Pout, OUTPUT POWER (W)
Vp = 5 V
RL = 8
F = 1 kHz
THD + N < 0.1%
Vp = 3.3 V
RL = 8
F = 1 kHz
THD + N < 0.1%
Figure 33. Power Dissipation versus Output
Power
0 0.1 0.2 0.3 0.4
0.25
0
0.05
P
D
, POWER DISSIPA TION (W)
Pout, OUTPUT POWER (W) Figure 34. Power Dissipation versus Output
Power
0 0.05 0.1 0.15 0.4
0.4
0
0.1
PD, POWER DISSIPATION (W)
Pout, OUTPUT POWER (W)
Vp = 3 V
RL = 8
F = 1 kHz
THD + N < 0.1%
Figure 35. Power Derating − 9−Pin Flip−Chip CSP
0 20 160
700
0
P
D
, POWER DISSIPA TION (mW)
TA, AMBIENT TEMPERATURE (°C) Figure 36. Maximum Die Temperature versus
PCB Heatsink Area
50 100 250
180
40
60
DIE TEMPERATURE (°C) @
AMBIENT TEMPERATURE 25°C
PCB HEATSINK AREA (mm2)
120
150 200
0.5
0.4 0.6 0.8 1 1.2
0.2
0.4 0.
5
0.1
100
200
300
400
500
600
80
100
160
140
PDmax = 633 mW
for Vp = 5 V,
RL = 8
0.2
0.3
0.4
0.6
0.05
0.15
0.25
0.15
0.2
0.2 0.25 0.3 0.35
0.05
0.2
0.15
0.3
0.25
0.35
Vp = 2.6 V
F = 1 kHz
THD + N < 0.1%
RL = 8
RL = 4
40 60 80 100 120 140
PCB Heatsink Area
500 mm2
50 mm2
200 mm2
300
Maximum Die Temperature 150°C
Vp = 2.6 V
Vp = 5 V
Vp = 3.3 V
Vp = 4.2 V
RL = 8
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APPLICATION INFORMATION
Detailed Description
The NCP2890 audio amplifier can operate under 2.6 V
until 5.5 V power supply. It delivers 320 mW rms output
power to 4.0 load (Vp = 2.6 V) and 1.0 W rms output
power to 8.0 load (Vp = 5.0 V).
The structure of the NCP2890 is basically composed of
two identical internal power amplifiers; the first one is
externally configurable with gain−setting resistors Rin and
Rf (the closed−loop gain is fixed by the ratios of these
resistors) and the second is internally fixed in an inverting
unity−gain configuration by two resistors of 20 k. So the
load is driven differentially through OUTA and OUTB
outputs. This configuration eliminates the need for an
output coupling capacitor.
Internal Power Amplifier
The output PMOS and NMOS transistors of the amplifier
were designed to deliver the output power of the
specifications without clipping. The channel resistance
(Ron) of the NMOS and PMOS transistors does not exceed
0.6 when they drive current.
The structure of the internal power amplifier is
composed of three symmetrical gain stages, first and
medium gain stages are transconductance gain stages to
obtain maximum bandwidth and DC gain.
Turn−On and Turn−Off Transitions
A cycle with a turn−on and turn−off transition is
illustrated with plots that show both single ended signals on
the previous page.
In order to eliminate “pop and click” noises during
transitions, output power in the load must be slowly
established or cut. When logic high is applied to the
shutdown pin, the bypass voltage begins to rise
exponentially and once the output DC level is around the
common mode voltage, the gain is established slowly
(50 ms). This way to turn−on the device is optimized in
terms of rejection of “pop and click” noises.
The device has the same behavior when it is turned−off
by a logic low on the shutdown pin. During the shutdown
mode, amplifier outputs are connected to the ground.
When a shutdown low level is applied, it takes 350 ms
before the DC output level is tied to Ground. However, as
shown on Figure 30, the turn off time of the audio signal is
40 ms.
A theoretical value of turn−on time at 25°C is given by
the following formula.
Cby: bypass capacitor
R: internal 300 k resistor with a 25% accuracy
Ton = 0.95 * R * Cby (285 ms with Cby = 1 F)
If a faster turn on time is required then a lower bypass
capacitor can be used. The other option is to use NCP2892
which offers 100 ms with 1 F bypass capacitor.
Shutdown Function
The device enters shutdown mode when shutdown signal
is low. During the shutdown mode, the DC quiescent
current of the circuit does not exceed 100 nA.
Current Limit Circuit
The maximum output power of the circuit (Porms =
1.0 W, Vp = 5.0 V, RL = 8.0 ) requires a peak current in
the load of 500 mA.
In order to limit the excessive power dissipation in the
load when a short−circuit occurs, the current limit in the
load is fixed to 800 mA. The current in the four output MOS
transistors are real−time controlled, and when one current
exceeds 800 mA, the gate voltage of the MOS transistor is
clipped and no more current can be delivered.
Thermal Overload Protection
Internal amplifiers are switched off when the
temperature exceeds 160°C, and will be switched on again
only when the temperature decreases fewer than 140°C.
The NCP2890 is unity−gain stable and requires no
external components besides gain−setting resistors, an
input coupling capacitor and a proper bypassing capacitor
in the typical application.
The first amplifier is externally configurable (Rf and
Rin), while the second is fixed in an inverting unity gain
configuration.
The differential−ended amplifier presents two major
advantages:
− The possible output power is four times larger (the
output swing is doubled) as compared to a single−ended
amplifier under the same conditions.
− Output pins (OUTA and OUTB) are biased at the same
potential Vp/2, this eliminates the need for an output
coupling capacitor required with a single−ended
amplifier configuration.
The differential closed loop−gain of the amplifier is
given by Avd +2* Rf
Rin +Vorms
Vinrms .
Output power delivered to the load is given by
Porms +(Vopeak)2
2*R
L (Vopeak is the peak differential
output voltage).
When choosing gain configuration to obtain the desired
output power, check that the amplifier is not current limited
or clipped.
The maximum current which can be delivered to the load
is 500 mA Iopeak +Vopeak
RL.
NCP2890, NCV2890
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12
Gain−Setting Resistor Selection (Rin and Rf)
Rin and Rf set the closed−loop gain of the amplifier.
In order to optimize device and system performance, the
NCP2890 should be used in low gain configurations.
The low gain configuration minimizes THD + noise
values and maximizes the signal to noise ratio, and the
amplifier can still be used without running into the
bandwidth limitations.
A closed loop gain in the range from 2 to 5 is
recommended to optimize overall system performance.
An input resistor (Rin) value of 22 k is realistic in most
of applications, and doesn’t require the use of a too large
capacitor Cin.
Input Capacitor Selection (Cin)
The input coupling capacitor blocks the DC voltage at
the amplifier input terminal. This capacitor creates a
high−pass filter with Rin, the cut−off frequency is given by
fc +1
2**Rin *C
in .
The size of the capacitor must be large enough to couple
in low frequencies without severe attenuation. However a
large input coupling capacitor requires more time to reach
its quiescent DC voltage (Vp/2) and can increase the
turn−on pops.
An input capacitor value between 0.1 and 0.39 F
performs well in many applications (With Rin = 22 K).
Bypass Capacitor Selection (Cby)
The bypass capacitor Cby provides half−supply filtering
and determines how fast the NCP2890 turns on.
This capacitor is a critical component to minimize the
turn−on pop. A 1.0 F bypass capacitor value
(Cin = < 0.39 F) should produce clickless and popless
shutdown transitions. The amplifier is still functional with
a 0.1 F capacitor value but is more susceptible to “pop and
click” noises.
Thus, a 1.0 F bypassing capacitor is recommended.
Figure 37. Schematic of the Demonstration Board of the 9−Pin Flip−Chip CSP Device
+
−
+
−
Vp
INM
Vp
Vp
300 k
300 k
8
OUTA
OUTB
20 k
20 k
INP
BYPASS
20 k
1 F
390 nF
VMVM_P
SHUTDOWN
CONTROL
C3
1 FC1
SHUTDOWN
R2
C2
AUDIO
INPUT
Vp
R3
20 k
R4*
R1
100 k
C4*
* R4, C4: Not Mounted
NCP2890, NCV2890
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13
Figure 38. Demonstration Board for 9−Pin Flip−Chip CSP Device − PCB Layers
Silkscreen Layer
Top Layer Bottom Layer
NCP2890, NCV2890
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14
BILL OF MATERIAL
Item Part Description Ref. PCB
Footprint Manufacturer Manufacturer
Reference
1NCP2890 Audio Amplifier − − ON Semiconductor NCP2890
2SMD Resistor 100 KR1 0805 Vishay−Draloric D12CRCW Series
3SMD Resistor 20 KR2, R3 0805 Vishay−Draloric CRCW0805 Series
4Ceramic Capacitor 1.0 F 16 V X7R C1 1206 Murata GRM42−6X7R105K16
5Ceramic Capacitor 390 nF 50 V Z5U C2 1812 Kemet C1812C394M5UAC
6Ceramic Capacitor 1.0 F 16 V X7R C3 1206 Murata GRM42−6X7R105K16
7Not Mounted R4, C4 − − −
8BNC Connector J3 − Telegartner JO1001A1948
9I/O Connector. It can be plugged by BLZ5.08/2
(Weidmüller Reference) J4, J5 − Weidmüller SL5.08/2/90B
ORDERING INFORMATION
Device Marking Package Shipping†
NCP2890AFCT2 MAG 9−Pin Flip−Chip CSP 3000/Tape and Reel
NCP2890AFCT2G MAH 9−Pin Flip−Chip CSP
(Pb−Free) 3000/Tape and Reel
NCP2890DMR2 MAB Micro8 4000/Tape and Reel
NCP2890DMR2G MAB Micro8
(Pb−Free) 4000/Tape and Reel
NCV2890DMR2G MBZ Micro8
(Pb−Free) 4000/Tape and Reel
NOTE: This product is of fered with either eutectic (SnPb−tin/lead) or lead−free solder bumps (G suffix) depending on the PCB assembly
process. The NCP2890AFCT2G version requires a lead−free solder paste and should not be used with a SnPb solder paste.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCP2890, NCV2890
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15
PACKAGE DIMENSIONS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
ǒmm
inchesǓ
SCALE 20:1
0.265
0.01
0.50
0.0197
0.50
0.0197
9 PIN FLIP−CHIP
CASE 499E−01
ISSUE A
DIM MIN MAX
MILLIMETERS
A0.540 0.660
A1 0.210 0.270
A2
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
E
D
−A−
−B−
0.10 C
A2
A
A1
−C−
0.05 C
0.10 C
4 X
SEATING
PLANE
D1
e
E1
e
0.05 C
0.03 C
A B
9 X b
C
B
A
123
D1.450 BSC
E
0.330 0.390
b0.290 0.340
e0.500 BSC
D1 1.000 BSC
E1 1.000 BSC
1.450 BSC
SIDE VIEW
T OP VIEW
BOTTOM VIEW
NCP2890, NCV2890
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16
PACKAGE DIMENSIONS
Micro8t
CASE 846A−02
ISSUE G
S
B
M
0.08 (0.003) A S
T
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
5. 846A−01 OBSOLETE, NEW STANDARD 846A−02.
b
e
PIN 1 ID
8 PL
0.038 (0.0015)
−T− SEATING
PLANE
A
A1 cL
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
8X 8X
6X ǒmm
inchesǓ
SCALE 8:1
1.04
0.041 0.38
0.015
5.28
0.208
4.24
0.167
3.20
0.126
0.65
0.0256
DIM
AMIN NOM MAX MIN
MILLIMETERS
−− −− 1.10 −−
INCHES
A1 0.05 0.08 0.15 0.002
b0.25 0.33 0.40 0.010
c0.13 0.18 0.23 0.005
D2.90 3.00 3.10 0.114
E2.90 3.00 3.10 0.114
e0.65 BSC
L0.40 0.55 0.70 0.016
−− 0.043
0.003 0.006
0.013 0.016
0.007 0.009
0.118 0.122
0.118 0.122
0.026 BSC
0.021 0.028
NOM MAX
4.75 4.90 5.05 0.187 0.193 0.199HE
HE
DD
E
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
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subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
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SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
NCP2890/D
Micro8 is a trademark of International Rectifier Corporation.
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