CD74FCT540 BiCMOS OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCBS740 - JULY 2000 D D D D D D D D D E OR M PACKAGE (TOP VIEW) BiCMOS Technology With Low Quiescent Power Buffered Inputs Inverted Outputs Input/Output Isolation From VCC Controlled Output Edge Rates 64-mA Output Sink Current Output Voltage Swing Limited to 3.7 V SCR Latch-Up-Resistant BiCMOS Process and Circuit Design Package Options Include Plastic Small-Outline (M) Package and Standard Plastic (E) DIP OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 description The CD74FCT540 is an octal buffer/driver with 3-state ouputs that is ideal for driving bus lines or buffer memory address registers and uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 64 mA. The 3-state control gate is a two-input AND gate with active-low inputs, so that if either output-enable (OE1 or OE2) input is high, all corresponding outputs are in the high-impedance state. The outputs provide inverted data when they are not in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The CD74FCT540 is characterized for operation from 0C to 70C. FUNCTION TABLE (each buffer/driver) INPUTS A OUTPUT Y L L H L H L H X X Z X H X Z OE1 OE2 L L Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 CD74FCT540 BiCMOS OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCBS740 - JULY 2000 logic symbol OE1 OE2 A1 A2 A3 A4 A5 A6 A7 A8 1 & 19 EN 2 18 1 3 17 4 16 5 15 6 14 7 13 8 12 9 11 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) OE1 OE2 A1 1 19 2 18 Y1 To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted) DC supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6 V DC input clamp current, IIK (VI < -0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA DC output clamp current, IOK (VO < -0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA DC output sink current per output pin, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA DC output source current per output pin, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -30 mA Continuous current through VCC, ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 mA Continuous current through GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 mA Package thermal impedance, JA (see Note 1): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69C/W M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 CD74FCT540 BiCMOS OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCBS740 - JULY 2000 recommended operating conditions (see Note 2) MIN MAX UNIT 4.75 5.25 V VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 IOL t/v Low-level output current High-level input voltage 2 High-level output current Input transition rise or fall rate 0 V 0.8 V VCC VCC V -15 mA V 64 mA 10 ns/V TA Operating free-air temperature 0 70 C NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25C MIN MAX MIN UNIT -1.2 V VIK VOH II = -18 mA IOH = -15 mA 4.75 V VOL II IOL = 64 mA VI = VCC or GND 4.75 V 0.55 0.55 V 5.25 V 0.1 1 mA IOZ IOS VO = VCC or GND VI = VCC or GND, ICC VI = VCC or GND, One input at 3.4 V, Other inputs at VCC or GND ICC Ci Co 4.75 V -1.2 MAX 2.4 0.5 5.25 V VO = 0 IO = 0 5.25 V 2.4 V 10 -60 -60 mA mA 5.25 V 8 80 mA 5.25 V 1.6 1.6 mA 10 10 pF 15 15 pF VI = VCC or GND VO = VCC or GND Not more than one output should be tested at a time, and the duration of the test should not exceed 100 ms. This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC. switching characteristics over recommended operating conditions, VCC = 5 V 0.25 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TA = 25C TYP tpd A Y ten OE tdis OE MIN MAX UNIT 6.4 2 8.5 ns Y 7.5 2 10 ns Y 7.1 2 9.5 ns TYP MAX noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25C PARAMETER MIN UNIT VOL(P) VOH(V) Quiet output, maximum dynamic VOL 1 V Quiet output, minimum dynamic VOH 0.5 V VIH(D) VIL(D) High-level dynamic input voltage 2 Low-level dynamic input voltage V 0.8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 V 3 CD74FCT540 BiCMOS OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCBS740 - JULY 2000 operating characteristics, TA = 25C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance No load, POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 f = 1 MHz TYP 37 UNIT pF CD74FCT540 BiCMOS OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCBS740 - JULY 2000 PARAMETER MEASUREMENT INFORMATION 7V CL = 50 pF (see Note A) 500 From Output Under Test Test Point From Output Under Test Open TEST GND CL = 50 pF (see Note A) 500 S1 S1 Open 7V Open 7V tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Open Drain LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 90% 1.5 V 10% 3V 1.5 V 10% 0 V 90% tr tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES 3V 1.5 V Timing Input 0V tw tsu 3V 1.5 V 1.5 V Input th 3V 1.5 V 1.5 V Data Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V 1.5 V Input 0V tPLH tPHL 1.5 V 1.5 V VOL tPHL Out-of-Phase Output tPLZ 3.5 V 1.5 V tPZH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V Output Waveform 1 (see Note B) tPLH 1.5 V 1.5 V tPZL VOH In-Phase Output 3V Output Control Output Waveform 2 (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V V VOH - 0.3 V OH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr and tf = 2.5 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) CD74FCT540E OBSOLETE PDIP N 20 TBD Call TI Call TI CD74FCT540M OBSOLETE SOIC DW 20 TBD Call TI Call TI CD74FCT540M96 OBSOLETE SOIC DW 20 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. 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