Full-speed Universal Serial Bus single-chip host and device

Rev. 01 — 20 December 2002 Product data

1. General description

Device Controller (DC). The Host Controller portion of the ISP1161A1 complies with

Universal Serial Bus Specification Rev. 2.0,

supporting data transfer at full-speed

acknowledge input pins. This makes it possible for a microprocessor to control both

the USB HC and the USB DC at the same time.

The ISP1161A1 provides two downstream ports for the USB HC and one upstream

pin and power supply switching control output pin. The upstream port has a VBUS

detection input pin.The ISP1161A1 also provides separate wake-up input pins and

suspended status output pins for the USB HC and the USB DC, respectively. This

makes power management flexible. The downstream ports for the HC can be

The ISP1161A1 is well suited for embedded systems and portable devices that

require a USB host only, a USB device only, or a combination of a configurable USB

host and USB device. The ISP1161A1 brings high flexibility to the systems that have

it built-in. For example, a system that uses an ISP1161A1 allows it not only to be

connected to a PC or USB hub with a USB downstream port, but also to be

connected to a device that has a USB upstream port such as a USB printer, USB

camera, USB keyboard or a USB mouse. Therefore, the ISP1161A1 enables

point-to-point connectivity between embedded systems. An interesting application

example is to connect an ISP1161A1 HC with an ISP1161A1 DC.

Consider an example of an ISP1161A1 being used in a Digital Still Camera (DSC)

Universal Serial Bus Specification Rev. 2.0

(12 Mbit/s) and low-speed (1.5 Mbit/s)

full-speed (12 Mbit/s)

11.1 Mbyte/s data transfer rate between the microprocessor and the DC

transfer for both DC transfers and HC isochronous (ISO) transactions

for HC and DC

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Philips Semiconductors ISP1161A1

USB bus

BUS I/F

clock recovery

3.3 V

6. Pinning information

8.4 FIFO buffer RAM access by PIO mode

buffer RAM is mapped to dedicated register fields. Therefore, accessing the internal

FIFO buffer RAM is similar to accessing the internal control registers in multiple data

phases.

write cycle, the microprocessor first writes the FIFO buffer RAM’s command code to

the command port, and then writes the data words one by one to the data port until

8.5 FIFO buffer RAM access by DMA mode

The DMA interface between a microprocessor and the ISP1161A1 is shown in

DMA request to the microprocessor via the DREQ pin (DREQ1 for HC, DREQ2

for DC). After receiving this signal, the microprocessor will reply with a DMA

acknowledge via the DACK pin (DACK1 for HC, DACK2 for DC), and at the same

time, execute the DMA transfer through the data bus. In the DMA mode, the

DMACounterSelect of the HcDMAConfiguration register (21H to read, A1H to write)

to logic 1 will enable the DMA counter for DMA transfer. When the DMA counter

reaches the value of the HcTransferCounter register, the internal EOT signal will be

generated to terminate the DMA transfer.

The ISP1161A1 supports either single-cycle DMA operation or burst mode DMA

operation.

The ISP1161A1 has separate interrupt request pins for the USB HC (INT1) and the

USB DC (INT2).

The interrupt output signals have four configuration modes:

Mode 0 Level trigger, active LOW (default at power-up)

Mode 1 Level trigger, active HIGH

Mode 2 Edge trigger, active LOW

Mode 3 Edge trigger, active HIGH.

via the HcHardwareConfiguration register (see Section 10.4.1), which are also used

To program the four configuration modes of the HC’s interrupt output signal (INT1),

set bits InterruptPinTrigger and InterruptOutputPolarity of the

HcHardwareConfiguration register (20H for read, A0H for write).

Bit InterruptPinEnable is used as the master enable setting for pin INT1.

INT1 has many associated interrupt events, as shown as in Figure 20.

write) affect only bit OPR_Reg of the HcµPInterrupt register. They cannot directly

change the status of pin INT1.

There are two groups of interrupts represented by group 1 and group 2 in Figure 20.

A pair of registers control each group.

Group 2 contains six possible interrupt events (recorded in the HcInterruptStatus

logic 1; and if the corresponding bit in the HcInterruptEnable register is also logic 1,

the 6-input OR gate would output a logic 1. This output is ANDed with the value of

MIE (bit 31 of HcInterruptEnable). Logic 1 at the AND gate will cause bit OPR in the

the ISP1161A1 Host Controller, the following procedure should be followed:

set to logic 1.

2. Clear all bits in the HcµPInterrupt register.

3. Set bit InterruptPinEnable to logic 0.

The four configuration modes of DC’s interrupt output pin INT2 can also be

programmed by setting bits INTPOL and INTLVL of the DcHardwareConfiguration

Interrupts can be masked globally by means of bit INTENA of the DcMode register

Event B (see Figure 22): When bit INTENA is set to logic 1, pin INT2 is asserted

because bit SOF in the DcInterrupt register is already asserted.

De-assertion of pin INT2 can be achieved in the following manner. Bits[23:8] of the

DcInterrupt register are endpoint interrupts. These interrupts are cleared on reading

their respective DcEndpointStatus register. Bits[7:0] of the DcInterrupt register are

bus status and EOT interrupts that are cleared on reading the DcInterrupt register.

Make sure that bit INTENA is set to logic 1 when you perform the clear interrupt

commands.

For more information on interrupt control, see Section 13.1.3,Section 13.1.5 and

9. USB host controller (HC)

The ISP1161A1 USB HC has four USB states −USBOperational, USBReset,

responsibilities.

The USB states are reflected in the HostControllerFunctionalState field of the

HcControl register (01H to read, 81H to write), which is located at bits 7 and 6 of the

9.2 Generating USB traffic

USB traffic can be generated only when the ISP1161A1 USB HC is in the

USBOperational state. Therefore, the HCD must set the

HostControllerFunctionalState field of the HcControl register before generating USB

traffic.

A simplistic flow diagram showing when and how to generate USB traffic is shown in

protocol and ISP1161A1 USB HC register usage.

This includes hardware reset by pin RESET and software reset by the

See also Section 9.5.

To generate USB traffic, the HCD must enter the USB transaction loop.

The communication between the HCD and the ISP1161A1 HC is in the form of

Philips Transfer Descriptor (PTD) data. The PTD data provides USB traffic

information about the commands, status, and USB data packets.

The physical storage media of PTD data for the HCD is the microprocessor’s

access port is a 16-bit register. Therefore, each read/write operation on the port

buffer RAM by two. The lower byte of the access port register corresponds to the

data byte at the even location of the buffer RAM, and the upper byte corresponds to

data bytes to be transferred, the command code must be issued merely once, and it

will be followed by a number of accesses of the data port (see Section 8.4).

When the pointer of the buffer RAM reaches the value of the HcTransferCounter

register, an internal EOT signal will be generated to set bit 2, AllEOTInterrupt, of the

HcµPinterrupt register and update the HcBufferStatus register, to indicate that the

buffer RAM. The total number of data bytes to be transferred is 80 (decimal) which

of PTD data:

1. The first PTD header (IN) is 8 bytes, followed by 16 bytes of space reserved for

its payload data;

2. The second PTD header (IN) is also 8 bytes, followed by 8 bytes of space

reserved for its payload data;

values beginning from 0H to FH incrementing by 1;

HcµPInterrupt register) triggers reading and writing of the ITL buffer by the

microprocessor, after which the interrupt is cleared by the microprocessor.

can result.

same frame, bit Active and a TotalBytes field are introduced (see Table 5). Bit Active

In example 2 (Figure 31), the microprocessor is still busy transferring the AT data

AT traffic in frame N + 1. The HC does not raise an AT interrupt in frame N + 1. The

AT part is simply postponed until frame N + 2. On the AT N + 2 interrupt, the transfer

mechanism is back to normal operation. This simple mechanism ensures, among

other things, that Control transfers are not dropped systematically from the USB in

case of an overloaded microprocessor.

In example 3 (Figure 32), the ISO part is still being written while the Start of Frame

The maximum amount of data that can be transferred for an endpoint during one

frame is 1023 bytes. The number of USB packets that are needed for this batch of

data depends on the maximum packet size that is specified.

The HCD has to schedule the transactions in a frame. On the other hand, the HCD

also be able to do the scheduling for the next frame, reading the frame information

end of the current frame and the start of the next frame.

9.7 Internal pull-down resistors for downstream ports

bit 12 is logic 0. If using the internal resistors, the HCD must set this bit status after

every reset, because a reset action (hardware or software) will clear this bit.

9.8 OC detection and power switching control

A downstream port provides 5 V power supply to VBUS. The ISP1161A1 has built-in

hardware functions to monitor the downstream ports loading conditions and control

their power switching. These hardware functions are implemented by the internal

power switching control circuit and overcurrent detection circuit. H_PSW1 and

H_PSW2 are power switching control output pins (active LOW, open-drain) for

input pins for downstream ports 1 and 2, respectively.

bit 12 of the HcHardwareConfiguration register, respectively.

When H_OCn detects an overcurrent status on a downstream port, H_PSWn will

When there is no such condition, H_PSWn will output LOW, a logic 0 to turn on the

5 V power supply to the downstream port VBUS.

In general applications, a P-channel MOSFET can be used as the power switch for

VBUS. Connect the 5 V power supply to the drain of the P-channel MOSFET, VBUS to

the source, and H_PSWn to the gate. Call the voltage drop across the drain and

used instead. Regardless of the VCC value, an external OC detection circuit can

always be used. To use an external OC detection circuit, AnalogOCEnable, bit 10 of

the HcHardwareConfiguration register, must be logic 0. By default after reset, this bit

is already logic 0; therefore, the HCD does not need to clear this bit.