M485L2829MT0 200pin DDR SDRAM SODIMM 1GB DDR SDRAM MODULE (128Mx72 based on stacked 128Mx8 DDR SDRAM) 200pin DIMM 72-bit ECC/Parity Revision 0.0 Sep. 2002 Rev. 0.0 Sep. 2002 M485L2829MT0 200pin DDR SDRAM SODIMM Revision History Revision 0.0 (Sep. 2002) 1. First release for internal usage Rev. 0.0 Sep. 2002 M485L2829MT0 200pin DDR SDRAM SODIMM M485L2829MT0 200pin DDR SDRAM SODIMM 128Mx72 200pin DDR SDRAM SODIMM based on stacked 128Mx8 GENERAL DESCRIPTION FEATURE The Samsung M485L2829MT0 is 128M bit x 72 Double Data * Performance range Part No. Rate SDRAM high density memory modules. The Samsung M485L2829MT0 consists of nine CMOS stacked Max Freq. Interface M485L2829MT0-C(L)A2 133MHz(7.5ns@CL=2) 128M x 8bit with 4banks Double Data Rate SDRAMs in 66pin M485L2829MT0-C(L)B0 133MHz(7.5ns@CL=2.5) TSOP-II (400mil) packages mounted on a 200pin glass-epoxy M485L2829MT0-C(L)A0 100MHz(10ns@CL=2) SSTL_2 substrate. three 0.1uF decoupling capacitors are mounted on ( C : Normal Power_IDD6 , L : Low Power_IDD6 ) * Power supply : Vdd: 2.5V 0.2V, Vddq: 2.5V 0.2V the printed circuit board in parallel for each DDR SDRAM. * Double-data-rate architecture; two data transfers per clock cycle The M485L2829MT0 is Dual In-line Memory Modules and intended for mounting into 200pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * Bidirectional data strobe(DQS) * Differential clock inputs(CK and CK) * DLL aligns DQ and DQS transition with CK transition * Programmable Read latency 2, 2.5 (clock) * Programmable Burst length (2, 4, 8) * Programmable Burst type (sequential & interleave) * Edge aligned data output, center aligned data input * Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) * Serial presence detect with EEPROM * PCB : Height 1,400 mil, double sided component PIN DESCRIPTION PIN CONFIGURATIONS (Front side/back side) Pin Front Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 /CK0 VSS Key DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 67 DQ27 135 DQ34 69 VDD 137 VSS 71 CB0 139 DQ35 73 CB1 141 DQ40 75 VSS 143 VDD 77 *DQS8 145 DQ41 79 CB2 147 DQS5 81 VDD 149 VSS 83 CB3 151 DQ42 85 DU 153 DQ43 87 VSS 155 VDD 89 *CK2 157 VDD 91 */CK2 159 VSS 93 VDD 161 VSS 95 CKE1 163 DQ48 97 DU 165 DQ49 99 A12 167 VDD 101 A9 169 DQS6 103 VSS 171 DQ50 105 A7 173 VSS 107 A5 175 DQ51 109 A3 177 DQ56 111 A1 179 VDD 113 VDD 181 DQ57 115 A10/AP 183 DQS7 117 BA0 185 VSS 119 /WE 187 DQ58 121 /CS0 189 DQ59 123 DU(A13) 191 VDD 125 VSS 193 SDA 127 DQ32 195 SCL 129 DQ33 197 VDDSPD 131 VDD 199 VDDID 133 DQS4 41 43 45 47 49 51 53 55 57 59 61 63 65 Front Pin Front Pin Back Pin Pin Back 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS Key DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 68 DQ31 136 70 VDD 138 72 CB4 140 74 CB5 142 76 VSS 144 78 DM8 146 80 CB6 148 82 VDD 150 84 CB7 152 86 DU/(RESET) 154 88 VSS 156 90 VSS 158 92 VDD 160 94 VDD 162 96 CKE0 164 98 DU(BA2) 166 100 A11 168 102 A8 170 104 VSS 172 106 A6 174 108 A4 176 110 A2 178 112 A0 180 114 VDD 182 116 BA1 184 118 /RAS 186 120 /CAS 188 122 /CS1 190 124 DU 192 126 VSS 194 128 DQ36 196 130 DQ37 198 132 VDD 200 134 DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD /CK1 CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU 42 44 46 48 50 52 54 56 58 60 62 64 66 Back Pin Name * Function A0 ~ A12 Address input (Multiplexed) BA0 ~ BA1 Bank Select Address DQ0 ~ DQ63 Data input/output CB0 ~ CB7 Check bit (Data-in/Data-out) DQS0 ~ DQS7 Data Strobe input/output CK0~CK1 CK0~CK1 Clock input CKE0~CKE1 Clock enable input CS0 ~CS1 Chip select input RAS Row address strobe CAS Column address strobe WE Write enable DM0 ~ DM7 Data - in mask VDD Power supply (2.5V) VDDQ Power Supply for DQS(2.5V) VSS Ground VREF Power supply for reference VDDSPD Serial EEPROM Power Supply (2.3V to 3.6V) SDA Serial data I/O SCL Serial clock SA0 ~ 2 Address in EEPROM NC No connection These pins are not used in this module. SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Rev. 0.0 Sep. 2002 M485L2829MT0 200pin DDR SDRAM SODIMM Functional Block Diagram DQS0 DM0 CS1 CS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQS4 DM4 CS DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 D0 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DM DQS D9 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQS D4 CS DQS D13 DQS5 DM5 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 D1 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D10 CS DQS D5 CS DQS * Clock Wiring D14 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 D2 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D11 CS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D6 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D12 CK0/CK0 CK1/CK1 5 DDR SDRAMs 4 DDR SDRAMs CS DQS D15 *Clock Net Wiring D0(D4) / D9D13) D1(D5) / D10(D14) R=120 DQS7 DM7 DQS3 DM3 DDR SDRAMs *D8 is assigned for ECC component. DQS6 DM6 DQS2 DM2 Clock Input CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D16 CK0/1 Card Edge D2(D6) / D11(D15) D3(D7) / D12(D16) D8(D17)/Cap Cap/Cap DQS8 DM8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D8 DQS CS DQS D17 Serial PD SCL SDA WP BA0 - BA1 BA0-BA1: DDR SDRAMs D0 - D8 A0 - A12 A0-A12: DDR SDRAMs D0 - D8 VDDSPD VDD/VDDQ RAS RAS: DDR SDRAMs D0 - D8 A0 A1 A2 SA0 SA1 SA2 SPD D0 - D8 D0 - D8 CAS CAS: DDR SDRAMs D0 - D8 CKE0,1 CKE: DDR SDRAMs D0 - D8 WE WE: DDR SDRAMs D0 - D8 VREF D0 - D8 VSS D0 - D8 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%. Rev. 0.0 Sep. 2002 M485L2829MT0 200pin DDR SDRAM SODIMM Absolute Maximum Rate Parameter Symbol Value Unit Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD & VDDQ supply relative to VSS VDD, VDDQ -1.0 ~ 3.6 V Storage temperature TSTG -55 ~ +150 C Power dissipation PD 27 W Short circuit current IOS 50 mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out) Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70C) Parameter Symbol Min Max Supply voltage(for device with a nominal VDD of 2.5V) VDD 2.3 2.7 I/O Supply voltage VDDQ 2.3 2.7 V I/O Reference voltage VREF VDDQ/2-50mV VDDQ/2+50mV V 1 I/O Termination voltage(system) VTT VREF-0.04 VREF+0.04 V 2 Input logic high voltage VIH(DC) VREF+0.15 VDDQ+0.3 V 4 Input logic low voltage VIL(DC) -0.3 VREF-0.15 V 4 Input Voltage Level, CK and CK inputs VIN(DC) -0.3 VDDQ+0.3 V Input Differential Voltage, CK and CK inputs VID(DC) 0.3 VDDQ+0.6 V 3 Input crossing point voltage, CK and CK inputs VIX(DC) 1.15 1.35 V 5 II -2 2 uA Output leakage current IOZ -5 5 uA Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V IOH -16.8 mA Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V IOL 16.8 mA Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V IOH -9 mA Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V IOL 9 mA Input leakage current Unit Note Notes 1. Includes 25mV margin for DC offset on VREF, and a combined total of 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of 3nH. 2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. 6. These charactericteristics obey the SSTL-2 class II standards. Rev. 0.0 Sep. 2002 M485L2829MT0 200pin DDR SDRAM SODIMM DDR SDRAM IDD spec table IDD6 Symbol A2 (DDR266@CL=2) B0 (DDR266@CL=2.5) A0 (DDR200@CL=2) Unit IDD0 2,340 2,340 2,070 mA IDD1 2,560 2,560 2,290 mA IDD2P 105 105 90 mA IDD2F 900 900 720 mA IDD2Q 450 450 360 mA IDD3P 900 900 720 mA IDD3N 1,710 1,710 1,440 mA IDD4R 2,835 2,835 2,430 mA IDD4W 3,100 3,100 2,700 mA IDD5 3,640 3,640 3,330 mA Normal 90 90 90 mA Low power 54 54 54 mA 5,170 5,170 4,500 mA IDD7A Notes Optional * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. AC Operating Conditions Parameter/Condition Symbol Min Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC) Max Unit V 3 VREF - 0.31 V 3 VDDQ+0.6 V 1 0.5*VDDQ+0.2 V 2 VREF + 0.31 Input Differential Voltage, CK and CK inputs VID(AC) 0.7 Input Crossing Point Voltage, CK and CK inputs VIX(AC) 0.5*VDDQ-0.2 Note Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz. AC OPERATING TEST CONDITIONS (VDD=2.5V, VDDQ=2.5V, TA= 0 to 70C) Parameter Value Unit Input reference voltage for Clock 0.5 * VDDQ V Input signal maximum peak swing 1.5 V VREF+0.31/VREF-0.31 V VREF V Vtt V Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Note See Load Circuit Rev. 0.0 Sep. 2002 M485L2829MT0 200pin DDR SDRAM SODIMM Vtt=0.5*VDDQ RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*VDDQ Output Load Circuit (SSTL_2) Input/Output CAPACITANCE (VDD=2.5V, VDDQ=2.5V, TA= 25C, f=1MHz) Parameter Symbol Min Max Unit Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS, WE ) CIN1 74 pF Input capacitance(CKE0, CKE1) CIN2 47 pF Input capacitance( CS0, CS1 ) CIN3 47 pF Input capacitance( CLK0, CLK1) CIN4 34 pF Input capacitance(DM0~DM8) CIN5 14 pF Data & DQS input/output capacitance(DQ0~DQ63) COUT1 14 pF Data input/output capacitance(CB0~CB7) COUT2 14 pF Rev. 0.0 Sep. 2002 M485L2829MT0 200pin DDR SDRAM SODIMM AC Timming Parameters & Specifications Parameter Symbol Row cycle time Refresh row cycle time A2 Min B0 Max Min A0 Max Min Max Unit tRC 65 65 70 ns tRFC 75 75 80 ns Row active time tRAS 45 RAS to CAS delay tRCD 20 20 20 ns Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay Clock cycle time CL=2.5 Clock high level width Clock low level width DQS-out access time from CK/CK 45 120K 48 120K ns tRP 20 20 20 ns tRRD 15 15 15 ns tWR 15 15 15 ns tWTR 1 1 1 tCK tCCD CL=2.0 120K tCK tCH 1 7.5 1 12 10 1 12 tCK 10 12 ns 5 ns 5 0.55 tCK 7.5 12 7.5 12 0.45 0.55 0.45 0.55 0.45 tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK tDQSCK -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns Output data access time from CK/CK tAC -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns Data strobe edge to ouput data edge tDQSQ - 0.5 - 0.5 - 0.6 ns Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRES 0 0 0 ns DQS-in hold time tWPRE 0.25 0.25 0.25 tCK tDSS 0.2 0.2 0.2 tCK DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time tDSH 0.2 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 tDSC 0.9 DQS-in cycle time 0.35 1.1 0.9 0.35 1.1 Note 0.9 5 2 tCK 1.1 tCK Address and Control Input setup time(fast) tIS 0.9 0.9 1.1 ns 6 Address and Control Input hold time(fast) tIH 0.9 0.9 1.1 ns 6 Address and Control Input setup time(slow) tIS 1.0 1.0 1.1 ns 6 Address and Control Input hold time(slow) tIH 1.0 1.0 1.1 ns 6 Data-out high impedence time from CK/CK tHZ -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns Data-out low impedence time from CK/CK tLZ -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns tSL(I) 0.5 0.5 0.5 V/ns 6 tSL(IO) 0.5 0.5 0.5 V/ns 7 V/ns 10 Input Slew Rate(for input only pins) Input Slew Rate(for I/O pins) Output Slew Rate(x4,x8) tSL(O) 1.0 4.5 1.0 4.5 1.0 4.5 Output Slew Rate Matching Ratio(rise to fall) tSLMR 0.67 1.5 0.67 1.5 0.67 1.5 Rev. 0.0 Sep. 2002 M485L2829MT0 Parameter 200pin DDR SDRAM SODIMM A2 Symbol Min B0 Max Min A0 Max Min Max Unit Note Mode register set cycle time tMRD 15 15 16 ns DQ & DM setup time to DQS tDS 0.5 0.5 0.6 ns 7,8,9 DQ & DM hold time to DQS tDH 0.5 0.5 0.6 ns 7,8,9 Control & Address input pulse width tIPW 2.2 2.2 2.5 ns tDIPW 1.75 1.75 2 ns Power down exit time tPDEX 7.5 7.5 10 ns Exit self refresh to non-Read command tXSNR 75 75 80 ns Exit self refresh to read command tXSRD 200 200 200 tCK Refresh interval time tREFI 7.8 7.8 7.8 us 1 Output DQS valid window tQH tHP -tQHS - tHP -tQHS - tHP -tQHS - ns 5 Clock half period tHP tCLmin or tCHmin - tCLmin or tCHmin - tCLmin or tCHmin - ns DQ & DM input pulse width Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time tQHS 0.75 0.6 0.75 tWPST 0.4 0.4 0.6 0.4 tRAP 20 20 20 tDAL (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) 4 0.8 ns 0.6 tCK 3 tCK 11 1. Maximum burst refresh cycle : 8 2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with tRCD satisfied after this command. 5. For registered DIMMs, tCL and tCH are 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM. 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate tIS tIH (V/ns) (ps) (ps) 0.5 0 0 0.4 +50 +50 0.3 +100 +100 This derating table is used to increase tIS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate tDS tDH (V/ns) (ps) (ps) 0.5 0 0 0.4 +75 +75 0.3 +150 +150 This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. Rev. 0.0 Sep. 2002 M485L2829MT0 200pin DDR SDRAM SODIMM 8. I/O Setup/Hold Plateau Derating I/O Input Level tDS tDH (mV) (ps) (ps) 280 +50 +50 This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF 310mV for a duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate tDS tDH (ns/V) (ps) (ps) 0 0 0 0.25 +50 +50 0.5 +100 +100 This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design. 11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time. <Reference> The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns. CK slew rate (Single ended) tIH/tIS (ps) tDSS/tDSH (ps) tAC/tDQSCK (ps) tLZ(min) (ps) tHZ(max) (ps) 1.0V/ns 0 0 0 0 0 0.75V/ns +50 +50 +50 -50 +50 0.5V/ns +100 +100 +100 -100 +100 Rev. 0.0 Sep. 2002 M485L2829MT0 200pin DDR SDRAM SODIMM (V=Valid, X=Dont Care, H=Logic High, L=Logic Low) Command Truth Table COMMAND CKEn-1 CKEn CS RAS CAS WE BA0,1 A0 ~ A9 A11, A12 A10/AP Note Register Extended MRS H X L L L L OP CODE 1, 2 Register Mode Register Set H X L L L L OP CODE 1, 2 L L L H X L H H H H X X X Auto Refresh Refresh Entry Self Refresh H L L H Bank Active & Row Addr. H X L L H H V Read & Column Address H X L H L H V Write & Column Address Exit H Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable H X L H L L H X L H H L H X L L H L Entry H L H X X X L V V V Exit L H X X X X Entry H L H X X X L H H H H X X X L V V V Auto Precharge Enable Burst Stop Precharge Bank Selection All Banks Active Power Down Precharge Power Down Mode Exit L DM H No operation (NOP) : Not defined H H X X X X X L H H H 3 3 X V 3 Row Address L H L H Column Address (A0~A9,A11) 4 Column Address (A0~A9,A11) 4 X V L X H 4 4, 6 7 X 5 X X X H 3 X 8 9 9 Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. Rev. 0.0 Sep. 2002 M485L2829MT0 200pin DDR SDRAM SODIMM PACKAGE DIMENSIONS Units : Inches (Millimeters) 2.70 (67.60) 2.50 (63.60) 199 39 41 0.456 11.40 0.086 2.15 0.07 (1.8) 0.79 (20.00) 0.24 (6.0) 1 2- 0.07 (1.80) 1.896 (47.40) 0.17 (4.20) 0.096 (2.40) 1.40 (35.56) Full R 2x 0.16 0.039 (4.00 0.10) Z Y 0.098 2.45 0.16 0.0039 (4.00 0.10) 0.04 0.0039 (1.00 0.10) 0.04 0.0039 (1.00 0.1) Detail Z (2.55 Min) (4.00) (0.157) 0.268 Max (6.81 Max) 0.102 Min 200 2 0.018 0.001 (0.45 0.03) 0.01 (0.25) 0.024 TYP (0.60 TYP) Detail Y Tolerances : .006(.15) unless otherwise specified The used device is stacked 128Mx8 DDR SDRAM, TSOP2 DDR SDRAM Part No. : K4H1G0738M - TC/L Rev. 0.0 Sep. 2002