Choosing the Right SerDes For Your System
As a designer, you have the choice of selecting components
from dierent vendors. But when it comes to designs with
serializers and deserializers, you rst have to choose an
architecture. In implementing a design with a serializer
and/or deserializer, you have 3 architectural choices at your
disposal: Gennum’s complete serializer/deserializer solution
architecture, an integrated-transceiver FPGA architecture
and an FPGA-helper architecture. Let’s explore these three
options with an assessment of the following key parameters:
jitter, power consumption, integration (component/features),
time-to-market, system size and cost.
GENNUM’S COMPLETE SOLUTION ARCHITECTURE
Leveraging our expertise in signal integrity and our deep
understanding of broadcast video technologies, Gennum’s
SDI serializer and deserializer oering encapsulates all
the analog components (SerDes, VCO, CD, EQ, Reclocker)
and digital SMPTE video and audio processing required
to transmit and receive SDI video. is optimized, cost-
eective and power ecient ASIC implementation that lets
you focus on your value-added processing for quicker time-
to-market. All of this integration into one package reduces
the PCB footprint required to implement SDI transmit/
receive, and you benet from Gennum’s superior jitter
performance. Only Gennum oers a solution that scores
high for each evaluation parameter.
INTEGRATED-TRANSCEIVER FPGA ARCHITECTURE
Integrated-transceiver FPGAs typically oer the worst
specications in terms of jitter. Maximum output jitter and
input jitter tolerance (IJT) are typically at the limit of the
SMPTE standards, and, in some cases, actually in violation
of industry norms. at is why extra components, namely
VCXOs and reclockers, are required to get the system jitter
performance to an acceptable level. is comes at a penalty
of higher power consumption, system footprint size and cost.
Because of all the ne tuning required to get this architecture
to work, and because of the IP licensing/development
Serializers/Deserializers
required for the digital SMPTE video processing, this
architecture unnecessarily prolongs time-to-market. Finally,
while FPGAs integrate transceivers, they do not integrate
routing components like cable drivers and equalizers.
FPGA-HELPER ARCHITECTURE
e FPGA-helper architecture, as depicted below, involves
the use of a component that includes the physical media
attachment part of a SMPTE deserializer/serializer, with
the digital SMPTE processing implemented in the FPGA.
e result is an architecture that is taxing in terms of power
consumption and those FPGA-helper parts are lacking, even
basic SMPTE digital processing. In many cases, product
specic FPGA IP already requires high utilization factors
in small, low-cost FPGAs and the added requirement of
digital SMPTE video processing in the FPGA may drive
adoption of a larger FPGA. is results in further penalties
in power consumption, size and system cost. And while
this architecture fares well in system jitter performance to
certain cases, the added engineering eort in developing
(or licensing) and stitching that video processing logic to
product specic code ensures a slower time-to-market.
Finally, while some FPGA-helper parts integrate a cable
driver, the oering lacks an integrated equalizer.
HOW THE GENNUM SOLUTION STACKS UP
Compare the ratings of each of the 3 architectures for key
parameters in an implementation of 1 Rx and 1 Tx channel.
EQ
Transmitter
w/CD
11
11
Complete Complete
Gennum: Complete Solution Transmitter/Receiver
EQ+Receiver
SDI Output
SDI Input Low-End FPGA
Spartan 3A, Cyclone III
Proprietary Customer
Logic
Receiver
VCXO
Digital
SMPTE processing
Proprietary Customer Logic
CD
Reclocker
EQ
Receiver
Transmitter
Integrated Transceiver FPGAs
12
EQ
Digital
SMPTE processing
Proprietary Customer Logic
Receiver Transmitter
w/CD
Partial Partial
12
FPGA-Helper SERDES
SDI Output SDI Input
High-End FPGA
Virtex 5,Stratix II GX
SDI Output SDI Input
High-End FPGA
Virtex 5,Stratix II
EQ
Transmitter
w/CD
11
11
Complete Complete
Gennum: Complete Solution Transmitter/Receiver
EQ+Receiver
SDI Output
SDI Input Low-End FPGA
Spartan 3A, Cyclone III
Proprietary Customer
Logic
Receiver
VCXO
Digital
SMPTE processing
Proprietary Customer Logic
CD
Reclocker
EQ
Receiver
Transmitter
Integrated Transceiver FPGAs
12
EQ
Digital
SMPTE processing
Proprietary Customer Logic
Receiver Transmitter
w/CD
Partial Partial
12
FPGA-Helper SERDES
SDI Output SDI Input
High-End FPGA
Virtex 5,Stratix II GX
SDI Output SDI Input
High-End FPGA
Virtex 5,Stratix II
EQ 11
11
Complete Complete
Gennum: Complete Solution Transmitter/Receiver
EQ+Receiver
SDI Output
SDI Input Low-End FPGA
Spartan 3A, Cyclone III
Proprietary Customer
Logic
Receiver
VCXO
Digital
SMPTE processing
Proprietary Customer Logic
CD
Reclocker
EQ
Receiver
Transmitter
Integrated Transceiver FPGAs
12
EQ
Digital
SMPTE processing
Proprietary Customer Logic
Receiver Transmitter
w/CD
Partial Partial
12
FPGA-Helper SerDes
SDI Output SDI Input
High-End FPGA
Virtex 5,Stratix II GX
SDI Output
SDI Input
High-End FPGA
Virtex 5,Stratix II
GENNUM
COMPLETE
SOLUTION
INTEGRATED-
TRANSCEIVER
FPGA
FPGA-HELPER
SERDES
Jitter Performance
Time-to-Market
Power Consumption
Integration
Overall PCB Space
System Cost
11 Gennum Fall 2011 Product Guide • Broadcast Video