DATA SH EET
Product specification
Supersedes data of 1998 May 20 2004 Mar 30
INTEGRATED CIRCUITS
74LVC161
Presettable synchronous 4-bit
binary counter; asynchronous reset
2004 Mar 30 2
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset 74LVC161
FEATURES
•5 V tolerant inputs for interfacing with 5 V logic
•Wide supply voltage range from 1.2 V to 3.6 V
•CMOS low power consumption
•Direct interface with TTL levels
•Inputs accept voltages up to 5.5 V
•Complies with JEDEC standard no. JESD8B/JESD36
•Asynchronous reset
•Synchronous counting and loading
•Two count enable inputs for n-bit cascading
•Positive edge-triggered clock
•ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
•Specified from −40 °C to +85 °C and −40 °C to +125 °C.
DESCRIPTION
The 74LVC161 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
The 74LVC161 is a synchronous presettable binary
counterwhichfeaturesaninternallook-headcarryandcan
be used for high-speed counting. Synchronous operation
is provided by having all flip-flops clocked simultaneously
on the positive-going edge of the clock (pin CP). The
outputs (pins Q0 to Q3) of the counters may be preset to a
HIGH-level or a LOW-level. A LOW-level at the parallel
enable input (pin PE) disables the counting action and
causes the data at the data inputs (pins D0 to D3) to be
loaded into the counter on the positive-going edge of the
clock (provided that the set-up and hold time requirements
forPEaremet). Preset takesplaceregardlessof the levels
at count enable inputs (pins CEP and CET). A LOW-level
at the master reset input (pin MR) sets all four outputs of
the flip-flops (pins Q0 to Q3) to LOW-level regardless of
the levels at input pins CP, PE, CET and CEP (thus
providing an asynchronous clear function).
The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (pins CEP and CET)
must be HIGH to count. The CET input is fed forward to
enable the terminal count output (pin TC). The TC output
thus enabled will produce a HIGH output pulse of a
durationapproximatelyequaltoaHIGH-leveloutputofQ0.
Thispulsecan beused to enablethe next cascadedstage.
The maximum clock frequency for the cascaded counters
is determined by tPHL (propagation delay CP to TC) and tsu
(set-up time CEP to CP) according to the following
formula:fmax 1
tPHL max()
tsu
+
-------------------------------------
=
2004 Mar 30 3
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset 74LVC161
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f≤2.5 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL×VCC2×fo) = sum of the outputs.
2. The condition is VI= GND to VCC.
ORDERING INFORMATION
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH propagation delay CL= 50 pF; VCC = 3.3 V
CP to Qn 3.9 ns
CP to TC 4.5 ns
MR to Qn 3.5 ns
MR to TC 4.7 ns
CET to TC 3.3 ns
fclk(max) maximum clock frequency 200 MHz
CIinput capacitance 5.0 pF
CPD power dissipation capacitance per gate notes 1 and 2 18 pF
TYPE NUMBER TEMPERATURE
RANGE PINS PACKAGE MATERIAL CODE
74LVC161D −40 °C to +125 °C 16 SO16 plastic SOT109-1
74LVC161DB −40 °C to +125 °C 16 SSOP16 plastic SOT338-1
74LVC161PW −40 °C to +125 °C 16 TSSOP16 plastic SOT403-1
74LVC161BQ −40 °C to +125 °C 16 DHVQFN16 plastic SOT763-1
2004 Mar 30 4
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset 74LVC161
FUNCTION TABLE
See note 1.
Note
1. * = The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH).
H = HIGH voltage level.
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition.
L = LOW voltage level.
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition.
q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock
transition.
X = don’t care.
↑=LOW-to-HIGH clock transition.
PINNING
OPERATING
MODES INPUT OUTPUT
MR CP CEP CET PE Dn Qn TC
Reset (clear) L XXXXXLL
Parallel load H ↑XX l l LL
H↑XX l hH*
Count H ↑h h h X count *
Hold
(do nothing) HXlXhXq
n*
HXX l hXq
nL
PIN SYMBOL DESCRIPTION
1 MR synchronous master reset (active LOW)
2 CP clock input (LOW-to-HIGH, edge-triggered)
3 D0 data input
4 D1 data input
5 D2 data input
6 D3 data input
7 CEP count enable inputs
8 GND ground (0 V)
9 PE parallel enable input (active LOW)
10 CET count enable carry input
11 Q3 flip-flop output
12 Q2 flip-flop output
13 Q1 flip-flop output
14 Q0 flip-flop output
15 TC terminal count output
16 VCC supply voltage
2004 Mar 30 5
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset 74LVC161
Fig.1 Pin configuration SO16 and (T)SSOP16.
handbook, halfpage
MR
CP
161
D0
D1
D2
D3
CEP
GND
VCC
TC
Q0
Q1
Q3
CET
Q2
PE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MNA904
Fig.2 Pin configuration DHVQFN16.
handbook, halfpage
116
GND(1)
MR VCC
8
2
3
4
5
7
CP
D0
D1
D2
D3
15
14
13
12
10
611
9
GND
Top view
MNA980
CEP
PE
CET
Q3
Q2
Q1
Q0
TC
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
handbook, halfpage
MNA905
Q0
Q1
CP
Q2
Q3
TC
3
4
2
5
6
9
14
13
15
12
11
MR
1
CEP
7
CET
10
D0
D1
D2
D3
PE
Fig.3 Logic symbol.
handbook, halfpage
MNA906
15
11
12
3
4
5
6
14
13
7
10 G3
1R
9M1
G4
2C2 /1,3,4+
1,2D
4 CT = 15
CTR4
Fig.4 Logic symbol (IEEE/IEC).
2004 Mar 30 6
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset 74LVC161
handbook, halfpage
MNA907
PARALLEL LOAD
CIRCUITRY
BINARY
COUNTER
CEP TC 15
CET
PE
CP
MR
Q0 Q1 Q2 Q3
D0 D1 D2 D3
14 13 12 11
3456
7
10
9
2
1
Fig.5 Functional diagram.
handbook, halfpage
MNA908
0
15
14
13
12
1 2 3 4
5
6
7
11 10 9 8
Fig.6 State diagram.
handbook, full pagewidth
MNA909
CP
PE
TC
MR
inhibitcount
CEP
CET
D0
D2
D1
D3
Q0
Q2
Q1
Q3
reset preset
12 13 14 15 0 1 2
Fig.7 Timing sequence.
Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one and two; inhibit.
2004 Mar 30 7
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset 74LVC161
handbook, full pagewidth
MNA910
Q3 TC
Q2
Q1
Q0
DFF0Q
CP
PE
CEP
CET
D0 D1 D2 D3
CP
MR
DFF1Q
CP
DFF2Q
CP
DFF3
RDRDRDRD
Q
CP
Q Q Q Q
Fig.8 Logic diagram.
2004 Mar 30 8
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset 74LVC161
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V);
note 1.
Notes
1. Stresses beyond those listed may cause permanent damage to the device. These are stress rating only and
functional operation of the device at these or any other condition beyond those indicated under “Recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. For SO16 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 °C derate linearly with 4.5 mW/K.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage for maximum speed performance 2.7 3.6 V
for low voltage applications 1.2 3.6 V
VIinput voltage 0 5.5 V
VOoutput voltage 0 VCC V
Tamb operating temperature in free-air −40 +125 °C
tr,t
finput rise and fall times VCC = 1.2 V to 2.7 V 0 20 ns/V
VCC = 2.7 V to 3.6 V 0 10 ns/V
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VCC supply voltage −0.5 −+6.5 V
IIK input diode current VI<0V −−50 −mA
VIinput voltage note 2 −0.5 −+6.5 V
IOK output diode current VO>V
CC or VO<0V −±50 −mA
VOoutput voltage note 2 −0.5 −VCC + 0.5 V
IOoutput source of sink current VO=0VtoV
CC −±50 −mA
ICC,I
GND VCC or GND current −±100 −mA
Tstg storage temperature −65 −+150 °C
Ptot power dissipation Tamb =−40 °C to +125 °C; note 3 −500 −mW
2004 Mar 30 9
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset 74LVC161
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
OTHER VCC (V)
Tamb =−40 °C to +85 °C
VIH HIGH-level input
voltage 1.2 VCC −−V
2.7 to 3.6 2.0 −−V
VIL LOW-level input
voltage 1.2 −−GND V
2.7 to 3.6 −−0.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL
IO=−100 µA 2.7 to 3.6 VCC −0.2 VCC −V
IO=−12 mA 2.7 VCC −0.5 −−V
IO=−18 mA 3.0 VCC −0.6 −−V
IO=−24 mA 3.0 VCC −0.8 −−V
VOL LOW-level output
voltage VI=V
IH or VIL
IO= 100 µA 2.7 to 3.6 −GND 0.2 V
IO=12mA 2.7 −−0.4 V
IO=24mA 3.0 −−0.55 V
ILI input leakage
current VI= 5.5 Vor GND 3.6 −±0.1 ±5µA
ICC quiescent supply
current VI=V
CC or GND;
IO=0A 3.6 −0.1 10 µA
∆ICC additional quiescent
supply current per
input pin
VI=VCC −0.6 V;
IO=0A 2.7 to 3.6 −5 500 µA
2004 Mar 30 10
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset 74LVC161
Note
1. Typical values are measured at VCC = 3.3 V and Tamb =25°C.
Tamb =−40 °C to +125 °C
VIH HIGH-level input
voltage 1.2 VCC −−V
2.7 to 3.6 2.0 −−V
VIL LOW-level input
voltage 1.2 −−GND V
2.7 to 3.6 −−0.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL
IO=−100 µA 2.7 to 3.6 VCC −0.3 −−V
IO=−12 mA 2.7 VCC −0.65 −−V
IO=−18 mA 3.0 VCC −0.75 −−V
IO=−24 mA 3.0 VCC −1−−V
VOL LOW-level output
voltage VI=V
IH or VIL
IO= 100 µA 2.7 to 3.6 −−0.3 V
IO=12mA 2.7 −−0.6 V
IO=24mA 3.0 −−0.8 V
ILI input leakage
current VI= 5.5 Vor GND 3.6 −−±20 µA
ICC quiescent supply
current VI=V
CC or GND;
IO=0A 3.6 −−40 µA
∆ICC additional quiescent
supply current per
input pin
VI=VCC −0.6 V;
IO=0A 2.7 to 3.6 −−5000 µA
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
OTHER VCC (V)
2004 Mar 30 11
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset 74LVC161
AC CHARACTERISTICS
GND = 0 V; tr=t
f≤2.5 ns; CL= 50 pF; RL= 500 Ω.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
WAVEFORMS VCC (V)
Tamb =−40 °C to +85 °C; note 1
tPHL/tPLH propagation delay CP to Qn see Figs 9 and 14 1.2 −17 −ns
2.7 1.5 −7.2 ns
3.0 to 3.6 1.5 3.9(2) 7.3 ns
propagation delay CP to TC see Figs 9 and 14 1.2 −20 −ns
2.7 1.5 −7.8 ns
3.0 to 3.6 1.5 4.5(2) 7.8 ns
propagation delay CET to TC see Figs 10 and 14 1.2 −16 −ns
2.7 1.5 −6.5 ns
3.0 to 3.6 1.5 3.3(2) 6.0 ns
tPHL propagation delay MR to Qn see Figs 11 and 14 1.2 −17 −ns
2.7 1.5 −7.1 ns
3.0 to 3.6 1.5 3.5(2) 6.4 ns
propagation delay MR to TC see Figs 11 and 14 1.2 −18 −ns
2.7 1.5 −8.6 ns
3.0 to 3.6 1.5 4.7(2) 8.0 ns
tWclock pulse width
HIGH or LOW see Fig.9 2.7 5.0 −−ns
3.0 to 3.6 4.0 1.2(2) −ns
master reset width LOW see Fig.11 2.7 4.0 −−ns
3.0 to 3.6 3.0 1.6(2) −ns
trem removal time MR to CP see Fig.11 2.7 0.0 −−ns
3.0 to 3.6 0.5 0.0(2) −ns
tsu set-up time Dn to CP see Fig.12 2.7 3.0 −−ns
3.0 to 3.6 2.5 1.0(2) −ns
set-up time PE to CP see Fig.12 2.7 3.5 −−ns
3.0 to 3.6 3.0 1.2(2) −ns
set-up time CEP, CET to CP see Fig.13 2.7 5.5 −−ns
3.0 to 3.6 5.0 2.1(2) −ns
thhold time Dn, PE, CEP, CET
to CP see Figs 12 and 13 2.7 0.0 −−ns
3.0 to 3.6 0.5 0.0(2) −ns
fclk(max) maximum clock frequency see Fig.9 2.7 150 −−MHz
3.0 to 3.6 150 200(2) −MHz
tsk(0) skew note 3 3.0 to 3.6 −−1.0 ns
2004 Mar 30 12
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset 74LVC161
Notes
1. All typical values are measured at Tamb =25°C.
2. Typical values are measured at VCC = 3.3 V.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
by design.
Tamb =−40 °C to +125 °C
tPHL/tPLH propagation delay CP to Qn see Figs 9 and 14 1.2 −−−ns
2.7 1.5 −9.0 ns
3.0 to 3.6 1.5 −9.5 ns
propagation delay CP to TC see Figs 9 and 14 1.2 −−−ns
2.7 1.5 −10.0 ns
3.0 to 3.6 1.5 −10.0 ns
propagation delay CET to TC see Figs 10 and 14 1.2 −−−ns
2.7 1.5 −8.5 ns
3.0 to 3.6 1.5 −7.5 ns
tPHL propagation delay MR to Qn see Figs 11 and 14 1.2 −−−ns
2.7 1.5 −9.0 ns
3.0 to 3.6 1.5 −8.0 ns
propagation delay MR to TC see Figs 11 and 14 1.2 −−−ns
2.7 1.5 −11.0 ns
3.0 to 3.6 1.5 −10.0 ns
tWclock pulse width
HIGH or LOW see Fig.9 2.7 5.0 −−ns
3.0 to 3.6 4.0 −−ns
master reset width LOW see Fig.11 2.7 4.0 −−ns
3.0 to 3.6 3.0 −−ns
trem removal time MR to CP see Fig.11 2.7 0.0 −−ns
3.0 to 3.6 0.5 −−ns
tsu set-up time Dn to CP see Fig.12 2.7 3.0 −−ns
3.0 to 3.6 2.5 −−ns
set-up time PE to CP see Fig.12 2.7 3.5 −−ns
3.0 to 3.6 3.0 −−ns
set-up time CEP, CET to CP see Fig.13 2.7 5.5 −−ns
3.0 to 3.6 5.0 −−ns
thhold time Dn, PE, CEP, CET
to CP see Figs 12 and 13 2.7 0.0 −−ns
3.0 to 3.6 0.5 −−ns
fclk(max) maximum clock frequency see Fig.9 2.7 150 −−MHz
3.0 to 3.6 150 −−MHz
tsk(0) skew note 3 3.0 to 3.6 −−1.5 ns
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
WAVEFORMS VCC (V)
2004 Mar 30 13
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset 74LVC161
AC WAVEFORMS
handbook, full pagewidth
MNA911
CP input
Qn, TC output
tPHL tPLH
tW
1/fmax
VM
VOH
VI
GND
VOL
VM
Fig.9 Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width and the maximum clock
frequency.
VM= 1.5 V at VCC ≥2.7 V.
VM= 0.5VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
handbook, halfpage
MNA912
tPHL
tPLH
VM
VM
TC output
CET input
GND
VI
VOH
VOL
VM= 1.5 V at VCC ≥2.7 V.
VM= 0.5VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.10 Input (CET) to output (TC) propagation delays.
2004 Mar 30 14
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset 74LVC161
handbook, full pagewidth
MNA913
MR input
CP input
Qn, TC output
tPHL
tW
trem
VM
VOH
VI
VI
GND
GND
VOL
VM
VM
Fig.11 Master reset (MR) pulse width, the master reset to output (Qn, TC) propagation delays and the master
reset to clock (CP) removal times.
handbook, full pagewidth
MNA914
GND
GND
GND
th
th
tsu
tsu tsu
th
th
tsu
VM
VM
VM
VI
VI
CP input
PE input
Dn input
VI
Fig.12 Set-up and hold times for the input (Dn) and parallel enable input (PE).
The shaded areas indicate when the input is permitted to change for predictable output performance.
2004 Mar 30 15
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset 74LVC161
handbook, full pagewidth
MNA915
th
tsu
th
tsu
GND
VI
VM
VM
GND
VI
CP input
CEP, CET input
Fig.13 CEP and CET set-up and hold times.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VEXT
VCC
VIVO
mna616
D.U.T.
CL
RT
RL
RL
PULSE
GENERATOR
Fig.14 Load circuitry for switching times.
Definitions for test circuit:
RL= Load resistor.
CL= Load capacitance including jig and probe capacitance.
RT= Termination resistance should be equal to the output impedance Zo of the pulse generator.
Note
1. The circuit performs better when RL= 1000 Ω.
VCC VICLRLVEXT
tPLH/tPHL tPZH/tPHZ tPZL/tPLZ
1.2 V VCC 50 pF 500 Ω(1) open GND 2 ×VCC
2.7 V 2.7 V 50 pF 500 Ωopen GND 2 ×VCC
3.0 V to 3.6 V 2.7 V 50 pF 500 Ωopen GND 2 ×VCC
2004 Mar 30 16
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset 74LVC161
PACKAGE OUTLINES
X
w
M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A
1
A
2
A
3
b
p
cD
(1)
E
(1) (1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 10.0
9.8 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.39
0.38 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.020 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
2004 Mar 30 17
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset 74LVC161
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25
7.9
7.6 1.03
0.63 0.9
0.7 1.00
0.55 8
0
o
o
0.130.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1 99-12-27
03-02-19
(1)
w
M
b
p
D
H
E
E
Z
e
c
v
M
A
X
A
y
18
16 9
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
A
max.
2
2004 Mar 30 18
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset 74LVC161
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(2) (1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
w
M
b
p
D
Z
e
0.25
18
16 9
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v
M
A
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
2004 Mar 30 19
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset 74LVC161
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.6
3.4
Dh
2.15
1.85
y1
2.6
2.4 1.15
0.85
e1
2.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT763-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT763-1
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
A
(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
27
15 10
9
8
1
16
X
D
E
C
BA
terminal 1
index area
AC
CB
v
M
w
M
E
(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D
(1)
02-10-17
03-01-27
2004 Mar 30 20
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset 74LVC161
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL DATA SHEET
STATUS(1) PRODUCT
STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseor at anyotherconditions above thosegivenin the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythatsuchapplicationswillbe
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusingorsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
© Koninklijke Philips Electronics N.V. 2004 SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors – a worldwide compan y
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands R20/03/pp21 Date of release: 2004 Mar 30 Document order number: 9397 750 10505
