LTC3300-1
1
Rev. C
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APPLICATIONS
TYPICAL APPLICATION
FEATURES DESCRIPTION
High Efficiency Bidirectional
Multicell Battery Balancer
The LTC
®
3300-1 is a fault-protected controller IC for
transformer-based bidirectional active balancing of multi-
cell battery stacks. All associated gate drive circuitry,
precision current sensing, fault detection circuitry and a
robust serial interface with built-in watchdog timer are
integrated.
Each LTC3300-1 can balance up to 6 series-connected bat-
tery cells with an input common mode voltage up to 36V.
Charge from any selected cell can be transferred at high
efficiency to or from 12 or more adjacent cells. A unique
level-shifting SPI-compatible serial interface enables
multiple LTC3300-1 devices to be connected in series,
without opto-couplers or isolators, allowing for balancing
of every cell in a long string of series-connected batteries.
When multiple LTC3300-1 devices are connected in series
they can operate simultaneously, permitting all cells in
the stack to be balanced concurrently and independently.
Fault protection features include readback capability, cy-
clic redundancy check (CRC) error detection, maximum
on-time volt-second clamps, and overvoltage shutoffs.
High Efficiency Bidirectional Balancing
Balancer Efficiency
n Bidirectional Synchronous Flyback Balancing
of Up to 6 Li-Ion or LiFePO4 Cells in Series
n Up to 10A Balancing Current (Set by Externals)
n Integrates Seamlessly with the LTC680x Family of
Multicell Battery Stack Monitors
n Bidirectional Architecture Minimizes Balancing
Time and Power Dissipation
n Up to 92% Charge Transfer Efficiency
n Stackable Architecture Enables >1000V Systems
n Uses Simple 2-Winding Transformers
n 1MHz Daisy-Chainable Serial Interface with 4-Bit
CRC Packet Error Checking
n High Noise Margin Serial Communication
n Numerous Fault Protection Features
n 48-Lead Exposed Pad QFN and LQFP Packages
n AEC-Q100 Qualified for Automotive Applications
n Electric Vehicles/Plug-in HEVs
n High Power UPS/Grid Energy Storage Systems
n General Purpose Multicell Battery Stacks All registered trademarks and trademarks are the property of their respective owners.
SERIAL
DATA OUT
TO LTC3300-1
ABOVE
SERIAL
DATA IN
FROM
LTC3300-1
BELOW
3
+CELL 1
ICHARGE
CHARGE
SUPPLY
CHARGE
SUPPLY
(I
CHARGE 1-6)
NEXT CELL BELOW
33001 TA01a
LTC3300-1
LTC3300-1
NEXT CELL ABOVE
3
3
3
•
•
+CELL 6
+CELL 7
+CELL 12
IDISCHARGE
CHARGE
RETURN
CHARGE
RETURN
(IDISCHARGE 1-6)
•
•
NUMBER OF CELLS (SECONDARY SIDE)
6
80
CHARGE TRANSFER EFFICIENCY (%)
85
95
90
100
8 10
CHARGE
DISCHARGE
33001 TA01b
12
DC2064A DEMO BOARD
ICHARGE = IDISCHARGE = 2.5A
VCELL = 3.6V
LTC3300-1
2
Rev. C
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (C6 to V–) .................................36V
Input Voltage (Relative to V–)
C1 ........................................................... –0.3V to 6V
I1P ....................................................... –0.3V to 0.3V
I1S, I2S, I3S, I4S, I5S, I6S .................... –0.3V to 0.3V
CSBI, SCKI, SDI ....................................... –0.3V to 6V
CSBO, SCKO, SDOI ................................ –0.3V to 36V
VREG, SDO ............................................... –0.3V to 6V
RTONP, RTONS ........... –0.3V to Min[VREG + 0.3V, 6V]
TOS, VMODE, CTRL,
BOOST, WDT ..............–0.3V to Min[VREG + 0.3V, 6V]
(Note 1)
TOP VIEW
49
V–
UK PACKAGE
48-LEAD (7mm × 7mm) PLASTIC QFN
G6S 1
I6S 2
G5S 3
I5S 4
G4S 5
I4S 6
G3S 7
I3S 8
G2S 9
I2S 10
G1S 11
I1S 12
36 C5
35 G5P
34 I5P
33 C4
32 G4P
31 I4P
30 C3
29 G3P
28 I3P
27 C2
26 G2P
25 I2P
48 VREG
47 TOS
46 VMODE
45 CSBO
44 SCKO
43 SDOI
42 BOOST
41 BOOST–
40 BOOST+
39 C6
38 G6P
37 I6P
RTONS 13
RTONP 14
CTRL 15
CSBI 16
SCKI 17
SDI 18
SDO 19
WDT 20
V– 21
I1P 22
G1P 23
C1 24
TJMAX = 150°C, θJA = 34°C/W, θJC = 3°C/W
EXPOSED PAD (PIN 49) IS V–, MUST BE SOLDERED TO PCB
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
G6S
I6S
G5S
I5S
G4S
I4S
G3S
I3S
G2S
I2S
G1S
I1S
13
14
15
16
17
18
19
20
21
22
23
24
RTONS
RTONP
CTRL
CSBI
SCKI
SDI
SDO
WDT
V–
I1P
G1P
C1
48
47
46
45
44
43
42
41
40
39
38
37
VREG
TOS
VMODE
CSBO
SCKO
SDOI
BOOST
BOOST–
BOOST+
C6
G6P
I6P
C5
G5P
I5P
C4
G4P
I4P
C3
G3P
I3P
C2
G2P
I2P
TOP VIEW
49
V–
LXE PACKAGE
48-LEAD (7mm
×
7mm) PLASTIC LQFP
TJMAX = 150°C, θJA = 20.46°C/W, θJC = 3.68°C/W
EXPOSED PAD (PIN 49) IS V–, MUST BE SOLDERED TO PCB
PIN CONFIGURATION
Voltage Between Pins
Cn to Cn-1* .............................................. –0.3V to 6V
InP to Cn-1* .......................................... –0.3V to 0.3V
BOOST+ to C6 .......................................... –0.3V to 6V
CSBO to SCKO, CSBO to SDOI,
SCKO to SDOI ....................................... –0.3V to 0.3V
SDO Current ...........................................................10mA
G1P, G nP, G1S, GnS, BOOST– Current ............... ±200mA
Operating Junction Temperature Range (Notes 2, 7)
LTC3300I-1 ........................................ –40°C to 125°C
LTC3300H-1 .......................................–40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
*n = 2 to 6
LTC3300-1
3
Rev. C
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3300IUK-1#PBF LTC3300IUK-1#TRPBF LTC3300UK-1 48-Lead (7mm × 7mm) Plastic QFN –40°C to 125°C
LTC3300HUK-1#PBF LTC3300HUK-1#TRPBF LTC3300UK-1 48-Lead (7mm × 7mm) Plastic QFN –40°C to 150°C
LEAD FREE FINISH TRAY PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3300ILXE-1#PBF LTC3300ILXE-1#PBF LTC3300LXE-1 48-Lead (7mm × 7mm) Plastic eLQFP –40°C to 125°C
LTC3300HLXE-1#PBF LTC3300HLXE-1#PBF LTC3300LXE-1 48-Lead (7mm × 7mm) Plastic eLQFP –40°C to 150°C
AUTOMOTIVE PRODUCTS*
LEAD FREE FINISH TRAY PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3300ILXE-1#WPBF LTC3300ILXE-1#WPBF LTC3300LXE-1 48-Lead (7mm × 7mm) Plastic eLQFP –40°C to 125°C
LTC3300HLXE-1#WPBF LTC3300HLXE-1#WPBF LTC3300LXE-1 48-Lead (7mm × 7mm) Plastic eLQFP –40°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
*Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local
Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.
LTC3300-1
4
Rev. C
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) BOOST+ = 25.2V, C6 = 21.6V, C5 = 18V, C4 = 14.4V,
C3 = 10.8V, C2 = 7.2V, C1 = 3.6V, V– = 0V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DC Specifications
IQ_SD Supply Current When Not
Balancing (Post Suspend or Pre
First Execute)
Measured at C1, C2, C3, C4, C5
Measured at C6
Measured at BOOST+
7
0
16
0
1
25
10
µA
µA
µA
IQ_ACTIVE Supply Current When Balancing
(Note 3)
Balancing C1 Only (Note 4 for V–, C2, C6)
Measured at C1
Measured at C2, C3, C4, C5
Measured at C6
Measured at BOOST+
250
70
560
0
375
105
840
10
µA
µA
µA
µA
Balancing C2 Only (Note 4 for C1, C3, C6)
Measured at C1
Measured at C2
Measured at C3, C4, C5
Measured at C6
Measured at BOOST+
–105
–70
250
70
560
0
375
105
840
10
µA
µA
µA
µA
µA
Balancing C3 Only (Note 4 for C2, C4, C6)
Measured at C1, C4, C5
Measured at C2
Measured at C3
Measured at C6
Measured at BOOST+
–105
70
–70
250
560
0
105
375
840
10
µA
µA
µA
µA
µA
Balancing C4 Only (Note 4 for C3, C5, C6)
Measured at C1, C2, C5
Measured at C3
Measured at C4
Measured at C6
Measured at BOOST+
–105
70
–70
250
560
0
105
375
840
10
µA
µA
µA
µA
µA
Balancing C5 Only (Note 4 for C4, C6)
Measured at C1, C2, C3
Measured at C4
Measured at C5
Measured at C6
Measured at BOOST+
–105
70
–70
250
560
0
105
375
840
10
µA
µA
µA
µA
µA
Balancing C6 Only (Note 4 for C5, C6, BOOST+)
Measured at C1, C2, C3, C4
Measured at C5
Measured at C6
Measured at BOOST+ (BOOST = V–)
Measured at BOOST+ (BOOST = VREG)
–105
70
–70
740
60
0
105
1110
90
10
µA
µA
µA
µA
µA
IQ_EXTRA Supply Current Extra
(Serial I/O in Current Mode)
Additional Current Measured at C6, VMODE = V–
(CSBI Logic Low, SCKI and SDI Both Logic High;
Refer to IIL1, IIH1, IOH1, IOL1 Specs)
3.75 mA
VCELL|MIN Minimum Cell Voltage (Rising)
Required for Primary Gate Drive
Cn to Cn – 1 Voltage to Balance Cn, n = 2 to 6
C1 Voltage to Balance C1
Cn + 1 to Cn Voltage to Balance Cn, n = 1 to 5
BOOST+ to C6 Voltage to Balance C6, BOOST = V–
l
l
l
l
1.8
1.8
1.8
1.8
2
2
2
2
2.2
2.2
2.2
2.2
V
V
V
V
VCELL|MIN(HYST) VCELL|MIN Comparator Hysteresis 70 mV
VCELL|MAX Maximum Cell Voltage (Rising)
Before Disabling Balancing
C1, Cn to Cn – 1 Voltage to Balance Any Cell,
n = 2 to 6
l4.7 5 5.3 V
VCELL|MAX(HYST) VCELL|MAX Comparator Hysteresis 0.5 V
VCELL|RECONNECT Maximum Cell Voltage (Falling) to
Re-Enable Balancing
l4.25 V
VREG Regulator Pin Voltage 9V ≤ C6 ≤ 36V, 0mA ≤ ILOAD ≤ 20mA l4.4 4.8 5.2 V
LTC3300-1
5
Rev. C
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) BOOST+ = 25.2V, C6 = 21.6V, C5 = 18V, C4 = 14.4V,
C3 = 10.8V, C2 = 7.2V, C1 = 3.6V, V– = 0V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VREG|POR VREG Voltage (Rising) for
Power-On Reset
4.0 V
VREG|MIN Minimum VREG Voltage (Falling)
for Secondary Gate Drive
VREG Voltage to Balance Cn, n = 1 to 6 l3.8 V
IREG_SC Regulator Pin Short Circuit Current
Limit
VREG = 0V 55 mA
VRTONP RTONP Servo Voltage RRTONP = 20kΩ l1.158 1.2 1.242 V
VRTONS RTONS Servo Voltage RRTONS = 15kΩ l1.158 1.2 1.242 V
IWDT_RISING WDT Pin Current, Balancing RTONS = 15kΩ, WDT = 0.5V l72 80 88 µA
IWDT_FALLING WDT Pin Current as a Percentage
of IWDT_RISING, Secondary OV
RTONS = 15kΩ, WDT = 2V l85 87.5 90 %
VPEAK_P Primary Winding Peak Current
Sense Voltage
I1P
InP to Cn – 1, n = 2 to 6
l
l
45
45
50
50
55
55
mV
mV
VPEAK_P Matching (All 6) ±[(Max – Min)/(Max + Min)] • 100% l±1.7 ±5 %
VPEAK_S Secondary Winding Peak Current
Sense Voltage
I1S
InS to Cn – 1, n = 2 to 6, CTRL = 0 Only
l
l
45
45
50
50
55
55
mV
mV
VPEAK_S Matching (All 6) ±[(Max – Min)/(Max + Min)] • 100% l±0.5 ±3 %
VZERO_P Primary Winding Zero Current
Sense Voltage (Note 5)
I1P
InP to Cn – 1, n = 2 to 6
l
l
–7
–7
–2
–2
3
3
mV
mV
VZERO_P Matching (All 6)
Normalized to Mid-Range VPEAK_P
±{[(Max – Min)/2]/(VPEAK_P|MIDRANGE)} • 100%
(Note 6)
l±1.7 ±5 %
VZERO_S Secondary Winding Zero Current
Sense Voltage (Note 5)
I1S
InS to Cn – 1, n = 2 to 6, CTRL = 0 Only
l
l
–12
–12
–7
–7
–2
–2
mV
mV
VZERO_S Matching (All 6)
Normalized to Mid-Range VPEAK_S
±{[(Max – Min)/2]/(VPEAK_S|MIDRANGE)} • 100%
(Note 6)
l±0.5 ±3 %
RBOOST_L BOOST– Pin Pull-Down RON Measured at 100mA Into Pin, BOOST = VREG 2.5 Ω
RBOOST_H BOOST– Pin Pull-Up RON Measured at 100mA Out of Pin, BOOST = VREG 4 Ω
TSD Thermal Shutdown Threshold
(Note 7)
Rising Temperature 155 °C
THYS Thermal Shutdown Hysteresis 10 °C
Timing Specifications
tr_P Primary Winding Gate Drive Rise
Time (10% to 90%)
G1P Through G6P, CGATE = 2500pF 35 70 ns
tf_P Primary Winding Gate Drive Fall
Time (90% to 10%)
G1P Through G6P, CGATE = 2500pF 20 40 ns
tr_S Secondary Winding Gate Drive
Rise Time (10% to 90%)
G1S, CGATE = 2500pF
G2S Through G6S, CTRL = 0 Only, CGATE = 2500pF
30
30
60
60
ns
ns
tf_S Secondary Winding Gate Drive Fall
Time (90% to 10%)
G1S, CGATE = 2500pF
G2S Through G6S, CTRL = 0 Only, CGATE = 2500pF
20
20
40
40
ns
ns
tONP|MAX Primary Winding Switch Maximum
On-Time
RRTONP = 20kΩ (Measured at G1P-G6P) l6 7.2 8.4 µs
tONP|MAX Matching (All 6) ±[(Max – Min)/(Max + Min)] • 100% l±1 ±4 %
tONS|MAX Secondary Winding Switch
Maximum On-Time
RRTONS = 15kΩ (Measured at G1S-G6S) l1 1.2 1.4 µs
tONS|MAX Matching (All 6) ±[(Max – Min)/(Max + Min)] • 100% l±1 ±4 %
tDLY_START Delayed Start Time After New/
Different Balance Command or
Recovery from Voltage/Temp Fault
2 ms
LTC3300-1
6
Rev. C
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) BOOST+ = 25.2V, C6 = 21.6V, C5 = 18V, C4 = 14.4V,
C3 = 10.8V, C2 = 7.2V, C1 = 3.6V, V– = 0V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Voltage Mode Timing Specifications
t1SDI Valid to SCKI Rising Setup Write Operation l10 ns
t2SDI Valid from SCKI Rising Hold Write Operation l250 ns
t3SCKI Low l400 ns
t4SCKI High l400 ns
t5CSBI Pulse Width l400 ns
t6SCKI Rising to CSBI Rising l100 ns
t7CSBI Falling to SCKI Rising l100 ns
t8SCKI Falling to SDO Valid Read Operation l250 ns
fCLK Clock Frequency l1 MHz
tWD1 Watchdog Timer Timeout Period WDT Assertion Measured from Last Valid
Command Byte
l0.75 1.5 2.25 second
tWD2 Watchdog Timer Reset Time WDT Negation Measured from Last Valid
Command Byte
l1.5 5 µs
Current Mode Timing Specifications
tPD1 CSBI to CSBO Delay CCSBO = 150pF l600 ns
tPD2 SCKI Rising to SCKO Delay CSCKO = 150pF l300 ns
tPD3 SDI to SDOI Delay CSDOI = 150pF, Command Byte l300 ns
tPD4 SCKI Falling to SDOI Valid CSDOI = 150pF, Write Balance Command l300 ns
tPD5 SCKI Falling to SDI Valid CSDI = 150pF, Read Operation l300 ns
tSCKO SCKO Pulse Width CSCKO = 150pF 100 ns
Voltage Mode Digital I/O Specifications
VIH Digital Input Voltage High Pins CSBI, SCKI, SDI; VMODE = VREG
Pins CTRL, BOOST, VMODE, TOS
Pin WDT
l
l
l
VREG – 0.5
VREG – 0.5
2
V
V
V
VIL Digital Input Voltage Low Pins CSBI, SCKI, SDI; VMODE = VREG
Pins CTRL, BOOST, VMODE, TOS
Pin WDT
l
l
l
0.5
0.5
0.8
V
V
V
IIH Digital Input Current High Pins CSBI, SCKI, SDI; VMODE = VREG
Pins CTRL, BOOST, VMODE, TOS
Pin WDT, Timed Out
–1
–1
–1
0
0
0
1
1
1
µA
µA
µA
IIL Digital Input Current Low Pins CSBI, SCKI, SDI; VMODE = VREG
Pins CTRL, BOOST, VMODE, TOS
Pin WDT, Not Balancing
–1
–1
–1
0
0
0
1
1
1
µA
µA
µA
VOL Digital Output Voltage Low Pin SDO, Sinking 500µA; VMODE = VREG; Read l0.3 V
IOH Digital Output Current High Pin SDO at 6V l100 nA
Current Mode Digital I/O Specifications
IIL1 Digital Input Current Low Pin CSBI; VMODE = V–
Pin SCKI; VMODE = V–
Pin SDI, VMODE = V–, Write
Pin SDOI, TOS = V–, Read
l
l
l
l
–1500
–5
–5
0
–1250
–2.5
–2.5
2.5
–1000
0
0
5
µA
µA
µA
µA
IIH1 Digital Input Current High Pin CSBI; VMODE = V–
Pin SCKI; VMODE = V–
Pin SDI, VMODE = V–, Write
Pin SDOI, TOS = V–, Read
l
l
l
l
–5
–1500
–1500
1000
–2.5
–1250
–1250
1250
0
–1000
–1000
1500
µA
µA
µA
µA
LTC3300-1
7
Rev. C
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3300-1 is tested under pulsed load conditions such
that TJ ≈ TA. The LTC3300I-1 is guaranteed over the –40°C to 125°C
operating junction temperature range and the LTC3300H-1 is guaranteed
over the –40°C to 150°C operating junction temperature. High junction
temperatures degrade operating lifetimes; operating lifetime is derated
for junction temperatures greater than 125°C. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors. The junction
temperature (TJ, in °C) is calculated from the ambient temperature
(TA, in °C) and power dissipation (PD, in Watts) according to the formula:
TJ = TA + (PD • θJA)
where θJA (in °C/W) is the package thermal impedance.
Note 3: When balancing more than one cell at a time, the individual cell
supply currents can be calculated from the values given in the table as
follows: First add the appropriate table entries cell by cell for the balancers
that are on. Second, for each additional balancer that is on, subtract 70µA
from the resultant sums for C1, C2, C3, C4, and C5, and 450µA from the
resultant sum for C6. For example, if all six balancers are on, the resultant
current for C1 is [250 – 70 + 70 + 70 + 70 + 70 – 5(70)]µA = 110µA and
for C6 is [560 + 560 + 560 + 560 + 560 + 740 – 5(450)]µA = 1290µA.
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency during active balancing. See Gate
Drivers/Gate Drive Comparators and Voltage Regulator in the Operation
section for more information on estimating these currents.
Note 5: The zero current sense voltages given in the table are DC
thresholds. The actual zero current sense voltage seen in application will
be closer to zero due to the slew rate of the winding current and the finite
delay of the current sense comparator.
Note 6: The mid-range value is the average of the minimum and maximum
readings within the group of six.
Note 7: This IC includes overtemperature protection intended to protect
the device during momentary overload conditions. The maximum junction
temperature may be exceeded when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may result in device degradation or failure.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IOH1 Digital Output Current High Pin CSBO; TOS = V–
Pin SCKO; TOS = V–
Pin SDOI, TOS = V–, Write
Pin SDI, VMODE = V–, Read
l
l
l
l
0
1000
1000
2.5
1250
1250
5
–1000
µA
µA
µA
µA
IOL1 Digital Output Current Low Pin CSBO; TOS = V–
Pin SCKO; TOS = V–
Pin SDOI, TOS = V–, Write
Pin SDI, VMODE = V–, Read
l
l
l
l
1000
0
0
–5
1250
2.5
2.5
5
5
µA
µA
µA
µA
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) BOOST+ = 25.2V, C6 = 21.6V, C5 = 18V, C4 = 14.4V,
C3 = 10.8V, C2 = 7.2V, C1 = 3.6V, V– = 0V, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
LTC3300-1
8
Rev. C
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Cell Voltage to Allow
Balancing vs Temperature VREG Load Regulation VREG Voltage vs Temperature
C6 Supply Current When Not
Balancing vs Temperature
TA = 25°C unless otherwise specified.
Supply Current When Balancing
vs Temperature Normalized to 25°C
Minimum Cell Voltage Required
for Primary Gate Drive vs
Temperature
VREG POR Voltage and Minimum
Secondary Gate Drive vs
Temperature
VREG Short-Circuit Current Limit
vs Temperature VRTONP, VRTONS vs Temperature
TEMPERATURE (°C)
–50
IQ(SD) (µA)
16
18
20
25 75 150
33001 G01
14
12
10 –25 0 50 100 125
C6 = 21.6V
TEMPERATURE (°C)
–50
0.94
IQ(ACTIVE)/IQ(ACTIVE AT 25°C)
0.96
0.98
1.00
1.02
0 50 100 150
33001 G02
1.04
1.06
–25 25 75 125
TYP = 740µA
TYP = 560µA
TYP = 250µA
TYP = 70µA
TYP = 60µA
TYP = –70µA
3.6V PER CELL
MATCH CURVE WITH TABLE ENTRY
TEMPERATURE (°C)
–50
1.80
VCELL(MIN) (V)
1.85
1.90
1.95
2.00
0 50 100 150
33001 G03
2.05
2.10
–25 25 75 125
CELL VOLTAGE RISING
CELL VOLTAGE FALLING
TEMPERATURE (°C)
–50
4.2
VCELL(MAX) (V)
4.3
4.5
4.6
4.7
5.2
4.9
050 75
LT1372 • G10
4.4
5.0
5.1
4.8
–25 25 100 125 150
CELL VOLTAGE RISING
CELL VOLTAGE FALLING
IVREG (mA)
0
VREG (V)
4.8
4.9
5.0
40
33001 G05
4.7
4.6
4.5 5 10 15 20 25 30 35 45 50
TA = 25°C
C6 = 36V
C6 = 9V
TEMPERATURE (°C)
–50
4.60
VREG (V)
4.61
4.63
4.64
4.65
4.70
4.67
050 75
33001 G06
4.62
4.68
4.69
4.66
–25 25 100 125 150
IVREG = 10mA
C6 = 36V
C6 = 9V
TEMPERATURE (°C)
–50
VREG (V)
4.000
4.050
150
33001 G07
3.950
3.900 050 100
–25 25 75 125
4.100
3.975
4.025
3.925
4.075
C6 = 21.6V
VREG RISING (POR)
VREG FALLING
(MIN SEC. GATE DRIVE
TEMPERATURE (°C)
–50
50
IVREG (mA)
51
53
54
55
60
57
050 75
33001 G08
52
58
59
56
–25 25 100 125 150
C6 = 21.6V
TEMPERATURE (°C)
–50
1.164
VRTONP, VRTONS (V)
1.176
1.188
1.200
1.212
0 50 100 150
33001 G09
1.224
1.236
–25 25 75 125
VRTONP
VRTONS
LTC3300-1
9
Rev. C
Peak Current Sense Threshold
vs Temperature
Zero Current Sense Threshold
vs Temperature
Primary Winding Switch Maximum
On-Time vs Temperature
VRTONP, VRTONS
vs External Resistance WDT Pin Current vs Temperature WDT Pin Current vs RTONS
RTONP, RTONS RESISTANCE (kΩ)
1
1.164
VRTONP, VRTONS (V)
1.176
1.188
1.200
1.212
1.236
10 100
33001 G10
1.224
VRTONS VRTONP
TA = 25°C
TEMPERATURE (°C)
–50
65
IWDT (µA)
70
75
80
85
–25 0 25 50
33001 G11
75 100 125 150
RTONS = 15k
BALANCING
WDT = 0.5V
SECONDARY OV
WDT = 2V
RTONS (kΩ)
5
0
IWDT (µA)
40
80
120
160
15 25 35 45
33001 G12
200
240
10 20 30 40
TA = 25°C
BALANCING
WDT = 0.5V
SECONDARY OV
WDT = 2V
TEMPERATURE (°C)
–50
VPEAK_P, VPEAK_S (mV)
51
53
55
25 75 150
33001 G13
49
47
45 –25 0 50 100 125
VCELL = 3.6V
RANDOM CELL SELECTED
PRIMARY
SECONDARY
TEMPERATURE (°C)
–50
–10.0
VZERO_P, VZERO_S (mV)
–7.5
–5.0
–2.5
0
0 50 100 150
33001 G14
2.5
5.0
–25 25 75 125
VCELL = 3.6V
RANDOM CELL SELECTED
PRIMARY
SECONDARY
TEMPERATURE (°C)
–50
6.0
tONP(MAX) (µs)
6.4
6.8
7.2
7.6
0 50 100 150
33001 G15
8.0
8.4
–25 25 75 125
RTONP = 20k
VCELL = 3.6V
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C unless otherwise specified.
LTC3300-1
10
Rev. C
CSBO Digital Output Current High
vs Temperature
CSBO Digital Output Current Low
vs Temperature
Balancer Efficiency
vs Cell Voltage
TEMPERATURE (°C)
–50
2.00
IOH1 (µA)
2.25
2.50
2.75
3.00
–25 0 25 50
33001 G19
75 100 125 150
TOS = V–
TEMPERATURE (°C)
–50
IOL1 (µA)
1300
1400
1500
25 75 150
33001 G20
1200
1100
1000 –25 0 50 100 125
TOS = V–
VOLTAGE PER CELL (V)
2.8
89
CHARGE TRANSFER EFFICIENCY (%)
90
91
92
93
3.0 3.2 3.4 3.6
33001 G21
3.8 4.0 4.2
DC2064A DEMO BOARD
ICHARGE = IDISCHARGE = 2.5A
FOR 12-CELL STACK ONLY
DISCHARGE, 12-CELL STACK
DISCHARGE, 6-CELL STACK
CHARGE, 6-CELL STACK
CHARGE, 12-CELL STACK
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C unless otherwise specified.
Secondary Winding Switch
Maximum On-Time vs Temperature
Maximum On-Time
vs RTONP, RTONS
Watchdog Timer Timeout Period
vs Temperature
TEMPERATURE (°C)
–50
1.0
tONS(MAX) (µs)
1.1
1.2
1.3
1.4
–25 0 25 50
33001 G16
75 100 125 150
RTONS = 15k
RTONP, RTONS (kΩ)
5
0
tONP(MAX),tONS(MAX) (µs)
2
6
8
10
20
14
15 25 30
33001 G17
4
16
18
12
10 20 35 40 45
TA = 25°C
PRIMARY
SECONDARY
TEMPERATURE (°C)
–50
1.35
tWD1 (SECONDS)
1.40
1.45
1.50
1.55
0 50 100 150
33001 G18
1.60
1.65
–25 25 75 125
LTC3300-1
11
Rev. C
Balance Current vs Cell Voltage
Protection for Broken Connection
to Cell While Charging
Protection for Broken Connection
to Secondary Stack While
Discharging
Typical Charge Waveforms Typical Discharge Waveforms
Changing Balancer Direction
“On the Fly”
VOLTAGE PER CELL (V)
2.8
BALANCE CURRENT (A)
2.5
2.6
2.7
3.4 3.8
33001 G22
2.4
2.3
3.0 3.2 3.6 4.0 4.2
2.2
2.1
DC2064A DEMO BOARD
ICHARGE = IDISCHARGE = 2.5A
FOR 12-CELL STACK ONLY
CHARGE, 12-CELL STACK
CHARGE, 6-CELL STACK
DISCHARGE, 12-CELL STACK
DISCHARGE, 6-CELL STACK
I1S
50mV/DIV
I1P
50mV/DIV
SECONDARY
DRAIN
50V/DIV
PRIMARY
DRAIN
50V/DIV
2µs/DIV
DC2064A DEMO BOARD
ICHARGE = 2.5A
T = 2
S = 12
33001 G23
I1P
50mV/DIV
I1S
50mV/DIV
SECONDARY
DRAIN
50V/DIV
PRIMARY
DRAIN
50V/DIV 2µs/DIV
DC2064A DEMO BOARD
IDISCHARGE = 2.5A
T = 2
S = 12
33001 G24
C1 PIN
1V/DIV
G1P
2V/DIV
50µs/DIV 33001 G25
3.6V
~5.2V
CONNECTION TO
C1 BROKEN
BALANCING
SHUTS OFF
SECONDARY
STACK VOLTAGE
10V/DIV
G1P
2V/DIV
500µs/DIV 33001 G26
43.2V
~66V
CONNECTION TO
STACK BROKEN
BALANCING
SHUTS OFF
SCKI
5V/DIV
I1P
50mV/DIV
G1P
2V/DIV
20µs/DIV 33001 G27
2ms
CHARGING
DISCHARGING
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C unless otherwise specified.
LTC3300-1
12
Rev. C
PIN FUNCTIONS
Note: The convention adopted in this data sheet is to refer
to the transformer winding paralleling an individual battery
cell as the primary and the transformer winding paralleling
multiple series-stacked cells as the secondary, regardless
of the direction of energy transfer.
G6S, G5S, G4S, G3S, G2S, G1S (Pins 1, 3, 5, 7, 9,
11): G1S through G6S are gate driver outputs for driving
external NMOS transistors connected in series with the
secondary windings of transformers whose primaries are
connected in parallel with battery cells 1 through 6. For
the minimum part count balancing application employing
a single transformer (CTRL = VREG), G2S through G6S
are no connects.
I6S, I5S, I4S, I3S, I2S, I1S (Pins 2, 4, 6, 8, 10, 12): I1S
through I6S are current sense inputs for measuring sec-
ondary winding current in transformers whose primaries
are connected in parallel with battery cells 1 through 6.
For the minimum part count balancing application employ-
ing a single transformer (CTRL = VREG), I2S through I6S
should be tied to V–.
RTONS (Pin 13): Secondary Winding Max tON Setting
Resistor. The RTONS pin servos to 1.2V. A resistor to V–
programs the maximum on-time for all external NMOS
transistors connected in series with secondary windings.
This protects against a short-circuited current sense re-
sistor in any secondary winding. To defeat this function,
connect RTONS to VREG. The secondary winding OVP
threshold (see WDT pin) is also slaved to the value of the
RTONS resistor.
RTONP (Pin 14): Primary Winding Max tON Setting
Resistor. The RTONP pin servos to 1.2V. A resistor to V–
programs the maximum on-time for all external NMOS
transistors connected in series with primary windings.
This protects against a short-circuited current sense
resistor in any primary winding. To defeat this function,
connect RTONP to VREG.
CTRL: (Pin 15): Control Input. The CTRL pin configures
the LTC3300-1 for the minimum part count application
employing a single transformer if CTRL is tied to VREG or
for the multiple transformer application if CTRL is tied to
V–. This pin must be tied to either VREG or V–.
CSBI (Pin 16): Chip Select (Active Low) Input. The CSBI
pin interfaces to a rail-to-rail output logic gate if VMODE
is tied to VREG. CSBI must be driven by the CSBO pin of
another LTC3300-1 if VMODE is tied to V–. See Serial Port
in the Applications Information section.
SCKI (Pin 17): Serial Clock Input. The SCKI pin interfaces
to a rail-to-rail output logic gate if VMODE is tied to VREG.
SCKI must be driven by the SCKO pin of another LTC3300-1
if VMODE is tied to V–. See Serial Port in the Applications
Information section.
SDI (Pin 18): Serial Data Input. When writing data to the
LTC3300-1, the SDI pin interfaces to a rail-to-rail output
logic gate if VMODE is tied to VREG or must be driven by
the SDOI pin of another LTC3300-1 if VMODE is tied to V–.
See Serial Port in the Applications Information section.
SDO (Pin 19): Serial Data Output. When reading data
from the LTC3300-1, the SDO pin is an NMOS open-drain
output if VMODE is tied to VREG. The SDO pin is not used
if VMODE is tied to V–. See Serial Port in the Applications
Information section.
WDT (Pin 20): Watchdog Timer Output (Active High). At
initial power-up and when not attempting to execute a valid
balance command, the WDT pin is high impedance and will
be pulled high (internally clamped to ~5.6V) if an external
pull-up resistor is present. While balancing (or attempt-
ing to balance but not able to due to voltage/temperature
faults) and during normal communication activity, the WDT
pin is pulled low by a precision current source slaved to
the RTONS resistor. However, if no valid command byte is
written for 1.5 seconds (typical), the WDT output will go
back high. When WDT is high, all balancers are off. The
watchdog timer function can be disabled by connecting
WDT to V–. The secondary winding OVP function can also
be implemented using this pin (See Operation section).
V– (Pin 21): Connect V– to the most negative potential in
the series of cells.
I1P, I2P, I3P, I4P, I5P, I6P (Pins 22, 25, 28, 31, 34, 37):
I1P through I6P are current sense inputs for measuring
primary winding current in transformers connected in
parallel with battery cells 1 through 6.
LTC3300-1
13
Rev. C
PIN FUNCTIONS
G1P, G2P, G3P, G4P, G5P, G6P (Pins 23, 26, 29, 32, 35,
38): G1P through G6P are gate driver outputs for driving
external NMOS transistors connected in series with the
primary windings of transformers connected in parallel
with battery cells 1 through 6.
C1, C2, C3, C4, C5, C6 (Pins 24, 27, 30, 33, 36, 39):
C1 through C6 connect to the positive terminals of bat-
tery cells 1 through 6. Connect the negative terminal of
battery cell 1 to V–.
BOOST+ (Pin 40): Boost+ Pin. Connects to the anode of
the external flying capacitor used for generating sufficient
gate drive necessary for balancing the topmost battery cell
in a given LTC3300-1 sub-stack. A Schottky diode from C6
to BOOST+ is needed as well. Alternately, the BOOST+ pin
can connect to one cell up in the above sub-stack (if pres-
ent). This pin is effectively C7. (Note: “Sub-stack” refers
to the 3-6 battery cells connected locally to an individual
LTC3300-1 as part of a larger stack.)
BOOST– (Pin 41): Boost– Pin. Connects to the cathode of
the external flying capacitor used for generating sufficient
gate drive necessary for balancing the topmost battery cell
in a given LTC3300-1 sub-stack. Alternately, if the BOOST+
pin connects to the next higher cell in the above sub-stack
(if present), this pin is a no connect.
BOOST (Pin 42): Enable Boost Pin. Connect BOOST to VREG
to enable the boosted gate drive needed for balancing the
top cell in a given LTC3300-1 sub-stack. If the BOOST+ pin
can be connected to the next cell up in the stack (i.e., C1
of the next LTC3300-1 in the stack), then BOOST should
be tied to V– and BOOST– no connected. This pin must
be tied to either VREG or V–.
SDOI (Pin 43): Serial Data Output/Input. SDOI transfers
data to and from the next IC higher in the daisy chain when
writing and reading. See Serial Port in the Applications
Information section.
SCKO (Pin 44): Serial Clock Output. SCKO is a buffered
and one-shotted version of the serial clock input, SCKI,
when CSBI is low. SCKO drives the next IC higher in the
daisy chain. See Serial Port in the Applications Informa-
tion section.
CSBO (Pin 45): Chip Select (Active Low) Output. CSBO
is a buffered version of the chip select input, CSBI. CSBO
drives the next IC higher in the daisy chain. See Serial Port
in the Applications Information section.
VMODE (Pin 46): Voltage Mode Input. When VMODE is tied
to VREG, the CSBI, SCKI, SDI and SDO pins are configured
as voltage inputs and outputs. This means these pins
accept VREG-referred rail-to-rail logic levels. Connect
VMODE to VREG when the LTC3300-1 is the bottom device
in a daisy chain.
When VMODE is tied to V–, the CSBI, SCKI and SDI pins
are configured as current inputs and outputs, and SDO is
unused. Connect VMODE to V– when the LTC3300-1 is be-
ing driven by another LTC3300-1 lower in the daisy chain.
This pin must be tied to either VREG or V –.
TOS (Pin 47): Top Of Stack Input. Tie TOS to VREG when
the LTC3300-1 is the top device in a daisy chain. Tie TOS
to V– when the LTC3300-1 is any other device in the daisy
chain. When TOS is tied to VREG, the LTC3300-1 ignores
the SDOI input. When TOS is tied to V–, the LTC3300-1
expects data to be passed to and from the SDOI pin. This
pin must be tied to either VREG or V–.
VREG (Pin 48): Linear Voltage Regulator Output. This 4.8V
output should be bypassed with a 1µF or larger capacitor
to V–. The VREG pin is capable of supplying up to 40mA
to internal and external loads. The VREG pin does not sink
current.
V– (Exposed Pad Pin 49): The exposed pad should be
connected to a continuous (ground) plane biased at V– on
the second layer of the printed circuit board by several
vias directly under the LTC3300-1.
LTC3300-1
14
Rev. C
BLOCK DIAGRAM
+
–
+
BOOST+
BOOST
GATE DRIVE
GENERATOR
6-CELL
SYNCHRONOUS
FLYBACK
CONTROLLER
BALANCER
C6
C6
C5
DATA
12
STATUS
12
C5
50mV/0
0/50mV
VREG
V–
+
–
39
BOOST
BOOST–
VREG
SD
C6 40mA
MAX
V–POR
4.8V 42
41
G6P 38
I6P 37
I6S 2
G6S
PINS 3 TO 10,
25 TO 36
1
BALANCER
CONTROLLER
+
–
C2
C1
V–
50mV/0
0/50mV
VREG
V–
+
–
24
G1P 23
I1P 22
I1S 12
G1S 11
20
BALANCER
CONTROLLER
2
ACTIVE
2
MAX ON-TIME
VOLT-SEC
CLAMPS
THERMAL
SHUTDOWN
BOOST+
40
V–RTONS
13
CTRL
15
V–
WDT
16 CSBI
17 SCKI
18 SDI
19 SDO
43 SDOI
44 SCKO
45 CSBO
RESET
RTONP
33001 BD
14
TOS
47
V–
5.6V
1.2V
RTONS
V–
21
EXPOSED
PAD
49
VMODE
46
LEVEL-SHIFTING
SERIAL
INTERFACE
VREG
48
VOLTAGE
REGULATOR
CRC/RCRC
PACKET ERROR
CHECKING
16
WATCHDOG
TIMER
LTC3300-1
16
Rev. C
OPERATION
Battery Management System (BMS)
The LTC3300-1 multicell battery cell balancer is a key
component in a high performance battery management
system (BMS) for series-connected Li-Ion cells. It is de-
signed to operate in conjunction with a monitor, a charger,
and a microprocessor or microcontroller (see Figure1).
The function of the balancer is to efficiently transfer charge
to/from a given out-of-balance cell in the stack from/to
a larger group of neighboring cells (which includes that
individual cell) in order to bring that cell into voltage or
capacity balance with its neighboring cells. Ideally, this
charge would always be transferred directly from/to the
entire stack, but this is impractical for voltage reasons
when the number of cells in the overall stack is large. The
LTC3300-1 is designed to interface to a group of up to 6
series cells, so the number of LTC3300-1 ICs required
to balance a series stack of N cells is N/6 rounded up to
the nearest integer, with no limitation imposed on how
large N can be. For connecting an individual LTC3300-1
in the stack to fewer than 6 cells, refer to the Applications
Information section.
Because the balancing function entails switching large
(multiampere) currents between cells, precision voltage
monitoring in the BMS is better served by a dedicated
monitor component such as the LTC6803-1 or one of its
family of parts. The LTC6803-1 provides for high precision
A/D monitoring of up to 12 series cells. The only voltage
monitoring provided by the LTC3300-1 is a coarse “out-
of-range” overvoltage and undervoltage cell balancing
disqualification, which provides a safety shutoff in the
event Kelvin sensing to the monitor component is lost.
In the process of bringing the cells into balance, the over-
all stack is slightly discharged. The charger component
provides a means for net charging of the entire stack from
an alternate power source.
The last component in the BMS is a microprocessor/
microcontroller which communicates directly with the
balancer, monitor, and charger to receive voltage, current,
and temperature information and to implement a balanc-
ing algorithm.
There is no single balancing algorithm optimal for all
situations. For example, during net charging of the overall
stack, it may be desirable to discharge the highest voltage
cells first to avoid reaching terminal charge on any cell
before the entire stack is fully charged. Similarly, during
net discharging of the overall stack, it may be desirable
to charge the lowest voltage cells first to keep them from
reaching a critically low level. Other algorithms may
prioritize fastest time to overall balance. The LTC3300-1
implements no algorithm for balancing the stack. Instead it
provides maximum flexibility by imposing no limitation on
the algorithm implemented as all individual cell balancers
can operate simultaneously and bidirectionally.
Unidirectional Versus Bidirectional Balancing
Most balancers in use today employ a unidirectional (dis-
charge only) approach. The simplest of these operate by
switching in a resistor across the highest voltage cell(s)
in the stack (passive balancing). No charge is recovered
in this approach -instead it is dissipated as heat in the
resistive element. This can be improved by employing an
energy storage element (inductive or capacitive) to transfer
LTC3300-1
17
Rev. C
CELL N
CELL N – 1
CELL N – 2
CELL N – 3
CELL N – 4
CELL N – 5
CELL N – 6
CELL N – 7
CELL N – 8
CELL N – 9
CELL N – 10
CELL N – 11
CELL 12
CELL 11
CELL 10
CELL 9
CELL 8
CELL 7
CELL 6
CELL 5
CELL 4
CELL 3
CELL 2
CELL 1
C5
C4
C3
C2
C1
SERIAL
COMMUNICATION
ICHARGE
SERIAL
COMMUNICATION
SERIAL COMMUNICATION BUS
SERIAL
COMMUNICATION
V–
C6 C11 I
LOAD
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1 V–
C12
LTC3300-1
BALANCER
LTC6803-1
MONITOR
TOP OF STACK
CHARGER
CN
V–
C5
C4
C3
C2
C1
LTC3300-1
BALANCER
SERIAL
COMMUNICATION
V–
•
•
•
•
•
•
•
•
•
C6
C5
C4
C3
C2
C1
V–
C6 C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
33001 F01
V–
C12
LTC3300-1
BALANCER
LTC6803-1
MONITOR
C5
C4
C3
C2
C1
LTC3300-1
BALANCER
V–
C6
µP/µC
VCC
VEE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Figure1. LTC3300-1/LTC6803-1 Typical Battery Management System (BMS)
OPERATION
LTC3300-1
18
Rev. C
OPERATION
charge from the highest voltage cell(s) in the stack to other
lower voltage cells in the stack (active balancing). This
can be very efficient (in terms of charge recovery) for the
case where only a few cells in the overall stack are high,
but will be very inefficient (and time consuming) for the
case where only a few cells in the overall stack are low. A
bidirectional active balancing approach, such as employed
by the LTC3300-1, is needed to achieve minimum balanc-
ing time and maximum charge recovery for all common
cell capacity errors.
VCC
ICHARGE
ISECONDARY
IPRIMARY
VPRIMARY
V
SECONDARY
VTOP_OF_STACK
LPRI
10µH
G1P
I1P
RSNS_SEC
25mΩ
RSNS_PRI
25mΩ
G1S
I1S
ILOAD
(48V)
(4V)
T: 1•
•
5µs
Single-Cell Discharge Cycle for Cell 1 Single-Cell Charge Cycle for Cell 1
IPEAK_PRI = 2A
(I1P = 50mV)
t
IPRIMARY
5µs
2A
t
–IPRIMARY
~417ns
2A
t
–ISECONDARY
52V
52.05V
t
VPRIMARY
4V
50mV
50mV
50mV 48V
4V
48V
52V
t
VSECONDARY
~417ns
IPEAK_SEC = 2A
(I1S = 50mV)
t
ISECONDARY
33001 F02
52V 51.95V
t
VPRIMARY
4V
50mV
4V
48V
50mV
50mV 52V
48V
t
VSECONDARY
CELL 1
+
CELL 2
+
CELL 12
+
CELL 13
+
CELL N
+
Figure2. Synchronous Flyback Balancing Example with T = 1, S = 12
Synchronous Flyback Balancer
The balancing architecture implemented by the LTC3300-1
is bidirectional synchronous flyback. Each LTC3300-1
contains six independent synchronous flyback controllers
that are capable of directly charging or discharging an
individual cell. Balance current is scalable with external
components. Each balancer operates independently of
the others and provides a means for bidirectional charge
transfer between an individual cell and a larger group of
adjacent cells. Refer to Figure2.
LTC3300-1
19
Rev. C
OPERATION
Cell Discharging (Synchronous)
When discharging is enabled for a given cell, the primary
side switch is turned on and current ramps in the primary
winding of the transformer until the programmed peak
current (IPEAK_PRI) is detected at the InP pin. The primary
side switch is then turned off, and the stored energy in
the transformer is transferred to the secondary-side cells
causing current to flow in the secondary winding of the
transformer. The secondary-side synchronous switch
is turned on to minimize power loss during the transfer
period until the secondary current drops to zero (detected
at InS). Once the secondary current reaches zero, the
secondary switch turns off and the primary-side switch
is turned back on thus repeating the cycle. In this manner,
charge is transferred from the cell being discharged to all
of the cells connected between the top and bottom of the
secondary side—thereby charging the adjacent cells. In the
example of Figure2, the secondary-side connects across
12 cells including the cell being discharged.
IPEAK_PRI is programmed using the following equation:
IPEAK _PRI =
50mV
RSNS_PRI
Cell discharge current (primary side) and secondary-side
charge recovery current are determined to first order by
the following equations:
IDISCHARGE =
I
PEAK _PRI
2
S
S+T
⎛
⎝
⎜⎞
⎠
⎟
ISECONDARY =IPEAK _PRI
2
1
S+T
⎛
⎝
⎜⎞
⎠
⎟ηDISCHARG
E
where S is the number of secondary-side cells, 1:T is the
transformer turns ratio from primary to secondary, and
ηDISCHARGE is the transfer efficiency from primary cell
discharge to the secondary side stack.
Cell Charging
When charging is enabled for a given cell, the secondary-
side switch for the enabled cell is turned on and current
flows from the secondary-side cells through the trans-
former. Once IPEAK_SEC is reached in the secondary side
(detected at the InS pin), the secondary switch is turned
off and current then flows in the primary side thus charging
the selected cell from the entire stack of secondary cells. As
with the discharging case, the primary-side synchronous
switch is turned on to minimize power loss during the cell
charging phase. Once the primary current drops to zero,
the primary switch is turned off and the secondary-side
switch is turned back on thus repeating the cycle.
IPEAK_SEC is programmed using the following equation:
IPEAK _SEC =
50mV
RSNS_SEC
Cell charge current and corresponding secondary-side
discharge current are determined to first order by the
following equations:
ICHARGE =
I
PEAK _ SEC
2
ST
S+T
⎛
⎝
⎜⎞
⎠
⎟ηCHARGE
ISECONDARY =IPEAK _ SEC
2
T
S+T
⎛
⎝
⎜⎞
⎠
⎟
where S is the number of secondary cells in the stack, 1:T
is the transformer turns ratio from primary to secondary,
and ηCHARGE is the transfer efficiency from secondary-side
stack discharge to the primary-side cell.
Each balancer’s charge transfer “frequency” and duty
factor depend on a number of factors including IPEAK_PRI,
IPEAK_SEC, transformer winding inductances, turns ratio,
cell voltage and the number of secondary-side cells.
The frequency of switching seen at the gate driver outputs
is given by:
fDISCHARGE =
S
S+T•
V
CELL
LPRI •IPEAK _PRI
fCHARGE =S
S+T•VCELL
LPRI •IPEAK _SEC • T
where LPRI is the primary winding inductance.
Figure3 shows a fully populated LTC3300-1 application
employing all six balancers.
LTC3300-1
20
Rev. C
OPERATION
Figure3. LTC3300-1 6-Cell Active Balancer Module Showing Power Connections for the Multi-Transformer Application (CTRL = V–)
+
+
+
+
1:1
•
•
•
•
•
•
•
•
25mΩ
10µH
CELL 6
UP TO
CELL 12
CELL 5
CELL 2
CELL 1
10µH
C6
0.1µF
10µF
G6P
CSBO
SCKO
SDOI
CSBI
SCKI
SDI
SDO
TOS
VMODE
WDT
I6P
G6S
SERIAL
COMMUNICATION
RELATED
PINS
I6S
C5
G5P
I5P
G5S
I5S
C4
C3
LTC3300-1
C2
G2P
I2P
G2S
I2S
C1
G1P
I1P
G1SVREG
BOOST I1S
RTONSRTONP
BOOST+
6.8Ω
BOOST–
CTRL V–
25mΩ
1:1
25mΩ
10µH10µH
25mΩ
1:1
25mΩ
10µH10µH
25mΩ
1:1
25mΩ
10µH10µH
25mΩ
6.98k
33001 F03
22.6k10µF
•
•
•
•
•
•
•
•
10µF
•
•
10µF
•
•
10µF
LTC3300-1
21
Rev. C
OPERATION
Figure4. Diagram of Power Transfer Interleaving Through the
Stack, Transformer Connections for High Voltage Stacks
Balancing High Voltage Battery Stacks
Balancing series connected batteries which contain >>12
cells in series requires interleaving of the transformer sec-
ondary connections in order to achieve full stack balancing
while limiting the breakdown voltage requirements of the
primary- and secondary-side power FETs. Figure4 shows
typical interleaved transformer connections for a multicell
battery stack in the generic sense, and Figure5 for the
specific case of an 18-cell stack. In these examples, the
secondary side of each transformer is connected to the
top of the cell that is 12 positions higher in the stack than
the bottom of the lowest voltage cell in each LTC3300-1
sub-stack. For the top most LTC3300-1 in the stack, it is
not possible to connect the secondary side of the trans-
former across 12 cells. Instead, it is connected to the top
of the stack, or effectively across only 6 cells. Interleaving
in this fashion allows charge to transfer between 6-cell
sub-stacks throughout the entire battery stack.
Max On-Time Volt-Sec Clamps
The LTC3300-1 contains programmable fault protection
clamps which limit the amount of time that current is
allowed to ramp in either the primary or secondary wind-
ings in the event of a shorted sense resistor. Maximum
on time for all primary connections (active during cell
discharging) and all secondary connections (active during
cell charging) is individually programmable by connecting
resistors from the RTONP and RTONS pins to V– according
to the following equations:
tON(MAX)|PRIMARY =7.2µs
R
TONP
20kΩ
tON(MAX)|SECONDARY =1.2µsRTONS
15kΩ
For more information on selecting the appropriate
maximum on-times, refer to the Applications Information
section.
To defeat this function, short the appropriate RTON pin(s)
to VREG.
+
+
•
•
•
•
LTC3300-1
POWER STAGES
LTC3300-1
POWER STAGES
FROM CELL N-12
SECONDARY
TO CELL 24
PRI SEC
+
+
+
+
+
+
•
•
•
•
•
•
•
•
•
•
•
•
LTC3300-1
POWER STAGES
•
•
•
•
•
•
•
•
•
•
•
•
SEC PRI
SEC PRI
+
+
•
•
•
•
CELL 18
CELL 13
CELL 6
CELL 7
CELL 12
CELL N-6
CELL N
CELL 1
CELL 2
CELL 3
CELL 4
CELL 5
33001 F04
LTC3300-1
POWER STAGES
PRI
TOP
SEC
+
+
•
•
•
•
LTC3300-1
22
Rev. C
OPERATION
Figure5. 18-Cell Active Balancer Showing Power Connections, Interleaved
Transformer Secondaries and BOOST+ Rail Generation Up the Stack
1:1
10µH
TO TRANSFORMER
SECONDARIES OF
BALANCERS 14 TO 18
10µH
CELL 18
25mΩ
25mΩ
C1
C6
G1P
I1P
G1S
I1S
VREG
V–
LTC3300-1
BOOST
BOOST+
BOOST–
0.1µF
6.8Ω
1:1
10µH
TO TRANSFORMER
SECONDARIES OF
BALANCERS 8 TO 12
10µH
25mΩ
25mΩ
C1
C6
G1P
I1P
G1S
I1S
V–
LTC3300-1
BOOST
BOOST+
1:1
10µH
TO TRANSFORMER
SECONDARIES OF
BALANCERS 2 TO 6
10µH
25mΩ
25mΩ
33001 F05
C1
C6
G1P
I1P
G1S
I1S
V–
LTC3300-1
BOOST
BOOST+
+
CELL 13
+
CELL 12
+
CELL 7
+
CELL 6
+
CELL 1
+
•
•
10µF
•
•
10µF
•
•
10µF
LTC3300-1
23
Rev. C
OPERATION
Gate Drivers/Gate Drive Comparators
All secondary-side gate drivers (G1S through G6S) are
powered from the VREG output, pulling up to 4.8V when
on and pulling down to V– when off. All primary-side
gate drivers (G1P through G6P) are powered from their
respective cell voltage and the next cell voltage higher in
the stack (see Table 1). An individual cell balancer will only
be enabled if its corresponding cell voltage is greater than
2V and the cell voltage of the next higher cell in the stack
is also greater than 2V. For the G6P gate driver output,
the next higher cell in the stack is C1 of the next higher
LTC3300-1 in the stack (if present) and is only used if the
boosted gate drive is disabled (by connecting BOOST =
V–). If the boosted gate drive is enabled (by connecting
BOOST = VREG), only the C6 cell voltage is looked at to
enable balancing of Cell 6. In the case of the topmost
LTC3300-1 in the stack, the boosted gate drive must be
enabled. The boosted gate drive requires an external diode
from C6 to BOOST+ and a boost capacitor from BOOST+ to
BOOST–. For information on selecting these components,
refer to the Applications Information section. Also note
that the dynamic supply current referred to in Note 4 of
the Electrical Characteristics table adds to the terminal
currents of the pins indicated in the Voltage When Off and
Voltage When On columns of Table 1.
The gate drive comparators have a DC hysteresis of 70mV.
For improved noise immunity, the inputs are internally
low pass filtered and the outputs are filtered so as to
not transition unless the internal comparator state is
unchanged for 3µs to 6µs (typical). If insufficient gate drive
is detected while active balancing is in progress (perhaps,
for example, if the stack is under heavy load), the affected
balancer(s) and only the affected balancer(s) will shut off.
The balance command remains stored in memory, and
active balancing will resume where it left off if sufficient
gate drive is subsequently restored. This can happen if,
for example, the stack is being charged.
Cell Overvoltage Comparators
In addition to sufficient gate drive being required to enable
balancing, there are additional comparators which disable
all active balancing if any of the six individual cell voltages
is greater than 5V. These comparators have a DC hysteresis
of 500mV. For improved noise immunity, the inputs are
internally low pass filtered and the outputs are filtered so
as to not transition unless the internal comparator state
is unchanged for 3µs to 6µs (typical). If any cell voltage
goes overvoltage while active balancing is in progress,
all active balancers will shut off. The balance command
remains stored in memory, and active balancing will resume
where if left off if the cell voltage subsequently comes back
in range. These comparators will protect the LTC3300-1 if
a connection to a battery is lost while balancing and the
cell voltage is still increasing as a result of that balancing.
Table 1
DRIVER OUTPUT VOLTAGE WHEN OFF VOLTAGE WHEN ON GATE DRIVE REQUIRED TO ENABLE BALANCING
G1P V- C2 (C2 – C1) ≥ 2V and (C1 – V–) ≥2V
G2P C1 C3 (C3 – C2) ≥ 2V and (C2 – C1) ≥2V
G3P C2 C4 (C4 – C3) ≥ 2V and (C3 – C2) ≥2V
G4P C3 C5 (C5 – C4) ≥ 2V and (C4 – C3) ≥2V
G5P C4 C6 (C6 – C5) ≥ 2V and (C5 – C4) ≥2V
G6P C5 If BOOST = VREG: BOOST+ (Generated) (C6 – C5) ≥ 2V
If BOOST = V–: BOOST+ = C7* (C7* – C6) ≥ 2V and (C6 – C5) ≥ 2V
*C7 is equal to C1 of the next higher LTC3300-1 in the stack if this connection is used.
LTC3300-1
24
Rev. C
Voltage Regulator
A linear voltage regulator powered from C6 creates a
4.8V rail at the VREG pin which is used for powering
certain internal circuitry of the LTC3300-1 including all 6
secondary gate drivers. The VREG output can also be used
for powering external loads, provided that the total DC
loading of the regulator does not exceed 40mA at which
point current limit is imposed to limit on-chip power dis-
sipation. The internal component of the DC load current
is dominated by the average gate driver current(s) (G1S
through G6S), each approximated by C • V • f, where C
is the gate capacitance of the external NMOS transistor,
V = VREG = 4.8V, and f is the frequency that the gate
driver output is running at. FET manufacturers usually
specify the C • V product as Qg (gate charge) measured
in coulombs at a given gate drive voltage. The frequency,
f, is dependent on many terms, primarily the voltage of
each individual cell, the number of cells in the secondary
stack, the programmed peak balancing current, and the
transformer primary and secondary winding inductances.
In a typical application, the C • V • f current loading the
VREG output is expected to be low single-digit milliamperes
per driver. Note that the VREG loading current is ultimately
delivered from the C6 pin. For applications involving very
large balance currents and/or employing external NMOS
transistors with very large gate capacitance, the VREG
output may need to source more than 40mA average. For
information on how to design for these situations, refer
to the Applications Information section.
One additional function slaved to the VREG output is
the power-on reset (POR). During initial power-up and
subsequently if the VREG pin voltage ever falls below ap-
proximately 4V (e.g., due to overloading), the serial port
is cleared to the default power-up state with no balancers
active. This feature thus guarantees that the minimum gate
drive provided to the external secondary side FETs is also
4V. For a 10µF capacitor loading the output at initial power-
up, the output reaches regulation in approximately 1ms.
Thermal Shutdown
The LTC3300-1 has an overtemperature protection circuit
which shuts down all active balancing if the internal silicon
die temperature rises to approximately 155°C. When in
thermal shutdown, all serial communication remains active
and the cell balancer status (which contains temperature
information) can be read back. The balance command
which had been being executed remains stored in memory.
This function has 10°C of hysteresis so that when the die
temperature subsequently falls to approximately 145°C,
active balancing will resume with the previously execut-
ing command.
Watchdog Timer Circuit
The watchdog timer circuit provides a means of shutting
down all active balancing in the event that communica-
tion to the LTC3300-1 is lost. The watchdog timer initiates
when a balance command begins executing and is reset
to zero every time a valid 8-bit command byte (see Serial
Port Operation) is written. The valid command byte can
be an execute, a write, or a read (command or status).
“Partial” reads and writes are considered valid, i.e., it is
only necessary that the first 8 bits have to be written and
contain the correct address.
Referring to Figure 6a, at initial power-up and when not
balancing, the WDT pin is high impedance and will be
pulled high (internally clamped to ~5.6V) if an external
pull-up resistor is present. While balancing and during
normal communication activity, the WDT pin is pulled
low by a precision current source equal to 1.2V/RTONS.
(Note: if the secondary volt-second clamp is defeated
by connecting RTONS to VREG, the watchdog function is
also defeated.) If no valid command byte is written for
1.5 seconds (typical), the WDT output will go back high.
When WDT is high, all balancers will be shut down but
the previously executing balance command still remains
in memory. From this timed-out state, a subsequent valid
command byte will reset the timer, but the balancers will
OPERATION
LTC3300-1
25
Rev. C
OPERATION
ACTIVE 5.6V
LTC3300-1
VREG
WDT
RTONS
RTONS
33001 F06a
V–
1.2V
RTONS
RWDT
ACTIVE 5.6V
LTC3300-1VTH = 1.4V
VREG
WDT
RTONS
RTONS
PAUSE/
RESUME
33001 F06b
1.2V
RTONS
ACTIVE 5.6V
VREG
VREG
TO TRANSFORMER
SECONDARY WINDINGS
LTC3300-1
WDT
RTONS
RTONS
VREG
VREG
PAUSE/
RESUME
EITHER/OR
PAUSE/
RESUME
33001 F06c
1.2V
RTONS
RSEC_OVP
(6a) Watchdog Timer Only (WDT = V– to Defeat) (6b) Pause/Resume Balancing Only
(6c) Watchdog Timer with Pause/Resume Balancing and Secondary Winding OVP Protection
Figure6. WDT Pin Connection Options
only restart if an execute command is written. To defeat
the watchdog function, simply connect the WDT pin to V–.
Pause/Resume Balancing (via WDT Pin)
The WDT output pin doubles as a logic input (TTL levels)
which can be driven by an external logic gate as shown in
Figure 6b (no watchdog), or by a PMOS/three-state logic
gate as shown in Figure 6c (with watchdog) to pause and
resume balancing in progress. The external pull-up must
have sufficient drive capability to override the current source
to ground at the WDT pin (=1.2V/RTONS). Provided that
the internal watchdog timer has not independently timed
out, externally pulling the WDT pin high will immediately
pause balancing, and it will resume where it left off when
the pin is released.
Secondary Winding OVP Function (via WDT pin)
The precision current source pull-down on the WDT pin
during balancing can be used to construct an accurate
secondary winding OVP protection circuit as shown in
Figure 6c. A second external resistor, scaled to RTONS
and connected to the transformer secondary winding, is
used to set the comparator threshold. An NMOS cascode
device (with gate tied to VREG) is also needed to protect
LTC3300-1
26
Rev. C
OPERATION
the WDT pin from high voltage. The secondary winding
OVP thresholds are given by:
VSEC|OVP(RISING) = 1.4V + 1.2V • (RSEC_OVP/RTONS)
VSEC|OVP(FALLING) = 1.4V + 1.05V • (RSEC_OVP/RTONS)
This comparator will protect the LTC3300-1 application
circuit if the secondary winding connection to the battery
stack is lost while balancing and the secondary winding
voltage is still increasing as a result of that balancing. The
balance command remains stored in memory, and active
balancing will resume where it left off if the stack voltage
subsequently falls to a safer level.
Single Transformer Application (CTRL = VREG)
Figure7 shows a fully populated LTC3300-1 application
employing all six balancers with a single shared custom
transformer. In this application, the transformer has six
primary windings coupled to a single secondary winding.
Only one balancer can be active at a given time as all six
share the secondary gate driver G1S and secondary current
sense input I1S. The unused gate driver outputs G2S-G6S
must be left floating and the unused current sense inputs
I2S-I6S should be connected to V–. Any balance command
which attempts to operate more than one balancer at a time
will be ignored. This application represents the minimum
component count active balancer achievable.
SERIAL PORT OPERATION
Overview
The LTC3300-1 has an SPI bus compatible serial port.
Several devices can be daisy chained in series. There are
two sets of serial port pins, designated as low side and
high side. The low side and high side ports enable devices
to be daisy chained even when they operate at different
power supply potentials. In a typical configuration, the
positive power supply of the first, bottom device is con-
nected to the negative power supply of the second, top
device. When devices are stacked in this manner, they can
be daisy chained by connecting the high side port of the
bottom device to the low side port of the top device. With
this arrangement, the master writes to or reads from the
cascaded devices as if they formed one long shift register.
The LTC3300-1 translates the voltage level of the signals
between the low side and high side ports to pass data up
and down the battery stack.
Physical Layer
On the LTC3300-1, seven pins comprise the low side and
high side ports. The low side pins are CSBI, SCKI, SDI
and SDO. The high side pins are CSBO, SCKO and SDOI.
CSBI and SCKI are always inputs, driven by the master
or by the next lower device in a stack. CSBO and SCKO
are always outputs that can drive the next higher device
in a stack. SDI is a data input when writing to a stack of
devices. For devices not at the bottom of a stack, SDI is a
data output when reading from the stack. SDOI is a data
output when writing to and a data input when reading from
a stack of devices. SDO is an open-drain output that is
only used on the bottom device of a stack, where it may
be tied with SDI, if desired, to form a single, bidirectional
port. The SDO pin on the bottom device of a stack requires
a pull-up resistor. For devices up in the stack, SDO should
be tied to the local V– or left floating.
To communicate between daisy-chained devices, the high
side port pins of a lower device (CSBO, SCKO and SDOI)
should be connected through high voltage diodes to the
respective low side port pins of the next higher device
(CSBI, SCKI and SDI). In this configuration, the devices
communicate using current rather than voltage. To signal
a logic high from the lower device to the higher device,
the lower device sinks a smaller current from the higher
device pin. To signal a logic low, the lower device sinks
a larger current. Likewise, to signal a logic high from
the higher device to the lower device, the higher device
sources a larger current to the lower device pin. To signal
a logic low, the higher device sources a smaller current.
LTC3300-1
27
Rev. C
OPERATION
Figure7. LTC3300-1 6-Cell Active Balancer Module Showing Power Connections For The Single Transformer Application (CTRL = VREG)
10µH
EACH
1:1 •
UP TO CELL 12
•
•
•
25mΩ
CELL 6
+
10µH
25mΩ
CELL 5
+
10µH
10µH
10µH
10µH
•
•
•
•
•
•
25mΩ
CELL 4
+
25mΩ
CELL 3
+
25mΩ
CELL 2
+
25mΩ
CELL 1
NC
33001 F07
6.98k
+25mΩ
22.6k10µF
BOOST+
C6
G6P
I6P
C5
G5P
I5P
C4
G4P
I4P
C3
G3P
I3P
C2
G2P
LTC3300-1
I2P
C1
G1P
G1S
I1S
G2S-G6S
I2S-I6S
V–
CTRL
BOOST
VREG
10µF
I1P
BOOST–
RTONSRTONP
0.1µF
6.8Ω
CSBO
SCKO
SDOI
CSBI
SCKI
SDI
SDO
TOS
VMODE
WDT
SERIAL
COMMUNICATION
RELATED
PINS
10µF
10µF
10µF
10µF
10µF
LTC3300-1
28
Rev. C
CSBI
SCKI
SDI MSB (CMD) LSB (CMD)
33001 F08
CSBI
SCKI
SDI MSB (CMD) LSB (CMD) LSB (DATA)
MSB (DATA)
Transmission Format (Write)
Transmission Format (Read)
LSB (DATA)
MSB (DATA)SDO
Figure8.
OPERATION
Figure9. Current Mode Interface
+
–
WRITE
READ 1
VSENSE
(WRITE)
+
–
VSENSE
(READ)
33001 F09
HIGH SIDE PORT
ON LOWER DEVICE
LOW SIDE PORT
ON HIGHER DEVICE
See Figure9. Since CSBO, SCKO and SDOI voltages are
close to the V– of the high side device, the V– of the high
side device must be at least 5V higher than that of the low
side device to guarantee current flows of the current mode
interface. It is recommended that high voltage diodes be
placed in series with the SPI daisy-chain signals as shown
if Figure13. These diodes prevent reverse voltage stress
on the IC if a battery group bus bar is removed. See Bat-
tery Interconnection Integrity for additional information.
Standby current consumed in the current mode serial
interface is minimized when CSBI is logic high.
The voltage mode pin (VMODE) determines whether the low
side serial port is configured as voltage mode or current
mode. For the bottom device in a daisy-chain stack, this
LTC3300-1
29
Rev. C
OPERATION
pin must be pulled high (tied to VREG). The other devices
in the daisy chain must have this pin pulled low (tied to V–)
to designate current mode communication. To designate
the top-of-stack device, the TOS pin on the top device of
a daisy chain must be tied high. The other devices in the
stack must have TOS tied low. See the application on the
last page of this data sheet.
Command Byte
All communication to the LTC3300-1 takes place with CSBI
logic low. The first 8 clocked in data bits after a high-to-
low transition on CSBI represent the command byte and
are level-shifted through all LTC3300-1 ICs in the stack
so as to be simultaneously read by all LTC3300-1 ICs in
the stack. The 8-bit command byte is written MSB first
per Table 2. The first 5 bits must match a fixed internal
address [10101] which is common to all LTC3300-1’s in
the stack, or all subsequent data will be ignored until CSBI
transitions high and then low again. The 6th and 7th bits
program one of four commands as shown in Table 3. The
8th bit in the command byte must be set such that the
entire 8-bit command byte has even parity. If the parity is
incorrect, the current balance command being executed
(from the last previously successful write) is terminated
immediately and all subsequent (write) data is ignored until
CSBI transitions high and then low again. Incorrect parity
takes this action whether or not the address matches. This
thereby provides a fast means to immediately terminate
balancing-in-progress by intentionally writing a command
byte with incorrect parity.
Table 2. Command Byte Bit Mapping
(Defaults to 0x00 in Reset State)
1
(MSB)
0 1 0 1 CMDA CMDB Parity Bit
(LSB)
Table 3. Command Bits
CMDA CMDB Communication Action
0 0 Write Balance Command (without Executing)
0 1 Readback Balance Command
1 0 Read Balance Status
1 1 Execute Balance Command
Write Balance Command
If the command bits program Write Balance Command,
all subsequent write data must be mod 16 bits (before
CSBI transitions high) or it will be ignored. The internal
command holding register will be cleared which can be
verified on readback. The current balance command being
executed (from the last previously successful write) will
continue, but all active balancing will be turned off if an
Execute Balance Command is subsequently written. Each
LTC3300-1 in the stack expects 16 bits of write data writ-
ten MSB first per Table 4. Successive 16-bit write data is
shifted in starting with the highest LTC3300-1 in the stack
and proceeding down the stack. In this manner, the first
16 bits will be the write data for the topmost LTC3300-1 in
the stack and will have shifted through all other LTC3300-1
ICs in the stack. The last 16 bits will be the write data for
the bottom-most LTC3300-1 in the stack.
Table 4. Write Balance Command Data Bit Mapping (Defaults to 0x000F in Reset State)
D1A
(MSB)
D1B D2A D2B D3A D3B D4A D4B D5A D5B D6A D6B CRC[3] CRC[2] CRC[1] CRC[0]
(LSB)
LTC3300-1
30
Rev. C
OPERATION
The first 12 bits of the 16-bit balance command are used
to indicate which balancer (or balancers) is active and in
which direction (charge or discharge). Each of the 6 cell
balancers is controlled by 2 bits of this data per Table 5.
The balancing algorithm for a given cell is:
Charge Cell n: Ramp up to IPEAK in secondary winding,
ramp down to IZERO in primary winding. Repeat.
Discharge Cell n (Synchronous): Ramp up to Ipeak in
primary winding, ramp down to IZERO in secondary
winding. Repeat.
Table 5. Cell Balancer Control Bits
DnA DnB Balancing Action (n = 1 to 6)
0 0 None
0 1 Discharge Cell n (Nonsynchronous)
1 0 Discharge Cell n (Synchronous)
1 1 Charge Cell n
For nonsynchronous discharging of cell n, both the sec-
ondary winding gate drive and (zero) current sense amp
are disabled. The secondary current will conduct either
through the body diode of the secondary switch (if pres-
ent) or through a substitute Schottky diode. The primary
will only turn on again after the secondary winding Volt-
sec clamp times out. In a bidirectional application with a
secondary switch, it may be possible to achieve slightly
higher discharge efficiency by opting for nonsynchronous
discharge mode (if the gate charge savings exceed the
added diode drop losses) but the balancing current will be
less predictable because the secondary winding Volt-sec
clamp must be set longer than the expected time for the
current to hit zero in order to guarantee no current reversal.
In the case where a Schottky diode replaces the secondary
switch, it is possible to build a undirectional discharge-only
balancing application charging an isolated auxiliary cell
as shown in Figure19 in the Typical Applications section.
In the CTRL = 1 application of Figure7 employing a single
transformer which can only balance one cell at a time, any
command requesting simultaneous balancing of more than
one cell will be ignored. All active balancing will be turned
off if an Execute Balance Command is subsequently written.
The last 4 bits of the 16-bit balance command are used
for packet error checking (PEC). The 16 bits of write data
(12-bit message plus 4-bit CRC) are input to a cyclic re-
dundancy check (CRC) block employing the International
Telecommunication Union CRC-4 standard characteristic
polynomial:
x4 + x + 1
In the write data, the 4-bit CRC appended to the message
must be selected such that the remainder of the CRC divi-
sion is zero. Note that the CRC bits in the Write Balance
Command are inverted. This was done so that an “all zeros”
command is invalid. The LTC3300-1 will ignore the write
data if the remainder is not zero and the internal command
holding register will be cleared which can be verified on
readback. The current balance command being executed
(from the last previously successful write) will continue,
but all active balancing will be turned off if an Execute Bal-
ance Command is subsequently written. For information
on how to calculate the CRC including an example, refer
to the Applications Information section.
Readback Balance Command
The bit mapping for Readback Balance Command is identi-
cal to that for Write Balance Command. If the command
bits program Readback Balance Command, successive
16-bit previously written data (latched in 12-bit message
plus newly calculated 4-bit CRC) are shifted out in the
same order bitwise (MSB first) starting with the lowest
LTC3300-1 in the stack and proceeding up the stack. Thus,
the sequence of outcoming data during readback is:
Command data (bottom chip), Command data (2nd chip
from bottom), …, Command data (top chip)
This command allows for microprocessor verification of
written commands before executing. Note that the CRC
bits in the Readback Balance Command are also inverted.
This was done so that an “all zeros” readback is invalid.
LTC3300-1
31
Rev. C
Read Balance Status
If the command bits program Read Balance Status, suc-
cessive 16-bit status data (12 bits of data plus associated
4-bit CRC) are shifted out MSB first per Table 6. Similar
to a Readback Balance Command, the last 4 bits in each
16-bit balance status are used for error detection. The
first 12 bits of the status are input to a cyclic redundancy
check (CRC) block employing the same characteristic
polynomial used for write commands. The LTC3300-1
will calculate and append the appropriate 4-bit CRC to
the outgoing 12-bit message which can then be used for
microprocessor error checking. The sequence of outcom-
ing data during readback is:
Status data (bottom chip), Status data (2nd chip from
bottom), …, Status data (top chip)
Note that the CRC bits in the Read Balance Status are
inverted. This was done so that an “all zeros” readback
is invalid.
The first 6 bits of the read balance status indicate if there
is sufficient gate drive for each of the 6 balancers. These
bits correspond to the right-most column in Table 1, but
can only be logic high for a given balancer following an
execute command involving that same balancer. If a bal-
ancer is not active, its Gate Drive OK bit will be logic low.
The 7th, 8th, and 9th bits in the read balance status indicate
that all 6 cells are not overvoltage, that the transformer
secondary is not overvoltage, and that the LTC3300-1 die
is not overtemperature, respectively. These 3 bits can only
be logic high following an execute command involving at
least one balancer. The 10th, 11th, and 12th bits in the
OPERATION
read balance status are currently not used and will always
be logic zero. As an example, if balancers 1 and 4 are both
active with no voltage or temperature faults, the 12-bit
read balance status should be 100100111000.
Execute Balance Command
If the command bits program Execute Balance Command,
the last successfully written and latched in balance com-
mand will be executed immediately. All subsequent (write)
data will be ignored until CSBI transitions high and then
low again.
Pause/Resume Balancing (via SPI Port)
The LTC3300-1 provides a simple means to interrupt bal-
ancing in progress (stack wide) and then restart without
having to rewrite the previous balance command to all
LTC3300-1 ICs in the stack. To pause balancing, simply
write an 8-bit Execute Balance Command with the parity
bit flipped: 10101110. To resume balancing, simply write
an Execute Balance Command with the correct parity:
10101111. This feature is useful if precision cell voltage
measurements want to be performed during balancing
with the stack “quiet.” Immediate pausing of balancing
in progress will occur for any 8-bit Command Byte with
incorrect parity.
The restart time is typically 2ms which is the same as the
delayed start time after a new or different balance command
(tDLY_START). It is measured from the 8th rising SCKI edge
until the balancer turns on and is illustrated in G27 in the
Typical Performance Characteristics section.
Table 6. Read Balance Status Data Bit Mapping (defaults to 0x000F in Reset State)
Gate
Drive 1
OK
(MSB)
Gate
Drive 2
OK
Gate
Drive 3
OK
Gate
Drive 4
OK
Gate
Drive 5
OK
Gate
Drive 6
OK
Cells
Not OV
Sec
Not OV
Temp
OK
0 0 0 CRC[3] CRC[2] CRC[1] CRC[0]
(LSB)
LTC3300-1
32
Rev. C
APPLICATIONS INFORMATION
External Sense Resistor Selection
The external current sense resistors for both primary
and secondary windings set the peak balancing current
according to the following formulas:
RSENSE|PRIMARY =
50mV
IPEAK _PRI
RSENSE|SECONDARY =50mV
IPEAK _SEC
Balancer Synchronization
Due to the stacked configuration of the individual synchro-
nous flyback power circuits and the interleaved nature of
the gate drivers, it is possible at higher balance currents
for adjacent and/or penadjacent balancers within a group
of six to sync up. The synchronization will typically be to
the highest frequency of any active individual balancer and
can result in a slightly lower balance current in the other
affected balancer(s). This error will typically be very small
provided that the individual cells are not significantly out
of balance voltage-wise and due to the matched IPEAK/
IZERO’s and matched power circuits. Balancer synchro-
nization can be reduced by lowpass filtering the primary
and/or secondary current sense signals with a simple RC
network as shown in Figure10. A good starting point for
the RC time constant is one-tenth of the on-time of the
associated switch (primary or secondary). In the case
of IPEAK sensing, phase lag associated with the lowpass
filter will result in a slightly lower voltage seen by the
LTC3300-1 compared to the true sense resistor voltage.
This error can be compensated for by selecting the R value
to add back this same drop using the typical current value
of 20µA out of the LTC3300-1 current sense pins at the
comparator trip point.
Setting Appropriate Max On-Times
The primary and secondary winding volt-second clamps
are intended to be used as a current runaway protection
feature and not as a substitute means of current control
replacing the sense resistors. In order to not interfere with
normal IPEAK/IZERO operation, the maximum on times must
be set longer than the time required to ramp to IPEAK (or
IZERO) for the minimum cell voltage seen in the application:
tON(MAX)|PRIMARY > LPRI • IPEAK_PRI/VCELL(MIN)
tON(MAX)|SECONDARY > LPRI • IPEAK_SEC • T/(S • VCELL(MIN))
These can be further increased by 20% to account for
manufacturing tolerance in the transformer winding
inductance and by 10% to account for IPEAK variation.
LTC3300-1
n = 2 TO 6
20µA R
CR
SNS
33001 F10
G1P/GnP/G1S/GnS
I1P/InP/I1S/InS
V
–
/Cn – 1/V
–
/V
–
Figure10. Using an RC Network to Filter Current Sense Inputs to
the LTC3300-1
LTC3300-1
33
Rev. C
APPLICATIONS INFORMATION
External FET Selection
In addition to being rated to handle the peak balancing
current, external NMOS transistors for both primary and
secondary windings must be rated with a drain-to-source
breakdown such that for the primary MOSFET:
VDS(BREAKDOWN)|MIN >VCELL +
V
STACK
+V
DIODE
T
=VCELL 1+S
T
⎛
⎝
⎜⎞
⎠
⎟+VDIODE
T
and for the secondary MOSFET:
VDS(BREAKDOWN)|MIN
>
VSTACK
+
T VCELL
+
VDIODE
( )
=VCELL S+T
( )
+T VDIODE
where S is the number of cells in the secondary winding
stack and 1:T is the transformer turns ratio from primary
to secondary. For example, if there are 12 Li-Ion cells in
the secondary stack and using a turns ratio of 1:2, the
primary FETs would have to be rated for greater than 4.2V
(1 + 6) + 0.5 = 29.9V and the secondary FETs would have
to be rated for greater than 4.2V (12 + 2) + 2V = 60.8V.
Good design practice recommends increasing this voltage
rating by at least 20% to account for higher voltages present
due to leakage inductance ringing. See Table 7 for a list of
FETs that are recommended for use with the LTC3300-1.
Table 7
PART NUMBER MANUFACTURER IDS(MAX) VDS(MAX)
SiR882DP Vishay 60A 100V
SiS892DN Vishay 25A 100V
IPD70N10S3-12 Infineon 70A 100V
IPB35N10S3L-26 Infineon 35A 100V
RJK1051DPB Renesas 60A 100V
RJK1054DPB Renesas 92A 100V
Transformer Selection
The LTC3300-1 is optimized to work with simple 2-wind-
ing transformers with a primary winding inductance of
between 1 and 20 microhenries, a 1:2 turns ratio (primary
to secondary), and the secondary winding paralleling up
to 12 cells. If a larger number of cells in the secondary
stack is desired for more efficient balancing, a transformer
with a higher turns ratio can be selected. For example, a
1:10 transformer would be optimized for up to 60 cells in
the secondary stack. In this case the external FETs would
need to be rated for a higher voltage (see above). In all
cases the saturation current of the transformer must be
selected to be higher than the peak currents seen in the
application.
See Table 8 for a list of transformers that are recommended
for use with the LTC3300-1.
Table 8
PART NUMBER MANUFACTURER
TURNS
RATIO*
PRIMARY
INDUCTANCE ISAT
750312504 (SMT) Würth Electronics 1:1 3.5µH 10A
750312677 (THT) Würth Electronics 1:1 3.5µH 10A
MA5421-AL Coilcraft 1:1 3.4µH 10A
CTX02-18892-R Coiltronics 1:1 3.4µH 10A
XF0036-EP13S XFMRS Inc 1:1 3µH 10A
LOO-321 BH Electronics 1:1 3.4µH 10A
DHCP-X79-1001 TOKO 1:1 3.4µH 10A
C128057LF GCI 1:1 3.4µH 10A
T10857-1 Inter Tech 1:1 3.4µH 10A
*All transformers listed in the table are 8-pin components and can be
configured with turns ratios of 1:1, 1:2, 2:1, or 2:2.
Snubber Design
Careful attention must be paid to any transient ringing
seen at the drain voltages of the primary and secondary
winding FETs in application. The peak of the ringing should
not approach and must not exceed the breakdown voltage
rating of the FETs chosen. Minimizing leakage inductance
present in the application and utilizing good board layout
techniques can help mitigate the amount of ringing. In
some applications, it may be necessary to place a series
resistor + capacitor snubber network in parallel with each
winding of the transformer. This network will typically
lower efficiency by a few percent, but will keep the FETs
in a safer operating region. Determining values for R and
C usually requires some trial-and-error optimization in the
application. For the transformers shown in Table 8, good
starting point values for the snubber network are 330Ω
in series with 100pF.
LTC3300-1
34
Rev. C
APPLICATIONS INFORMATION
Boosted Gate Drive Component Selection
(BOOST = VREG)
The external boost capacitor connected from BOOST+ to
BOOST– supplies the gate drive voltage required for turning
on the external NMOS connected to G6P. This capacitor
is charged through the external Schottky diode from C6
to BOOST+ when the NMOS is off (G6P = BOOST– = C5).
When the NMOS is to be turned on, the BOOST– driver
switches the lower plate of the capacitor from C5 to C6,
and the BOOST+ voltage common modes up to one cell
voltage higher than C6. When the NMOS turns off again,
the BOOST– driver switches the lower plate of the capaci-
tor back to C5 so that the boost capacitor is refreshed.
A good rule of thumb is to make the value of the boost
capacitor 100 times that of the input capacitance of the
NMOS at G6P. For most applications, a 0.1µF/10V capacitor
will suffice.The reverse breakdown of the Schottky diode
must only be greater than 6V. To prevent an excessive and
potentially damaging surge current from flowing in the
boosted gate drive components during initial connection of
the battery voltages to the LTC3300-1, it is recommended
to place a 6.8Ω resistor in series with the Schottky diode
as shown in Figure 3. The surge current must be limited
to 1A to avoid potential damage.
Sizing the Cell Bypass Caps for Broken Connection
Protection
If a single connection to the battery stack is lost while bal-
ancing, the differential cell voltages seen by the LTC3300-1
power circuit on each side of the break can increase or
decrease depending on whether charging or discharging
and where the actual break occurred. The worst-case
scenario is when the balancers on each side of the break
are both active and balancing in opposite directions. In
this scenario, the differential cell voltage will increase
rapidly on one side of the break and decrease rapidly
on the other. The cell overvoltage comparators working
in conjunction with appropriately-sized differential cell
bypass capacitors protect the LTC3300-1 and its associated
power components by shutting off all balancing before
any local differential cell voltage reaches its absolute
maximum rating. The comparator threshold (rising) is 5V,
and it takes 3µs to 6μs for the balancing to stop, during
which the bypass capacitor must prevent the differential
cell voltage from increasing past 6V. Therefore, the mini-
mum differential bypass capacitor value for full broken
connection protection is:
CBYPASS(MIN) =ICHARGE +IDISCHARGE
( )
•6µs
6V – 5V
If ICHARGE and IDISCHARGE are set nominally equal, then
approximately 12µF of real capacitance per amp of balance
current is required.
Protection from a broken connection to a cluster of sec-
ondary windings is provided local to each LTC3300-1 in
the stack by the secondary winding OVP function (via
WDT pin) described in the Operation section. However,
because of the interleaving of the transformer windings
up the stack, it is possible for a remote LTC3300-1 to still
act on the cell voltage seen locally by another LTC3300-1
at the point of the break which has shut itself off. For this
reason, each cluster of secondary windings must have
a dedicated connection to the stack separate from the
individual cell connection that it connects to.
Using the LTC3300-1 with Fewer Than 6 Cells
To balance a series stack of N cells, the required number
of LTC3300-1 ICs is N/6 rounded up to the nearest integer.
Additionally, each LTC3300-1 in the stack must interface
to a minimum of 3 cells (must include C4, C5, and C6).
Thus, any stack of 3 or more cells can be balanced us-
ing an appropriate stack of LTC3300-1 ICs. Unused cell
inputs (C1, C1 + C2, or C1 + C2 + C3) in a given LTC3300
-1 sub-stack should be shorted to V– (see Figure11).
However, in all configurations, the write data remains at
16 bits. The LTC3300-1 will not act on the cell balancing
bits for the unused cell(s) but these bits are still included
in the CRC calculation.
Supplementary Voltage Regulator Drive (>40mA)
The 4.8V linear voltage regulator internal to the LTC3300-1
is capable of providing 40mA at the VREG pin. If additional
current capability is required, the VREG pin can be back-
driven by an external low cost 5V buck DC/DC regulator
powered from C6 as shown in Figure 12. The internal
regulator of the LTC3300-1 has very limited sink current
capability and will not fight the higher forced voltage.
LTC3300-1
35
Rev. C
APPLICATIONS INFORMATION
Figure12. Adding External Buck DC/DC for >40mA VREG Drive
4.8V
LINEAR
VOLTAGE
REGULATOR
VREG
COUT
RFB2
V–
LTC3300-1
C6
5V
IOUT > 40mA
L
RFB1
CIN
33001 F12
SW
GND
VIN
BUCK
DC/DC
FB
Figure11. Battery Stack Connections For 5, 4 or 3 Cells
+CELL n + 4
•
•
•
•
•
•
+CELL n + 3
+CELL n + 2
+CELL n + 1
+CELL n
C6
LTC3300-1
(11a) Sub-Stack Using Only 5 Cells (11b) Sub-Stack Using Only 4 Cells (11c) Sub-Stack Using Only 3 Cells
V–
C5
C4
C3
C2
C1
+
•
•
•
•
•
•
+
CELL n + 3
+
CELL n + 2
+
CELL n + 1
CELL n
C6
LTC3300-1
V–
C5
C4
C3
C2
C1
+
•
•
•
•
•
•
+
+
CELL n + 2
CELL n + 1
CELL n
33001 F11
C6
LTC3300-1
V–
C5
C4
C3
C2
C1
LTC3300-1
36
Rev. C
Table 9. LTC3300-1 Failure Mechanism Effect Analysis
SCENARIO EFFECT DESIGN MITIGATION
Top cell (C6) input connection loss to LTC3300-1. Power will come from highest connected cell
input or via data port fault current.
Clamp diodes at each pin to C6 and V– (within IC)
provide alternate power path. Diode conduction at
data ports will impair communication with higher
potential units.
Bottom cell (V–) input connection loss to
LTC3300-1.
Power will come from lowest connected cell
input or via data port fault current.
Clamp diodes at each pin to C6 and V– (within IC)
provide alternate power path. Diode conduction at
data ports will impair communication with higher
potential units.
Random cell (C1-C5) input connection loss to
LTC3300-1.
Power-up sequence at IC inputs/differential
input voltage overstress.
Clamp diodes at each pin to C6 and V– (within IC)
provide alternate power path. Zener diodes across
each cell voltage input pair (within IC) limit stress.
Disconnection of a harness between a sub-stack
of battery cells and the LTC3300-1 (in a system of
stacked groups).
Loss of all supply connections to the IC. Clamp diodes at each pin to C6 and V– (within
IC) provide alternate power path if there are other
devices (which can supply power) connected to
the LTC3300-1. Diode conduction at data ports
will impair communication with higher potential
units.
Secondary winding connection loss to battery
stack.
Secondary winding power FET could be
subjected to a higher voltage as bypass
capacitor charges up.
WDT pin implements a secondary winding OVP
circuit which will detect overvoltage and terminate
balancing.
Shorted primary winding sense resistor. Primary winding peak current cannot be
detected to shut off primary switch.
Maximum ON-time set by RTONP resistor will shut
off primary switch if peak current detect doesn’t
occur.
Shorted secondary winding sense resistor. Secondary winding peak current cannot be
detected to shut off secondary switch.
Maximum ON-time set by RTONS resistor will
shut off secondary switch if peak current detect
doesn’t occur.
Data link disconnection between stacked LTC3300-1
units.
Break of daisy-chain communication (no stress
to ICs). Communication will be lost to devices
above the disconnection. The devices below the
disconnection are still able to communicate and
perform all functions.
If the watchdog timer is enabled, all balancers
above the fault will be turned off after 1.5
seconds. The individual WDT pins will go Hi-Z and
be pulled up by external resistors.
Data error (noise margin induced or otherwise)
occurs during a write command.
Incoming checksum will not agree with the
incoming message when read in by any
individual LTC3300-1 in the stack.
Since the CRC remainder will not be zero, the
LTC3300-1 will not execute the write command,
even if an execute command is given. All
balancers with nonzero remainders will be off.
Data error (noise margin induced or otherwise)
occurs during a read command.
Outgoing checksum (calculated by
the LTC3300-1) will not agree with the
outgoing message when read in by the host
microprocessor.
Since the CRC remainder (calculated by the
host) will not be zero, the data cannot be trusted.
All balancers will remain in the state of the last
previously successful write.
APPLICATIONS INFORMATION
Fault Protection
Care should always be taken when using high energy
sources such as batteries. There are numerous ways
that systems can be misconfigured when considering
the assembly and service procedures that might affect a
battery system during its useful lifespan. Table 9 shows
the various situations that should be considered when
planning protection circuitry. The first four scenarios
are to be anticipated during production and appropriate
protection is included within the LTC3300-1 device itself.
LTC3300-1
37
Rev. C
Figure13. Reverse-Voltage Protection for the Daisy Chain (One Link Connection Shown)
+
+
RSO7J
×3
LTC3300-1
(NEXT HIGHER IN STACK)
SDI SCKI CSBISDO
V–
OPTIONAL
REDUNDANT
CURRENT
PATH
PROTECT
AGAINST
BREAK
HERE
LTC3300-1
(NEXT LOWER IN STACK)
SDOI SCKO CSBO
C6
33001 F13
APPLICATIONS INFORMATION
Battery Interconnection Integrity
The FMEA scenarios involving a break in the stack of battery
cells are potentially the most damaging. In the case where
the battery stack has a discontinuity between groupings
of cells balanced by LTC3300-1 ICs, any load will force a
large reverse potential on the daisy-chain connection. This
situation might occur in a modular battery system during
initial installation or a service procedure. The daisy-chain
ports are protected from the reverse potential in this
scenario by external series high voltage diodes required
in the upper port data connections as shown in Figure13.
During the charging phase of operation, this fault would
lead to forward biasing of daisy-chain ESD clamps that
would also lead to part damage. An alternative connection
to carry current during this scenario will avoid this stress
from being applied (Figure13).
Internal Protection Diodes
Each pin of the LTC3300-1 has protection diodes to help
prevent damage to the internal device structures caused
by external application of voltages beyond the supply rails
as shown in Figure14. The diodes shown are conventional
silicon diodes with a forward breakdown voltage of 0.5V.
The unlabeled Zener diode structures have a reverse-
breakdown characteristic which initially breaks down at
9V then snaps back to a 7V clamping potential. The Zener
diodes labeled ZCLAMP are higher voltage devices with an
initial reverse breakdown of 25V snapping back to 22V.
The forward voltage drop of all Zeners is 0.5V.
The internal protection diodes shown in Figure 14 are
power devices which are intended to protect against
limited-power transient voltage excursions. Given that
these voltages exceed the absolute maximum ratings of
the LTC3300-1, any sustained operation at these voltage
levels will damage the IC.
Initial Battery Connection to LTC3300-1
In addition to the above-mentioned internal protection
diodes, there are additional lower voltage/lower current
diodes across each of the six differential cell inputs (not
shown in Figure14) which protect the LTC3300-1 during
initial installation of the battery voltages in the application.
These diodes have a breakdown voltage of 5.3V with 20kΩ
of series resistance and keep the differential cell voltages
below their absolute maximum rating during power-up
when the cell terminal currents are zero to tens of mi-
croamps. This allows the six batteries to be connected in
any random sequence without fear of an unconnected cell
input pin overvoltaging due to leakage currents acting on
its high impedance input. Differential cell-to-cell bypass
capacitors used in the application must be of the same
nominal value for full random sequence protection.
LTC3300-1
38
Rev. C
Figure14. Internal Protection Diodes
APPLICATIONS INFORMATION
48
VREG
20
WDT
19
SDO
18
SDI
17
SCKI
1645 CSBICSBO
LTC3300-1
47
TOS
44 SCKO
43 SDOI
40 BOOST+
41 BOOST–
38 G6P
37 I6P
C5
39 C6
46
VMODE
42
BOOST
15
CTRL
14
RTONP
13
RTONS
1
G6S
2
I6S
3
G5S
4
I5S
5
G4S
6
I4S
7
G3S
8
I3S
9
G2S
ZCLAMP
ZCLAMP
ZCLAMP
ZCLAMP
10
I2S
11
G1S
12
I1S
33001 F14
36
35 G5P
34 I5P
C4
33
32 G4P
31 I4P
C3
30
29 G3P
28 I3P
C2
27
26 G2P
25 I2P
C1
24
23 G1P
22 I1P
4Ω
EXPOSED PAD
21
V–
49
LTC3300-1
39
Rev. C
APPLICATIONS INFORMATION
Figure15. Stack Terminal Currents in Shutdown
+
+
16µA
V–
C6 LTC3300-1
7.5µA
16µA
V–
C6 LTC3300-1
7.5µA
16µA
V–
33001 F15
C6 LTC3300-1
7.5µA
16µA
3
V–
CELL N – 6
C6CELL N LTC3300-1
TOP OF STACK
BOTTOM OF STACK
23.5µA
TOS = 1
+
+CELL N – 12
CELL N – 7 7.5µA
7.5µA
23.5µA
0µA
0µA
+
+
+
CELL 7
CELL 6
CELL 12
+CELL 1
3
3
3
ALL
ZERO
C5
C4
C3
C2
C1
ALL
ZERO
C5
C4
C3
C2
C1
ALL
ZERO
C5
C4
C3
C2
C1
ALL
ZERO
C5
C4
C3
C2
C1
Analysis of Stack Terminal Currents in Shutdown
As given in the Electrical Characteristics table, the qui-
escent current of the LTC3300-1 when not balancing is
16μA at the C6 pin and zero at the C1 through C5 pins.
All of this 16μA shows up at the V– pin of the LTC3300-1.
In addition, the SPI port when not communicating (i.e.,
CSBI = 1) contributes an additional 2.5μA per high side
line (CSBO/SCKO/SDOI), or 7.5μA to the V– pin current
of each LTC3300-1 in the stack which is not top of stack
(TOS = 0). This additional current does not add to the local
C6 pin current but rather to the C6 pin current of the next
higher LTC3300-1 in the stack as it is passed in through
the CSBI/SCKI/SDI pins. To the extent that the 16μA and
7.5μA currents match perfectly chip-to-chip in a long series
stack, the resultant stack terminal currents in shutdown
are as follows: 23.5μA out of the top of stack node, 7.5μA
out of the node 6 cells below top of stack, 7.5μA into the
node 6 cells above bottom of stack, and 23.5μA into the
bottom of stack node. All other intermediate node cur-
rents are zero. This is shown graphically in Figure15. For
the specific case of a 12-cell stack, this reduces to only
23.5µA out of the top of stack node and 23.5µA into the
bottom of stack node.
LTC3300-1
40
Rev. C
How to Calculate the CRC
One simple method of computing an n-bit CRC is to perform
arithmetic modulo-2 division of the n+1 bit characteristic
polynomial into the m bit message appended with n ze-
ros (m+n bits). Arithmetic modulo-2 division resembles
normal long division absent borrows and carries. At each
intermediate step of the long division, if the leading bit
of the dividend is a 1, a 1 is entered in the quotient and
the dividend is exclusive-ORed bitwise with the divisor. If
the leading bit of the dividend is a 0, a 0 is entered in the
quotient and the dividend is exclusive-ORed bitwise with
n zeros. This process is repeated m times. At the end of
the long division, the quotient is disregarded and the n-
bit remainder is the CRC. This will be more clear in the
example to follow.
For the CRC implementation in the LTC3300-1, n = 4 and
m = 12. The characteristic polynomial employed is x4 + x
+ 1, which is shorthand for 1x4 + 0x3 + 0x2 + 1x1 + 1x0,
resulting in 10011 for the divisor. The message is the first
12 bits of the balance command. Suppose for example the
APPLICATIONS INFORMATION
desired balance command calls for simultaneous charging
of Cell 1 and synchronous discharging of Cell4. The 12-bit
message (MSB first) will be 110000010000. Appending
4 zeros results in 1100000100000000 for the dividend.
The long division is shown in Figure 16a with a resultant
CRC of 1101. Note that the CRC bits in the write balance
command are inverted. Thus the correct 16-bit balance
command is 1100000100000010. Figure16b shows the
same long division procedure being used to check the
CRC of data (command or status) read back from the
LTC3300-1. In this scenario, the remainder after the long
division must be zero (0000) for the data to be valid. Note
that the readback CRC bits must be inverted in the dividend
before performing the division.
An alternate method to calculate the CRC is shown in
Figure17 in which the balance command bits are input to
a combinational logic circuit comprised solely of 2-input
exclusive-OR gates. This “brute force” implementation is
easily replicated in a few lines of C code.
Figure16. (a) Long Division Example to Calculate CRC for
Writes. (b) Long Division Example to Check CRC for Reads
1 1 0 1 0 1 1 0 1 0 1 1
1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0
1 0 0 1 1
1 0 1 1 0
1 0 0 1 1
0 1 0 1 0
0 0 0 0 0
1 0 1 0 1
1 0 0 1 1
0 1 1 0 0
0 0 0 0 0
1 1 0 0 0
1 0 0 1 1
1 0 1 1 0
1 0 0 1 1
0 1 0 1 0
0 0 0 0 0
1 0 1 0 0
1 0 0 1 1
0 1 1 1 0
0 0 0 0 0
1 1 1 0 0
1 0 0 1 1
1 1 1 1 0
1 0 0 1 1
REMAINDER = 1 1 0 1 = 4-BIT CRC
1 1 0 1 0 1 1 0 1 0 1 1
1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 1
1 0 0 1 1
1 0 1 1 0
1 0 0 1 1
0 1 0 1 0
0 0 0 0 0
1 0 1 0 1
1 0 0 1 1
0 1 1 0 0
0 0 0 0 0
1 1 0 0 0
1 0 0 1 1
1 0 1 1 0
1 0 0 1 1
0 1 0 1 0
0 0 0 0 0
1 0 1 0 1
1 0 0 1 1
0 1 1 0 1
0 0 0 0 0
1 1 0 1 0
1 0 0 1 1
1 0 0 1 1
1 0 0 1 1
REMAINDER = 0
33001 F16
0 0 1 0 = 4-BIT CRC INVERTED
READBACK = 1100000100000010
DIVIDEND = 1100000100001101
(b)(a)
LTC3300-1
41
Rev. C
Serial Communication Using the LTC6803 and LTC6804
The LTC3300-1 is compatible with and convenient to
use with all LTC monitor chips, such as the LTC6803 and
LTC6804. Figure20 in the Typical Applications section
shows the serial communications connections for a joint
LTC3300-1/LTC6803-1 BMS using a common micropro-
cessor SPI port. The SCKI, SDI, and SDO lines of the
lowermost LTC3300-1 and LTC6803-1 are tied together. The
CSBI lines, however, must be separated to prevent talking
to both ICs at the same time. This is easily accomplished
by using one of the GPIO outputs from the LTC6803-1
to gate and invert the CSBI line to the LTC3300-1. In this
setup, communicating to the LTC6803-1 is no different
than without the LTC3300-1, as the GPIO1 output bit is
normally high. To talk to the LTC3300-1, written commands
must be “bookended” with a GPIO1 negation write to the
LTC6803-1 prior to talking to the LTC3300-1 and with
a GPIO1 assertion write after talking to the LTC3300-1.
Communication “up the stack” passes between LTC3300-1
ICs and between LTC6803-1 ICs as shown.
APPLICATIONS INFORMATION
Figure17. Combinational Logic Circuit Implementation of The CRC Calculator
CRC [3]
CRC [3]
CRC [2]
CRC [1]
CRC [0]
33001 F17
D6B
“Ø”
“Ø”
“Ø”
“Ø”
D5B
D3B
D1B
D2A
D5A
D3A
D1A
D4B
D2B
D4A
D6A
CRC [2]
CRC [1]
CRC [0]
The Typical Application shown on the back page of this
data sheet shows the serial communication connections for
a joint LTC3300-1/LTC6804-1 BMS. Each stacked 12-cell
module contains two LTC3300-1 ICs and a single LTC6804-1
monitor IC. The upper LTC3300-1 in each module is con-
figured with VMODE = 0, TOS = 1, and receives its serial
communication from the lower LTC3300-1 in the same
module, which itself is configured with VMODE = 1, TOS
= 0. The LTC6804-1 in the same module is configured to
provide an effective SPI port output at its GPIO3, GPIO4,
and GPIO5 pins which connect directly to the low side
communication pins (CSBI, SDI=SDO, SCKI) of the lower
LTC3300-1. Communication to the lowermost LTC6804-1
and between monitor chips is done via the LTC6820 and
the isoSPI™ interface. In this application, unused battery
cells can be shorted from the bottom of any module (i.e.,
outside the module, not on the module board) as shown
without any decrease in monitor accuracy.
LTC3300-1
42
Rev. C
Figure18. Typical Pin Voltages for Six 4.2V Cells
LTC3300-1
(EXPOSED PAD = 0V)
0V TO 4.8V
0V
0V TO 4.8V
0V
0V TO 4.8V
0V
0V TO 4.8V
0V
0V TO 4.8V
0V
0V TO 4.8V
0V
21V
16.8V TO 25.2V
16.8V
16.8V
12.6V TO 21V
12.6V
12.6V
8.4V TO 16.8V
8.4V
8.4V
4.2V TO 12.6V
4.2V
G6S—PIN 1
I6S
G5S
I5S
G4S
I4S
G3S
I3S
G2S
I2S
G1S
I1S
C5
G5P
I5P
C4
G4P
I4P
C3
G3P
I3P
C2
G2P
I2P
VREG
TOS
VMODE
CSBO
SCKO
SDOI
BOOST
BOOST–
BOOST+
C6
G6P
I6P
1.2V
1.2V
0V/4.8V
0V TO 4.8V
0V TO 4.8V
0V TO 4.8V
0V TO 4.8V
0V TO 4.8V
0V
0V
0V TO 8.4V
4.2V
RTONS
RTONP
CTRL
CSBI
SCKI
SDI
SDO
WDT
V–
I1P
G1P
C1
4.8V
0V/4.8V
0V/4.8V
24.5V
24.5V
24.5V
0V/4.8V
21V TO 25.2V
25.2V TO 29.4V
25.2V
21V TO 29.4V
21V
33001 F18
APPLICATIONS INFORMATION
PCB Layout Considerations
The LTC3300-1 is capable of operation with as much as
40V between BOOST+ and V–. Care should be taken on
the PCB layout to maintain physical separation of traces
at different potentials. The pinout of the LTC3300-1 was
chosen to facilitate this physical separation. There is no
more than 8.4V between any two adjacent pins with the
exception of two instances (VMODE to CSBO, BOOST to
SDOI/BOOST–). In both instances, one of the pins (VMODE,
BOOST) is pin-strapped in the application to V– or VREG
and does not need to route far from the LTC3300-1. The
package body is used to separate the highest voltage
(e.g., 25.2V) from the lowest voltage (0V). As an example,
Figure18 shows the DC voltage on each pin with respect
to V– when six 4.2V battery cells are connected to the
LTC3300-1.
2. The differential cell inputs (C6 to C5, C5 to C4, …, C1 to
exposed pad) should be bypassed with a 1µF or larger
capacitor as close to the LTC3300-1 as possible. This
is in addition to bulk capacitance present in the power
stages.
3. Pin 21 (V–) is the ground sense for current sense resis-
tors connected to I1S-I6S and I1P (seven resistors).
Pin 21 should be Kelvined as well as possible with low
impedance traces to the ground side of these resistors
before connecting to the LTC3300-1 exposed pad.
4. Cell inputs C1 to C5 are the ground sense for current
sense resistors connected to I2P-I6P (five resistors).
These pins should be Kelvined as well as possible
with low impedance traces to the ground side of these
resistors.
5. The ground side of the maximum on-time setting resis-
tors connected to the RTONS and RTONP pins should
be Kelvined to Pin 21 (V–) before connecting to the
LTC3300-1 exposed pad.
6. Trace lengths from the LTC3300-1 gate drive outputs
(G1S-G6S and G1P-G6P) and current sense inputs
(I1S-I6S and I1P-I6P) should be as short as possible.
7. The boosted gate drive components (diode and ca-
pacitor), if used, should form a tight loop close to the
LTC3300-1 C6, BOOST+, and BOOST– pins.
8. For the external power components (transformer, FETs
and current sense resistors), it is important to keep the
area encircled by the two high speed current switching
loops (primary and secondary) as tight as possible.
This is greatly aided by having two additional bypass
capacitors local to the power circuit: one differential
cell to cell and one from the transformer secondary to
local V–.
A representative layout incorporating all of these recom-
mendations is implemented on the DC2064A demo board
for the LTC3300-1 (with further explanation in its accom-
panying demo board manual). PCB layout files (.GRB) are
also available from the factory.
Additional “good practice” layout considerations are as
follows:
1. The VREG pin should be bypassed to the exposed pad
and to V–, each with 1µF or larger capacitors as close
to the LTC3300-1 as possible.
LTC3300-1
43
Rev. C
TYPICAL APPLICATIONS
1:1
1:1
1:1
1:1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
25mΩ
10µH10µH
C6
0.1µF
10µF
CELL 6
G6P
CSBO
SCKO
SDOI
CSBI
SCKI
SDI
SDO
TOS
VMODE
WDT
I6P
SERIAL
COMMUNICATION
RELATED
PINS
LTC3300-1
VREG
BOOST
RTONS ISOLATION
BOUNDARY
RTONP
BOOST+
6.8Ω
BOOST–
CTRL
V–
41.2k
33001 F19
28k10µF
•
•
•
•
•
•
+
•
25mΩ
10µH10µH
C5
10µF
CELL 5
G5P
I5P
C4
+
•
25mΩ
10µH10µH
C2
C3
10µF
CELL 2
G2P
I2P
+
•
25mΩ
NC
10µH10µH
C1
10µF
CELL 1
G1P
I1P
G1S-G6S
I1S-I6S
+ISOLATED
12V LEAD ACID
AUXILIARY
CELL
+
•
•
•
•
•
•
•
•
•
Figure19. LTC3300-1 Unidirectional Discharge-Only Balancing Application to Charge an Isolated Auxiliary Cell
LTC3300-1
44
Rev. C
TYPICAL APPLICATIONS
Figure20. LTC3300-1/LTC6803-1 Battery and Serial Communication Connections for a 24-Cell Stack
+
C5
C4
C3
C2
C1
VREG
TOS
VMODE
SDOI
SCKO
CSBO
NC
NC
NC
NC
NC
NC
NC
CSBI
SCKI
SDI
SDO
C6 SDOI
SCKO
CSBO
GPIO2
GPIO1
CSPI
SCKI
SDI
SDO
C11
C10
C9
C8
C7
C5
C4
C3
C2
C1
C6
C12
TOP OF BATTERY STACK
LTC3300-1
LTC6803-1
V–CVREG4
D7D8D9
D4D5D6 D10D11D12
D1D2D3
CELL 24
+CELL 23
+CELL 22
+CELL 21
+CELL 20
+CELL 19
+CELL 18
+CELL 17
+CELL 16
+CELL 15
+CELL 14
+CELL 13
C5
C4
C3
C2
C1
VREG
TOS
VMODE
VREG
TOS
VMODE
SDOI
SCKO
CSBO
NC
CSBI
SCKI
SDI
SDO
C6
LTC3300-1
V–V–
CVREG3 CVREG6
+
NC
NC
NC
NC
33001 F20
SDOI
SCKO
CSBO
GPIO2
GPIO1
CSBI
SCKI
SDI
SDO
C11
C10
C9
C8
C7
C5
C4
C3
C2
C1
C6
C12
LTC6803-1
CELL 12
+CELL 11
+CELL 10
+CELL 9
+CELL 8
+CELL 7
+CELL 6
+CELL 5
+CELL 4
+CELL 3
VREG1 VREG5
+CELL 2
+CELL 1
VREG
TOS
VMODE V–
CVREG5
C5
C4
C3
C2
C1
VREG
TOS
VMODE
SDOI
SCKO
CSBO
NC
CSBI
SCKI
SDI
SDO
C6
LTC3300-1
V–CVREG2
C5
C4
C3
C2
C1
VREG
TOS
VMODE
SDOI
SCKO
CSBO
CSBI
SCKI
SDI
SDO
C6
LTC3300-1
VREG1 OR VREG5
V–CVREG1
V1+V2+
V1–V2–
CS
CLK
MOSI
MPU
3V
DIGITAL
ISOLATOR
MOSO
LTC3300-1
45
Rev. C
UK Package
48-Lead Plastic QFN (7mm × 7mm)
(Reference LTC DWG # 05-08-1704 Rev C)
7.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 TOP MARK
(SEE NOTE 6)
PIN 1
CHAMFER
C = 0.35
0.40 ±0.10
4847
1
2
BOTTOM VIEW—EXPOSED PAD
5.50 REF
(4-SIDES)
0.75 ±0.05 R = 0.115
TYP
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UK48) QFN 0406 REV C
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
5.50 REF
(4 SIDES) 6.10 ±0.05 7.50 ±0.05
0.25 ±0.05
0.50 BSC
PACKAGE OUTLINE
5.15 ±0.10
5.15 ±0.10
5.15 ±0.05
5.15 ±0.05
R = 0.10
TYP
PACKAGE DESCRIPTION
LTC3300-1
46
Rev. C
LXE48 LQFP 0410 REV B
0° – 7°
11° – 13°
0.45 – 0.75
1.00 REF
11° – 13°
1
48
1.60
MAX
1.35 – 1.45
0.05 – 0.150.09 – 0.20 0.50
BSC 0.17 – 0.27
GAUGE PLANE
0.25
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT
3. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
4. DRAWING IS NOT TO SCALE
R0.08 – 0.20
7.15 – 7.25
5.50 REF
136
25
12
5.50 REF
7.15 – 7.25
48
13 24
37
C0.30
PACKAGE OUTLINE
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM OF PACKAGE—EXPOSED PAD (SHADED AREA)
SIDE VIEW
SECTION A – A
0.50 BSC
0.20 – 0.30
1.30 MIN
9.00 BSC
A A
7.00 BSC
1
12
7.00 BSC 3.60 ± 0.10
3.60 ±0.10
9.00 BSC
48 37
1324
37
13 24
36 36
25
25
SEE NOTE: 3
C0.30 – 0.50
3.60 ± 0.05
3.60 ± 0.05
C0.30
12
LXE Package
48-Lead Plastic Exposed Pad LQFP (7mm × 7mm)
(Reference LTC DWG # 05-08-1832 Rev B)
PACKAGE DESCRIPTION
LTC3300-1
47
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 6/13 Added Tray ordering option for LXE package
Modified transformer part number in Table 8
3
31
B 12/13 Add new bullet Integrates Seamlessly with the LTC680x Family of Multicell Battery Stack Monitors
Change part number XF0036-EP135 to XF0036-EP13S
1
31
C 06/19 Add AEC-Q100 Qualification and Orderable Part Numbers 1, 3
LTC3300-1
48
Rev. C
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC6801 Independent Multicell Battery Stack Monitor Monitors Up to 12 Series-Connected Battery Cells for Undervoltage or
Overvoltage, Companion to LTC6802, LTC6803 and LTC6804
LTC6802-1/LTC6802-2 Multicell Battery Stack Monitors Measures Up to 12 Series-Connected Battery Cells, 1st Generation:
Superseded by the LTC6803 and LTC6804 for New Designs
LTC6803-1/LTC6803-3
LTC6803-2/LTC6803-4
Multicell Battery Stack Monitors Measures Up to 12 Series-Connected Battery Cells, 2nd Generation:
Functionally Enhanced and Pin Compatible to the LTC6802
LTC6804-1/LTC6804-2 Multicell Battery Monitors Measures Up to 12 Series-Connected Battery Cells, 3rd Generation:
Higher Precision Than LTC6803 and Built-In isoSPI Interface
LTC6820 isoSPI Isolated Communications Interface Provides an Isolated Interface for SPI Communication Up to 100m Using a
Twisted Pair, Companion to the LTC6804
TYPICAL APPLICATIONS
ISO OUT
9 CELLS
12 CELLS
12-CELL
MODULE 2
ISO IN
GPIO5
GPIO4
GPIO3
SCKI
SDI
SDO
CSBI
LTC6804-1
DATA
LTC3300-1
LTC3300-1
3
ISO OUT
12-CELL
MODULE 1
ISO
33001 TA02
SPI 4
ISO IN
GPIO5
GPIO4
GPIO3
SCKI
SDI
SDO
CSBI
LTC6804-1 LTC6820
isoSPI
LTC3300-1
LTC3300-1
3
LTC3300-1/LTC6804-1 Serial Communication Connections
ANALOG DEVICES, INC. 2013–2019
06/19
www.analog.com
