ISL61851IIBZ-T - Intersil Corporation

Dual USB Port Power Supply Controller

ISL6185

The ISL6185 USB power controller family provides fully

independent overcurrent (OC) fault protection for two or more

USB ports.

This product family consists of sixteen individual functional

product variants and three package options. It is operation

rated for a nominal +2.5V to +5V range and is specified over the

full commercial and industrial temperature ranges.

Each ISL6185 type incorporates in a single package two 71mΩ

P-channel MOSFET power switches for power control. Each

features internal current monitoring, accurate current limiting,

and current limited delay to turn-off, for system supply

protection along with control and communication I/O.

The ISL6185 family offers product variants with specified

continuous output current levels of 0.6A, 1.1A, 1.5A or 1.8A; enable

active high or low inputs; and latch off or automatic retry after

overcurrent turn-off, making these devices well suited for many

low-power applications.

This family of ICs is offered in an industry-standard SOIC pinout

and also in the 70% smaller 3x3 DFN packages providing similar

or enhanced performance in the smallest possible package.

Features

• 2.5V to 5V Operating Range

•71mΩ Integrated Power P-channel MOSFET Switches

• Continuous Current Options for 0.6A, 1.1A, 1.5A and 1.8A

• Thermally Insensitive 12ms of Current Limiting Prior to

Turn-Off

• Output Discharges with Reverse Current Blocking When

Disabled

• Latch-off or Auto Restart Options

• 1µA Off-State Supply Current

• Enable Polarity Options

• Industry-standard Pin for Pin SOIC, and Smaller DFN Packages

Available

• UL Recognized, File Number: E333469

Applications

• USB 1, 2, 3 Port Power Management

• Low Power (18W) Electronic Circuit Limiting and Breaker

FIGURE 1. TYPICAL APPLICATION FIGURE 2. NORMALIZED rDS(ON) TEMPERATURE

CHARACTERISTIC CURVE

D+

D-

D+

D-

+5V VIN

ENABLE_2

FAULT_1

ENABLE_1

FAULT_2

GND

OUT_1

OUT_2

ISL6185

VBUS

USB

PORT 1

USB

PORT_2

USB PORT POWER

0.7

0.8

0.9

1.0

1.1

1.2

1.3

-40 -25 0 25 45 75 85 115

TEMPERATURE (°C)

NORMALIZED rDS(ON)

March 8, 2012

FN6937.3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

ISL6185

2FN6937.3

March 8, 2012

Simplified Block Diagram

GND

VIN

EN_1

EN_2 FAULT_2

OUT_2

OUT_1

FAULT_1

POR

CHANNEL 1 LIKE CHANNEL 2

-V

comp

CURRENT AND TEMP.

MONITORING, GATE,

DELAY & OUTPUT CONTROL

LOGIC

Ordering Information

PART

NUMBER

(Notes 1, 2, 3) PART MARKING

EN/EN

INPUT

VIN = 5V

MAXIMUM

CONTINUOUS IOUT

(A)

LATCH/AUTO

RETRY

TEMP.

RANGE (°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

ISL61851ACBZ 61851A CBZ EN 0.6 LATCH 0 to +70 8 Lead SOIC M8.15

ISL61851BCBZ 61851B CBZ EN 0.6 RETRY 0 to +70 8 Lead SOIC M8.15

ISL61851CCBZ 61851C CBZ EN 1.1 LATCH 0 to +70 8 Lead SOIC M8.15

ISL61851DCBZ 61851D CBZ EN 1.1 RETRY 0 to +70 8 Lead SOIC M8.15

ISL61851ECBZ 61851E CBZ EN 0.6 LATCH 0 to +70 8 Lead SOIC M8.15

ISL61851FCBZ 61851F CBZ EN 0.6 RETRY 0 to +70 8 Lead SOIC M8.15

ISL61851GCBZ 61851G CBZ EN 1.1 LATCH 0 to +70 8 Lead SOIC M8.15

ISL61851HCBZ 61851H CBZ EN 1.1 RETRY 0 to +70 8 Lead SOIC M8.15

ISL61851ICBZ 61851I CBZ EN 1.5 LATCH 0 to +70 8 Lead SOIC M8.15

ISL61851JCBZ 61851J CBZ EN 1.5 RETRY 0 to +70 8 Lead SOIC M8.15

ISL61851KCBZ 61851K CBZ EN 1.5 LATCH 0 to +70 8 Lead SOIC M8.15

ISL61851LCBZ 61851L CBZ EN 1.5 RETRY 0 to +70 8 Lead SOIC M8.15

ISL61852ACRZ 52AC EN 0.6 LATCH 0 to +70 8 Lead DFN L8.3x3J

ISL61852BCRZ 52BC EN 0.6 RETRY 0 to +70 8 Lead DFN L8.3x3J

ISL61852CCRZ 52CC EN 1.1 LATCH 0 to +70 8 Lead DFN L8.3x3J

ISL61852DCRZ 52DC EN 1.1 RETRY 0 to +70 8 Lead DFN L8.3x3J

ISL61852ECRZ 52EC EN 0.6 LATCH 0 to +70 8 Lead DFN L8.3x3J

ISL6185

3FN6937.3

March 8, 2012

ISL61852FCRZ 52FC EN 0.6 RETRY 0 to +70 8 Lead DFN L8.3x3J

ISL61852GCRZ 52GC EN 1.1 LATCH 0 to +70 8 Lead DFN L8.3x3J

ISL61852HCRZ 52HC EN 1.1 RETRY 0 to +70 8 Lead DFN L8.3x3J

ISL61852ICRZ 52IC EN 1.5 LATCH 0 to +70 8 Lead DFN L8.3x3J

ISL61852JCRZ 52JC EN 1.5 RETRY 0 to +70 8 Lead DFN L8.3x3J

ISL61852KCRZ 52KC EN 1.5 LATCH 0 to +70 8 Lead DFN L8.3x3J

ISL61852LCRZ 52LC EN 1.5 RETRY 0 to +70 8 Lead DFN L8.3x3J

ISL61853ACRZ 53AC EN 0.6 LATCH 0 to +70 10 Lead DFN L10.3x3

ISL61853BCRZ 53BC EN 0.6 RETRY 0 to +70 10 Lead DFN L10.3x3

ISL61853CCRZ 53CC EN 1.1 LATCH 0 to +70 10 Lead DFN L10.3x3

ISL61853DCRZ 53DC EN 1.1 RETRY 0 to +70 10 Lead DFN L10.3x3

ISL61853ECRZ 53EC EN 0.6 LATCH 0 to +70 10 Lead DFN L10.3x3

ISL61853FCRZ 53FC EN 0.6 RETRY 0 to +70 10 Lead DFN L10.3x3

ISL61853GCRZ 53GC EN 1.1 LATCH 0 to +70 10 Lead DFN L10.3x3

ISL61853HCRZ 53HC EN 1.1 RETRY 0 to +70 10 Lead DFN L10.3x3

ISL61853ICRZ 53IC EN 1.5 LATCH 0 to +70 10 Lead DFN L10.3x3

ISL61853JCRZ 53JC EN 1.5 RETRY 0 to +70 10 Lead DFN L10.3x3

ISL61853KCRZ 53KC EN 1.5 LATCH 0 to +70 10 Lead DFN L10.3x3

ISL61853LCRZ 53LC EN 1.5 RETRY 0 to +70 10 Lead DFN L10.3x3

ISL61853MCRZ 53MC EN 1.8 LATCH 0 to +70 10 Lead DFN L10.3x3

ISL61853NCRZ 53NC EN 1.8 RETRY 0 to +70 10 Lead DFN L10.3x3

ISL61853OCRZ 53OC EN 1.8 LATCH 0 to +70 10 Lead DFN L10.3x3

ISL61853PCRZ 53PC EN 1.8 RETRY 0 to +70 10 Lead DFN L10.3x3

ISL61851AIBZ 61851A IBZ EN 0.6 LATCH -40 to +85 8 Lead SOIC M8.15

ISL61851BIBZ 61851B IBZ EN 0.6 RETRY -40 to +85 8 Lead SOIC M8.15

ISL61851CIBZ 61851C IBZ EN 1.1 LATCH -40 to +85 8 Lead SOIC M8.15

ISL61851DIBZ 61851D IBZ EN 1.1 RETRY -40 to +85 8 Lead SOIC M8.15

ISL61851EIBZ 61851E IBZ EN 0.6 LATCH -40 to +85 8 Lead SOIC M8.15

ISL61851FIBZ 61851F IBZ EN 0.6 RETRY -40 to +85 8 Lead SOIC M8.15

ISL61851GIBZ 61851G IBZ EN 1.1 LATCH -40 to +85 8 Lead SOIC M8.15

ISL61851HIBZ 61851H IBZ EN 1.1 RETRY -40 to +85 8 Lead SOIC M8.15

ISL61851IIBZ 61851I IBZ EN 1.5 LATCH -40 to +85 8 Lead SOIC M8.15

ISL61851JIBZ 61851J IBZ EN 1.5 RETRY -40 to +85 8 Lead SOIC M8.15

ISL61851KIBZ 61851K IBZ EN 1.5 LATCH -40 to +85 8 Lead SOIC M8.15

ISL61851LIBZ 61851L IBZ EN 1.5 RETRY -40 to +85 8 Lead SOIC M8.15

ISL61852AIRZ 52AI EN 0.6 LATCH -40 to +85 8 Lead DFN L8.3x3J

ISL61852BIRZ 52BI EN 0.6 RETRY -40 to +85 8 Lead DFN L8.3x3J

ISL61852CIRZ 52CI EN 1.1 LATCH -40 to +85 8 Lead DFN L8.3x3J

ISL61852DIRZ 52DI EN 1.1 RETRY -40 to +85 8 Lead DFN L8.3x3J

ISL61852EIRZ 52EI EN 0.6 LATCH -40 to +85 8 Lead DFN L8.3x3J

Ordering Information (Continued)

PART

NUMBER

(Notes 1, 2, 3) PART MARKING

EN/EN

INPUT

VIN = 5V

MAXIMUM

CONTINUOUS IOUT

(A)

LATCH/AUTO

RETRY

TEMP.

RANGE (°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

ISL6185

4FN6937.3

March 8, 2012

ISL61852FIRZ 52FI EN 0.6 RETRY -40 to +85 8 Lead DFN L8.3x3J

ISL61852GIRZ 52GI EN 1.1 LATCH -40 to +85 8 Lead DFN L8.3x3J

ISL61852HIRZ 52HI EN 1.1 RETRY -40 to +85 8 Lead DFN L8.3x3J

ISL61852IIRZ 52II EN 1.5 LATCH -40 to +85 8 Lead DFN L8.3x3J

ISL61852JIRZ 52JI EN 1.5 RETRY -40 to +85 8 Lead DFN L8.3x3J

ISL61852KIRZ 52KI EN 1.5 LATCH -40 to +85 8 Lead DFN L8.3x3J

ISL61852LIRZ 52LI EN 1.5 RETRY -40 to +85 8 Lead DFN L8.3x3J

ISL61853AIRZ 53AI EN 0.6 LATCH -40 to +85 10 Lead DFN L10.3x3

ISL61853BIRZ 53BI EN 0.6 RETRY -40 to +85 10 Lead DFN L10.3x3

ISL61853CIRZ 53CI EN 1.1 LATCH -40 to +85 10 Lead DFN L10.3x3

ISL61853DIRZ 53DI EN 1.1 RETRY -40 to +85 10 Lead DFN L10.3x3

ISL61853EIRZ 53EI EN 0.6 LATCH -40 to +85 10 Lead DFN L10.3x3

ISL61853FIRZ 53FI EN 0.6 RETRY -40 to +85 10 Lead DFN L10.3x3

ISL61853GIRZ 53GI EN 1.1 LATCH -40 to +85 10 Lead DFN L10.3x3

ISL61853HIRZ 53HI EN 1.1 RETRY -40 to +85 10 Lead DFN L10.3x3

ISL61853IIRZ 53II EN 1.5 LATCH -40 to +85 10 Lead DFN L10.3x3

ISL61853JIRZ 53JI EN 1.5 RETRY -40 to +85 10 Lead DFN L10.3x3

ISL61853KIRZ 53KI EN 1.5 LATCH -40 to +85 10 Lead DFN L10.3x3

ISL61853LIRZ 53LI EN 1.5 RETRY -40 to +85 10 Lead DFN L10.3x3

ISL61853MIRZ 53MI EN 1.8 LATCH -40 to +85 10 Lead DFN L10.3x3

ISL61853NIRZ 53NI EN 1.8 RETRY -40 to +85 10 Lead DFN L10.3x3

ISL61853OIRZ 53OI EN 1.8 LATCH -40 to +85 10 Lead DFN L10.3x3

ISL61853PIRZ 53PI EN 1.8 RETRY -40 to +85 10 Lead DFN L10.3x3

ISL61851EVAL1Z 8 Lead SOIC Evaluation Platform with ISL61851A installed

ISL61852EVAL1Z 8 Lead DFN Evaluation Platform with ISL61852H installed

ISL61853EVAL1Z 10 Lead DFN Evaluation Platform with ISL61853I installed

NOTES:

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-

free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information pages for ISL6185XXC (commercial version) and ISL6185XXI (industrial version).

For more information on MSL please see techbrief TB363.

Ordering Information (Continued)

PART

NUMBER

(Notes 1, 2, 3) PART MARKING

EN/EN

INPUT

VIN = 5V

MAXIMUM

CONTINUOUS IOUT

(A)

LATCH/AUTO

RETRY

TEMP.

RANGE (°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

ISL6185

5FN6937.3

March 8, 2012

Pin Configurations

ISL6185

(8 LD SOIC/DFN)

TOP VIEW

ISL6185

(10 LD DFN)

TOP VIEW

VIN OUT1

OUT2

FLT1

FLT2

GND

(GND)

EPAD

DFN Only

EN1/EN1

EN2/EN2

VIN OUT1

OUT2

FLT1

FLT2

GND

(GND)

EPAD

VIN NC

EN1/EN1

EN2/EN2

Pin Descriptions

PIN NUMBER

SYMBOL DESCRIPTION

8 Ld

SOIC/DFN 10 Ld DFN

1 1 GND IC ground reference.

2 2, 3 VIN Chip bias, Controlled Voltage Input, Undervoltage Lock Out (UVLO). VIN provides chip bias voltage. At

VIN < 1.7V chip functionality is disabled, FLT is active and floating, and OUT is held low. Range 0V to

5.5V.

EN1, EN1/

EN2, EN2

Enable/Disable inputs, Active high (EN) and active low (EN) options enable the power switch. These

inputs have internal 1MΩ pull-off resistors. Range 0V to VIN.

FLT2

FLT1

Overcurrent Fault Indicator. FLT floats and is disabled until VIN >VUVLO. This output is pulled low after

the current limit time-out period has expired. Fault is not signaled due to over-temperature shut down.

Range 0V to VIN.

OUT2,

OUT1

Controlled Supply Output. Upon an OC condition, IOUT is current limited. Current limit response time is

within 200µs. This output remains in current limit for a nominal 12ms before being turned off either for

the latch or auto retry versions. Range 0V to VIN.

- 8 NC This pin is not electrically connected internally.

(DFN only)

PD EPAD Thermal Dissipation Exposed PAD Range: Connect to GND.

ISL6185

6FN6937.3

March 8, 2012

Absolute Maximum Ratings Thermal Information

Supply Voltage (VIN to GND, Note 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5V

EN, FAULT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VIN

OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VIN 0.3V

Output Current . . . . . . . . . . . Short Circuit Protected Current Limit of 2.5A

ESD Rating

Human Body Model (Per MIL-STD-883 Method 3015.7). . . . . . . . . . 3kV

Machine Model (Per MIL-STD-883 Method 3015.7) . . . . . . . . . . . . 300V

Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA

Operating Conditions

Commercial Temperature Range . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 5.5V

Thermal Resistance (Typical, Note 4) θJA (°C/W) θJC (°C/W)

8 Lead SOIC Package (Note 4). . . . . . . . . . 120 N/A

8 Lead 3x3 DFN Package (Notes 5, 6) . . . 48 6

10 Lead 3x3 DFN Package (Notes 5, 6) . . 53 6

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

Brief TB379.

6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

7. All voltages are relative to GND, unless otherwise specified.

Electrical Specifications VIN = 5V, TA = TJ, Unless Otherwise Specified. Boldface limits apply over the operating temperature

range, 0°C to +75°C or -40°C to +85°C.

SYMBOL PARAMETER TEST CONDITIONS

MIN

(Note 8) TYP

MAX

(Note 8) UNITS

POWER SWITCH

rDS(ON)_50 ON-Resistance at 5.0V (Pulse Tested) VIN = 5V, IOUT = 0.1A, TA = TJ = +25°C - 71 87 mΩ

TA = TJ = +85°C - 110 mΩ

rDS(ON)_33 ON-Resistance at 3.3V (Pulse Tested) VIN = 3.3V, IOUT = 0.1A, TA = TJ = +25°C - 90 105 mΩ

TA = TJ = +85°C - 130 mΩ

rDS(ON)_25 On Resistance at 2.5V (Pulse Tested) VIN = 2.5V, IOUT = 0.1A, TA = TJ = +25°C - 114 127 mΩ

TA = TJ = +85°C - 150 mΩ

VOUT_DIS Disabled Output Voltage VIN = 5V, Switch Disabled, 50µA Load - 50 70 mV

ROUT_PU Output Pull-Down Resistor VIN = 5V, Switch Disabled 89.6 12 kΩ

tRVOUT Rise Time RL = 10Ω, CL = 10µF, 10% to 90% - 100 - µs

tFSlow VOUT Turn-off Fall Time RL = 10Ω, CL = 10µF, 90% to 10% - 200 - µs

tF_fast Fast VOUT Turn-off Fall Time RL = 1Ω, CL = 10µF, 80% to 20% - 23 - µs

CURRENT CONTROL

IOUT_CONT_5 Maximum Continuous Current, VIN =

5V.

Guaranteed by Itrip minimum

specification.

ISL6185xA,B,E,F - 0.6 A

IOUT_CONT_5 ISL6185xC,D,G,H - 1.1 A

IOUT_CONT_5 ISL6185xI,J,K,L - 1.5 A

IOUT_CONT_5 ISL61853M,N,O,P (10 Ld DFN) - 1.8 A

IOUT_CONT_3 Maximum Continuous Current, VIN =

3.3V.

Guaranteed by Itrip minimum

specification.

ISL6185xA,B,E,F - 0.6 A

IOUT_CONT_3 ISL6185xC,D,G,H - 0.9 A

IOUT_CONT_3 ISL61851I,J,K,L (SOIC) - 1.3 A

IOUT_CONT_3 ISL61852, ISL61853 (DFN) - 1.5 A

ISL6185

7FN6937.3

March 8, 2012

IOUT_CONT_2 Maximum Continuous Current, VIN =

2.5V

ISL6185xA,B,E,F - 0.6 - A

IOUT_CONT_2 ISL61851C,D,G,H,I,J,K,L (SOIC) - 0.9 - A

IOUT_CONT_2 ISL61852, ISL61853 C,D,G,H (DFN) - 1 - A

IOUT_CONT_2 ISL61853I,J,K,L (10 Ld DFN) - 1 - A

IOUT_CONT_2 ISL61853M,N,O,P (10 Ld DFN) - 1 - A

ITRIP_5 Trip Current, VIN = 5V ISL6185xA,B,E,F 0.70 1.02 1.52 A

ITRIP_5 ISL6185xC,D,G,H 1.15 1.45 1.95 A

ITRIP_5 ISL6185xI,J,K,L 1.55 1.82 2.25 A

ITRIP_5 ISL61853M.N,O,P 1.85 1.99 2.45 A

ITRIP_3 Trip Current, VIN = 3.3V ISL6185xA,B,E,F 0.65 0.86 1.20 A

ITRIP_3 ISL6185xC,D,G,H 0.95 1.25 1.60 A

ITRIP_3 ISL6185xI,J,K,L 1.35 1.60 1.85 A

ITRIP_3 ISL61853M.N,O,P 1.55 1.89 2.25 A

ITRIP_2 Trip Current, VIN = 2.5V ISL6185xA,B,E,F -0.65 - A

ITRIP_2 ISL6185xC,D,G,H -1- A

ITRIP_2 ISL6185xI,J,K,L -1.2 - A

ITRIP_2 ISL61853M.N,O,P -1.6 -A

ILIM_5 Current Limit, VIN = 5V ISL6185xA,B,E,F, VIN - VOUT = 1V 0.50 0.65 0.78 A

ILIM_5 ISL6185xC,D,G,H, VIN - VOUT = 1V 0.98 1.14 1.28 A

ILIM_5 ISL6185xI,J,K,L, VIN - VOUT = 1V 1.30 1.55 1.72 A

ILIM_5 ISL61853M,N,O,P, VIN - VOUT = 1V 1.52 1.83 2.20 A

ILIM_3 Current Limit, VIN = 3.3V ISL6185xA,B,E,F, VIN - VOUT = 1V 0.45 0.63 0.75 A

ILIM_3 ISL6185xC,D,G,H, VIN - VOUT = 1V 0.90 1.10 1.26 A

ILIM_3 ISL6185xI,J,K,L, VIN - VOUT = 1V 1.25 1.50 1.68 A

ILIM_3 ISL61853M,N,O,P, VIN - VOUT = 1V 1.48 1.78 2.05 A

ILIM_2 Current Limit, VIN = 2.5V ISL6185xA,B,E,F, VIN - VOUT = 1V 0.47 0.61 0.74 A

ILIM_2 ISL6185xC,D,G,H, VIN - VOUT = 1V 0.90 1.05 1.17 A

ILIM_2 ISL6185xI,J,K,L, VIN - VOUT = 1V 1.15 1.37 1.58 A

ILIM_2 ISL61853M,N,O,P, VIN - VOUT = 1V 1.3 1.63 1.90 A

Isc_5 Short Circuit Current, VIN = 5V ISL6185xA,B,E,F, VOUT = 0V 0.60 0.80 1.00 A

Isc_5 ISL6185xC,D,G,H, VOUT = 0V 1.00 1.27 1.55 A

Isc_5 ISL6185xI,J,K,L, VOUT = 0V 1.15 1.61 1.85 A

Isc_5 ISL61853M,N,O,P, VOUT = 0V 1.20 1.70 2.5 A

Isc_3 Short Circuit Current, VIN = 3.3V ISL6185XA,B,E,F, VOUT = 0V 0.35 0.48 0.60 A

Isc_3 ISL6185XC,D,G,H, VOUT = 0V 0.65 0.80 0.95 A

Isc_3 ISL6185xI,J,K,L, VOUT = 0V 0.70 1.06 1.25 A

Isc_3 ISL61853M,N,O,P, VOUT = 0V 0.90 1.24 1.50 A

Electrical Specifications VIN = 5V, TA = TJ, Unless Otherwise Specified. Boldface limits apply over the operating temperature

range, 0°C to +75°C or -40°C to +85°C. (Continued)

SYMBOL PARAMETER TEST CONDITIONS

MIN

(Note 8) TYP

MAX

(Note 8) UNITS

ISL6185

8FN6937.3

March 8, 2012

Isc_2 Short Circuit Current, VIN = 2.5V ISL6185xA,B,E,F, VOUT = 0V -0.61 A

Isc_2 ISL6185xC,D,G,H, VOUT = 0V -1.06 -A

Isc_2 ISL6185xI,J,K,L, VOUT = 0V -1.30 -A

Isc_2 ISL61853M,N,O,P, VOUT = 0V -1.39 -A

Isc_5.5 Short Circuit Current, VIN = 5.5V All ISL6185X Variants --2.5A

tsettIlim OC to Limit Settling Time VIN/RL = 2ILIM, CL = 10µF to within 10% of ILIM -200- µs

tsettIlim_sev Severe OC to Limit Settling Time VIN/RL = 4ILIM, CL = 10µF to within 10% of ILIM -30- µs

tCL Current Limit Duration IOUT = ILIM 9.2 12 15 ms

tRTY Automatic Retry Period 0.80 11.35 s

I/O PARAMETERS

Vfault_lo Fault Output Voltage Fault IOUT = 10mA - - 0.4 V

Ifault Fault Leakage -5-µA

Venr_5 EN / EN Rising Threshold VIN = 5V 1.5 1.8 2V

Hys_Venr_5 EN / EN Rising Threshold Hysteresis VIN = 5V 80 140 175 mV

Venr_3 EN / EN Rising Threshold VIN = 3.3V 1.0 1.3 1.6 V

Hys_Venr_3 EN / EN Rising Threshold Hysteresis VIN = 3.3V 58 80 120 mV

Venr_2 EN / EN Rising Threshold VIN = 2.5V 0.95 1.1 1.3 V

Hys_Venr_2 EN / EN Rising Threshold Hysteresis VIN = 2.5V 30 70 110 mV

Ren_h ENABLE Pull-Down Resistor Enable asserted high options 0.6 11.55 MΩ

Ren_l ENABLE Pull-Up Resistor Enable asserted low options 0.6 11.55 MΩ

tON Enable to Output Turn-on Time RL = 10Ω, CL = 10µF, Enable 50% to Output 90% - 0.1 - ms

tOFF Enable to Output Turn-off Time RL = 10Ω, CL = 10µF, Enable 50% to Output 10% - 0.25 - ms

BIAS PARAMETERS

IVDD Enabled VIN Current Switches Closed, OUTPUT = OPEN 50 75 µA

IVDD Disabled VIN Current Switches Open, OUTPUT = OPEN - 2 5µA

VUVLO Rising POR Threshold VIN Rising to functional operation 1.7 2.1 2.3 V

IVR Reverse Blocking Leakage Current VIN = 0V, VOUT = 5V - 2µA

Temp_dis Over-Temperature Disable - 150 - °C

Temp_hys Over-Temperature Hysteresis - 20 - °C

NOTE:

8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

Electrical Specifications VIN = 5V, TA = TJ, Unless Otherwise Specified. Boldface limits apply over the operating temperature

range, 0°C to +75°C or -40°C to +85°C. (Continued)

SYMBOL PARAMETER TEST CONDITIONS

MIN

(Note 8) TYP

MAX

(Note 8) UNITS

ISL6185

9FN6937.3

March 8, 2012

Introduction

The ISL6185 is a dual channel fully independent overcurrent (OC)

fault protection IC for the +2.5V to +5V environment. Each

ISL6185 incorporates in a single package two 85mΩ P-channel

MOSFET power switches for power control. Independent enabling

inputs and fault reporting outputs compatible with 2.5V to 5V

logic allow for external control and reporting. This device features

integrated power switches with current monitoring, accurate

current limiting, reverse bias protection and current limited

timed delay to turn-off for system reliability. See Figures 13

through 28 for typical operational waveforms including both

under-current and over-current situations.

The ISL6185 offers current sense and limiting, with VIN =5V

guaranteed continuous current product variants of 0.6A, 1.1A, 1.5A

and 1.8A, making these devices well suited for a myriad of USB and

other low power (9W max) port power management applications

and configurations.

The ISL6185 also provides thermally insensitive timed OC turn-off

and fault notification. This isolates and protects the voltage bus in

the event of a peripheral OC event or short circuit event,

independent of the adjoining switch’s electrical or the ambient

thermal condition.

The ISL6185 undervoltage lockout feature prevents turn-on of

the outputs unless the correct ENABLE state and VIN > VUVLO

are present. During initial turn-on, the ISL6185 prevents fault

reporting by blanking the fault signal.

During operation, once an OC condition is detected, the output

is current limited for tCL to allow transient OC conditions to

pass. If still in current limit after the current limit period has

elapsed, the output is turned off, and the fault is reported by

pulling the corresponding FAULT output low. On the latch-off

options, after turn-off, both the output and the FAULT signal are

latched low until reset by the enable signal being de-asserted or

until a POR occurs. At this time, the FAULT signal clears, and

the switch is ready to be turned back on. On the auto restart

options, the ISL6185 attempts to periodically turn on the

output, as long as the enable is asserted.

When disabled, the ISL6185 has a low quiescent supply current

and an output-to-input reverse current flow blocking capability.

The ISL6185 family is provided with enable polarity options and

an industry-standard 8 lead SOIC pinout, along with two versions

in the 70% smaller 3x3 DFN. The 8 Ld DFN package offers the

same performance as the 8 Ld SOIC, whereas the 10 Ld DFN

offers higher current capability in the smallest possible package

because of lower package electrical and thermal resistance.

Functional Description

Power On Preset (POR)

The ISL6185 POR feature inhibits device functionality when

VIN < VUVLO.

Reverse Polarity Protection

In any event in which the power switch is disabled and

VOUT >V

IN, there will be no output-to-input current flow, nor will

the output voltage appear on the input.

Soft-Start

Upon enable, the switch passes a constant current to the load.

The voltage on the VOUT pin ramps up according the equation,

ILIM/COUT (V/s). Resistive or active load slows the VOUT ramp-up

toward the top of its curve.

Fault Blanking On Start-Up

During initial turn-on, the ISL6185 prevents nuisance faults from

being reported to the system controller by blanking the fault

signal until the internal FET is fully enhanced.

Current Trip and Limiting Levels

The ISL6185 provides integrated current sensing in the MOSFET

that allows for rapid control of OC events. Once an OC condition is

detected, the ISL6185 goes into its current limiting (CL) control

mode. The ISL6185 is variant specified to allow a continuous

current (ICONT) operation of 0.6A, 1.1A, 1.5A or 1.8A. As the

current increases past its continuous current rating, it will reach

a level that causes the device to enter its current limit mode; that

is, the current trip level. The current trip level is in all cases

adequately above the ICONT rating so as not to cause unintended

false faults. The current limit is specified at VOUT = VIN - 1V to test

a known representative condition and is featured at a nominal

value slightly higher than the continuous current rating. The

speed of this current limiting control is inversely related to the

magnitude of the OC fault. Thus, a hard overcurrent is more

quickly pulled to its limiting value than a marginal OC condition.

Over-Temperature Shutdown

Although the ISL6185 has an over-temperature shutdown and

lockout feature, because of the 12ms timed shutdown, the

thermal shutdown is likely to be invoked only in extremely high

ambient temperatures.

The over-temperature protection invokes and disables the switch

turn-on operation once the die temperature is ~+140°C. It turns

off an already on switch at ~+150°C and releases the part to

operation once the die temperature falls to ~+120°C.

ISL6185

10 FN6937.3

March 8, 2012

Turn-off Time Delay

During operation, once an OC condition is detected, the output

is current limited for ~12ms to allow transient OC conditions to

pass. If still in current limit and after the current limit period

has elapsed, the output is turned off, and the fault is reported

by pulling the corresponding FAULT low. The internal 12ms timer

starts upon current limiting and is independent of ambient or IC

thermal conditions, thus providing more consistent operation

over the entire temperature range.

Latch-off Restart/Auto-Restart Start

After turn-off, with the latch-off options, both the output and the

FAULT signal are latched low until they are reset by the enable

signal being de-asserted. At this time, the FAULT signal clears,

and the IC is ready for enable to assert. On the auto restart

options, the ISL6185 attempts to periodically turn-on the

output at approximately 1s intervals, as long as the enable is

asserted. If the OC condition remains indefinitely, the fault

indication and the restart attempts also continue until the

thermal protection feature is invoked, thus increasing the

restart period.

Active Output Pull-down

Another ISL6185 feature is the 10kΩ active pull-down on the

outputs to <60mV above GND when the device is disabled, thus

ensuring discharge of the load.

Typical Performance Curves

FIGURE 3. SWITCH ON-RESISTANCE AT 0.5A FIGURE 4. NORMALIZED SWITCH RESISTANCE

FIGURE 5. 0.6A CONTINUOUS CURRENT CHARACTERISTICS FIGURE 6. 1.1A CONTINUOUS CURRENT CHARACTERISTICS

150

140

130

120

110

100

50 -40-25 0 25457585115

TEMPERATURE (°C)

rDS(ON) @ 0.5A (mΩ)

VIN = 2.5V

VIN = 3.3V

VIN = 5V

0.7

0.8

0.9

1.0

1.1

1.2

1.3

-40-25 0 25457585115

TEMPERATURE (°C)

NORMALIZED rDS(ON)

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

-40-25 0 25457585115

TEMPERATURE (°C)

OUTPUT CURRENT (A)

5V ISC

5V ILIM

3.3V ILIM

3.3V ISC

5V ITRIP

3.3V I

TRIP

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

-40-25 0 25457585115

TEMPERATURE (°C)

OUTPUT CURRENT (A)

3.3V I

TRIP

5V ISC

5V ILIM

3.3V ILIM

3.3V ISC

5V ITRIP

ISL6185

11 FN6937.3

March 8, 2012

FIGURE 7. 1.5A CONTINUOUS CURRENT CHARACTERISTICS FIGURE 8. 1.8A CONTINUOUS CURRENT CHARACTERISTICS

FIGURE 9. LIMITING CURRENT ±3 SIGMA, VIN = 5V FIGURE 10. LIMITING CURRENT ±3 SIGMA, VIN = 5V

FIGURE 11. LIMITING CURRENT ±3 SIGMA, VIN = 5V FIGURE 12. LIMITING CURRENT ±3 SIGMA, VIN = 5V

Typical Performance Curves (Continued)

0.8

1.0

1.2

1.4

1.6

1.8

2.0

-40-25 0 25457585115

TEMPERATURE (°C)

OUTPUT CURRENT (A)

3.3V ITRIP 5V ISC

3.3V ILIM

3.3V ISC

5V ITRIP

5V ILIM

1.0

1.2

1.4

1.6

1.8

2.0

2.2

-40-25 0 25457585115

TEMPERATURE (°C)

OUTPUT CURRENT (A)

3.3V ITRIP

3.3V ILIM

3.3V ISC

5V ITRIP

5V I

LIM

5V ISC

0.50

0.55

0.60

0.65

0.70

0.75

-40-25 0 25457585115

LIMIT

± 3 SIGMA

TEMPERATURE (°C)

+3 SIGMA

TYPICAL

-3 SIGMA

0.6A CONTINUOUS IOUT VERSION

1.00

1.05

1.10

1.15

1.20

1.25

-40-25 0 25457585115

LIMIT

± 3 SIGMA

TEMPERATURE (°C)

+3 SIGMA

TYPICAL

-3 SIGMA

1.1A CONTINUOUS IOUT VERSION

1.35

1.40

1.45

1.50

1.55

1.60

1.65

-40-25 0 25457585115

LIMIT

± 3 SIGMA

TEMPERATURE (°C)

+3 SIGMA

TYPICAL

-3 SIGMA

1.5A CONTINUOUS IOUT VERSION

2.00

1.95

1.90

1.85

1.80

1.75

1.70

1.65

1.60

-40-25 0 25457585115

TEMPERATURE (°C)

+3 SIGMA

TYPICAL

-3 SIGMA

1.8A CONTINUOUS IOUT VERSION

LIMIT

± 3 SIGMA

ISL6185

12 FN6937.3

March 8, 2012

FIGURE 13. VOUT TURN-ON/RISE TIME vs CLOAD. VIN = 5V,

RL = 10Ω

FIGURE 14. VOUT TURN-OFF/FALL TIME

vs CLOAD. VIN = 5V, RL = 10Ω

FIGURE 15. LATCH-OFF vs CLOAD FIGURE 16. ILIM WAVEFORM

FIGURE 17. OC RAMP RATE ILIM WAVEFORMS FIGURE 18. PEAK CURRENT SETTLING TIMES

Typical Performance Curves (Continued)

CL=1µF

ENABLE

CL= 100µF

CL= 10µF

VOUT

1V/DIV

VOUT

ENABLE

CL= 10µF

CL= 100µF

CL=1µF

1V/DIV

VOUT

CL=10µF

CL= 100µF

CL=1µF

1V/DIV

FLT

VOUT

IIN

0.6A ICONT VARIANT

IIN 2A/DIV

0.72A CURRENT LIMIT

0.53A LOAD CURRENT

0.08A/ms

0.6A/ms

6A/ms

0.6A ICONT VARIANT

0.66A CURRENT LIMIT

0.56A LOAD CURRENT

2A OC 27µs

1A OC 57µs

0.5A OC 200µs

0.6A ICONT VARIANT

ISL6185

13 FN6937.3

March 8, 2012

FIGURE 19. TURN-ON INTO A SHORT FIGURE 20. TURN-ON INTO MOMENTARY OC

FIGURE 21. ISL6185 RETRY FUNCTION FIGURE 22. ILIM WAVEFORM

FIGURE 23. VIN = 2.5V TURN-ON INTO 2.2Ω FIGURE 24. VIN = 5V TURN-ON INTO 2.7Ω

Typical Performance Curves (Continued)

ENABLE

VOUT

FAULT

0.6A ICONT VARIANT

LIMITED TO 0.64A

IIN

ENABLE

VOUT

FAULT

IIN

0.6A ICONT VARIANT

VOUT

FLT

IIN

VOUT

FLT

IIN

1.1A ICONT VARIANT

ENABLE

VOUT

FAULT

IIN 1.8A ICONT VARIANT

ENABLE

VOUT

FAULT

Iin

1.8A ICONT VARIANT

ISL6185

14 FN6937.3

March 8, 2012

FIGURE 25. TURN-ON INTO A SHORT FIGURE 26. TURN-ON 2ND OUTPUT TO FULL LOAD

FIGURE 27. ISL6185 RETRY FUNCTION FIGURE 28. ILIM WAVEFORM

FIGURE 28. PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

Typical Performance Curves (Continued)

ENABLE

VOUT

FAULT

IIN

1.8A ICONT VARIANT

LIMITED TO 1.7A

ENABLE

VOUT

FAULT

IIN

CH1 ON

CH1 and CH2 ON

(1.8A)

(3.6A TOTAL IIN)

VOUT

FLT

IIN

VOUT

FLT

IIN

1.1A ICONT VARIANT

Test Circuits

FIGURE 29A. rDS(ON) FIGURE 29B. CURRENT LIMITING

FIGURE 29. DC TEST CIRCUIT

5V OUTPUT

ISL6185

VIN

FLT

10k

10µF

OUT

V-

rDS(ON) = V/(VOUT/10W)

OUTPUT

ISL6185

VIN

FLT

10k

10µF

OUT RL sized

for desired

OC level

ISL6185

15 FN6937.3

March 8, 2012

FIGURE 30. TRANSIENT TEST CIRCUIT FIGURE 31. TRANSIENT WAVEFORM MEASUREMENT POINTS

Test Circuits (Continued)

5V OUTPUT

ISL6185

VIN

FLT

10k

10µF

0-VIN

OUT

VIN

0.5VIN

VIN

GND

OUTPUT

tON tOFF

OUTPUT

VIN

-GND

90% 90%

10% 10%

90%

10%

ISL6185xEVAL1Z Schematic and Photo

FIGURE 32A. ISL6185xEVAL SCHEMATIC FIGURE 32B. ISL61851EVAL1Z BOARD PHOTO

FIGURE 32. ISL6185xEVAL1Z SCHEMATIC and ISL61851EVAL1Z PHOTOGRAPH

NOTE: EXPOSED PAD on DFN packages only

ISL6185

10k

AGND

V+

EN1

EN2

2.2µF

10k

FLT1

FLT2

OUT1

OUT2

10µF

AGND

FLT1

OUT1

OUT2

FLT2

10µF

AV+

ISL6185

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6937.3

March 8, 2012

For additional products, see www.intersil.com/product_tree

Application Information

Using the ISL6185xEVAL1Z Platform

General and Biasing Information

There are three evaluation platforms for the ISL6185 family.

There is one platform for each package style, each with a

different continuous output current level and a mix of enable

polarity and output retry or latch options. See page 4, at the end

of the “Ordering Information” table, for information on the

standard available evaluation board options. Figure 32A shows

the common schematic for all three evaluation boards. See “Pin

Configurations” on page 5 for details and differences.

The evaluation platform is biased and monitored through

numerous labeled test points. See Table 1 for test point

assignments and descriptions.

Upon proper bias of the evaluation platform and correct enabling

of the IC, the ISL6185 will have a nominal VIN/10Ω load current

that is lower than the continuous current rating passing through

each enabled switch. See Figures 13 and 14 for typical ISL6185

turn-on and turn-off waveforms.

External current loading in excess of the trip current level for the

particular part being evaluated will result in the ISL6185 entering

the current limiting mode. Figure 16 illustrates the current

limiting mode for the ISL6185 product variants with 0.6A of

continuous load current rating. The scope shot shows current

limiting for ~12ms before it is turned off and the fault signal is

asserted.

Application Considerations

The application considerations for the ISL6185 family are widely

accepted best industry practices. Good decoupling practices on

the VIN pin must be followed: placement close to the IC, with at

least 2.2µF recommended. It is recommended to reduce the

input and output inductance to the ISL6185 with good PCB

layout practices.

When designing with the 1.5A and 1.8A versions in an

implementation in which the output may be unloaded (open)

while the ISL6185 is turned on, a minimum of 4.7µF of

capacitive output load is recommended to prevent high dv/dt

from unnecessarily activating the surge/ESD control circuit.

The ISL6185 provides several continuous current rated devices

specified at VIN = 5V; these are 0.6A, 1.1A, 1.5A and 1.8A

options that are capable over the entire temperature extreme. At

VIN = 3.3V, the current capability is degraded, and the ISL6185 is

specified at 0.6A, 1.1A, 1.3A and 1.5A, respectively. At

VIN = 2.5V, there are no minimum specifications, but a typical

value is provided for +25°C operation (see “Electrical

Specifications” on page 6). This degraded capability is due to the

higher rDS(ON) of the FET switch at the lower bias voltage.

The enhanced thermal characteristics and increased number of

bond wires allow the 10 Ld DFN to have a higher current

capability than either the 8 Ld SOIC or the DFN.

TABLE 1. ISL61851EVAL1Z TEST POINT ASSIGNMENTS

TP NAME DESCRIPTION

GND Eval Board and IC Gnd

V+ Eval Board and IC Bias

EN1 Enable Switch 1

EN2 Enable Switch 2

FLT2 Switch 2 Fault

OUT2 Switch Out 2

OUT1 Switch Out 1

FLT1 Switch 1 Fault

TABLE 2. ISL6185XEVAL1Z BOARD COMPONENT LISTING

COMPONENT

DESIGNATOR

COMPONENT

FUNCTION COMPONENT DESCRIPTION

U1 ISL6185 Intersil, ISL6185

R3 - R4 Output Load

Resistors

10Ω, 5%, 3W

R1 - R2 FLT Output Pull-up

Resistor

10kΩ, 0805

C1 Decoupling

Capacitor

2.2µF, 0805

C2 - C3 Load Capacitor 10µF 16V Electrolytic,

Radial Lead

ISL6185

17 FN6937.3

March 8, 2012

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products

address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.

Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

complete list of Intersil product families.

For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information pages

on intersil.com for ISL6185XXC (commercial version) and ISL6185XXI (industrial version).

To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff

FITs are available from our website at: http://rel.intersil.com/reports/sear

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest Rev.

DATE REVISION CHANGE

March 1, 2012 FN6937.3 In “Features” on page 1 changed from:

UL Recognized, File Number: E333469

(Applies to DFN Packages, SOIC Package to be Qualified Shortly)

to:

UL Recognized, File Number : E333469

In “Absolute Maximum Ratings” on page 6:

Changed from:

Output Current . . . . . . . . . Short Circuit Protected

to:

Output Current . . . . . . . . . .Short Circuit Protected Current Limit of 2.5A

Updated “Package Outline Drawing” on page 20. Changed Note 1 "1982" to "1994".

December 2, 2011 FN6937.2 Page 1: Added "UL Recognized, File Number: E333469 (Applies to DFN packages, SOIC pkg to be qualified

shortly)" to "Features"

Page 8: Added Isc_5.5, Short Circuit Current with max of 2.5A to “Electrical Specifications”

Page 19: Updated package outline drawing to most updated revision. Removed package outline and included

center to center distance between lands on recommended land pattern. Removed Note 4 "Dimension b applies

to the metallized terminal and is measured between 0.18mm and 0.30mm from the terminal tip." since it is

not applicable to this package. Renumbered notes accordingly.

June 14, 2011 FN6937.1 Page 2: “Ordering Information”: added part numbers of parts installed on evaluation boards to Description

column.

Page 7: “Electrical Specifications” table:

- For “Maximum Continuous Current, VIN = 2.5V,” changed “ISL61851C,D,G,H (SOIC)” to

“ISL61851C,D,G,H,I,J,K,L (SOIC)”

- For “Trip Current, VIN = 5V”, changed “ISL61853I,J,K,L” to “ISL6185xI,J,K,L”. For “ISL61853M.N,O,P” changed

MAX from “2.15” to “2.45”.

- For “Trip Current, VIN = 3.3V” and “Trip Current, VIN = 2.5V” changed “ISL61853I,J,K,L“ to “ISL6185xI,J,K,L“.

- For “Current Limit, VIN = 5V”, “Current Limit, VIN = 3.3V”, and “Current Limit, VIN = 2.5V”, changed

“ISL61853I,J,K,L, VIN - VOUT = 1V” to “ISL6185xI,J,K,L, VIN - VOUT = 1V”

- For “Short Circuit Current, VIN = 5V”, “Short Circuit Current, VIN = 3.3V” and “Short Circuit Current, VIN = 2.5V”

changed “ISL61853I,J,K,L, VOUT = 0V” to “ISL6185xI,J,K,L, VOUT = 0V”

Page 8: “Electrical Specifications” table: For the I/O Parameters Venr_5, Hys_Venr_5, Venr_3, Hys_Venr_3,

Venr_2, and Hys_Venr_2: changed "ENABLE Rising Threshold" and "ENABLE Rising Threshold Hysteresis" to "EN

/ EN Rising Threshold" and "EN / EN Rising Threshold Hysteresis," for clarity.

Page 8: Electrical Specifications table: Removed UVHYS, POR Hysteresis specification.

Page 20: Replaced Rev. 1 of M8.15 package outline drawing, dated 6/05, with Rev 2 (latest version), dated

11/10.

Applied current Intersil datasheet template to document.

October 22, 2010 FN6937.0 Initial release.

ISL6185

18 FN6937.3

March 8, 2012

Package Outline Drawing

L8.3x3J

8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

Rev 0 9/09

located within the zone indicated. The pin #1 identifier may be

Unless otherwise specified, tolerance : Decimal ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

between 0.15mm and 0.30mm from the terminal tip.

Dimension applies to the metallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

either a mold or mark feature.

Dimensions are in millimeters.1.

NOTES:

BOTTOM VIEW

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

SIDE VIEW

C0 . 2 REF

0 . 05 MAX.

0 . 00 MIN.

3.00 A

3.00

(4X) 0.15

PIN 1

INDEX AREA PIN #1 INDEX AREA

6X 0.65

1.64 +0.10/ - 0.15

8X 0.400 ± 0.10

Max 1.00

SEE DETAIL "X"

0.08

0.10

( 2.80 )

(1.64)

( 8 X 0.30)

( 8X 0.60)

( 2.38 )

( 1.95)

2.38

0.10

8X 0.30

AMC B

2X 1.950

+0.10/ - 0.15

(6x 0.65)

PIN 1

ISL6185

19 FN6937.3

March 8, 2012

Package Outline Drawing

L10.3x3

10 LEAD DUAL FLAT PACKAGE (DFN)

Rev 7, 10/11

located within the zone indicated. The pin #1 identifier may be

Unless otherwise specified, tolerance : Decimal ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

either a mold or mark feature.

Dimensions are in millimeters.1.

NOTES:

BOTTOM VIEW

DETAIL "X"

SIDE VIEW

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

(4X) 0.10

INDEX AREA

PIN 1

PIN #1 INDEX AREA

SEATING PLANE

BASE PLANE

0.08

SEE DETAIL "X"

0.10 C

1.00

0.20

8x 0.50

2.00

3.00

(10x 0.23)

(8x 0.50)

2.00

1.60

(10 x 0.55)

3.00

0.05

0.20 REF

10 x 0.23

10x 0.35

1.60

MAX

(4X) 0.10 AB

0.415

0.23

0.35

0.200

2.85 TYP

ISL6185

20 FN6937.3

March 8, 2012

Package Outline Drawing

M8.15

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 4, 1/12

DETAIL "A"

TOP VIEW

INDEX

AREA

123

-C-

SEATING PLANE

x 45°

NOTES:

1. Dimensioning and tolerancing per ANSI Y14.5M-1994.

2. Package length does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

3. Package width does not include interlead flash or protrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

4. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

5. Terminal numbers are shown for reference only.

6. The lead width as measured 0.36mm (0.014 inch) or greater above the

seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).

7. Controlling dimension: MILLIMETER. Converted inch dimensions are not

necessarily exact.

8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.

SIDE VIEW “A

SIDE VIEW “B”

1.27 (0.050)

6.20 (0.244)

5.80 (0.228)

4.00 (0.157)

3.80 (0.150)

0.50 (0.20)

0.25 (0.01)

5.00 (0.197)

4.80 (0.189)

1.75 (0.069)

1.35 (0.053)

0.25(0.010)

0.10(0.004)

0.51(0.020)

0.33(0.013)

8°

0°

0.25 (0.010)

0.19 (0.008)

1.27 (0.050)

0.40 (0.016)

1.27 (0.050)

5.20(0.205)

TYPICAL RECOMMENDED LAND PATTERN

2.20 (0.087)

0.60 (0.023)