Publication# 17908 Rev. DAmendment/0
Issue Date: May 1995
MACHLV210-12/15/20
High Density EE CMOS Programmable Logic
COM’L: -12/15/20
FINAL IND: -18/24
DISTINCTIVE CHARACTERISTICS
■Low-voltage operation, 3.3-V JEDEC
compatible
—VCC = +3.0 V to +3.6 V
■< 5 mA standby current
■Patented design allows minimal standby
current without speed degradation
■Exclusively designed for 3.3-V applications
■44 Pins
■64 Macrocells
■12 ns tPD Commercial
18 ns tPD Industrial
■83.3 MHz fCNT
■38 Bus-Friendly Inputs
■32 Outputs
■64 Flip-flops; 2 clock choices
■4 “PAL22V16” blocks with buried macrocells
■Pin-, function-, and JEDEC-compatible with
MACH210
■Pin-compatible with MACH110, MACH111,
MACH210, MACH211, and MACH215
GENERAL DESCRIPTION
The MACHLV210 is a member of the high-
performance EE CMOS MACH 2 device family. This
device has approximately six times the logic macrocell
capability of the popular PAL22V10 at an equal speed
with a lower cost per macrocell. It is architecturally
identical to the MACH210, with the addition of I/O
pull-up/pull-down resistors and low-voltage, low-power
operation.
The MACHLV210 provides 3.3-V operation with low-
power CMOS technology. The patented design
allows for minimal standby current without speed
degradation by limiting the leakage current when
signals are not switching. At less than 5 mA maximum
standby current, the MACHLV210 is ideal for low-power
applications.
The MACHLV210 consists of four PAL blocks intercon-
nected by a programmable switch matrix. The four PAL
blocks are essentially “PAL22V16” structures complete
with product-term arrays and programmable macro-
cells, including additional buried macrocells. The switch
matrix connects the PAL blocks to each other and to all
input pins, providing a high degree of connectivity
between the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.
The MACHLV210 has two kinds of macrocell: output
and buried. The MACHLV210 output macrocell pro-
vides registered, latched, or combinatorial outputs with
programmable polarity. If a registered configuration is
chosen, the register can be configured as D-type or
T-type to help reduce the number of product terms. The
register type decision can be made by the designer or by
the software. All output macrocells can be connected to
an I/O cell. If a buried macrocell is desired, the internal
feedback path from the macrocell can be used, which
frees up the I/O pin for use as an input.
The MACHLV210 has dedicated buried macrocells
which, in addition to the capabilities of the output
macrocell, also provide input registers or latches for
use in synchronizing signals and reducing setup time
requirements.
Lattice Semiconductor
2 MACHLV210-12/15/20
BLOCK DIAGRAM
Switch Matrix
I/O Cells
Macrocells
I/O Cells
Macrocells
8
8
8
I/O Cells
Macrocells
I/O0–I/O7
Macrocells
I/O Cells
Macrocells
8
8
8
8
8
888
8
I0–I1,
I3–I4
I/O8–I/O15
2
I/O16–I/O23 CLK0/I2,
CLK1/I5
I/O24–I/O31
17908D-1
44 x 68
AND Logic Array
and
Logic Allocator
22 22
22 22
44 x 68
AND Logic Array
and
Logic Allocator
4
2
8
44 x 68
AND Logic Array
and
Logic Allocator
44 x 68
AND Logic Array
and
Logic Allocator
8
2
OE
Macrocells
8
8
Macrocells Macrocells
OE
OE OE
3MACHLV210-12/15/20
CONNECTION DIAGRAM
Top View PLCC
17908D-2
I/O5
I/O6
I/O7
I0
I1
CLK0/I2
I/O8
I/O9
GND
I/O10
I/O11
I/O4
I/O3
I/O2
I/O1
I/O0
GND
VCC
I/O31
I/O30
I/O29
I/O28
I/O27
I/O26
I/O25
I3
I4
I/O24
CLK1/I5
GND
I/O23
I/O22
I/O21
I/O12
I/O13
I/O14
VCC
GND
I/O16
I/O15
I/O17
I/O18
I/O19
I/O20
7
8
9
10
11
12
13
15
16
14
17
561324 4443424140
29
30
31
32
33
34
35
36
37
38
39
18 282726252423222119 20
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage
Note:
Pin-compatible with MACH110, MACH111, MACH210, MACH211, and MACH215.
4 MACHLV210-12/15/20 (Com’l)
ORDERING INFORMATION
Commercial Products
Valid Combinations list configurations planned to be
supported in volume for this device. Consult your local
sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
Programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
OPERATING CONDITIONS
C = Commercial (0°C to +70 °C)
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
SPEED
-12 = 12 ns tPD
-15 = 15 ns tPD
-20 = 20 ns tPD
MACHLV210-12
MACHLV210-15
MACHLV210-20
MACH -12 J C
Valid Combinations
Valid Combinations
OPTIONAL PROCESSING
Blank = Standard Processing
210
DEVICE NUMBER
210 = 64 Macrocells, 44 Pins, Input Pull-Up/Pull-Down
Resistors
PACKAGE TYPE
J = 44-Pin Plastic Leaded Chip
Carrier (PL 044)
JC
LV
TECHNOLOGY
LV = Low Voltage
5MACHLV210-18/24 (Ind)
ORDERING INFORMATION
Industrial Products
Valid Combinations list configurations planned to be
supported in volume for this device. Consult your local
sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
Programmable logic products for industrial applications are available with several ordering options. The order number (Valid
Combination) is formed by a combination of:
OPERATING CONDITIONS
I = Industrial (–40°C to +85 °C)
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
SPEED
-18 = 18 ns tPD
-24 = 24 ns tPD
MACHLV210-18
MACHLV210-24
MACH -18 J I
Valid Combinations
Valid Combinations
OPTIONAL PROCESSING
Blank = Standard Processing
210
DEVICE NUMBER
210 = 64 Macrocells, 44 Pins, Input Pull-Up/Pull-Down
Resistors
PACKAGE TYPE
J = 44-Pin Plastic Leaded Chip
Carrier (PL 044)
JI
LV
TECHNOLOGY
LV = Low Voltage
6 MACHLV210-12/15/20
FUNCTIONAL DESCRIPTION
The MACHLV210 consists of four PAL blocks
connected by a switch matrix. There are 32 I/O pins and
4 dedicated input pins feeding the switch matrix. These
signals are distributed to the four PAL blocks for efficient
design implementation. There are two clock pins that
can also be used as dedicated inputs.
The MACHLV210 inputs and I/O pins have advanced
pull-up/pull-down resistors that enable the inputs to be
pulled to the last driven state. While it is always a good
design practice to tie unused pins high or low, the
MACHLV210 pull-up/pull-down resistors provide design
security and stability in the event that unused pins are
left disconnected.
The PAL Blocks
Each PAL block in the MACHLV210 (Figure 1) contains
a 64-product-term logic array, a logic allocator, 8 output
macrocells, 8 buried macrocells, and 8 I/O cells. The
switch matrix feeds each PAL block with 22 inputs. This
makes the PAL block look effectively like an
independent “PAL22V16” with 8 buried macrocells.
In addition to the logic product terms, two output enable
product terms, an asynchronous reset product term,
and an asynchronous preset product term are provided.
One of the two output enable product terms can be
chosen within each I/O cell in the PAL block. All flip-flops
within the PAL block are initialized together.
The Switch Matrix
The MACHLV210 switch matrix is fed by the inputs and
feedback signals from the PAL blocks. Each PAL block
provides 16 internal feedback signals and 8 I/O feed-
back signals. The switch matrix distributes these signals
back to the PAL blocks in an efficient manner that also
provides for high performance. The design software
automatically configures the switch matrix when fitting a
design into the device.
The Product-term Array
The MACHLV210 product-term array consists of 64
product terms for logic use, and 4 special-purpose
product terms. Two of the special-purpose product
terms provide programmable output enable; one
provides asynchronous reset, and one provides
asynchronous preset.
The Logic Allocator
The logic allocator in the MACHLV210 takes the 64 logic
product terms and allocates them to the 16 macrocells
as needed. Each macrocell can be driven by up to 16
product terms. The design software automatically
configures the logic allocator when fitting the design into
the device.
Table 1 illustrates which product term clusters are avail-
able to each macrocell within a PAL block. Refer to
Figure 1 for cluster and macrocell numbers.
Table 1. Logic Allocation
Available
Output Buried Clusters
M0C0, C1, C2
M1C0, C1, C2, C3
M2C1, C2, C3, C4
M3C2, C3, C4, C5
M4C3, C4, C5, C6
M5C4, C5, C6, C7
M6C5, C6, C7, C8
M7C6, C7, C8, C9
M8C7, C8, C9, C10
M9C8, C9, C10, C11
M10 C9, C10, C11, C12
M11 C10, C11, C12, C13
M12 C11, C12, C13, C14
M13 C12, C13, C14, C15
M14 C13, C14, C15
M15 C14, C15
Macrocell
The Macrocell
The MACHLV210 has two types of macrocell: output
and buried. The output macrocells can be configured as
either registered, latched, or combinatorial, with
programmable polarity. The macrocell provides internal
feedback whether configured with or without the
flip-flop. The registers can be configured as D-type or
T-type, allowing for product-term optimization.
The flip-flops can individually select one of two clock/
gate pins, which are also available as data inputs. The
registers are clocked on the LOW-to-HIGH transition of
the clock signal. The latch holds its data when the gate
input is HIGH, and is transparent when the gate input is
LOW. The flip-flops can also be asynchronously initial-
ized with the common asynchronous reset and preset
product terms.
The buried macrocells are the same as the output
macrocells if they are used for generating logic. In that
case, the only thing that distinguishes them from the
output macrocells is the fact that there is no I/O cell
connection, and the signal is only used internally. The
buried macrocell can also be configured as an input
register or latch.
The I/O Cell
The I/O cell in the MACHLV210 consists of a three-state
output buffer. The three-state buffer can be configured
in one of three ways: always enabled, always disabled,
or controlled by a product term. If product term control is
chosen, one of two product terms may be used to
provide the control. The two product terms that are
available are common to all I/O cells in a PAL block.
These choices make it possible to use the macrocell as
an output, an input, a bidirectional pin, or a three-state
output for use in driving a bus.
7MACHLV210-12/15/20
Benefits of Lower Operating Voltage
The MACHLV210 has an operating voltage range of
3.0 V to 3.6 V. Low voltage allows for lower operating
power consumption, longer battery life, and/or smaller
batteries for portable applications.
Because power is proportional to the square of the volt-
age, reduction of the supply voltge from 5.0 V to 3.3 V
significantly reduces power consumption. This directly
translates to longer battery life for portable applications.
Lower power consumption can also be used to reduce
the size and weight of the battery. Thus, 3.3-V designs
facilitate a reduction in the form factor.
The MACHLV210 is not designed to interface between
3.3-V and 5.0-V logic. Latch-up may occur if VOH for the
MACHLV210 is greater than VIH for the 5.0-V device.
Although this scenario is unlikely, interfacing the
MACHLV210 with 5.0-V devices is not encouraged
without necessary latch-up design precautions.
8 MACHLV210-12/15/20
0 4 8 12 16 20 24 28 4032 43
36
0 4 8 12 16 20 24 28 4032 43
36
8
I/O
Cell I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Switch
Matrix
Output Enable
Output Enable
Asynchronous Reset
Asynchronous Preset
CLK0
CLK1
2
2
2
2
2
2
2
2
2
16
0I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
Buried
Macro
cell
Output
Macro
cell
2
2
2
2
2
2
2
Buried
Macro
cell
Output
Macro
cell
Output
Macro
cell
Buried
Macro
cell
Output
Macro
cell
Buried
Macro
cell
Output
Macro
cell
Buried
Macro
cell
Output
Macro
cell
Buried
Macro
cell
Output
Macro
cell
Buried
Macro
cell
Output
Macro
cell
Buried
Macro
cell
I/O
Cell
14128G-2
Logic Allocator
63
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
M3
M6
M5
M4
M2
M1
M0
M9
M8
M7
M10
M11
M12
M13
M14
M15
17908D-3
Figure 1. MACHLV210 PAL Block
9
MACHLV210-12 (Com’l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature –65°C to +150°C. . . . . . . . . . .
Ambient Temperature
with Power Applied –55°C to +125°C. . . . . . . . . . . . .
Supply Voltage with
Respect to Ground –0.5 V to +5.0 V. . . . . . . . . . . . .
DC Input Voltage –0.5 V to VCC + 0.5 V. . . . . . . . . . .
DC Output or
I/O Pin Voltage –0.5 V to VCC + 0.5 V. . . . . . . . . . . .
Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . . .
Latchup Current (TA = 0°C to +70°C) 200 mA. . . . . .
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Temperature (TA) Operating
in Free Air 0°C to +70°C. . . . . . . . . . . . . . . . . . . . . . .
Supply Voltage (VCC) with
Respect to Ground +3.0 V to +3.6 V. . . . . . . . . . . . . .
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit
VOH Output HIGH Voltage IOH = –2 mA, VCC = Min 2.4 V
VIN = VIH or VIL
VOL Output LOW Voltage IOL = 2 mA, V CC = Min 0.4 V
VIN = VIH or VIL
VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V
Voltage for all Inputs (Note 1)
VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V
Voltage for all Inputs (Note 1)
IIH Input HIGH Leakage Current VIN = 3.6 V, V CC = Max (Note 2) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, V CC = Max (Note 2) –10 µA
IOZH Off-State Output Leakage VOUT = 3.6 V, VCC = Max 10 µA
Current HIGH V IN = VIH or VIL (Note 2)
IOZL Off-State Output Leakage VOUT = 0 V, VCC = Max –10 µA
Current LOW VIN = VIH or VIL (Note 2)
ISC Output Short-Circuit Current VOUT = 0.5 V, V CC = Max (Note 3) –30 –160 mA
ICC Supply Current (Typical) VCC = 3.3 V, TA = 25°C, f = 0 MHz 2 mA
f = 25 MHz 60 mA
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of I
IL
and I
OZL
(or I
IH
and I
OZH
).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
V
OUT
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being
loaded, enabled, and reset.
(Note 4)
MACHLV210-12 (Com’l)
10
CAPACITANCE (Note 1)
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance VCC = 3.3 V, TA = 25°C, f = 1 MHz 6 pF
COUT Output Capacitance 8pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol Parameter Description Min Max Unit
tPD Input, I/O, or Feedback to Combinatorial Output 12 ns
D-type 9 ns
T-type 10 ns
tHRegister Data Hold Time 0 ns
tCO Clock to Output 8ns
t
WL Clock LOW 5 ns
tWH Width HIGH 6 ns
D-type 58.8 MHz
T-type 55.6 MHz
fMAX D-type 83.3 MHz
T-type 76.9 MHz
90.9 MHz
tSL Setup Time from Input, I/O, or Feedback to Gate 9 ns
tHL Latch Data Hold Time 0 ns
tGO Gate to Output 9ns
t
GWL Gate Width LOW 5 ns
tPDL Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch 15 ns
tSIR Input Register Setup Time 2 ns
tHIR Input Register Hold Time 1.5 ns
tICO Input Register Clock to Combinatorial Output 15 ns
tICS Input Register Clock to Output Register Setup D-type 12 ns
T-type 13 ns
tWICL Input Register LOW 5 ns
tWICH Clock Width HIGH 6 ns
fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH) 90.9 MHz
tSIL Input Latch Setup Time 2 ns
tHIL Input Latch Hold Time 1.5 ns
tIGO Input Latch Gate to Combinatorial Output 17 ns
tIGOL Input Latch Gate to Output Through Transparent
Output Latch 19 ns
tSLL Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate 10 ns
tIGS Input Latch Gate to Output Latch Setup 13 ns
Maximum
Frequency
(Note 1)
Setup Time from Input, I/O,
or Feedback to Clock
External Feedback
Internal Feedback (fCNT)
-12
tS
No Feedback (fCNT)
11
MACHLV210-12 (Com’l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
(continued)
Parameter
Symbol Parameter Description Min Max Unit
tWIGL Input Latch Gate Width LOW 5 ns
tPDLL Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches 17 ns
tAR Asynchronous Reset to Registered or Latched Output 16 ns
tARW Asynchronous Reset Width (Note 1) 12 ns
tARR Asynchronous Reset Recovery Time (Note 1) 12 ns
tAP Asynchronous Preset to Registered or Latched Output 16 ns
tAPW Asynchronous Preset Width (Note 1) 12 ns
tAPR Asynchronous Preset Recovery Time (Note 1) 12 ns
tEA Input, I/O, or Feedback to Output Enable 12 ns
tER Input, I/O, or Feedback to Output Disable 12 ns
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
2. See Switching Test Circuit, for test conditions.
-12
MACHLV210-15/20 (Com’l)
12
ABSOLUTE MAXIMUM RATINGS
Storage Temperature –65°C to +150°C. . . . . . . . . . .
Ambient Temperature
with Power Applied –55°C to +125°C. . . . . . . . . . . . .
Supply Voltage with
Respect to Ground –0.5 V to +5.0 V. . . . . . . . . . . . .
DC Input Voltage –0.5 V to VCC + 0.5 V. . . . . . . . . . .
DC Output or
I/O Pin Voltage –0.5 V to VCC + 0.5 V. . . . . . . . . . . .
Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . . .
Latchup Current (TA = 0°C to +70°C) 200 mA. . . . . .
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Temperature (TA) Operating
in Free Air 0°C to +70°C. . . . . . . . . . . . . . . . . . . . .
Supply Voltage (VCC) with
Respect to Ground +3.0 V to +3.6 V. . . . . . . . . . . .
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit
VOH Output HIGH Voltage I OH = –2 mA, VCC = Min 2.4 V
VIN = VIH or VIL
VOL Output LOW Voltage IOL = 2 mA, V CC = Min 0.4 V
VIN = VIH or VIL
VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V
Voltage for all Inputs (Note 1)
VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V
Voltage for all Inputs (Note 1)
IIH Input HIGH Leakage Current VIN = 3.6 V, V CC = Max (Note 2) 10 µA
VIN = 0 V, VCC = Max (Note 2) –10 µA
Off-State Output Leakage VOUT = 3.6 V, VCC = Max
Current HIGH VIN = VIH or VIL (Note 2)
Off-State Output Leakage VOUT = 0 V, VCC = Max
Current LOW VIN = VIH or VIL (Note 2)
ISC Output Short-Circuit Current VOUT = 0.5 V, V CC = Max (Note 3) –30 –160 mA
ICC Supply Current VCC = 3.3 V, TA = 25°CmA
(Typical) (Note 4) mA
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of I
IL
and I
OZL
(or I
IH
and I
OZH
).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
V
OUT
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded,
enabled, and reset.
Input LOW Leakage Current
IIL
µA
µA
10
–10
IOZH
IOZL
f = 0 MHz
f = 25 MHz 2
60
13MACHLV210-15/20 (Com’l)
CAPACITANCE (Note 1)
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance VCC = 3.3 V, TA = 25°C, f = 1 MHz 6 pF
COUT Output Capacitance 8pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol Parameter Description Min Max Min Max Unit
tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) 15 20 ns
10 14 ns
11 15 ns
tHRegister Data Hold Time 0 0 ns
tCO Clock to Output (Note 3) 10 12 ns
tWL Clock 5 7 ns
tWH Width 6 8 ns
50 38.5 MHz
47.6 37 MHz
fMAX 66.6 50 MHz
62.5 47.6 MHz
90.9 66.7 MHz
tSL Setup Time from Input, I/O, or Feedback to Gate 10 14 ns
tHL Latch Data Hold Time 0 0 ns
tGO Gate to Output (Note 3) 11 15 ns
tGWL Gate Width LOW 5 7 ns
tPDL Input, I/O, or Feedback to Output Through 17 23 ns
tSIR Input Register Setup Time 2.5 3 ns
tHIR Input Register Hold Time 1.5 3 ns
tICO Input Register Clock to Combinatorial Output 18 24 ns
tICS Input Register Clock to Output Register Setup 13 27 ns
14 20 ns
tWICL Input Register 5 7 ns
tWICH Clock Width 6 8 ns
fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH) 90.9 66.7 MHz
tSIL Input Latch Setup Time 2.5 3 ns
tHIL Input Latch Hold Time 1.5 2 ns
tIGO Input Latch Gate to Combinatorial Output 19 25 ns
tIGOL Input Latch Gate to Output Through Transparent Output Latch 22 29 ns
tSLL Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate 12 16 ns
tIGS Input Latch Gate to Output Latch Setup 14 18 ns
Maximum
Frequency
(Note 1)
Setup Time from Input, I/O,
or Feedback to Clock
External Feedback 1/(t S + t CO)
Internal Feedback (fCNT)
No Feedback 1/(tWL + tWH)
-15 -20
tSD-type
T-type
LOW
HIGH
D-type
T-type
D-type
T-type
D-type
T-type
LOW
HIGH
14 MACHLV210-15/20 (Com’l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
(continued)
Parameter
Symbol Parameter Description Min Max Min Max Unit
tWIGL Input Latch Gate Width LOW 5 7 ns
tPDLL Input, I/O, or Feedback to Output Through Transparent 21 28 ns
Input and Output Latches
tAR Asynchronous Reset to Registered or Latched Output 20 26 ns
tARW Asynchronous Reset Width (Note 1) 15 20 ns
tARR Asynchronous Reset Recovery Time (Note 1) 15 20 ns
tAP Asynchronous Preset to Registered or Latched Output 20 26 ns
tAPW Asynchronous Preset Width (Note 1) 15 20 ns
tAPR Asynchronous Preset Recovery Time (Note 1) 15 20 ns
tEA Input, I/O, or Feedback to Output Enable (Note 3) 15 20 ns
tER Input, I/O, or Feedback to Output Disable (Note 3) 15 20 ns
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
2. See Switching Test Circuit for test conditions.
3. Parameters measured with 16 outputs switching.
-15 -20
15MACHLV210-18/24 (Ind)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature –65°C to +150°C. . . . . . . . . . .
Ambient Temperature
with Power Applied –55°C to +125°C. . . . . . . . . . . . .
Supply Voltage with
Respect to Ground –0.5 V to +5.0 V. . . . . . . . . . . . .
DC Input Voltage –0.5 V to VCC + 0.5 V. . . . . . . . . . .
DC Output or
I/O Pin Voltage –0.5 V to VCC + 0.5 V. . . . . . . . . . . .
Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . . .
Latchup Current (TA = –40°C to +85°C) 200 mA. . . .
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.
INDUSTRIAL OPERATING RANGES
Temperature (TA) Operating
in Free Air –40°C to +85°C. . . . . . . . . . . . . . . . . . . . .
Supply Voltage (VCC) with
Respect to Ground +3.0 V to +3.6 V. . . . . . . . . . . . . .
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit
VOH Output HIGH Voltage I OH = –2 mA, VCC = Min 2.4 V
VIN = VIH or VIL
VOL Output LOW Voltage IOL = 2 mA, V CC = Min 0.4 V
VIN = VIH or VIL
VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V
Voltage for all Inputs (Note 1)
VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V
Voltage for all Inputs (Note 1)
IIH Input HIGH Leakage Current VIN = 3.6 V, V CC = Max (Note 2) 10 µA
VIN = 0 V, VCC = Max (Note 2) –10 µA
Off-State Output Leakage VOUT = 3.6 V, VCC = Max
Current HIGH VIN = VIH or VIL (Note 2)
Off-State Output Leakage VOUT = 0 V, VCC = Max
Current LOW VIN = VIH or VIL (Note 2)
ISC Output Short-Circuit Current VOUT = 0.5 V, V CC = Max (Note 3) –30 –160 mA
Supply Current VCC = 3.3 V, TA = 25°CmA
(Typical) (Note 4) mA
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of I
IL
and I
OZL
(or I
IH
and I
OZH
).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
V
OUT
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded,
enabled, and reset.
Input LOW Leakage Current
IIL
µA
µA
10
–10
IOZH
IOZL
ICC f = 0 MHz
f = 25 MHz 2
60
16 MACHLV210-18/24 (Ind)
CAPACITANCE (Note 1)
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance VCC = 3.3 V, TA = 25°C, f = 1 MHz 6 pF
COUT Output Capacitance 8pF
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
Parameter
Symbol Parameter Description Min Max Min Max Unit
tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) 18 24 ns
12 17 ns
13.5 18 ns
tHRegister Data Hold Time 0 0 ns
tCO Clock to Output (Note 3) 12 14.5 ns
tWL Clock 6 8.5 ns
tWH Width 7.5 10 ns
40 30.5 MHz
38 29.5 MHz
fMAX 53 40 MHz
50 38 MHz
72.5 53 MHz
tSL Setup Time from Input, I/O, or Feedback to Gate 12 17 ns
tHL Latch Data Hold Time 0 0 ns
tGO Gate to Output (Note 3) 13.5 18 ns
tGWL Gate Width LOW 6 8.5 ns
tPDL Input, I/O, or Feedback to Output Through Latch 20.5 28 ns
tSIR Input Register Setup Time 3 4 ns
tHIR Input Register Hold Time 2.5 4 ns
tICO Input Register Clock to Combinatorial Output 22 29 ns
tICS Input Register Clock to Output Register Setup 16 32.5 ns
17 24 ns
tWICL Input Register 6 8.5 ns
tWICH Clock Width 7.5 10 ns
fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH) 72.5 53 MHz
tSIL Input Latch Setup Time 3 4 ns
tHIL Input Latch Hold Time 2.5 3 ns
tIGO Input Latch Gate to Combinatorial Output 23 30 ns
tIGOL Input Latch Gate to Output Through Transparent Output Latch 26.5 34.5 ns
tSLL Setup Time from Input, I/O, or Feedback Through 14.5 19.5 ns
Transparent Input Latch to Output Latch Gate
tIGS Input Latch Gate to Output Latch Setup 17 22 ns
Maximum
Frequency
(Note 1)
Setup Time from Input, I/O,
or Feedback to Clock
External Feedback 1/(t S + t CO)
Internal Feedback (fCNT)
No Feedback 1/(tWL + tWH)
-18 -24
tSD-type
T-type
LOW
HIGH
D-type
T-type
D-type
T-type
D-type
T-type
LOW
HIGH
17MACHLV210-18/24 (Ind)
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
(continued)
Parameter
Symbol Parameter Description Min Max Min Max Unit
tWIGL Input Latch Gate Width LOW 6 8.5 ns
tPDLL Input, I/O, or Feedback to Output Through Transparent 25.5 34 ns
Input and Output Latches
tAR Asynchronous Reset to Registered or Latched Output 24 31.5 ns
tARW Asynchronous Reset Width (Note 1) 18 24 ns
tARR Asynchronous Reset Recovery Time (Note 1) 18 24 ns
tAP Asynchronous Preset to Registered or Latched Output 24 31.5 ns
tAPW Asynchronous Preset Width (Note 1) 18 24 ns
tAPR Asynchronous Preset Recovery Time (Note 1) 18 24 ns
tEA Input, I/O, or Feedback to Output Enable (Note 3) 18 24 ns
tER Input, I/O, or Feedback to Output Disable (Note 3) 18 24 ns
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
2.See Switching Test Circuit at the back of this Data Sheet for test conditions.
3. Parameters measured with 16 outputs switching.
-18 -24
18 MACHLV210-12/15/20
KEYS TO SWITCHING WAVEFORMS
KS000010-PAL
Must be
Steady
May
Change
from H to L
May
Change
from L to H
Does Not
Apply
Don’t Care;
Any Change
Permitted
Will be
Steady
Will be
Changing
from H to L
Will be
Changing
from L to H
Changing,
State
Unknown
Center
Line is High-
Impedance
“Off” State
WAVEFORM INPUTS OUTPUTS
SWITCHING TEST CIRCUIT*
Measured
Specification S1CLR1R2Output Value
tPD, tCO Closed 1.5 V
tEA Z → H: Open 30 pF 1.5 V
Z → L: Closed 1.6 K 1.6 K
tER H →Z: Open 5 pF H →Z: VOH – 0.5 V
L →Z: Closed L →Z: VOL + 0.5 V
Commercial
CL
Output
R1
R2
S1
Test Point
3.3 V
17908D-4
*Switching several outputs simultaneously should be avoided for accurate measurement.
19MACHLV210-12/15/20
TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS
VCC = 3.3 V, TA = 25°C
Input
20
–40
–60
–80
–2 –1 123
Output, HIGH
II (mA)
VI (V)
–20
IOH (mA)
VOH (V)
25
–50
–75
–100
–3 –2 –1
123
–25
–125
–150
45
45
–100
–0.8 –0.6 –0.4 .2–0.2–1.0
17908D-5
Output, LOW
.4 .6 1.0.8
60
40
20
–20
–40
80
–60
–80
IOL (mA)
VOL (V)
17908D-6
17908D-7
20 MACHLV210-12/15/20
TYPICAL ICC CHARACTERISTICS
VCC = 3.3 V, TA = 25°C
17908D-8
150
125
100
75
50
25
00 1020304050 6070
MACHLV210
ICC (mA)
Frequency (MHz)
The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of
being loaded, enabled, and reset.
Maximum frequency shown uses internal feedback and a D-type register.
21MACHLV210-12/15/20
ENDURANCE CHARACTERISTICS
The MACHLV210 is manufactured using our ad-
vanced Electrically Erasable process. This technology
uses an EE cell to replace the fuse link used in bipolar
parts. As a result, the device can be erased and
reprogrammed, a feature which allows 100% testing at
the factory.
Parameter
Symbol Parameter Description Test Conditions Min Unit
Max Storage 10 Years
Temperature
Max Operating 20 Years
Temperature
N Max Reprogramming Cycles Normal Programming 100 Cycles
Conditions
tDR Min Pattern Data Retention Time
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Program/Verify
Circuitry
Input
Output
Preload
Circuitry
17908D-9
ESD
Protection
Feedback
Input
VCC
VCC
>50 kΩ
>50 kΩ
22 MACHLV210-12/15/20
TYPICAL THERMAL CHARACTERISTICS
Measured at 25°C ambient. These parameters are not tested.
Parameter
Symbol Parameter Description PLCC Units
θjc Thermal impedance, junction to case 15 °C/W
θja Thermal impedance, junction to ambient 40 °C/W
θjma Thermal impedance, junction to ambient with air flow 200 lfpm air 36 °C/W
400 lfpm air 33 °C/W
600 lfpm air 31 °C/W
800 lfpm air 29 °C/W
Plastic
θ
jc Considerations
The data listed for plastic
θ
jc are for reference only and are not recommended for use in calculating junction temperatures. The
heat-flow paths in plastic-encapsulated devices are complex, making the
θ
jc measurement relative to a specific location on the
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the
package. Furthermore,
θ
jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a
constant temperature. Therefore, the measurements can only be used in a similar environment.
Typ
23MACHLV210-12/15/20
SWITCHING WAVEFORMS
Notes:
1. V
T
= 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
tPD
Input, I/O, or
Feedback
Combinatorial
Output
VT
VT
Combinatorial Output
VT
Input, I/O,
or Feed-
back
Registered
Output
Registered Output
tS
tCO
VT
tH
VT
Clock
tWH
Clock
Clock Width
tWL
VT
Combinatorial
Output
Registered Input (MACH 2 and 4)
tSIR
tICO
VT
tHIR
VT
Input
Register
Clock
Registered
Input
Latched Output (MACH 2, 3, and 4)
Gate
Gate Width (MACH 2, 3, and 4)
tGWS
VT
VT
VT
VT
tICS
Input Register to Output Register Setup
(MACH 2 and 4)
Output
Register
Clock
Input
Register
Clock
Registered
Input
tPDL
Input, I/O, or
Feedback
Latched
Out
Gate
VT
tHL
tSL
tGO
VT
VT
17908D-10
17908D-11 17908D-12
17908D-13 17908D-14
17908D-15 17908D-16
24 MACHLV210-12/15/20
SWITCHING WAVEFORMS
Notes:
1. V
T
= 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
Latched Input (MACH 2 and 4)
Latched Input and Output
(MACH 2, 3, and 4)
Latched
In
Output
Latch Gate
Latched
Out
tSLL
Combinatorial
Output
Gate tHIL
tSIL
tIGO
Latched
In
tPDLL
tIGOL
tIGS
Input
Latch Gate
VT
VT
VT
VT
VT
VT
17908D-17
17908D-18
25MACHLV210-12/15/20
SWITCHING WAVEFORMS
tWICH
Clock
Input Register Clock Width
(MACH 2 and 4)
VT
tWICL
VT
VT
tARW
VT
tAR
Asynchronous Reset
Input, I/O, or
Feedback
Registered
Output
Clock
tARR
Asynchronous Preset
Registered
Output
Clock
VT
VT
Outputs
Output Disable/Enable
tER tEA
VOH - 0.5V
VOL + 0.5V
Notes:
1. V
T
= 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
Input, I/O,
or Feedback
VT
VT
Input, I/O, or
Feedback
tAPW
VT
tAP
tAPR
Input
Latch
Gate
Input Latch Gate Width
(MACH 2 and 4)
tWIGL
VT
17908D-19 17908D-20
17908D-21 17908D-22
17908D-23
26 MACHLV210-12/15/20
fMAX PARAMETERS
The parameter fMAX is the maximum clock rate at which
the device is guaranteed to operate. Because the flexi-
bility inherent in programmable logic devices offers a
choice of clocked flip-flop designs, fMAX is specified for
three types of synchronous designs.
The first type of design is a state machine with feedback
signals sent off-chip. This external feedback could go
back to the device inputs, or to a second device in a
multi-chip state machine. The slowest path defining the
period is the sum of the clock-to-output time and the in-
put setup time for the external signals (tS + tCO). The re-
ciprocal, fMAX, is the maximum frequency with external
feedback or in conjunction with an equivalent speed de-
vice. This fMAX is designated “fMAX external.”
The second type of design is a single-chip state ma-
chine with internal feedback only. In this case, flip-flop
inputs are defined by the device inputs and flip-flop out-
puts. Under these conditions, the period is limited by the
internal delay from the flip-flop outputs through the inter-
nal feedback and logic to the flip-flop inputs. This fMAX is
designated “fMAX internal”. A simple internal counter is a
good example of this type of design; therefore, this pa-
rameter is sometimes called “fCNT.”
The third type of design is a simple data path applica-
tion. In this case, input data is presented to the flip-flop
and clocked through; no feedback is employed. Under
these conditions, the period is limited by the sum of the
data setup time and the data hold time (tS + tH). However,
a lower limit for the period of each fMAX type is the mini-
mum clock period (tWH + tWL). Usually, this minimum
clock period determines the period for the third fMAX, des-
ignated “fMAX no feedback.”
For devices with input registers, one additional fMAX pa-
rameter is specified: fMAXIR. Because this involves no
feedback, it is calculated the same way as fMAX no feed-
back. The minimum period will be limited either by the
sum of the setup and hold times (tSIR + tHIR) or the sum of
the clock widths (tWICL + tWICH). The clock widths are nor-
mally the limiting parameters, so that fMAXIR is specified
as 1/(tWICL + tWICH). Note that if both input and output reg-
isters are use in the same path, the overall frequency will
be limited by tICS.
All frequencies except fMAX internal are calculated from
other measured AC parameters. fMAX internal is meas-
ured directly.
tHIR
tSIR
LOGIC REGISTER
tt
CLK
(SECOND
CHIP)
SCO
t
S
f
MAX External; 1/(tS + t CO)
LOGIC REGISTER
CLK
fMAX Internal (fCNT)
LOGIC REGISTER
t
CLK
S
fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL)
17908D-24
LOGIC
REGISTER
CLK
fMAXIR ; 1/(tSIR + tHIR) or 1/(tWICL + tWICH)
27MACHLV210-12/15/20
POWER-UP RESET
The MACH devices have been designed with the capa-
bility to reset during system power-up. Following power-
up, all flip-flops will be reset to LOW. The output state
will depend on the logic polarity. This feature provides
extra flexibility to the designer and is especially valuable
in simplifying state machine initialization. A timing dia-
gram and parameter table are shown below. Due to the
synchronous operation of the power-up reset and the
wide range of ways VCC can rise to its steady state, two
conditions are required to insure a valid power-up reset.
These conditions are:
1. The VCC rise must be monotonic.
2. Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter
Symbol Parameter Descriptions Max Unit
tPR Power-Up Reset Time 10 µs
tSInput or Feedback Setup Time
tWL Clock Width LOW
See
Switching
Characteristics
tPR
tWL
tS
4 V VCC
Power
Registered
Output
Clock
17908D-25
Power-Up Reset Waveform
28 MACHLV210-12/15/20
USING PRELOAD AND OBSERVABILITY
In order to be testable, a circuit must be both controllable
and observable. To achieve this, the MACH devices
incorporate register preload and observability.
In preload mode, each flip-flop in the MACH device can
be loaded from the I/O pins, in order to perform
functional testing of complex state machines. Register
preload makes it possible to run a series of tests from a
known starting state, or to load illegal states and test for
proper recovery. This ability to control the MACH
device’s internal state can shorten test sequences,
since it is easier to reach the state of interest.
The observability function makes it possible to see the
internal state of the buried registers during test by
overriding each register’s output enable and activating
the output buffer. The values stored in output and buried
registers can then be observed on the I/O pins. Without
this feature, a thorough functional test would be
impossible for any designs with buried registers.
While the implementation of the testability features is
fairly straightforward, care must be taken in certain
instances to insure valid testing.
One case involves asynchronous reset and preset. If the
MACH registers drive asynchronous reset or preset
lines and are preloaded in such a way that reset or
preset are asserted, the reset or preset may remove the
preloaded data. This is illustrated in Figure 2. Care
should be taken when planning functional tests, so that
states that will cause unexpected resets and presets are
not preloaded.
Another case to be aware of arises in testing combinato-
rial logic. When an output is configured as combinato-
rial, the observability feature forces the output into
registered mode. When this happens, all product terms
are forced to zero, which eliminates all combinatorial
data. For a straight combinatorial output, the correct
value will be restored after the preload or observe
function, and there will be no problem. If the function
implements a combinatorial latch, however, it relies on
feedback to hold the correct value, as shown in Figure 3.
As this value may change during the preload or observe
operation, you cannot count on the data being correct
after the operation. To insure valid testing in these
cases, outputs that are combinatorial latches should not
be tested immediately following a preload or observe
sequence, but should first be restored to a known state.
All MACH 2 devices support both preload and
observability.
Contact individual programming vendors in order to
verify programmer support.
AR
Figure 2. Preload/Reset Conflict
Q1
On
Off
Preload
Mode
Q2
AR
Preloaded
HIGH
D
Q
Q1
D
Q
AR
Preloaded
HIGH
Q2
17908D-26
Figure 3. Combinatorial Latch
Set
Reset
17908D-27
33MACHLV210-12/15/20
PHYSICAL DIMENSIONS*
PL 044
44-Pin Plastic Leaded Chip Carrier (measured in inches)
TOP VIEW
SEATING PLANE
.685
.695 .650
.656
Pin 1 I.D.
.685
.695
.650
.656
.026
.032 .050 REF
.042
.056
.062
.083
.013
.021
.590
.630
.500
REF
.009
.015
.165
.180
.090
.120 16-038-SQ
PL 044
DA78
6-28-94 ae
SIDE VIEW
*For reference only. BSC is an ANSI standard for Basic Space Centering.
