AS3930 Single Channel Low Frequency Wakeup Receiver General Description The AS3930 is a single-channel low power ASK receiver that is able to generate a wake-up upon detection of a data signal which uses a LF carrier frequency between 110 - 150 kHz. The integrated correlator can be used for detection of a programmable 16-bit wake-up pattern. The AS3930 provides a digital RSSI value, it supports a programmable data rate. The AS3930 offers a real-time clock (RTC), which is either derived from a crystal oscillator or the internal RC oscillator. The programmable features of AS3930 enable to optimize its settings for achieving a longer distance while retaining a reliable wake-up generation. The sensitivity level of AS3930 can be adjusted in presence of a strong field or in noisy environments. The device is available in a 16-pin TSSOP and a 16-LD QFN (4x4) package. Ordering Information and Content Guide appear at end of datasheet. Key Benefits & Features The benefits and features of AS3930, Single Channel Low Frequency Wakeup Receiver are listed below: Figure 1: Added Value of Using AS3930 Benefits Features Enables low power active tags Single channel ASK wake-up receiver Selectable carrier frequency Carrier frequency range 110 - 150 kHz Highly resistant to false wake-ups 16-bit programmable wake-up pattern Improved immunity to false wake-ups Supporting doubling of wake-up pattern Allows frequency only detection Wake-up without pattern detection selectable Improved range with best-in-class sensitivity Wake-up sensitivity 100VRMS (typ.) Adjustable range Sensitivity level adjustable Provides tracking of false wake-ups False wake-up counter Ensures wake-up in a noise environment Periodical forced wake-up supported (1s - 2h) Extended battery life Current consumption in listening mode 1.37 A (typ.) Flexible clock configuration RTC based 32 kHz XTAL, RC-OSC, or external clock ams Datasheet [v1-62] 2014-Nov-27 Page 1 Document Feedback AS3930 - General Description Benefits Features Operates from a 3V battery Operating supply range 2.4V - 3.6V (TA = 25C) Industrial temperature range Operation temperature range -40C to +85C Applications The AS3930, Single Channel Low Frequency Wakeup Receiver is ideal for Active RFID tags, real-time location systems, operator identification, access control, and wireless sensors. Figure 2: AS3930 Typical Application Diagram with Crystal Oscillator VCC CL CBAT VCC CS XIN TRANSMITTER TX Page 2 Document Feedback Transmitting Antenna XTAL XOUT DAT LF1P NC WAKE AS3930 SCL NC SDO LFN SDI VSS GND ams Datasheet [v1-62] 2014-Nov-27 AS3930 - General Description Figure 3: AS3930 Typical Application Diagram without Crystal Oscillator VCC VCC CS CBAT TRANSMITTER TX Transmitting Antenna XIN XOUT DAT LF1P WAKE AS3930 NC SCL NC SDO LFN SDI VSS GND Figure 4: AS3930 Typical Application Diagram with Clock from External Source VCC CBAT External Clock VCC CS R XIN C TX ams Datasheet [v1-62] 2014-Nov-27 Transmitting Antenna XOUT TRANSMITTER DAT LF1P NC AS3930 WAKE SCL NC SDO LFN SDI VSS GND Page 3 Document Feedback AS3930 - Pin Assignments Pin Assignments 16-pin TSSOP Figure 5: Pin Diagram (Top View) CS 1 16 NC SCL 2 15 DAT SDI 3 14 WAKE SDO 4 13 VSS VCC 5 12 XOUT GND 6 11 XIN NC 7 10 LFN NC 8 9 AS3930 LF1P Figure 6: Pin Description Pin Number Pin Name 1 CS 2 SCL 3 SDI 4 SDO 5 VCC Pin Type Description Chip select Digital input SDI interface clock SDI data input Digital output / tristate SDI data output (tristate when CS is low) Positive supply voltage Supply pad 6 GND 7 NC 8 NC 9 LF1P 10 LFN Negative supply voltage - Not Connected Input antenna Antenna ground Analog I/O 11 XIN Crystal oscillator input 12 XOUT Crystal oscillator output 13 VSS 14 WAKE Supply pad Substrate Wake-up output IRQ Digital output 15 DAT 16 NC Page 4 Document Feedback Data output - Not connected ams Datasheet [v1-62] 2014-Nov-27 AS3930 - Pin Assignments QFN 4x4 16 LD Figure 7: Pin Diagram (Top View) VSS Figure 8: Pin Description Pin Number Pin Name Pin Type Description 1 NC - 2 NC - 3 LF1P Input antenna 4 LFN Antenna ground 5 XIN 6 XOUT 7 VSS 8 WAKE Not connected Analog I/O Crystal oscillator input Crystal oscillator output Supply pad Substrate Wake-up output IRQ Digital output 9 DAT 10 NC 11 CS 12 SCL 13 SDI 14 SDO 15 VCC Data output - Not connected Chip select Digital input SDI interface clock SDI data input Digital output / tristate SDI data output (tristate when CS is low) Positive supply voltage Supply pad 16 ams Datasheet [v1-62] 2014-Nov-27 GND Negative supply voltage Page 5 Document Feedback AS3930 - Absolute Maximum Ratings Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings Figure 9: Absolute Maximum Ratings Parameter Min Max Unit Note Electrical Parameters DC supply voltage (VDD) -0.5 5 V Input pin voltage (VIN) -0.5 5 V Input current (latch up immunity) (ISOURCE) -100 100 mA Norm: Jedec 78 Electrostatic Discharge Electrostatic discharge (ESD) 2 kV Norm: MIL 883 E method 3015 (HBM) Continuous Power Dissipation Total power dissipation (all supplies and outputs) (Pt) 0.07 mW Temperature Ranges and Storage Conditions Storage temperature (Tstrg) -65 150 Package body temperature (Tbody) Humidity non-condensing Moisture Sensitivity Level (MSL) Page 6 Document Feedback 5 3 C 260 C 85 % Norm: IPC/JEDEC J-STD-020 The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020 "Moisture/Reflow Sensitivity Classification for Non-hermetic Solid State Surface Mount Devices". Represents a maximum floor life time of 168h ams Datasheet [v1-62] 2014-Nov-27 AS3930 - Electrical Characteristics Electrical Characteristics Figure 10: Electrical Characteristics Symbol Parameter Conditions Min Typ Max Unit Operating Conditions VDD Positive supply voltage 2.4 3.6 V VSS Negative supply voltage 0 0 V TAMB Ambient temperature -40 85 C DC/AC Characteristics for Digital Inputs and Outputs CMOS Input VIH High level input voltage 0.58* VDD 0.7* VDD 0.83* VDD V VIL Low level input voltage 0.125* VDD 0.2* VDD 0.3* VDD V ILEAK Input leakage current 100 nA CMOS Output VOH VDD 0.4 High level output voltage V With a load current of 1mA VOL Low level output voltage CL Capacitive load For a clock frequency of 1 MHz VSS + 0.4 V 400 pF Tristate CMOS Output VOH VDD 0.4 High level output voltage V With a load current of 1mA VOL Low level output voltage IOZ Tristate leakage current ams Datasheet [v1-62] 2014-Nov-27 To VDD and VSS VSS + 0.4 V 100 nA Page 7 Document Feedback AS3930 - Electrical Characteristics Figure 11: Electrical System Specifications Symbol Parameter Conditions Min Typ Max Unit Input Characteristics RIN Input Impedance Fmin Fmax In case no antenna damper is set (R1<4>=0) 2 M Minimum Input Frequency 110 kHz Maximum Input Frequency 150 kHz Current Consumption IPWD Power Down Mode 400 nA ICHRC Current Consumption in standard listening mode with channel active all the time and RC-oscillator as RTC 2.7 A ICHOORC Current Consumption in ON/OFF mode and RC-oscillator as RTC ICHXT Current Consumption in standard listening mode and crystal oscillator as RTC IDATA Current Consumption in Preamble detection / Pattern correlation / Data receiving mode (RC-oscillator) 11% Duty Cycle 1.37 50% Duty Cycle 2 A With 125 kHz carrier frequency and 1kbps data-rate. No load on the output pins. 3.5 5.9 A 5.3 9 A Input Sensitivity SENS Input Sensitivity With 125 kHz carrier frequency, chip in default mode, 4 half bits burst + 4 symbols preamble and single preamble detection 100 Vrms 250 s 32.768 kHz Channel Settling Time TSAMP Amplifier settling time Crystal Oscillator FXTAL Frequency Crystal dependent TXTAL Start-up Time IXTAL Current consumption Page 8 Document Feedback 1 1 s A ams Datasheet [v1-62] 2014-Nov-27 AS3930 - Electrical Characteristics Symbol Parameter Conditions Min Typ Max Unit External Clock Source IEXTCL Current consumption A 1 RC Oscillator (1) FRCNCAL If no calibration is performed 27 32.768 42 kHz FRCCAL32 If calibration with 32.768 kHz reference signal is performed 31 32.768 34.5 kHz Frequency FRCCALMAX Maximum achievable frequency after calibration 35 kHz FRCCALMIN Minimum achievable frequency after calibration 30 kHz TRC Start-up time TCALRC Calibration time IRC Current consumption From RC enable (R1<0> = 0) 200 1 s 65 Periods of reference clock nA Note(s) and/or Footnote(s): 1. RC calibration is only successful after start-up is completed. ams Datasheet [v1-62] 2014-Nov-27 Page 9 Document Feedback AS3930 - Typical Operating Characteristics Typical Operating Characteristics Figure 12: Sensitivity over Voltage and Temperature 120 95 oC 100 27 oC -40 oC Sensitivity [Vrms] 80 60 40 20 0 2.4 3 3.6 Supply Voltage [V] Figure 13: Sensitivity over RSSI 1000000 VIN = 2.4V 100000 Input Voltage [Vrms] VIN = 1.5V 10000 VIN = 1.0V 1000 100 10 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 RSSI [dB] Page 10 Document Feedback ams Datasheet [v1-62] 2014-Nov-27 AS3930 - Typical Operating Characteristics Figure 14: RC-Oscillator Frequency over Voltage (calibr.) 34.5 RC-OSC Frequency [KHz] 34 33.5 33 32.5 32 31.5 31 2.4 2.6 2.8 3 3.2 3.4 3.6 Supply Voltage [V] Figure 15: RC-Oscillator Frequency over Temperature (calibr.) 34.5 RC-OSC Frequency [KHz] 34 33.5 33 32.5 32 31.5 31 -36 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Operating Temperature [oC] ams Datasheet [v1-62] 2014-Nov-27 Page 11 Document Feedback AS3930 - Detailed Description The AS3930 is a one-dimensional low power low-frequency wake-up receiver. The AS3930 is capable of detecting the presence of an inductive coupled carrier and extract the envelope of the ON-OFF-Keying (OOK) modulated carrier. In case the carrier is Manchester coded, then the clock is recovered from the transmitted signal and the data can be correlated with a programmed pattern. If the detected pattern corresponds to the stored one, then a wake-up signal (IRQ) is risen up. The pattern correlation can be bypassed in which case the wake-up detection is based only on the frequency detection. Detailed Description The AS3930 is made up of a single receiving channel, one envelop detector, one data correlator, 8 programmable registers with the main logic and a real time clock. The digital logic can be accessed by an SDI. The real time clock can be based on a crystal or on an internal RC. If the internal RC oscillator is used, a calibration procedure can be performed to improve its accuracy. Figure 16: Block Diagram of LF Wake-up Receiver AS3930 AS3930, 1-D LF Wakeup Receiver IRQ Wakeup SCL Main Logic SDI SDI SDO RSSI LF1P CS Channel Amplifier1 Envelope Detector / Data Slicer Correlator DAT I/V Bias Xtal RTC RC RTC LFN VCC Page 12 Document Feedback GND XIN XOUT ams Datasheet [v1-62] 2014-Nov-27 AS3930 - Detailed Description AS3930 needs the following external components: * Power supply capacitor - CBAT - 100 nF. * 32.768 kHz crystal with its two pulling capacitors - XTAL and CL - (it is possible to omit these components if the internal RC oscillator is used instead of the crystal oscillator). * Input LC resonator. In case the internal RC-oscillator is used (no crystal oscillator is mounted), the pin XIN has to be connected to the supply, while pin XOUT should stay floating. Application diagrams with and without crystal are shown in Figure 2 and Figure 3. Operating Modes Power Down Mode In Power Down Mode AS3930 is completely switched OFF. The typical current consumption is 400 nA. Listening Mode In listening mode only the channel amplifier and the RTC are running. In this mode the system detects the presence of a carrier. In case the carrier is detected, the RSSI can be displayed. In this mode it is possible to distinguish the following three sub modes: Standard Listening Mode The channel amplifier that is capable of detecting the presence of the carrier frequency, is active all the time. ON/OFF Mode (Low Power mode ) The channel amplifier is active for one millisecond after which it is switched OFF. The OFF-time is programmable (see R4<7:6>). Figure 17: ON/OFF Mode Channel t0 t0 + 1ms t0 + T t0 + T + 1ms t0 + 2T Time Presence of Carrier Time ams Datasheet [v1-62] 2014-Nov-27 Page 13 Document Feedback AS3930 - Detailed Description Further, for both sub modes, it is possible to enable a feature called Artificial Wake-up. If the Artificial Wake-up is enabled, then the AS3930 produces an interrupt after a certain time regardless of whether any activity is detected on the input. The period of the Artificial Wake-up is defined in the register R8<2:0>. The user can distinguish between Artificial Wake-up and Wake-up based on the field detection (frequency or pattern detection) since the Artificial Wake-up interrupt lasts only 128s. With this interrupt the microcontroller (C) can get feedback on the surrounding environment (e.g. read the false wake-up register R13<7:0>) and/or take actions in order to change the setup. Preamble Detection / Pattern Correlation The preamble detection and pattern correlation are only considered for the wake-up when the data correlator function is enabled (see R1<1>). The correlator searches first for preamble frequency (constant frequency of Manchester clock defined according to bit-rate transmission, see Figure 36) and then for data pattern. If the pattern is matched, then the wake-up interrupt is displayed on the WAKE output and the chip goes in data receiving mode. If the pattern fails, then the internal wake-up is terminated and no IRQ is produced. Data Receiving After a successful wake-up the chip enters the data receiving mode. In this mode the chip can be retained a normal OOK receiver. The received data are streamed out on the pin DAT. It is possible to put the chip back to listening mode either with a direct command (CLEAR_WAKE see Figure 24) or by using the timeout feature. This feature automatically sets the chip back to listening mode after a certain time R7<7:5>. Page 14 Document Feedback ams Datasheet [v1-62] 2014-Nov-27 AS3930 - Detailed Description System and Block Specification Main Logic and SDI Figure 18: Register Table 7 6 R0 N.A.. R1 ABS_HY R2 S_ABSH R3 HY_20m R4 5 4 3 ON_OFF AGC_TLIM AGC_UD ATT_ON N.A. HY_POS R_VAL<1:0> T_OUT<2:0> EN_WPAT EN_RTC S_WU1<1:0> T_HBIT<4:0> N.A. T_AUTO<2:0> N.A. Reserved N.A.. RSSI1<4:0> R11 N.A.. R12 N.A.. R13 F_WAKE ams Datasheet [v1-62] 2014-Nov-27 PWD GR<3:0> TS1<7:0> R10 EN_A FS_ENV<2:0> R6 R9 EN_PAT2 FS_SLC<2:0> TS2<7:0> R8 0 Reserved R5 R7 1 Reserved W_PAT_T<1:0> T_OFF<1:0> 2 Page 15 Document Feedback Register Table Description and Default Values Figure 19: Description and Default Values of Registers Register Name Type Default Value Description R0<5> ON_OFF R/W 0 ON/OFF operation mode. (Duty-cycle defined in the register R4<7:6> R0<4> MUX_123 R/W 0 Reserved (it is not allowed to set this bit to 1) R0<3> Reserved 1 Reserved R0<2> Reserved 1 Reserved R0<1> EN_A R/W 1 Channel enable R0<0> PWD R/W 0 Power down R1<7> ABS_HY R/W 0 Data slicer absolute reference R1<6> AGC_TLIM R/W 0 AGC acting only on the first carrier burst R1<5> AGC_UD R/W 1 AGC operating in both direction (up-down) R1<4> ATT_ON R/W 0 Antenna damper enable R1<3> Reserved 0 Reserved R1<2> EN_PAT2 R/W 0 Double wake-up pattern correlation R1<1> EN_WPAT R/W 1 Data correlation enable R1<0> EN_RTC R/W 1 Crystal oscillator enable R2<7> S_ABSH R/W 0 Data slicer threshold reduction R2<6:5> W_PAT R/W 00 Pattern correlation tolerance (see Figure 37) R2<4:2> Reserved 000 Reserved R2<1:0> S_WU1 R/W 00 Tolerance setting for the stage wake-up (see Figure 31) R3<7> HY_20m R/W 0 Data slicer hysteresis if HY_20m = 0 then comparator hysteresis = 40mV if HY_20m = 1 then comparator hysteresis = 20mV R3<6> HY_POS R/W 0 Data slicer hysteresis on both edges (HY_POS = 0 hysteresis on both edges; HY_POS = 1 hysteresis only on positive edges) R3<5:3> FS_SCL R/W 100 Data slicer time constant (see Figure 35) R3<2:0> FS_ENV R/W 000 Envelop detector time constant (see Figure 34) Page 16 Document Feedback ams Datasheet [v1-62] 2014-Nov-27 AS3930 - Detailed Description Register Name Type Default Value Description OFF time in ON/OFF operation mode R4<7:6> T_OFF R/W 00 T_OFF=00 1ms T_OFF=01 2ms T_OFF=10 4ms T_OFF=11 8ms R4<5:4> D_RES R/W 01 Antenna damping resistor (see Figure 33) R4<3:0> GR R/W 0000 R5<7:0> TS2 R/W 01101001 2nd Byte of wake-up pattern R6<7:0> TS1 R/W 10010110 1st Byte of wake-up pattern R7<7:5> T_OUT R/W 000 R7<4:0> T_HBIT R/W 01011 Gain reduction (see Figure 32) Automatic time-out (see Figure 38) Bit rate definition (see Figure 36) Artificial wake-up R8<2:0> T_AUTO R9<6:0> Reserved R10<4:0> RSSI1 R/W 000 000000 T_AUTO=000 No artificial wake-up T_AUTO=001 1 sec T_AUTO=010 5 sec T_AUTO=011 20 sec T_AUTO=100 2 min T_AUTO=101 15min T_AUTO=110 1 hour T_AUTO=111 2 hour Reserved R RSSI channel R11<4:0> R N.A. R12<4:0> R N.A. R False wake-up register R13<7:0> F_WAK ams Datasheet [v1-62] 2014-Nov-27 Page 17 Document Feedback AS3930 - Detailed Description Serial Data Interface (SDI) This 4-wires interface is used by the Microcontroller (C) to program the AS3930. The maximum clock frequency of the SDI is 2MHz. Figure 20: Serial Data Interface (SDI) pins Name Signal Signal Level Description CS Digital Input with pull down CMOS Chip Select SDI Digital Input with pull down CMOS Serial Data input for writing registers, data to transmit and/or writing addresses to select readable register SDO Digital Output CMOS Serial Data output for received data or read value of selected registers SCLK Digital Input with pull down CMOS Clock for serial data read and write Note(s): SDO is set to tristate if CS is low. In this way more than one device can communicate on the same SDO bus. SDI Command Structure. To program the SDI the CS signal has to go high. A SDI command is made up by a two bytes serial command and the data is sampled on the falling edge of SCLK. Figure 21 shows how the command looks like, from the MSB (B15) to LSB (B0). The command stream has to be sent to the SDI from the MSB (B15) to the LSB (B0). Figure 21: SDI Command Structure Mode B15 B14 Register address / Direct Command B13 B12 B11 B10 B9 B8 Register Data B7 B6 B5 B3 B2 B1 B0 The first two bits (B15 and B14) define the operating mode. There are three modes available (write, read, direct command) plus one spare (not used), as shown in Figure 22. Figure 22: Bits B15, B14 Page 18 Document Feedback B15 B14 Mode 0 0 WRITE 0 1 READ 1 0 NOT ALLOWED 1 1 DIRECT COMMAND ams Datasheet [v1-62] 2014-Nov-27 In case a write or read command happens the next 6 bits (B13 to B8) define the register address which has to be written respectively read, as shown in Figure 23. Figure 23: Bits B13-B8 B13 B12 B11 B10 B9 B8 Read/Write register 0 0 0 0 0 0 R0 0 0 0 0 0 1 R1 0 0 0 0 1 0 R2 0 0 0 0 1 1 R3 0 0 0 1 0 0 R4 0 0 0 1 0 1 R5 0 0 0 1 1 0 R6 0 0 0 1 1 1 R7 0 0 1 0 0 0 R8 0 0 1 0 0 1 R9 0 0 1 0 1 0 R10 0 0 1 0 1 1 R11 0 0 1 1 0 0 R12 0 0 1 1 0 1 R13 The last 8 bits are the data that has to be written respectively read. A CS toggle high-low-high terminates the command mode. If a direct command is sent (B15-B14=11) the bits from B13 to B8 defines the direct command while the last 8 bits are omitted. Figure 24 shows all possible direct commands: Figure 24: List of Direct Commands COMMAND_MODE B13 B12 B11 B10 B9 B8 clear_wake 0 0 0 0 0 0 reset_RSSI 0 0 0 0 0 1 trim_osc 0 0 0 0 1 0 clear_false 0 0 0 0 1 1 preset_default 0 0 0 1 0 0 ams Datasheet [v1-62] 2014-Nov-27 Page 19 Document Feedback AS3930 - Detailed Description All direct commands are explained below: * clear_wake: Clears the wake state of the chip. In case the chip has woken up (WAKE pin is high) the chip is set back to listening mode. * reset_RSSI: Resets the RSSI measurement. * trim_osc: Starts the trimming procedure of the internal RC oscillator (see Figure 45). * clear_false: Resets the false wake-up register (R13<7:0>=00). * preset_default: Sets all register in the default mode, as shown in Figure 19. Note(s): In order to get the AS3930 work properly after sending the preset_default direct command, it is mandatory to write R0<3>=0 and R0<2>=0. Writing of Data to Addressable Registers (WRITE Mode). The SDI is sampled at the falling edge of SCLK (as shown in the following diagrams). A CS toggling high-low-high indicates the end of the WRITE command after register has been written. The following example shows a write command. Figure 25: Writing of a Single Byte (falling edge sampling) CS SCLK SDI X 0 0 Two leading Zeros indicate WRITE Mode A5 A4 A3 SCLK rising edge Data is transfered from C A2 A1 A0 D7 D6 D5 D4 D3 SCLK falling edge Data is sampled D2 D1 X D0 Data is moved to Address A5-A0 CS falling edge signals end of WRITE Mode Figure 26: Writing of Register Data with Auto-incrementing Address CS SCLK SDI A A A A A D D D D D D D D D D D D D D D D D D X 0 0 A 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 Two leading Zeros indicate WRITE Mode Page 20 Document Feedback Data is moved to Address <A5-A0 > Data is moved to Address <A5-A0 > + 1 D D D D D D D D D D 1 0 7 6 5 4 3 2 1 0 Data is moved to Address <A5-A0 > + (n-1) Data is moved to Address <A5-A0 > + n X CS falling edge signals end of WRITE Mode ams Datasheet [v1-62] 2014-Nov-27 AS3930 - Detailed Description Reading of Data from Addressable Registers (READ Mode). Once the address has been sent through SDI, the data can be fed through the SDO pin out to the microcontroller. A CS LOW toggling high-low-high has to be performed after finishing the read mode session, in order to indicate the end of the READ command and prepare the Interface to the next command control Byte. To transfer bytes from consecutive addresses, SDI master has to keep the CS signal high and the SCLK clock has to be active as long as data need to be read. Figure 27: Reading of Single Register Byte CS SCLK SDI X 0 1 A5 SDO A4 A3 A2 A1 X D7 SCLK rising edge Data is transfered from C 01 pattern indicates READ Mode X A0 SCLK falling edge Data is sampled D6 D5 SCLK rising edge Data is moved from Address <A5-A0> D4 D3 D2 D1 D0 X CS falling edge signals end of READ Mode SCLK falling edge Data is transfered to C Figure 28: Send Direct COMMAND Byte CS SCLK SDI X 1 1 Two leading ONE indicate COMMAND Mode ams Datasheet [v1-62] 2014-Nov-27 C5 C4 C3 SCLK rising edge Data is transfered from C C2 C1 SCLK falling edge Data is sampled C0 X CS falling edge signals the end of COMMAND Mode Page 21 Document Feedback AS3930 - Detailed Description SDI Timing Figure 29: SDI Timing Parameters Symbol Parameter Min Typ Max Units TCSCLK Time CS to Sampling Data 500 ns TDCLK Time Data to Sampling Data 300 ns THCL SCLK High Time 200 ns TCLK SCLK period 500 ns TCLKCS Time Sampling Data to CS down 500 ns TCST CS Toggling time 500 ns Figure 30: SDI Timing Diagram TCST CS SPI SCLK SCL t TCSCLK TDCLK t THCL TCLKCS t TCLK Channel Amplifier and Frequency Detector The channel amplifier consists of a variable gain amplifier (VGA), an automatic gain control, and a frequency detector. The latter detects the presence of a carrier. As soon as the carrier is detected the AGC is enabled, the gain of the VGA is reduced and set to the right value and the RSSI can be displayed. Page 22 Document Feedback ams Datasheet [v1-62] 2014-Nov-27 AS3930 - Detailed Description Frequency Detector / AGC The frequency detection uses the RTC as time base. In case the internal RC oscillator is used as RTC, it must be calibrated, but the calibration is guaranteed for a 32.768 kHz crystal oscillator only. The frequency detection criteria can be tighter or more relaxed according to the setup described in R2<1:0> (see Figure 31). Figure 31: Tolerance Settings for Wake-up R2<1> R2<0> Tolerance 0 0 Relaxed 0 1 Tighter (Medium) 1 0 Stringent 1 1 Reserved The AGC can operate in two modes: * AGC down only (R1<5>=0) * AGC up and down (R1<5>=1) As soon as the AGC starts to operate, the gain in the VGA is set to maximum. If the AGC down only mode is selected, the AGC can only decrease the gain. Since the RSSI is directly derived from the VGA gain, the system holds the RSSI peak. When the AGC up and down mode is selected, the RSSI can follow the input signal strength variation in both directions. Regardless which AGC operation mode is used, the AGC needs maximum 35 carrier periods to settle. The RSSI is stored in the register R10<4:0>. Both AGC modes (only down or down and up) can also operate with time limitation. This option allows AGC operation only in time slot of 256s following the internal wake-up. Then the AGC (RSSI) is frozen till the wake-up or RSSI reset occurs. The RSSI is reset either with the direct command 'clear_wakeup' or 'reset_RSSI'. The 'reset_RSSI' command resets only the AGC setting but does not terminate wake-up condition. This means that if the signal is still present the new AGC setting (RSSI) will appear not later than 300s (35 LF carrier periods) after the command was received. The AGC setting is reset if for duration of 3 Manchester half symbols no carrier is detected. If the wake-up IRQ is cleared the chip will go back to listening mode. In case the maximum amplification at the beginning is a drawback (e.g. in noisy environment) it is possible to set a smaller starting gain on the amplifier Figure 32. In this way it is possible to reduce the false frequency detection. ams Datasheet [v1-62] 2014-Nov-27 Page 23 Document Feedback AS3930 - Detailed Description Figure 32: Bit Setting of Gain Reduction R4<3> R4<2> R4<1> R4<0> Gain Reduction 0 0 0 0 No gain reduction 0 0 0 1 N.A.. 0 0 1 0 or 1 N.A.. 0 1 0 0 or 1 -4dB 0 1 1 0 or 1 -8dB 1 0 0 0 or 1 -12dB 1 0 1 0 or 1 -16dB 1 1 0 0 or 1 -20dB 1 1 1 0 or 1 -24dB Antenna Damper The antenna damper allows the chip to deal with higher field strength, it is enabled by register R1<4>. It consists of shunt resistors which degrade the quality factor of the resonator by reducing the signal at the input of the amplifier. In this way the resonator sees a smaller parallel resistance (in the band of interest) which degrades its quality factor in order to increase the linear range of the channel amplifier (the amplifier doesn't saturate in presence of bigger signals). Figure 33 shows the bit setup. Figure 33: Antenna Damper Bit Setup Page 24 Document Feedback R4<5> R4<4> Shunt resistor (parallel to the resonator at 125 kHz) 0 0 1 k 0 1 3 k 1 0 9 k 1 1 27 k ams Datasheet [v1-62] 2014-Nov-27 AS3930 - Detailed Description Demodulator / Data Slicer The performance of the demodulator can be optimized according to bit rate and preamble length as described in Figure 34 and Figure 35. Figure 34: Bit Setup for Envelop Detector for Different Symbol Rates R3<2> R3<1> R3<0> Symbol Rate [Manchester symbol/s] 0 0 0 4096 0 0 1 2184 0 1 0 1490 0 1 1 1130 1 0 0 910 1 0 1 762 1 1 0 655 1 1 1 512 If the bit rate gets higher, the time constant in the envelop detector must be set to a smaller value. This means that higher noise is injected because of the wider band. The next table is a rough indication of how the envelop detector looks like for different bit rates. By using proper data slicer settings it is possible to improve the noise immunity paying the penalty of a longer preamble. In fact if the data slicer has a bigger time constant it is possible to reject more noise, but every time a transmission occurs, the data slicer need time to settle. This settling time will influence the length of the preamble. Figure 35 gives a correlation between data slicer setup and minimum required preamble length. ams Datasheet [v1-62] 2014-Nov-27 Page 25 Document Feedback AS3930 - Detailed Description Figure 35: Bit Setup for Data Slicer for Different Preamble Length R3<5> R3<4> R3<3> Minimum Preamble Length [ms] 0 0 0 0.8 0 0 1 1.15 0 1 0 1.55 0 1 1 1.9 1 0 0 2.3 1 0 1 2.65 1 1 0 3 1 1 1 3.5 Note(s): These times are minimum required, but it is recommended to prolong the preamble. The comparator of the data slicer can work only with positive or with symmetrical threshold R3<6>. In addition the threshold can be 20 or 40 mV R3<7>. In case the length of the preamble is an issue the data slicer can also work with an absolute threshold R1<7>. In this case the bits R3<2:0> would not influence the performance. It is even possible to reduce the absolute threshold in case the environment is not particularly noisy R2<7>. Correlator After frequency detection the data correlation is only performed if the correlator is enabled (R1<1>=1). The data correlation consists of checking the presence of a preamble (ON/OFF modulated carrier) followed by a certain pattern. After the frequency detection the correlator waits 16 bits (see bit rate definition in Figure 36) and if no preamble is detected the chip is set back to listening mode and the false wake-up register (R13<7:0>) is incremented by one. To get started with the pattern correlation the correlator needs to detect at least 4 bits of the preamble (ON/OFF modulated carrier). The bit duration is defined in the register R7<4:0>(Figure 36) as function of the Real Time Clock (RTC) periods. Page 26 Document Feedback ams Datasheet [v1-62] 2014-Nov-27 AS3930 - Detailed Description Figure 36: Bit Rate Setup R7 <4> R7 <3> R7 <2> R7 <1> R7 <0> Bit Duration in RTC Clock Periods Bit Rate (bits/s) Symbol Rate (Manchester symbols/s) 0 0 0 1 1 4 8192 4096 0 0 1 0 0 5 6552 3276 0 0 1 0 1 6 5460 2730 0 0 1 1 0 7 4680 2340 0 0 1 1 1 8 4096 2048 0 1 0 0 0 9 3640 1820 0 1 0 0 1 10 3276 1638 0 1 0 1 0 11 2978 1489 0 1 0 1 1 12 2730 1365 0 1 1 0 0 13 2520 1260 0 1 1 0 1 14 2340 1170 0 1 1 1 0 15 2184 1092 0 1 1 1 1 16 2048 1024 1 0 0 0 0 17 1926 963 1 0 0 0 1 18 1820 910 1 0 0 1 0 19 1724 862 1 0 0 1 1 20 1638 819 1 0 1 0 0 21 1560 780 1 0 1 0 1 22 1488 744 1 0 1 1 0 23 1424 712 1 0 1 1 1 24 1364 682 1 1 0 0 0 25 1310 655 1 1 0 0 1 26 1260 630 1 1 0 1 0 27 1212 606 1 1 0 1 1 28 1170 585 1 1 1 0 0 29 1128 564 1 1 1 0 1 30 1092 546 1 1 1 1 0 31 1056 528 1 1 1 1 1 32 1024 512 ams Datasheet [v1-62] 2014-Nov-27 Page 27 Document Feedback AS3930 - Detailed Description If the preamble is detected correctly the correlator keeps searching for a data pattern. The duration of the preamble plus the pattern should not be longer than 40 bits (see bit rate definition in Figure 36). The data pattern can be defined by the user and consists of two bytes which are stored in the registers R5<7:0> and R6<7:0>. The two bytes define the pattern consisting of 16 half bit periods. This means the pattern and the bit period can be selected by the user. The only limitation is that the pattern (in combination with preamble) must obey Manchester coding and timing. It must be noted that according to Manchester coding a down-to-up bit transition represents a symbol "0", while a transition up-to-down represents a symbol "1". If the default code is used (96 [hex]) the binary code is (10 01 01 10 01 10 10 01). MSB has to be transmitted first. The user can also select (R1<2>) if single or double data pattern is used for wake-up. In case double pattern detection is set, the same pattern has to be repeated 2 times. Additionally it is possible to set the number of allowed missing zero bits (not symbols) in the received bitstream (R2<6:5>), as shown in the Figure 37. Figure 37: Allowed Pattern Detection Errors R2<6> R2<5> Maximum allowed error in the pattern detection 0 0 No error allowed 0 1 1 missed zero 1 0 2 missed zeros 1 1 3 missed zeros If the pattern matches the wake-up, interrupt is displayed on the WAKE output. If the pattern detection fails, the internal wake-up (on all active channels) is terminated with no signal sent to MCU and the false wake-up register will be incremented (R13<7:0>). The wake-up state is terminated with the direct command `clear_wake' (see Figure 24). This command terminates the MCU activity. The termination can also be automatic in case there is no response from MCU. The time out for automatic termination is set in a register R7<7:5>, as shown in theFigure 38. Page 28 Document Feedback ams Datasheet [v1-62] 2014-Nov-27 AS3930 - Detailed Description Figure 38: Timeout Setup R7<7> R7<6> R7<5> Time out 0 0 0 0 sec 0 0 1 50 msec 0 1 0 100 msec 0 1 1 150 msec 1 0 0 200 msec 1 0 1 250 msec 1 1 0 300 msec 1 1 1 350 msec Wake-up Protocol - Carrier Frequency 125 kHz Without Pattern Detection Figure 39: Wake-up Protocol Overview without Pattern Detection (only carrier frequency detection) Carrier Burst Data Carrier Burst > 550 us DAT WAKE Clear_wake ams Datasheet [v1-62] 2014-Nov-27 Page 29 Document Feedback AS3930 - Detailed Description In case the data correlation is disabled (R1<1>=0) the AS3930 wakes up upon detection of the carrier frequency only as shown in Figure 39. In order to ensure that AS3930 wakes up the carrier burst has to last longer than 550 s. To set AS3930 back to listening mode there are two possibilities: either the microcontroller sends the direct command clear_wake via SDI or the time out option is used ( R7<7:5>). In case the latter is chosen, AS3930 is automatically set to listening mode after the time defined in T_OUT ( R7<7:5>), counting starts at the low-to-high WAKE edge on the WAKE pin. Single Pattern Detection The Figure 40 shows the wake-up protocol in case the pattern correlation is enabled (R1<1>=1) for a 125 kHz carrier frequency. The initial carrier burst has to be longer than 550 s and can last maximum 16 bits (see bit rate definition in Figure 36). If the ON/OFF mode is used ( R1<5>=1), the minimum value of the maximum carrier burst duration is limited to 10 ms. This is summarized in Figure 41. In case the carrier burst is too long the internal wake-up will be set back to low and the false wake-up counter (R13<7:0>) will be incremented by one. The carrier burst must be followed by a preamble (0101... modulated carrier with a bit duration defined in Figure 36) and the wake-up pattern stored in the registers R5<7:0> and R6<7:0>. The preamble must have at least 4 bits and the preamble duration together with the pattern should not be longer than 40 bits. If the wake-up pattern is correct, the signal on the WAKE pin goes high one bit after the end of the pattern and the data transmission can get started. To set the chip back to listening mode the direct command clear_wake, as well as the time out option ( R7<7:5>) can be used. Figure 40: Wake-up Protocol Overview with Single Pattern Detection Carrier Burst Preamble Pattern Data 1-bit Preamble Carrier Burst>360 us Carrier Burst<16-bit duration Preamble > 4-bit duration Preamble + Pattern < 40-bit duration DAT WAKE Clear_wake Page 30 Document Feedback ams Datasheet [v1-62] 2014-Nov-27 AS3930 - Detailed Description Figure 41: Preamble Requirements in Standard Mode, Scanning Mode and ON/OFF Mode Bit Rate (bits/s) Maximum Duration of the Carrier Burst in Standard Mode and Scanning Mode (ms) Maximum Duration of the Carrier Burst in ON/OFF Mode (ms) 8192 1.95 10 6552 2.44 10 5460 2.93 10 4680 3.41 10 4096 3.90 10 3640 4.39 10 3276 4.88 10 2978 5.37 10 2730 5.86 10 2520 6.34 10 2340 6.83 10 2184 7.32 10 2048 7.81 10 1926 8.30 10 1820 8.79 10 1724 9.28 10 1638 9.76 10 1560 10.25 10.25 1488 10.75 10.75 1424 11.23 11.23 1364 11.73 11.73 1310 12.21 12.21 1260 12.69 12.69 1212 13.20 13.20 1170 13.67 13.67 1128 14.18 14.18 1092 14.65 14.65 1056 15.15 15.15 1024 15.62 15.62 ams Datasheet [v1-62] 2014-Nov-27 Page 31 Document Feedback AS3930 - Detailed Description False Wake-up Register The wake-up strategy in the AS3930 is based on 2 steps: 1. Frequency Detection: In this phase the frequency of the received signal is checked. 2. Pattern Correlation: Here the pattern is demodulated and checked whether it corresponds to the valid one. If there is a disturber or noise capable to overcome the first step (frequency detection) without producing a valid pattern, then a false wake-up call happens.Each time this event is recognized a counter is incremented by one and the respective counter value is stored in a memory cell (false wake-up register). Thus, the microcontroller can periodically look at the false wake-up register, to get a feeling how noisy the surrounding environment is and can then react accordingly (e.g. reducing the gain of the LNA during frequency detection, set the AS3930 temporarily to power down etc.), as shown in the Figure 42. The false wake-up counter is a useful tool to quickly adapt the system to any changes in the noise environment and thus avoid false wake-up events. Most wake-up receivers have to deal with environments that can rapidly change. By periodically monitoring the number of false wake-up events it is possible to adapt the system setup to the actual characteristics of the environment and enables a better use of the full flexibility of AS3930. Figure 42: Concept of the False Wake-up Register Together with System Wakeup Level 1 Frequency Detector Wakeup Level 2 Pattern Correlator WAKE Unsuccessful pattern correlation CHANGE SETUP TO MINIMIZE THE FALSE WAKEUP EVENTS Register Setup False wakeup register READ FALSE WAKEUP REGISTER Microcontroller Page 32 Document Feedback ams Datasheet [v1-62] 2014-Nov-27 AS3930 - Detailed Description Real Time Clock (RTC) The RTC can be based on a crystal oscillator (R1<0>=1), the internal RC-oscillator (R1<0>=0), or an external clock source (R1<0>=1). The crystal has higher precision of the frequency but a higher current consumption and needs three external components (crystal plus two capacitors). The RC-oscillator is completely integrated and can be calibrated if a reference signal is available for a very short time to improve the frequency accuracy. The calibration gets started with the trim_osc direct command. Since no non-volatile memory is available the calibration must be done every time after the RCO was turned OFF. The RCO is turned OFF when the chip is in power down mode, a POR happened, or the crystal oscillator is enabled. Since the RTC defines the time base of the frequency detection, the selected frequency (frequency of the crystal oscillator or the reference frequency used for calibration of the RC oscillator) should be about one forth of the carrier frequency: (EQ1) F RTC F CAR 0.25 Where: F CAR is the carrier frequency F RTC is the RTC frequency Note(s): The third option for the RTC is the use of an external clock source, which must be applied directly to the XIN pin (XOUT floating). Crystal Oscillator Figure 43: Characteristics of XTAL Parameter Conditions Crystal accuracy (initial) Overall accuracy Min Typ Crystal motional resistance Max Units 120 p.p.m. 60 K Frequency 32.768 kHz Contribution of the oscillator to the frequency error 5 p.p.m 1 s Start-up Time Duty cycle Current consumption ams Datasheet [v1-62] 2014-Nov-27 Crystal dependent 45 50 1 55 % A Page 33 Document Feedback AS3930 - Detailed Description RC-Oscillator Figure 44: Characteristics of RCO Parameter Conditions Min Typ Max Units If no calibration is performed 27 32.768 42 kHz If calibration is performed 31 32.768 34.5 kHz 65 cycles Frequency Calibration time Periods of reference clock Current consumption 200 nA To trim the RC-Oscillator, set the chip select (CS) to high before sending the direct command trim_osc over SDI. Then 65 digital clock cycles of the reference clock (e.g. 32.768 kHz) have to be sent on the clock bus (SCLK), as shown in Figure 45. After that the signal on the chip select (CS) has to be pulled down. The calibration is effective after the 65th reference clock edge and it will be stored in a volatile memory. In case the RC-oscillator is switched OFF or a power-ON-reset happens (e.g. battery change) the calibration has to be repeated. Figure 45: RC-Oscillator Calibration via SDI 65 clock cycles CS SCLK SDI X 1 1 0 0 0 DIRECT COMMAND Trim_osc 0 1 X 0 REFERENCE CLOCK External Clock Source To clock the AS3930 with an external signal the crystal oscillator has to be enabled (R1<0>=1). As shown in the Figure 4 the clock must be applied on the pin XIN while the pin XOUT must stay floating. The RC time constant has to be 100s with a tolerance of 10% (e.g. R=680 k and C=22pF). In the Figure 46 the clock characteristics are summarized. Page 34 Document Feedback ams Datasheet [v1-62] 2014-Nov-27 AS3930 - Detailed Description Figure 46: Characteristics of External Clock Symbol Parameter Min VI Low level Vh High level Tr Max Units 0 0.1 * VDD V 0.9 * VDD VDD V Rise-time 3 s Tf Fall-time 3 s T =1/2RC RC Time constant 110 s 90 Typ 100 Note(s): In power down mode the external clock has to be set to V DD. ams Datasheet [v1-62] 2014-Nov-27 Page 35 Document Feedback AS3930 - Package Drawings & Mark ings Package Drawings & Markings The product is available in a 16-pin TSSOP and QFN 4x4 16 LD package. Figure 47: 16-pin TSSOP Package AS3930 @ YYWWMZZ Symbol Min Nom Max A - - 1.20 A1 0.05 - 0.15 A2 0.80 1.00 1.05 b 0.19 - 0.30 c 0.09 - 0.20 D 4.90 5.00 5.10 E - 6.40 BSC - E1 4.30 4.40 4.50 e - 0.65 BSC - L 0.45 0.60 0.75 L1 - 1.00 REF - R 0.09 - - R1 0.09 - - - S 0.20 1 0 - 2 - 12 REF - 3 - 12 REF - 8 aaa - 0.10 - bbb - 0.10 - ccc - 0.05 - ddd - 0.20 - N 16 Green RoHS Note(s) and/or Footnote(s): 1. Dimensions and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters. Angles are in degrees. Figure 48: Marking: @YYWWMZZ @ YY WW M ZZ Sublot identifier Year Manufacturing Week Assembly plant identifier Assembly traceability code Page 36 Document Feedback ams Datasheet [v1-62] 2014-Nov-27 AS3930 - Package Drawings & Markings Figure 49: QFN 4x 4 16 LD Package AS3930 YYWWXZZ @ Symbol Min Nom Max A 0.80 0.85 0.90 A1 0 A3 0.05 0.203 REF b 0.18 0.23 0.28 D 4.00 BSC E 4.00 BSC D2 2.60 2.70 2.80 E2 2.60 2.70 2.80 e 0.65 BSC L 0.35 L1 0.00 0.40 0.10 aaa 0.10 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 RoHS 0.45 Green Note(s) and/or Footnote(s): 1. Dimensions and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters. Angles are in degrees. 3. Dimension b applies to metallized terminal and is measured between 0.25mm and 0.30mm from terminal tip. Dimension L1 represents terminal full back from package edge up to 0.15mm is acceptable. 4. Coplanarity applies to the exposed heat slug as well as the terminal. 5. Radius on terminal is optional. Figure 50: Marking: YYWWXZZ@ YY WW X ZZ @ Year Manufacturing Week Assembly plant identifier Assembly traceability code Sublot identifier ams Datasheet [v1-62] 2014-Nov-27 Page 37 Document Feedback AS3930 - Ordering & Contact Information Ordering & Contact Information Figure 51: Ordering Information Ordering Code Type Marking Delivery Form(1) Delivery Quantity AS3930-BTST 16-pin TSSOP AS3930 7 inches Tape & Reel 1000 pcs AS3930-BQFT QFN (4x4) 16LD AS3930 7 inches Tape & Reel 1000 pcs Note(s) and/or Footnote(s): 1. Dry Pack: Moisture Sensitivity Level (MSL) = 3, according to IPC/JEDEC J-STD-033A. Buy our products or get free samples online at: www.ams.com/ICdirect Technical Support is available at: www.ams.com/Technical-Support Provide feedback about this document at: www.ams.com/Document-Feedback For further information and requests, e-mail us at: ams_sales@ams.com For sales offices, distributors and representatives, please visit: www.ams.com/contact Headquarters ams AG Tobelbaderstrasse 30 8141 Unterpremstaetten Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com Page 38 Document Feedback ams Datasheet [v1-62] 2014-Nov-27 AS3930 - RoHS Compliant & ams Green Statement RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes. ams Green (RoHS compliant and no Sb/Br): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. ams Datasheet [v1-62] 2014-Nov-27 Page 39 Document Feedback AS3930 - Copyrights & Disclaimer Copyrights & Disclaimer Copyright ams AG, Tobelbader Strasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG "AS IS" and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services. Page 40 Document Feedback ams Datasheet [v1-62] 2014-Nov-27 AS3930 - Document Status Document Status Document Status Product Preview Preliminary Datasheet Datasheet Datasheet (discontinued) ams Datasheet [v1-62] 2014-Nov-27 Product Status Definition Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Page 41 Document Feedback AS3930 - Revision Information Revision Information Changes from 1.5 (2013-Feb-04) to current revision 1-62 (2014-Nov-27) Page Content was updated to the latest ams design Updated General Description & Figure 1 1 Updated Pin Assignments section 4 Added TRC (start-up time) parameter in Figure 11 and a note under it 8 Updated Figure 29 22 Updated Package Drawings & Markings section 36 Note(s) and/or Footnote(s): 1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision. 2. Correction of typographical errors is not explicitly mentioned. Page 42 Document Feedback ams Datasheet [v1-62] 2014-Nov-27 AS3930 - Content Guide Content Guide ams Datasheet [v1-62] 2014-Nov-27 1 1 2 General Description Key Benefits & Features Applications 4 4 5 Pin Assignments 16-pin TSSOP QFN 4x4 16 LD 6 7 10 Absolute Maximum Ratings Electrical Characteristics Typical Operating Characteristics 12 13 13 13 13 13 14 14 15 15 16 18 22 22 23 24 25 26 29 29 30 32 33 33 34 34 Detailed Description Operating Modes Power Down Mode Listening Mode Standard Listening Mode ON/OFF Mode (Low Power mode ) Preamble Detection / Pattern Correlation Data Receiving System and Block Specification Main Logic and SDI Register Table Description and Default Values Serial Data Interface (SDI) SDI Timing Channel Amplifier and Frequency Detector Frequency Detector / AGC Antenna Damper Demodulator / Data Slicer Correlator Wake-up Protocol - Carrier Frequency 125 kHz Without Pattern Detection Single Pattern Detection False Wake-up Register Real Time Clock (RTC) Crystal Oscillator RC-Oscillator External Clock Source 36 38 39 40 41 42 Package Drawings & Markings Ordering & Contact Information RoHS Compliant & ams Green Statement Copyrights & Disclaimer Document Status Revision Information Page 43 Document Feedback