SRAM
AS8S512K32
& AS8S512K32A
Austin Semiconductor, Inc.
AS8S512K32 & AS8S512K32A
Rev. 3.0 6/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
CS
CS
CS
CS
\
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8S512K32 and
AS8S512K32A are 16 Megabit CMOS SRAM Modules organized as
512Kx32 bits. These devices achieve high speed access, low power
consumption and high reliability by employing advanced CMOS
memory technology .
This military temperature grade product is ideally suited for
military and space applications.
FEATURES
Operation with single 5V supply
High speed: 17, 20, 25 and 35ns
Built in decoupling caps for low noise
Organized as 512Kx32 , byte selectable
Low power CMOS
TTL Compatible Inputs and Outputs
Future offerings
3.3V Power Supply
15 ns Ultra High Speed
OPTIONS MARKINGS
Operating Temperature Ranges
Military (-55oC to +125oC) XT
Industrial (-40oC to +85oC) IT
Timing
17ns -17
20ns -20
25ns -25
35ns -35
45ns -45
55ns -55
• Package
Ceramic Quad Flatpack Q No.702
Pin Grid Array P No.904
• Low Power Data Retention Mode L
• Pinout
Military (no indicator)
Commercial A
PIN ASSIGNMENT
(Top View)
AVAILABLE AS MILITARY
SPECIFICATIONS
SMD 5962-94611 (Military Pinout)
MIL-STD-883
68 Lead CQFP (Q)
Military SMD Pinout Option
512K x 32 SRAM
SRAM MEMORY ARRAY
For more products and information
please visit our web site at
www.austinsemiconductor.com
68 Lead CQFP
Commercial Pinout Option (A)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O17
I/O18
I/O19
Vss
I/O20
I/O21
I/O22
I/O23
Vcc
I/O24
I/O25
I/O26
I/O27
Vss
I/O28
I/O29
I/O30
I/O 14
I/O 13
I/O 12
Vss
I/O 11
I/O 10
I/O 9
I/O 8
Vcc
I/O 7
I/O 6
I/O 5
I/O 4
Vss
I/O 3
I/O 2
I/O 1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
I/O 31
A6
A5
A4
A3
A2
A1
A0
Vcc
A13
A12
A11
A10
A9
A8
A7
I/O 0
I/O 16
A18
A17
CS4\
CS3\
CS2\
CS1\
NC
Vcc
NC
NC
OE\
WE\
A16
A15
A14
I/O 15
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
GND
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
Vcc
A11
A12
A13
A14
A15
A16
CS1\
OE\
CS2
A17
WE2\
WE3\
WE4\
A18
NC
NC
NC
A0
A1
A2
A3
A4
A5
CS3\
GND
CS4\
WE1\
A6
A7
A8
A9
A10
Vcc
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
66 Lead PGA (P)
Military SMD Pinout
SRAM
AS8S512K32
& AS8S512K32A
Austin Semiconductor, Inc.
AS8S512K32 & AS8S512K32A
Rev. 3.0 6/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
CS\4
CS\3
CS\2
CS\1
WE\
OE\
A0 - A18
I/O 24 - I/O 31
I/O 16 - I/O 23
I/O 8 - I/O 15
I/O 0 - I/O 7
M3
M2
M1
M0
512K x 8
512K x 8
512K x 8
512K x 8
COMMERCIAL PINOUT/BLOCK DIAGRAM
CS
MILITARY PINOUT/BLOCK DIAGRAM
CS
CS
CS
TRUTH TABLE
MODE OE\ CE\ WE\ I/O POWER
Read LLH
DOUT ACTIVE
Write(2) XLLDIN ACTIVE
Standby XHX
High Z STANDBY
CS
SRAM
AS8S512K32
& AS8S512K32A
Austin Semiconductor, Inc.
AS8S512K32 & AS8S512K32A
Rev. 3.0 6/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
ABSOLUTE MAXIMUM RATINGS*
Voltage of Vcc Supply Relative to Vss......................-.5V to +7V
Storage T emperature............................................-65°C to +150°C
Short Circuit Output Current(per I/O).................................20mA
Voltage on Any Pin Relative to Vss....................-.5V to Vcc+1V
Maximum Junction T emperature**...................................+150°C
*Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation on the
device at these or any other conditions above those indicated
in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect reliability .
**Junction temperature depends upon package type, cycle time,
loading, ambient temperature and airflow . See the Application
Information section at the end of this datasheet for more infor-
mation.
DESCRIPTION SYMBOL -17 -20 -25 -35 -45 -55 UNITS NOTES
Power Supply
Current: Operating Icc 700 650 600 570 570 550 mA 3,13
Power Supply
Current: Standby I
SBT1
240 240 190 190 150 150 mA 3, 13
CMOS Standby I
SBT2
80 80 80 80 80 80 mA
VIN = VCC - 0.2V, or
VSS +0.2V
VCC=Max; f = 0Hz
MAX
CONDITIONS
CS\<VIL; VCC = MAX
f = MAX = 1/ tRC (MIN)
Outputs Open
CS\>VIH; VCC = MAX
f = MAX = 1/ tRC (MIN)
Outputs Open
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC < TA < 125oC and -40oC to +85oC; Vcc = 5V +10%)
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS
NOTES
Input High (logic 1) Voltage V
IH
2.2 V
CC
+.5 V1
Input Low (logic 1) Voltage V
IL
-0.5 0.8 V 1,2
Input Leakage Current
ADD,OE
I
LI1
-10 10
µ
A
Input Leakage Current
WE, CE
I
LI2
-10 10
µ
A
Output(s) Disabled
0V<V
OUT
<V
CC
Output High Voltage I
OH
= 4.0mA V
OH
2.4 V 1
Output Low Voltage I
OL
= 8.0mA V
OL
0.4 V 1
Supply Voltage V
CC
4.5 5.5 V 1
0V<V
IN
<V
CC
Output Leakage Current
I/O
ILO µA
10-10
SRAM
AS8S512K32
& AS8S512K32A
Austin Semiconductor, Inc.
AS8S512K32 & AS8S512K32A
Rev. 3.0 6/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
AC TEST CONDITIONS
NOTE:
1. This parameter is sampled.
OH
OL
I
I
Current Source
Current Source
Vz = 1.5V
(Bipolar
Supply)
Device
Under
Test
Ceff = 50pf
-+
+
NOTES:
Vz is programmable from -2V to + 7V.
IOL and IOH programmable from 0 to 16 mA.
Vz is typically the midpoint of VOH and VOL.
IOL and IOH are adjusted to simulate a typical resistive load
circuit.
Input pulse levels.........................................VSS to 3V
Input rise and fall times.........................................5ns
Input timing reference levels...............................1.5V
Output reference levels........................................1.5V
Output load..............................................See Figure 1
T est Specifications
SYMBOL PARAMETER MAX UNITS
C
ADD
A0 - A18 Capacitance 50 pF
C
OE
OE\ Capacitance 50 pF
C
WE,
C
CS
WE\ and CS\ Capacitance 20 pF
C
IO
I/O 0- I/O 31 Capacitance 20 pF
C
WE
("A" version) WE\ Capacitance 50 pF
CAPACITANCE (VIN = 0V, f = 1MHz, TA = 25oC)1
Figure 1
SRAM
AS8S512K32
& AS8S512K32A
Austin Semiconductor, Inc.
AS8S512K32 & AS8S512K32A
Rev. 3.0 6/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(NO TE 5) (-55oC<TA < 125oC and -40oC to +85oC; VCC = 5V +10%)
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
READ cycle time
t
RC 17 20 25 35 45 55 ns
Address access time
t
AA 17 20 25 35 45 55 ns
Chip select access time
t
ACS 17 20 25 35 45 55 ns
Output hold from address change
t
OH 22222 2 ns
Chip select to output in Low-Z
t
LZCS 2 2 2 2 2 2 ns 4,6,7
Chip select to output in High-Z
t
HZCS 9 10 12 15 20 20 ns 4,6,7
Output enable access time
t
AOE 9101215 20 20ns
Output enable to output in Low-Z
t
LZOE 0 0 0 0 0 0 ns 4,6
Output disable to output in High-Z
t
HZOE 12 12 12 15 20 20 ns 4,6
WRITE cycle time
t
WC 17 20 25 35 45 55 ns
Chip select to end of write
t
CW 15 15 17 20 25 25 ns
Address valid to end of write
t
AW 15 15 17 20 25 25 ns
Address setup time
t
AS 22222 2 ns
Address hold from end of write
t
AH 11111 1 ns
WRITE pulse width
t
WP1 15 15 17 20 25 25 ns
WRITE pulse width
t
WP2 15 15 17 20 25 25 ns
Data setup time
t
DS 12 10 12 15 20 20 ns
Data hold time
t
DH 00000 0 ns
Write disable to output in Low-z
t
LZWE 2 2 2 2 2 2 ns 4,6,7
Write enable to output in High-Z
t
HZWE 9 11 13 15 15 15 ns 4,6,7
-45 -55
WRITE CYCLE
READ CYCLE
DESCRIPTION -20-17 -25
SYMBOL NOTESUNITS
-35
SRAM
AS8S512K32
& AS8S512K32A
Austin Semiconductor, Inc.
AS8S512K32 & AS8S512K32A
Rev. 3.0 6/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
READ CYCLE NO. 1
READ CYCLE NO. 2
1234
1234
1234
1234
1234
1234
12345
1
234
5
12345
1
1
1
1
1
1
ADDRESS
DATA I/O PREVIOUS DATA VALID DATA VALID
tOH
tAA
tRC
ADDRESS
tRC
12345678
12345678
12345678
12345678
12345678
23
23
23
12345
1
234
5
1
234
5
12345
123456789
123456789
123456789
123456789
123456789
123456
1
2345
6
1
2345
6
1
2345
6
123456
1234567
1
23456
7
1
23456
7
1234567
123456789012
123456789012
123456789012
123456789012
123456789012
23
23
23
12345
1
234
5
1
234
5
12345
123456789012
123456789012
123456789012
123456789012
123456789012
123456
1
2345
6
1
2345
6
1
2345
6
123456
1234567
1
23456
7
1
23456
7
1
23456
7
1234567
1234
1234
1234
1234
1234
1234
1234
1234
123
1
2
3
1
2
3
123
1
1
1
1
1
1
1
1
HIGH IMPEDANCE DATA VALID
tAA
tACS
tLZCS tHZCS
tHZOE
tAOE
tLZOE
CS\
OE\
DAT A I/O
SRAM
AS8S512K32
& AS8S512K32A
Austin Semiconductor, Inc.
AS8S512K32 & AS8S512K32A
Rev. 3.0 6/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
WRITE CYCLE NO. 2
(Write Enable Controlled)
WRITE CYCLE NO. 1
(Chip Select Controlled)
ADDRESS
tWC
123456
123456
123456
123456
DATA VALID
tAW
tAS
tWP21
tCW
CS\
WE\
DAT A I/O tDH
tDS
12345678
12345678
12345678
12345678
123456789012
123456789012
123456789012
123456789012
12345
1
234
5
1
234
5
12345
123456
1
2345
6
1
2345
6
123456
tAH
ADDRESS
tWC
12345678
12345678
12345678
12345678
12345678
23
23
23
123456
1
2345
6
1
2345
6
1
2345
6
123456
123456789012
123456789012
123456789012
123456789012
123456789012
12345
1
234
5
1
234
5
1
234
5
12345
1234567
1
23456
7
1
23456
7
1
23456
7
1234567
123456
123456
123456
123456
1234
1234
1234
12345678901234
1
234567890123
4
12345678901234
1
1
1
1
1
1
DATA VALID
tAW tCW
tAS
tAH
tLZWE
tWP11
tHZWE
CS\
WE\
DAT A I/O
1234
1234
1234
1234
1
23
4
1
23
4
1234
1234
1
23
4
1
23
4
1234
tDH
tDS
SRAM
AS8S512K32
& AS8S512K32A
Austin Semiconductor, Inc.
AS8S512K32 & AS8S512K32A
Rev. 3.0 6/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
7. At any given temperature and voltage condition,
tHZCS, is less than tLZCS, and tHZWE is less than tLZWE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip selects and output
enable are held in their active state.
10. Address valid prior to or coincident with latest occurring
chip enable.
11. tRC= READ cycle time.
12. Chip enable (CS\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
13. ICC is for 32 bit mode.
NOTES
1. All voltages referenced to VSS (GND).
2. -2V for pulse width <20ns.
3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
4. This parameter guaranteed but not tested.
5. Test conditions as specified with output loading as
shown in Fig. 1 unless otherwise noted.
6. tHZCS, tHZOE and tHZWE are specified with CL= 5pF as in Fig. 2.
Transition is measured +/- 200 mV typical from steady state
voltage, allowing for actual tester RC time constant.
RC(MIN)
unloaded, and f= HZ.
t1
LOW VCC DATA RETENTION WAVEFORM
LOW POWER CHARACTERISTICS (L Version Only)
     

  










 
   
 


  


 !!
  "  " #  $
%
  $ %
&'  $ %

123456789012345678
123456789012345678
123456789012345678
123456789012345678
123456789012345678
123456789012345678
123456789012345678
123456789012345678
12345
1
234
5
1
234
5
1
234
5
1
234
5
1
234
5
1
234
5
12345
12345678
1
234567
8
1
234567
8
1
234567
8
1
234567
8
1
234567
8
1
234567
8
12345678
123456789012345678
123456789012345678
123456789012345678
123456789012345678
123456789012345678
123456789012345678
123456789012345678
123456789012345678
12345
1
234
5
1
234
5
1
234
5
1
234
5
1
234
5
1
234
5
12345
12345678
1
234567
8
1
234567
8
1
234567
8
1
234567
8
1
234567
8
1
234567
8
12345678
DATA RETENTION MODE
4.5V 4.5V
VDR>2V
VDR
tCDR tR
VCC
CS\ 1-4
SRAM
AS8S512K32
& AS8S512K32A
Austin Semiconductor, Inc.
AS8S512K32 & AS8S512K32A
Rev. 3.0 6/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
MECHANICAL DEFINITIONS*
ASI Case #702 (Package Designator Q)
SMD 5962-94611, Case Outline M
*All measurements are in inches.
4 x D2
4 x D1
D
b
e
MIN MAX
A 0.123 0.200
A1 0.118 0.186
A2 0.000 0.020
B
b 0.013 0.017
D
D1 0.870 0.890
D2 0.980 1.000
E 0.936 0.956
e
R 0.005 ---
L1 0.035 0.045
SYMBOL
0.800 BSC
0.050 BSC
SMD SPECIFICATIONS
0.010 REF
A2
SEE DETAIL A
A
A1
E
DET AIL A
L1
1o - 7o
R
B
SRAM
AS8S512K32
& AS8S512K32A
Austin Semiconductor, Inc.
AS8S512K32 & AS8S512K32A
Rev. 3.0 6/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
MECHANICAL DEFINITIONS*
ASI Case #904 (Package Designator P )
SMD 5962-94611, Case Outline T
*All measurements are in inches.
4 x D
D1
D2
E1
Pin 66 ePin 11
Pin 1
(identified by
0.060 square pad)
Pin 56
A
A1
L
φb
e
φb1
MIN
MAX
A 0.144 0.181
A1 0.025 0.035
φ
b0.016 0.020
φ
b1 0.045 0.055
D 1.065 1.085
D1/E1
D2
e
L 0.145 0.155
0.600 TYP
0.100 TYP
SYMBOL
1.000 TYP
SMD SPECIFICATIONS
SRAM
AS8S512K32
& AS8S512K32A
Austin Semiconductor, Inc.
AS8S512K32 & AS8S512K32A
Rev. 3.0 6/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11
Device Number Options** Package
T
yp
e
Speed
ns
Options** Process
AS8S512K32 A Q -17 L /*
AS8S512K32 A Q -20 L /*
AS8S512K32 A Q -25 L /*
AS8S512K32 A Q -35 L /*
AS8S512K32 A Q -45 L /*
AS8S512K32 A Q -55 L/*
Device Number Options** Package
T
yp
e
Speed
ns
Options** Process
AS8S512K32 A P -17 L /*
AS8S512K32 A P -20 L /*
AS8S512K32 A P -25 L /*
AS8S512K32 A P -35 L /*
AS8S512K32 A P -45 L /*
AS8S512K32 A P -55 L/*
EXAMPLE: AS8S512K32Q-25L/XT
EXAMPLE: AS8S512K32AP-25/XT
ORDERING INFORMATION
*AVAILABLE PROCESSES
IT = Industrial T emperature Range -40oC to +85oC
XT = Extended T emperature Range -55oC to +125oC
833C = Full Military Processing -55oC to +125oC
**DEFINITION OF OPTIONS
A = Commercial Pinout
no indicator = Military Pinout
L = Low Power Data Retention Mode
SRAM
AS8S512K32
& AS8S512K32A
Austin Semiconductor, Inc.
AS8S512K32 & AS8S512K32A
Rev. 3.0 6/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
12
ASI TO DSCC PART NUMBER
CROSS REFERENCE
Package Designator Q
ASI Part # SMD Part #
AS8S512K32Q-17L/883C 5962-9461110HMA
AS8S512K32Q-17L/883C 5962-9461110HMC
AS8S512K32Q-20L/883C 5962-9461109HMA
AS8S512K32Q-20L/883C 5962-9461109HMC
AS8S512K32Q-25L/883C 5962-9461108HMA
AS8S512K32Q-25L/883C 5962-9461108HMC
AS8S512K32Q-35L/883C 5962-9461107HMA
AS8S512K32Q-35L/883C 5962-9461107HMC
AS8S512K32Q-45L/883C 5962-9461106HMA
AS8S512K32Q-45L/883C 5962-9461106HMC
AS8S512K32Q-55L/883C 5962-9461105HMA
AS8S512K32Q-55L/883C 5962-9461105HMC
AS8S512K32Q-17/883C 5962-9461116HMA
AS8S512K32Q-17/883C 5962-9461116HMC
AS8S512K32Q-20/883C 5962-9461115HMA
AS8S512K32Q-20/883C 5962-9461115HMC
AS8S512K32Q-25/883C 5962-9461114HMA
AS8S512K32Q-25/883C 5962-9461114HMC
AS8S512K32Q-35/883C 5962-9461113HMA
AS8S512K32Q-35/883C 5962-9461113HMC
AS8S512K32Q-45/883C 5962-9461112HMA
AS8S512K32Q-45/883C 5962-9461112HMC
AS8S512K32Q-55/883C 5962-9461111HMA
AS8S512K32Q-55/883C 5962-9461111HMC
Package Designator P
ASI Part # SMD Part #
AS8S512K32P-17L/883C 5962-9461110HTA
AS8S512K32P-17L/883C 5962-9461110HTC
AS8S512K32P-20L/883C 5962-9461109HTA
AS8S512K32P-20L/883C 5962-9461109HTC
AS8S512K32P-25L/883C 5962-9461108HTA
AS8S512K32P-25L/883C 5962-9461108HTC
AS8S512K32P-35L/883C 5962-9461107HTA
AS8S512K32P-35L/883C 5962-9461107HTC
AS8S512K32P-45L/883C 5962-9461106HTA
AS8S512K32P-45L/883C 5962-9461106HTC
AS8S512K32P-55L/883C 5962-9461105HTA
AS8S512K32P-55L/883C 5962-9461105HTC
AS8S512K32P-17/883C 5962-9461116HTA
AS8S512K32P-17/883C 5962-9461116HTC
AS8S512K32P-20/883C 5962-9461115HTA
AS8S512K32P-20/883C 5962-9461115HTC
AS8S512K32P-25/883C 5962-9461114HTA
AS8S512K32P-25/883C 5962-9461113HTC
AS8S512K32P-35/883C 5962-9461113HTA
AS8S512K32P-35/883C 5962-9461113HTC
AS8S512K32P-45/883C 5962-9461112HTA
AS8S512K32P-45/883C 5962-9461112HTC
AS8S512K32P-55/883C 5962-9461111HTA
AS8S512K32P-55/883C 5962-9461111HTC