AS7C1025C-12JIN - Alliance Memory, Inc.

September 2006

Advance Information

AS7C1025C

5V 128K X 8 CMOS SRAM (Center power and ground)

12/5/06, v. 1.0 Alliance Memory P. 1 of 9

Features

• Industrial (-40o to 85oC) temperature.

• Organization: 131,072 x 8 bits

• High speed

- 15 ns address access time

- 6 ns output enable access time

• Low power consumption via chip deselect

• Easy memory expansion with

inputs

• Center power and ground

• TTL/LVTTL-compatible, three-state I/O

• JEDEC-standard package

- 32-pin, 400 mil SOJ

• ESD protection >

_ 2000 volts

Logic block diagram

131,072 x 8

Array

(1,048,576)

esn

Input buffer

01A 11

A31

A41

A51

A61

I/O0

I/O7

Address decoder

redo

Control

circuit

GND

Pin arrangement

A16

A15

A14

A13

I/O7

I/O6

GND

VCC

I/O5

I/O4

A12

A11

A10

I/O0

I/O1

VCC

GND

I/O2

I/O3

201C7SA

32-pin SOJ (400 mil)

AS7C1025C

12/5/06, v. 1.0 Alliance Memory P. 2 of 9

Functional description

The AS7C1025C is a 5V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized

as 131,072 x 8 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are

desired.

Equal address access and cycle times (tAA, tRC, tWC) of 15 ns with output enable access times (tOE) of 6 ns are ideal for high-

performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory

systems.

When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is

static, then full standby power is reached (ISB1).

A write cycle is accomplished by asserting write enable (

) and chip enable (

). Data on the input pins I/O0 through I/O7

is written on the rising edge of

(write cycle 1) or

(write cycle 2). To avoid bus contention, external devices should

drive I/O pins only after outputs have been disabled with output enable (

) or write enable (

A read cycle is accomplished by asserting output enable (

) and chip enable (

), with write enable (

) high. The chips

drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write

enable is active, output drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C1025C is packaged in

common industry standard packages.

Note:

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect reliability.

Key: X = don’t care, L = low, H = high.

Absolute maximum ratings

Parameter Symbol Min Max Unit

Voltage on VCC relative to GND Vt1 –0.50 +7.0 V

Voltage on any pin relative to GND Vt2 –0.50 VCC + 0.5 V

Power dissipation PD– 1.25 W

Storage temperature (plastic) Tstg –55 +125 oC

Ambient temperature with VCC applied Tbias –55 +125 oC

DC current into outputs (low) IOUT – 50 mA

Truth table

CE WE OE

Data Mode

H X X High Z Standby (ISB, ISB1)

L H H High Z Output disable (ICC)

L H L DOUT Read (ICC)

L L X DIN Write (ICC)

AS7C1025C

12/5/06, v. 1.0 Alliance Memory P. 3 of 9

Notes:

VIL min = -1.0V for pulse width less than 5ns, once per cycle.

VIH max = VCC+2.0V for pulse width less than 5ns, once per cycle.

Recommended operating conditions

Parameter Symbol Min Nominal Max Unit

Supply voltage VCC 4.5 5.0 5.5 V

Input voltage VIH 2.2 – VCC + 0.5 V

VIL –0.5 – 0.8 V

Ambient operating temperature (Industrial) TA–40 – 85 oC

DC operating characteristics (over the operating range)1

Parameter Symbol Test conditions

AS7C1025C-15

UnitMin Max

Input leakage current | ILI | VCC = Max, VIN = GND to VCC – 5 µA

Output leakage current | ILO | VCC = Max, CE = VIH,

Vout = GND to VCC

– 5 µA

Operating power supply current ICC

VCC = Max

CE ? VIL, f = fMax, IOUT = 0 mA – 160 mA

Standby power supply current1ISB

VCC = Max

CE ? VIH, f = fMax

– 40 mA

ISB1

VCC = Max

CE ? VCC–0.2 V,

VIN ? 0.2 V or VIN ? VCC –0.2 V,

f = 0

10 mA

Output voltage VOL IOL = 8 mA, VCC = Min – 0.4 V

VOH IOH = –4 mA, VCC = Min 2.4 – V

Capacitance (f = 1 MHz, Ta = 25o C, VCC = NOMINAL)2

Parameter Symbol Signals Test conditions Max Unit

Input capacitance CIN A,

VIN = 3dV 8 pF

I/O capacitance CI/O I/O VIN = VOUT = 3dV 8 pF

Note:

This parameter is guaranteed by device characterization, but is not production tested.

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Key to switching waveforms

Read waveform 1 (address controlled)3,6,7,9

Read waveform 2 (CE and OE controlled)3,6,8,9

Read cycle (over the operating range)3,9

Parameter Symbol

AS7C1025C-15

Unit NotesMin Max

Read cycle time tRC 15 – ns

Address access time tAA – 15 ns 3

Chip enable (

) access time tACE – 15 ns 3

Output enable (

) access time tOE – 6 ns

Output hold from address change tOH 4 – ns 5

low to output in low Z tCLZ 3 – ns 4, 5

low to output in high Z tCHZ 0 6 ns 4, 5

low to output in low Z tOLZ 0 – ns 4, 5

high to output in high Z tOHZ 0 5 ns 4, 5

Power up time tPU 0 – ns 4, 5

Power down time tPD – 12 ns 4, 5

Undefined/don’t careFalling inputRising input

ddress

OUT

Data valid

current

Supply

OUT

OLZ

ACE

CHZ

CLZ

50% 50%

Data valid

RC1

OHZ

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Write waveform 1 (WE controlled)10,11

Write cycle (over the operating range)11

Parameter Symbol

AS7C1025C-15

Unit NotesMin Max

Write cycle time tWC 15 – ns

Chip enable (

) to write end tCW 8 – ns

Address setup to write end tAW 8 – ns

Address setup time tAS 0 – ns

Write pulse width tWP 8 – ns

Write recovery time tWR 0 – ns

Address hold from end of write tAH 0 – ns

Data valid to write end tDW 6 – ns

Data hold time tDH 0 – ns 4, 5

Write enable to output in high Z tWZ – 5 ns 4, 5

Output active from write end tOW 3 – ns 4, 5

Address

OUT

Data valid

AS7C1025C

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Write waveform 2 (CE controlled)10,11

AC test conditions

Notes:

1 During VCC power-up, a pull-up resistor to VCC on

is required to meet ISB specification.

2 This parameter is sampled, but not 100% teste d.

3 For test conditions, see AC Test Conditions, Figures A and B.

CLZ and tCHZ are specified with CL = 5 pF, as in Figure B. Transition is measured ±200 mV from steady-state voltage.

5 This parameter is guarante ed, but not 100% tested.

is high for read cycle.

and

are low for read cycle.

8 Address is valid prior to or coincident with

transition low.

9 All read cycle timings are reference d from the last valid addre ss to the first transitioning address.

10 N/A

11 All write cycle timings are referenced fro m the last valid addre ss to the first transitioning addre ss.

12 N/A.

13 C = 30 pF, excep t all high Z and low Z parameters where C = 5 pF.

Address

OUT

Data valid

– Output load: see Figure B.

– Input pulse level: GND to 30 V. See Figure A.

– Input rise and fall times: 3 ns. See Figure A.

– Input and output timing reference levels: 1.5 V.

168

Thevenin equivalent:

OUT

+1.728 V

255

480

OUT

GND

+5 V

Figure B: 5 V Output load

10%

90%

10%

90%

GND

+3.0V

Figure A: Input pulse

3 ns

AS7C1025C

12/5/06, v. 1.0 Alliance Memory P. 7 of 9

Package dimensions

Pin 1

A2 c

Seating

plane

32-pin SOJ

400 mil

Symbol

32-pin SOJ

400 mil

Min Max

A0.132 0.146

A1 0.025 -

A2 0.105 0.115

B0.026 0.032

b0.015 0.020

c0.007 0.013

D0.820 0.830

E0.354 0.378

E1 0.395 0.405

E2 0.435 0.445

e0.050 BSC

Note: This part is compatible with both pin numbering

conventions used by various manufacturers.

AS7C1025C

12/5/06, v. 1.0 Alliance Memory P. 8 of 9

Ordering Codes

Package Volt/Temp 15 ns

Plastic SOJ, 400 mil 5V industrial AS7C1025C-15JIN

Part numbering system

AS7C 1025C –XX X X X

SRAM prefix Device

number Access time Package:

J = SOJ 400 mil

Temperature range

I = industrial, -40°

C to 85° C

N = LEAD FREE

PART

Alliance Memory, Inc.

1116 South Amphlett

San Mateo, CA 94402

Tel: 650-525-3737

Fax: 650-525-0449

www.alliancememory.com

Part Number: AS7C1025C

Document Version: v. 1.0

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AS7C1025C