DEMO MANUAL DC1369A LTC2262-14/-12, LTC2261-14/-12, LTC2260-14/-12, LTC2259-14/-12, LTC2258-14/-12, LTC2257-14/-12, LTC2256-14/-12, 14/12-Bit, 25Msps to 150Msps ADCs Description Demonstration circuit 1369A supports a family of 14/12-bit 25Msps to 150Msps ADCs. Each assembly features one of the following devices: LTC2262-14 or LTC2262-12, LTC2261-14, LTC2261-12, LTC2260-14, LTC2260-12, LTC2259-14, LTC2259-12, LTC2258-14, LTC2258-12, LTC2257-14, LTC2257-12, LTC2256-14, LTC2256-12, high speed, high dynamic range ADCs. Demonstration circuit 1369A supports the LTC2261 family DDR LVDS output mode. This family of ADCs is also supported by demonstration circuit 1370A, which is compatible with CMOS and DDR CMOS output modes. Performance Summary Several versions of the 1369A demo board supporting the LTC2261 14/12-bit series of A/D converters are listed in Table 1. Depending on the required resolution and sample rate, the DC1369A is supplied with the appropriate ADC. The circuitry on the analog inputs is optimized for analog input frequencies from 5MHz to 170MHz. Refer to the data sheet for proper input networks for different input frequencies. Design files for this circuit board are available at http://www.linear.com/demo L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope and QuikEval are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. (TA = 25C) Table 1 PARAMETER CONDITION VALUE Supply Voltage - DC1369A Depending on sampling rate and the A/D converter provided, this supply must provide up to 250mA Optimized for 3.6V 3.5V 6.0V Min/Max Analog Input Range Depending on SENSE Pin Voltage 1VP-P to 2VP-P Logic Input Voltages Minimum Logic High 1.3V Maximum Logic Low 0.6V Nominal Logic Levels (100 Load, 3.5mA Mode) 350mV/1.25V Common Mode Minimum Logic Levels (100 Load, 3.5mA Mode) 247mV/1.25V Common Mode Logic Output Voltages (Differential) Sampling Frequency (Convert Clock Frequency) See Table 1 Convert Clock Level Single-Ended Encode Mode (ENC - Tied to GND) 0V to 3.6V Convert Clock Level Differential Encode Mode (ENC - Not Tied to GND) 0.2V to 3.6V Resolution See Table 1 Input Frequency Range See Table 1 SFDR See Applicable Data Sheet SNR See Applicable Data Sheet dc1369af 1 DEMO MANUAL DC1369A Quick Start Procedure Table 2. DC1369A Variants DC1369A VARIANTS ADC PART NUMBER RESOLUTION MAXIMUM SAMPLE RATE INPUT FREQUENCY 1369A-A LTC2261-14 14-Bit 125Msps 5MHz to 170MHz 1369A-B LTC2260-14 14-Bit 105Msps 5MHz to 170MHz 1369A-C LTC2259-14 14-Bit 80Msps 5MHz to 170MHz 1369A-D LTC2258-14 14-Bit 65Msps 5MHz to 170MHz 1369A-E LTC2257-14 14-Bit 40Msps 5MHz to 170MHz 1369A-F LTC2256-14 14-Bit 25Msps 5MHz to 170MHz 1369A-G LTC2261-12 12-Bit 125Msps 5MHz to 170MHz 1369A-H LTC2260-12 12-Bit 105Msps 5MHz to 170MHz 1369A-I LTC2259-12 12-Bit 80Msps 5MHz to 170MHz 1369A-J LTC2258-12 12-Bit 65Msps 5MHz to 170MHz 1369A-K LTC2257-12 12-Bit 40Msps 5MHz to 170MHz 1369A-L LTC2256-12 12-Bit 25Msps 5MHz to 170MHz 1369A-M LTC2262-14 14-Bit 150Msps 5MHz to 170MHz 1369A-N LTC2262-12 12-Bit 150Msps 5MHz to 170MHz Demonstration circuit 1369A is easy to set up to evaluate the performance of the LTC2262 family of A/D converters. Refer to Figure 1 for proper measurement equipment setup and follow the procedure below: Setup If a DC890 QuikEvalTM II Data Acquisition and Collection System was supplied with the DC1369A demonstration circuit, follow the DC890 Quick Start Guide to install the required software and for connecting the DC890 to the DC1369A and to a PC. Applying Power and Signals to the DC1369A Demonstration Circuit If a DC890 is used to acquire data from the DC1369A, the DC890 must first be connected to a powered USB port or provided an external 6V to 9V before applying 3.6V to 6.0V across the pins marked V+ and GND on the DC1369A. DC1369A requires 3.6V for proper operation. Regulators on the board produce the voltages required for the ADC. The DC1369A demonstration circuit requires up to 250mA depending on the sampling rate and the A/D converter supplied. The DC1369A demonstration circuit board should have the following jumper settings as default positions (as per Figure 1): The DC890 data collection board is powered by the USB cable and does not require an external power supply unless it must be connected to the PC through an unpowered hub, in which case it must be supplied an external 6V to 9V on turrets G7(+) and G1(-) or the adjacent 2.1mm power jack. JP2: PAR/SER: Selects Parallel or Serial programming mode. (Default - Serial) Analog Input Network DC1369A Demonstration Circuit Board Jumpers JP3: Duty Cycle Stabilizer: Enables/Disable Duty Cycle Stabilizer. (Default - Enable) JP4: SHDN: Enables and disables the LTC2262 (Default - Enable) For optimal distortion and noise performance the RC network on the analog inputs may need to be optimized for different analog input frequencies. For input frequencies above 170MHz, refer to the LTC2262 data sheet for a proper input network. Other input networks may be more appropriate for input frequencies less that 5MHz. dc1369af 2 DEMO MANUAL DC1369A quick start procedure 3.5V to 6V + Jumpers Are Shown in Default Positions Analog Input Parallel Data Output to DC890 Parallel/Serial Programming Mode Duty Cycle Stabilizer DC1369A F01 SHDN Single-Ended Encode Clock Figure 1. DC1369A Setup dc1369af 3 DEMO MANUAL DC1369A quick start procedure In almost all cases, filters will be required on both analog input and encode clock to provide data sheet SNR. In the case of the DC1369A a bandpass filter used for the clock should be used prior to the DC1075A. The filters should be located close to the inputs to avoid reflections from impedance discontinuities at the driven end of a long transmission line. Most filters do not present 50 outside the passband. In some cases, 3dB to 10dB pads may be required to obtain low distortion. If your generator cannot deliver full-scale signals without distortion, you may benefit from a medium power amplifier based on a Gallium Arsenide Gain block prior to the final filter. This is particularly true at higher frequencies where IC based operational amplifiers may be unable to deliver the combination of low noise figure and High IP3 point required. A high order filter can be used prior to this final amplifier, and a relatively lower Q filter used between the amplifier and the demo circuit. Encode Clock NOTE: Apply an encode clock to the SMA connector on the DC1369A demonstration circuit board marked J7. As a default the DC1369A is populated to have a singleended input. For the best noise performance, the encode input must be driven with a very low jitter, square wave source. The amplitude should be large, up to 3VP-P or 13dBm. When using a sinusoidal signal generator a squaring circuit can be used. Linear Technology also provides demo board DC1075A that divides a high frequency sine wave by four, producing a low jitter square wave for best results with the LTC2262 family. Using bandpass filters on the clock and the analog input will improve the noise performance by reducing the wideband noise power of the signals. In the case of the DC1369A a bandpass filter used for the clock should be used prior to the DC1075A. Data sheet FFT plots are taken with 10 pole LC filters made by TTE (Los Angeles, CA) to suppress signal generator harmonics, non harmonically related spurs and broadband noise. Low phase noise Agilent 8644B generators are used with TTE bandpass filters for both the clock input and the analog input. Apply the analog input signal of interest to the SMA connectors on the DC1369A demonstration circuit board marked J5 AIN+. These inputs are capacitive coupled to Balun transformers ETC1-1-13. An internally generated conversion clock output is available on J1 which could be collected via a logic analyzer, or other data collection system if populated with a SAMTEC MEC8-150 type connector or collected by the DC890 QuikEval II Data Acquisition Board using PScopeTM software. dc1369af 4 DEMO MANUAL DC1369A quick start procedure Software Manual Configuration settings: The DC890 is controlled by the PScope System Software provided or downloaded from the Linear Technology website at http://www.linear.com/software/. If a DC890 was provided, follow the DC890 Quick Start Guide and the instructions below. Bits: 14 (or 12 for 12-bit parts) To start the data collection software if PScope.exe is installed (by default) in \Program Files\LTC\PScope\, double click the PScope Icon or bring up the run window under the start menu and browse to the PScope directory and select PScope. Bipolar: Checked If the DC1369A demonstration circuit is properly connected to the DC890, PScope should automatically detect the DC1369A, and configure itself accordingly. If necessary the procedure below explains how to manually configure PScope. Alignment: 14 FPGA Ld: DDR LVDS Channs: 2 Positive-Edge Clk: Checked If everything is hooked up properly, powered and a suitable convert clock is present, clicking the Collect button should result in time and frequency plots displayed in the PScope window. Additional information and help for PScope is available in the DC890 Quick Start Guide and in the online help available within the PScope program itself. Under the Configure menu, go to "ADC Configuration...." Check the Config Manually box and use the following configuration options (see Figure 2): Figure 2. ADC Configuration dc1369af 5 DEMO MANUAL DC1369A quick start procedure Serial Programming PScope has the ability to program the DC1369A board serially through the DC890. There are several options available in the LTC2262 family that are only available through serially programming. PScope allows all of these features to be tested. These options are available by first clicking on the Set Demo Bd Options icon on the PScope toolbar (Figure 3). This will bring up the menu shown in Figure 4. This menu allows any of the options available for the LTC2262 family to be programmed serially. The LTC2262 family has the following options: Power Control: Selects between normal operation, nap, and sleep modes * Normal (Default): Entire ADC is powered, and active * Nap: ADC core powers down while references stay active * Shutdown: The entire ADC is powered down Clock Inversion: Selects the polarity of the CLKOUT signal * Normal (Default): Normal CLKOUT polarity Figure 3. PScope Toolbar * Inverted: CLKOUT polarity is inverted Clock Delay: Selects the phase delay of the CLKOUT signal * None (Default): No CLKOUT delay * 45 deg: CLKOUT delayed by 45 degrees * 90 deg: CLKOUT delayed by 90 degrees * 135 deg: CLKOUT delayed by 135 degrees Clock Duty Cycle: Enable or Disables Duty Cycle Stabilizer * Stabilizer Off (Default): Duty cycle stabilizer disabled * Stabilizer On: Duty cycle stabilizer enabled Output Current: Selects the LVDS output drive current * 1.75mA (Default): LVDS output driver current * 2.1mA: LVDS output driver current * 2.5mA: LVDS output driver current Figure 4. Demo Board Configuration Options * 3.0mA: LVDS output driver current * 3.5mA: LVDS output driver current * 4.0mA: LVDS output driver current * 4.5mA: LVDS output driver current dc1369af 6 DEMO MANUAL DC1369A quick start procedure Internal Termination: Enables LVDS Internal Termination Alternate Bit: Alternate Bit Polarity (ABP) Mode * Off (Default): Disables internal termination * Off (Default): Disables alternate bit polarity * On: Enables internal termination * On: Enables alternate bit polarity (Before enabling ABP, be sure the part is in offset binary mode) Outputs: Enables Digital Outputs * Enabled (Default): Enables digital outputs Randomizer: Enables Data Output Randomizer * Disabled: Disables digital outputs * Off (Default): Disables data output randomizer Output Mode: Selects Digital Output Mode * Full Rate: Full rate CMOS output mode (This mode is not supported by the DC1369A, please use the DC1370) * Double LVDS (Default): Double data rate LVDS output mode * Double CMOS: Double data rate CMOS output mode (This mode is not supported by the DC1369A, please use the DC1370) * On: Enables data output randomizer Two's Complement: Enables Two's Complement Mode * Off (Default): Selects offset binary mode * On: Selects two's complement mode Once the desired settings are selected hit OK and PScope will automatically update the register of the device on the DC1369A demo board. Test Pattern: Selects Digital Output Test Patterns * Off (Default): ADC data presented at output * All Out = 1: All digital outputs are 1 * All Out = 0: All digital outputs are 0 * Checkerboard: OF, and D13-D0 Alternate between 101 0101 1010 0101 and 010 1010 0101 1010 on alternating samples. * Alternating: Digital outputs alternate between all 1's and all 0's on alternating samples. dc1369af 7 DEMO MANUAL DC1369A Parts List ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER 1 1 C1 RES, 0402 150 1% 1/16W VISHAY CRCW0402150RFKED 2 9 C2, C3, C6, C7, C38, C39, C59-C61 CAP, 0402 0.01uF 10% 16V X7R AVX 0402YC103KAT 3 2 C10, C9 CAP, 0402 8.2pF 5% 50V COG AVX 04025A8R2JAT2A 4 6 C12, C15, C18, C19, C21, C37 CAP, 0402 0.1uF 10% 10V X5R TDK C1005X5R1A104K 5 3 C13, C17, C23 CAP, 0402 1uF 10% 10V X5R TDK C1005X5R1A105K 6 2 C14, C22 CAP, 0603 1uF 10% 16V X7R TDK C1608X7R1C105K 7 1 C20 CAP, 0402 1uF 10% 10V X5R MURATA GRM155R61A105KE15D 8 1 C24 CAP, 0603 4.7uF 20% 6.3V X5R TDK C1608X5R0J475MT 9 12 C26-C36, C56 CAP, 0603 0.1uF 10% 50V X7R TDK C1608X7R1H104K 10 1 C51 CAP, 0402 4.7pF +/-0.25pF 50V NPO AVX 04025A4R7CAT2A 11 2 C53, C52 CAP, 0402 100pf 5% 50V COG TDK C1005C0G1H101J 12 2 C54, C55 CAP, 1206 22uF 10% 6.3V X5R AVX 12066D226KAT2A 13 7 R9, R10, R48, R54, R57, C57, C58 RES, 0402 0 JUMPER VISHAY CRCW04020000Z0ED 14 1 D1 DIODE, SCHOTTKY SOT-23 AVAGO HSMS-2822 15 3 JP2, JP3, JP4 HEADER, 3-PIN, 2mm SAMTEC TMM-103-02-L-S 16 3 J5, J7, J9 CONN, BNC, SMA 50 EDGE-LANCH E.F.JOHNSON, 142-0701-851 17 1 J8 HEADER, 2x7 2mm MOLEX 87331-1420 18 1 L1 IND, 0603 56uH 5% MURATA LQP18MN56NG02D 19 3 L2, L3, L4 FERRITE BEAD, 1206 MURATA BLM31PG330SN1L 20 1 L5 IND, 0603 BEAD ? 21 1 L6 IND, 0603 OPTION OPTION 22 1 P1 EDGE FINGERS ON PCB PART OF THE PCB 23 2 RN2, RN1 RES ARRAY, 33 VISHAY CRA04SS08333R0JTD 24 2 R1, R2 RES, 0402 301 1% 1/16W VISHAY CRCW0402301RFKED 25 3 R4, R5, R56 RES, 0402 OPTION OPTION 26 1 R6 RES, 0402 10k 5% 1/16W VISHAY CRCW040210K0JNED 27 1 R7 RES, 0402 10k 1% 1/16W VISHAY CRCW040210K0FKED 28 1 R8 RES, 0402 6.81k 1% 1/16W YAGEO RC0402FR-076K81L 29 4 R14, R33, R34, R35 RES, 0402 1k 5% 1/16W VISHAY CRCW04021K00JNTDE3 30 1 R16 RES, 0402 100 5% 1/16W VISHAY CRCW0402100RJNED 31 8 R17-R23, R30 RES, 0201 100 5% 1/16W VISHAY CRCW0201100RFNTD 32 1 R24 RES, 0402 100k 5% 1/16W VISHAY CRCW0402100KJNED 33 3 R25, R26, R29 RES, 0603 4.99k 1% 1/16W AAC CR16-4991FM 34 3 R36, R44, R45 RES, 0402 86.6 1% 1/16W VISHAY CRCW040286R6FKED 35 2 R40, R39 RES, 0402 24.9 1% 1/16W VISHAY CRCW040224R9FKED 36 0 R46, R49, R52, R53, R55 RES, 0402 OPTION VISHAY CRCW0402101J ? 37 1 R47 RES, 0402 20 1% 1/16W VISHAY CRCW040220R0FKED 38 1 R50 IND, 36nH COILCRAFT 0402CS-36NXJB 39 0 R51 RES, 0402 301 1% 1/16W OPTION VISHAY CRCW0402301RFKED OPTION 40 5 TP1, TP2, TP3, TP4, TP5 TURRETS MILLMAX 2501-2-00-80-00-00-07-0 41 1 T1 XFMR, 1:1 MACOM MABA-007159-000000 42 1 T2 XFMR, 1:1 CT M/A-C0M MABAES0060/COILCRAFT WBC1-1LB dc1369af 8 DEMO MANUAL DC1369A Parts List ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER 43 1 T3 XFMR, 1:4 CT COILCRAFT WBC4-1WLB 44 1 U1 IC, EEPROM MICROCHIP TECH. 24LC025-I/ST 45 1 U3 IC, FIN1108 FAIRCHILD FIN1108 46 1 U4 IC, LDO Micropower Regulators LINEAR TECH. LT1763CDE-1.8 47 1 U5 IC, 8-BIT I/0 EXPANDER PHILIPS SEMI PCF8574TS/3 48 1 U6 IC, LDO Micropower Regulators LINEAR TECH. LT1763CDE 49 1 U7 IC, EEPROM MICROCHIP TECH. 24LC32A-I/ST 50 3 XJP2, XJP3, XJP4 SHUNT, 2mm SAMTEC 2SN-BK-G 51 4 STANDOFF, SNAP ON KEYSTONE_8831 See page 2 of the Schematic Diagram for U2. dc1369af 9 A B C ENC- GND GND J9 J7 0.1uF C28 TP5 TP3 3.5V - 6V V+ 0.1uF TP2 TP4 2 4.7uF C24 OPT C1 0.1uF 0.1uF 1uF C22 1uF C14 VIN 0.01uF C60 OPT L6 C31 C30 C29 0.1uF C32 0.01uF C7 8 12 1 4 9 10 11 8 12 1 4 9 10 11 R57 0 GND BYP SENSE OUT OUT SHDN NC NC NC NC IN IN GND BYP SENSE OUT OUT U6 LT1763CDE SHDN NC NC NC NC IN IN U4 LT1763CDE-1.8 R53 OPT 2 7 6 5 2 3 7 6 5 2 3 C2 0.01uF R56 OPT 0.1uF 0.1uF 0.1uF 0.01uF C39 0.01uF C38 0.01uF C59 T3 WBC4-1WL VDD C36 C35 T2 MABAES0060 C34 D1 HSMS-2822 1 R50 36nH R47 0 0.1uF 0.1uF 0.1uF 0.1uF C33 C19 5 8.2pF C10 R44 86.6 1% 56uH T1 MABA-007159-000000 C18 8.2pF C9 R36 86.6 1% 0.01uF 1 C26 VOUT VDD J5 ENC+ GND AIN+ L1 2 1 R45 86.6 1% 3 C6 2 1 R2 301 1% 22uF C55 BEAD 4 R8 6.81K 1% VDD 1uF C13 C58 C57 2 2 VDD VDD PAR/SER REFL REFL REFH REFH GND AIN- AIN+ R55 OPT OPT R52 1 R51 OPT 1 OPT R49 C37 0.1uF VDD OVDD VOUT BEAD BEAD L4 L2 R54 0 R4 OPT 0.01uF C3 R7 10K 1% L3 C61 0.01uF R5 OPT R48 0 9 8 7 6 5 4 3 2 1 1uF C23 1uF C17 TP1 10 EXT REF VDD 1uF C20 4.7pF C51 PAR/SER 0.1uF C21 0.1uF C15 R10 0 R40 24.9 1% R46 OPT R1 301 1% 22uF C54 BEAD L5 0.1uF C12 R39 24.9 1% R9 0 GND 41 VDD 39 4 11 R14 1K R16 100 37 3 2 1 OX40 6 7 9 2 4 3 8 1 33 R33 1K A0 A1 A2 SCL SDA NC NC INT D8_9- D8_9+ R18 100 3 2 1 VDD OVDD 10 11 12 14 16 17 19 20 18 13 RN2 1 2 3 4 CS 3 33 8 7 6 5 R30 100 R19 100 R34 1K U2 * 3 DUTY CYCLE STAB. DIS EN 21 22 23 24 25 26 27 28 29 30 JP3 D4_5- D4_5+ D6_7- D6_7+ OGND OVDD CLKOUT- CLKOUT+ P0 P1 P2 P3 P4 P5 P6 P7 NC NC VOUT PAR/SER U5 PCF8574TS/3 PAR/SER SCL SDA SER PAR JP2 VDD 100 R17 32 D 2 1 2 1 2 1 2 1 40 VDD ENC+ 12 SENSE 38 VREF 13 ENC- 35 CS CS 36 OF+ VCM 14 SCK SCK 15 SDI SDI 16 SD0 OFSDO 31 D10_11- 34 D12_13+ D0_117 D12_1318 D10_11+ D2_319 D2_3+ 20 5 CS SCK SDI SD0 DIS EN VDD 3 2 1 R35 1K 10K R6 SHDN JP4 R20 100 VOUT SDI R21 100 R22 100 OXA2 R23 100 ENABLE VOUT VBB IN1IN1+ IN2+ IN2IN3IN3+ IN4+ IN4IN5IN5+ IN6+ IN6IN7IN7+ IN8+ IN8- EN12 EN34 EN56 EN78 EN 2 OUT1OUT1+ OUT2+ OUT2OUT3OUT3+ OUR4+ OUT4OUT5OUT5+ OUT6+ OUT6OUT7OUT7+ OUT8+ OUT8- C56 0.1uF VUNREG 5V J8 NC EEVCC EESDA EESCL EEGND RN1 1 2 3 4 33 APPROVALS 2 05/22/12 05:59:39 DESIGNER ENGINEER APPROVED CHECKED DRAWN MI 8 7 6 5 10/31/07 DATE +D12/D13 -D12/D13 +D10/D11 -D10/D11 +D8/D9 -D8/D9 +CLK -CLK +D6/D7 -D6/D7 +D4/D5 -D4/D5 +D2/D3 -D2/D3 +D0/D1 -D0/D0 VCC_IN VSS SCL SDA 45 44 43 42 41 40 39 38 35 34 33 32 31 30 29 28 CONTRACT NO. 14 10 9 11 12 6 4 7 5 1 2 U7 24LC32A-I/ST 8 A0 VCC 7 A1 WP 6 A2 SCL 5 A3 SDA CS SCK/SCL MOSI/SDA MISO 1 2 3 4 24 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 3 22 27 46 13 U3 FIN1108 GND GND GND 3 8 13 D0_1+ 5 VDD GND 15 12 25 26 47 48 VC1 VC2 VC3 VC4 VC5 VE1 VE2 VE3 VE4 VE5 10 1 2 23 36 37 This circuit is proprietary to Linear Technology and supplied for use with Linear Technology parts. Customer Notice:Linear Technology has made a best effort to design a circuit that meets customer-supplied specifications; however, it remains the customers responsibility to verify proper and reliable operation in the actual application, Component substitution and printed circuit board layout may significantly affect circuit performance or reliability. Contact Linear Applications Engineering for assistance. EDGE-CON-100 SDA VSS SCL R24 100K U1 24LC025-I/ST 8 A0 VCC 7 A1 WP 6 A2 SCL 5 A3 SDA TECHNOLOGY 1 2 3 4 C27 0.1uF 1% 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 Fax: (408)434-0507 R26 4.99K 1% SCL SDA R25 4.99K VSS VOUT SCALE:NONE DWG NO 1 SHEET DC1369A FILENAME: 1369A-3.DSN SIZE CAGE CODE 1 OF 2 3.1 REV SDA SCL VCC_IN ENABLE R29 4.99K 1% VCC_IN FAST DAACS BOARD ID CIRCUITRY 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 APPROVED Clarence M. SCH, LTC2261CUJ, HIGH SPEED LOW POWER 125MSPS ADC FAMILY, LVDS OXA0 100pF VCC_IN SDA SCL VSS C53 CS SCK SDI SD0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 P1 DATE 08/11/08 05/22/12 PROTO Change 3 100pF TITLE 1 REVISION HISTORY DESCRIPTION 3.1 REV C52 ECO A B C D DEMO MANUAL DC1369A Schematic Diagram dc1369af Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. A B C D 5 4 * LTC2261-14 LTC2160-14 LTC2259-14 LTC2258-14 LTC2257-14 LTC2256-14 LTC2261-12 LTC2260-12 LTC2259-12 LTC2258-12 LTC2257-12 LTC2256-12 LTC2262-14 LTC2262-12 -A -B -C -D -E -F -G -H -I -J -K -L -M -N 5 ADC ASSY 150Msps 150Msps 25Msps 40Msps 65Msps 80Msps 105Msps 125Msps 25Msps 40Msps 65Msps 80Msps 105Msps 125Msps SAMPLE RATE 12 14 12 12 12 12 12 12 14 14 14 14 14 14 4 No. of BITS This circuit is proprietary to Linear Technology and supplied for use with Linear Technology parts. Customer Notice:Linear Technology has made a best effort to design a circuit that meets customer-supplied specifications; however, it remains the customers responsibility to verify proper and reliable operation in the actual application, Component substitution and printed circuit board layout may significantly affect circuit performance or reliability. Contact Linear Applications Engineering for assistance. 5 < AIN < 170 5 < AIN < 170 5 < AIN < 170 5 < AIN < 170 5 < AIN < 170 5 < AIN < 170 5 < AIN < 170 5 < AIN < 170 5 < AIN < 170 5 < AIN < 170 5 < AIN < 170 5 < AIN < 170 5 < AIN < 170 5 < AIN < 170 FREQUENCY R APPROVALS 3 05/22/12 06:00:33 DESIGNER ENGINEER APPROVED CHECKED DRAWN MI 10/31/07 DATE TECHNOLOGY 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 Fax: (408)434-0507 1 SCALE:NONE 2 SHEET DC1369A FILENAME: 1369A-3.DSN DWG NO 1 2 OF SCH, LTC2261CUJ, HIGH SPEED LOW POWER 125MSPS ADC FAMILY, LVDS 2 SIZE CAGE CODE TITLE REPRESENTS STAND OFFS 1 X4 1 X3 1 X2 1 X1 USED TO MANUFACTURE PCB CONTRACT NO. 3 2 3.1 REV A B C D DEMO MANUAL DC1369A Schematic Diagram dc1369af 11 DEMO MANUAL DC1369A DEMONSTRATION BOARD IMPORTANT NOTICE Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions: This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations. If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user's responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive. Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer. Mailing Address: Linear Technology 1630 McCarthy Blvd. Milpitas, CA 95035 Copyright (c) 2004, Linear Technology Corporation dc1369af 12 Linear Technology Corporation LT 0612 * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com LINEAR TECHNOLOGY CORPORATION 2012