CY7C056V spec PRELIMINARY CY7C057V RESS 3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM Features . True Dual-Ported memory cells which allow simulta- neous access of the same memory location * 16K x 36 organization (CY7CO56V) * 32K x 36 organization (CY7C057V) * 0.25-micron CMOS for optimum speed/power High-speed access: 12/15/20 ns Low operating power Active: Igg = 195 mA (typical) Standby: Iggy = 10 pA (typical) Fully asynchronous operation Automatic power-down Expandable data bus to 72 bits or more using Mas- ter/Slave Chip Select when using more than one device On-Chip arbitration logic Semaphores included to permit software handshaking between ports INT flag for port-to-port communication Byte Select on Left Port Bus-Matching on Right Port Depth Expansion via dual-chip enables Pin select for Master or Slave Commercial and Industrial Temperature Ranges Compact package 144-Pin TQFP (20 x 20 x 1.4 mm) 144-Ball MiniBGA (.8 mm pitch) (12 x 12 x .51 mm) Logic Block Diagram RM Left CEo)- Port CE CE, Control OE, Logic VOo.-VOg, Og. -VO47L VO /O4g_-l/Ozer4 Control O57, -VO35)4 Address Decode (1 Aot-A13/14L Interrupt True Dual-Ported RAM Array Semaphore Arbitration RWr Right Port Control Logic Eor EiR OER BA WA 9/18/36 Op V/O Control BM SIZE Address Decode (1 Aor-Ai3/14R SEM, SEMp Bev! pnav BUSY, BUSY_ INTL. INT M/S Notes: 1. Ag-Ayg for 16K; ApAy, for 32K devices. 2. BUSY is an output in master mode and an input in slave mode. For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation + 3901 North First Street * SanJose + CA 95134 + 408-943-2600 February 23, 1999PHELIMINAAY CY7C056V CY7C057V (CYPRESS Functional Description The CY7CO56V and CY7057V are low-power CMOS 16K and 32K x 36 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are pro- vided permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be uti- lized as stand-alone 36-bit dual-port static RAMs or multiple devices can be combined in order to function as a 72-bit or wider master/slave dual-port static RAM. An M/S pin is provid- ed for implementing 72-bit or wider memory applications with- out the need for separate master and slave devices or addi- tional discrete logic. Application areas include interprocessor/multiprocessor designs, communications sta- tus buffering, and dual-port video/graphics memory. Note: 3. CE is LOW when CE) < Vj, and CE, 2 Viy. Each port has independent control pins: Chip Enable (CE)I, Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt Flag (INT) permits communication be- tween ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (sema- phore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic Power-Down feature is controlled independently on each port by Chip Select (CE, and CE,) pins. The CY7CO56V and CY7057V are available in 144-Pin Thin Quad Plastic Flatpacks (TQFP) and 144-Ball Mini-Ball Grid Array (MiniBGA).Pin Configurations VO32L VO31L GND PHELIMINAAY CY7C056V CY7C057V VO30L V/O29L VO28L VO27L voc VO17L VO16L 144-Pin Thin Quad Flatpack (TQFP) VO15L VO14L GND Top View GND VO14R VO15R VO16R VO17R voc 027R /028R \O29R O30R GND VO31R 032R 144 143 142 /O33L /034L (O33. == AOLD 2 AaL_ Co <r a ON ooh wnhm BE j-=-- oO RRS c| _ @ 290 <2 PSLLSRAZZeegHaAVem Al ssAgaqg>zes PFPePoPNPFPLP PAA Ae-Fooonn ree DOHOwYWwWAwWH WWONNNMNNNHNNNNNZAZZHZSZHZ BABA SBABAH HHO Oak won] CO WDNO OF WON HOO WAN DOA WNM = 0 GND VvO21L a aN Nw O90 =S Notes: 4. 5. This pin is A14L for CY7CO057V. This pin is A14R for CY7C057V. 144 140 139 138 137 136 135 134 133 132 VO20L VvO19L VO18L voc VO8L VO7L reanrmnowowOs HOANAAAA rrrr re ee TT 121 120 119 118 CY7CO56V (16K x 36) CY7C057V (32K x 36) VO5L GND VO4L VO3L VvOo2L VOL GND VO5R V/O6R VO7R V/O8R 417 116 115 voc VO18R 414 VO19R 113 O20R VO21R 112 444 GND O22R V/023R 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 i] 1/033R ] /034R ] 1/035R AOR AIR A2R ABR T] A4R i] A5R ASR i} AZR _] BM i] Size I] WA )_ Ai0R ] AiR i7 A12R [- Ai3R iI andi c]_ /026R )S1/025R 1/024RPHELIMINAAY CY7C056V CY7C057V Pin Configurations (continued) 144-Ball Mini-Ball Grid Array (MiniBGA) Top View 1 2 3 4 5 6 7 8 9 10 11 #12 #13 A VO32L | /O30L | VCC | VO15L} 1V/O13L} OIL | /O9R |1/011R}1/O13R}V/O15R] VCC | I/O30R]/O32R B AOL | I/O33L | /O29L | /O17L | VO14L | /O12L} VOSL |1/012R | 1/O14R | 1/017R | /O29R | /O33R] AOR Cc A4L A1L |I/O31L] GND | 1/027L]} GND |I/O10R} GND |1/027R} GND |I/O31R] AIR A4R D AZL ASL | I/O35L | /O34L | /O28L | /O16L} /O10L | I/O16R | I/O28R | 1/034R | /O35R] ASR A7R E B2 Bo A38L A2L A2R A3R BM WA F OEL B3 BY A6L A6R | SIZE BA OER G GND | VCC | GND | RAWL RAWR | voc | vec | GND H CEOL | CE1L | SEML| A8L A8R | SEMR] CE1R | CEOR I WS | INTL | A11L | A12L A12R | A11R | INTR | VCC J BUSYL| A9L | /O26L | VO25L | VO19L| VO7L | VO1L | O7R |/O19R|VO25R]O26R} ASR |BUSYR K AOL | A13L | i/O22L} GND | 1/018L] GND | I/O1R | GND |1/O18L] GND |I/O22R] A13R | A10R L GND] vo24L | vo20L | vosL | VOSL | VO3L | VOOL | /O3R | V/O5R | VO8R | /O20R| /024R] GNDE! M VO23L | VO21L| VCC | VO6L | VO4L | /O2L | VOOR | /O2R | /O4R | OBR | VCC |1/021R]/O23RCY7C056V Pae PRELIMINARY CY7C057V a Selection Guide CY7CO56V CY7CO56V CY7CO56V CY7C057V CY7C057V CY7C057V -12 -15 -20 Maximum Access Time (ns) 12 15 20 Typical Operating Current (mA) 195 190 180 Typical Standby Current for lgp, (mA) (Both Ports TTL level) 55 50 45 Typical Standby Current for lgpg (uA) (Both Ports CMOS level) 10 pA 10 pA 10 nA Pin Definitions Left Port Right Port Description AoLA13/14L Aor-Ai3/14R Address (ApAy3 for 16K; ApAy4 for 32K devices) SEM, SEMp Semaphore Enable CEo,, CEq, CEorn, CEir Chip Enable (CE is LOW ihen CE < Vy, and CE, = Viy) INT, INTR Interrupt Flag BUSY, BUSYpR Busy Flag Oo. -VOgz5. VOon/Oz5R Data Bus Input/Output OE, OER Output Enable AM, RWp; Read/Write Enable Bo-B3 Byte Select Inputs. Asserting these signals enables read and write oper- ations to the corresponding bytes of the memory array. BM, SIZE See Bus Matching for details. WA, BA See Bus Matching for details. M/S Master or Slave Select GND Ground Voc Power Maximum Ratings DC Input Voltage ......cccceeseeeee sees -0.5V to Voc +0.5V!4 Output Current into Outputs (LOW)... eeeeeeeeeeeees 20 mA (Above which the useful life may be impaired. For user guide- lines, not tested.) Static Discharge Voltage 0.0... eee eters >2001V Storage Temperature vcauaecaueaueaeeuacacuauurenunane -65C to +150C Latch-Up 070g - 10 | ee >200 mA Ambient Temperature with : Power Applied ........ecceecesesseeeeesneeeeneeeeneees 55C to +125C Operating Range Supply Voltage to Ground Potential ............... 0.5V to +4.6V Ambient . Range Temperature Vec DC Voltage Applied to - S S Outputs in High Z State... -0.5V to Voc +0.5V Commercial OC to +70C 3.3V + 150 mV Industrial 40C to +85C 3.3V + 150 mV Note: 6. Pulse width < 20 ns.CY7C056V pete PRELIMINARY CY7C057V Electrical Characteristics Over the Operating Range | ! CY7CO56V CY7C057V -12 -15 20 Symbol Parameter Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | Units Vou Output HIGH Voltage (Vec=Min, Igy=-4.0mA) | 2.4 2.4 2.4 Vv VoL Output LOW Voltage (Vec=Min, Io. = +4.0mA) 0.4 0.4 0.4 Vv Vin Input HIGH Voltage 2.2 2.2 2.2 V Vit Input LOW Voltage 0.8 0.8 0.8 Vv loz Output Leakage Current -10 10 | -10 10 | -10 10 HA loc Operating Current (Vec=Max, Com'l. 195 | 300 190 | 280 180 | 265 mA lour=0 mA) Outputs Disabled indust. 215 | 305 205 | 290 | mA Ispi Standby Current (Both Ports TTL Com'l. 55 | 75 50 | 70 45 | 65 mA Level and Deselected) f=fMax Indust. 65 95 60 90 mA Ispo Standby Current (One Port TTL Com'l. 125 | 190 120 | 180 110 | 160) mA Level and Deselected) f=fax Indust. 135 | 205 125 | 185 | mA Isp3 Standby Current (Both Ports CMOS | Com'l. 0.01 | 1 0.01 1 0.01 1 mA Level and Deselected) f=0 Indust. 0.01 1 0.01 1 mA Ispa Standby Current (One Port CMOS | Com'l. 115 | 170 110 | 160 100 | 140] mA Level and Deselected) f=fyax! Tagust 125 | 175 115 | 155 | mA Shaded areas contain advanced information. Capacitance! Parameter Description Test Conditions Max. Unit Cin Input Capacitance Ta = 25C, f = 1 MHz, 10 pF - Veco =3.3V Cout Output Capacitance 10 pF AC Test Load and Waveforms 3.3V Z)=502 R=500 OUTPUT R1 = 5900 ol OUTPUT = Voy = 1.5V C =5pF 4 P R2 = 4350 (a) Normal Load (Load 1) (b) Three-State Delay (Load 2) = 3.0V ALLINPUT PULSES GND Notes: 7. Cross Levels are Voc - 0.2V< Vz<0.2V. 8. Deselection for a port occurs if CEg is HIGH or if CE, is LOW. 9. fax = t/tRc = All inputs cycling at f = 1/tae (except Output Enable). f= 0 means no address or control lines change. This applies only to inputs at CMOS level standby Iga3. 10. Tested initially and after any design or process changes that may affect these parameters. 11 . Test Conditions: C = 10 pF.CY7C056V et PRELIMINARY CY7C057V CYPRESS Switching Characteristics Over the Operating Rangel'2! CY7CO56V CY7C057V -12 15 20 Parameter Description Min. Max. Min. Max. Min. Max. Unit Read Cycle tac Read Cycle Time 12 15 20 ns tAA Address to Data Valid 12 15 20 ns toHA Output Hold From Address Change 3 3 3 ns tace 19) CE LOW to Data Valid 12 15 20 ns too OE LOW to Data Valid 10 12 ns tizoc 4 1 161 | OE Low to Low Z 0 0 0 ns tuzoc 14 1% 161 | OE HIGH to High Z 10 10 12 ns tice? 1% 1 14 | CE LOW to Low Z 3 3 3 ns tuzce 14 1514 | CE HIGH to High Z 10 10 12 ns tLZ7BE Byte Enable to Low Z 3 3 3 ns tuzBE Byte Enable to High Z 10 10 12 ns tpy 141 CE LOW to Power-Up 0 0 ) ns tpp 141 CE HIGH to Power-Down 12 15 20 ns tape!) Byte Enable Access Time 12 15 20 ns Write Cycle twe Write Cycle Time 12 15 20 ns tgoe? 151 CE LOW to Write End 10 12 15 ns taw Address Valid to Write End 10 12 15 ns tua Address Hold From Write End 0 0 0 ns tgal!9) Address Set-Up to Write Start 0 0 0 ns tpwe Write Pulse Width 10 12 15 ns tsp Data Set-Up to Write End 10 10 15 ns tub Data Hold From Write End 0 0 0 ns tuzwell 141 R/W LOW to High Z 10 10 12 ns tzwel! 141 R/W HIGH to Low Z 3 3 3 ns twoo!! Write Pulse to Data Delay 25 30 45 ns topo! Write Data Valid to Read Data Valid 20 25 30 ns Busy Timing!" tBLa BUSY LOW from Address Match 12 15 20 ns teHa BUSY HIGH from Address Mismatch 12 15 20 ns tac BUSY LOW from CE LOW 12 15 20 ns tpHc BUSY HIGH from CE HIGH 12 15 20 ns Notes: 12. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified lovloy and 30-pF load capacitance. __ 13. To access RAM, CE=L and SEM=H. To access semaphore, CE=H and SEMEL. Either condition must be valid for the entire tgog time. 14. Atany given temperature and voltage condition for any given device, tyzoe is less than tLzce and tyzo. is less than t_zoE- 15. Test conditions used are Load 2. 16. This parameter is guaranteed by design, but it is not production tested.For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 17. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 18. Test conditions used are Load 1.CY7C056V PDO Pee PRELIMINARY CY7C057V CYPRESS Switching Characteristics Over the Operating Rangel'2! (continued) CY7CO56V CY7C057V -12 15 20 Parameter Description Min Max. Min Max. Min. Max. Unit tps Port Set-Up for Priority 5 5 5 ns twe R/W LOW after BUSY (Slave) 0 0 0 ns twu RW HIGH after BUSY HIGH (Slave) 14 13 15 ns tappl"! BUSY HIGH to Data Valid 12 15 20 ns Interrupt Timing!'l tins INT Set Time 12 15 20 ns tinr INT Reset Time 12 15 20 ns Semaphore Timing tsop SEM Flag Update Pulse (OE or SEM) 10 10 10 ns tswro SEM Flag Write to Read Time ns tsps SEM Flag Contention Window ns toaa SEM Address Access Time 12 15 20 ns Data Retention Mode Timing The CY7CO056V and CY7057V are designed with battery back- upin mind. Data retention voltage and supply current are guar- anteed over temperature. The following rules ensure data re- tention: 1. Chip Enable (CE)P must be held HIGH during data retention, within Voc to Voc -0.2V. 2. CE must be kept between Vcc 0.2V and 70% of Veo during the power-up and power-down transitions. 3. The RAM can begin operation >tpo after Voc reaches the minimum operating voltage (3.15 volts). Notes: 3.15V Data Retention Mode Vec > 2.0V Vee to Vee - 0.2V 3.15V Parameter Test Conditions! Max. Unit ICCpri @ VCCpp =2V 50 uA 19. tgpp is acalculated parameter and is the greater of twoptpwe (actual) or tgpptgp (actual). 20. CE=Veoc, Vin = GND to Veg, Ta = 25C. This parameter is guaranteed but not tested.CY7CO056V pec PHELIMINAAY CY7C057V Switching Waveforms Read Cycle No. 1 (Either Port Address Access)!*": 22, 23] a: tac > ADDRESS * * ant pe tonn > te tona DATA OUT PREVIOUS DATA VALID *K x x DATA VALID x x Read Cycle No. 2 (Either Port CE/OE Access)": 24, 25] tacE 0. CE}, By.B,} CE, a SELECT VALID Bo, Bz, WA, __ tpoe OE tHZOE tLZOE DATA OUT DATA VALID tLZcE tey < I cc CURRENT | 7 SB tpp Read Cycle No. 3 (Either Port)!?!) 23. 24, 25] < tac al ADDRESS _ x <____ tna Bo, By, Bo, B,, WA, BA BYTE SELECTIVALID tLZcE taBE CE, CE, CHIP|SELECT VALID DATA OUT Notes: 21. RAWis HIGH for read cycles. 22. Device is continuously selected. CEg = Vj_, CEy=Vjy, and Bo, By, Bs, Bs, WA, BA are valid. This waveform cannot be used for semaphore reads. 23. OE = ViL- 24. Address valid prior to or coinciding with CE transition LOW and CE; transition HIGH.. 25. To access RAM, CEg =V\_, CE;=Viy, Bo, By, Bo, Bg, WA, BA are valid, and SEM = Vj. To access semaphore, CE = Viy, CEy=Vi_ and SEM= Vj, or CEy and SEM=V, and CEy= Bg = By = Bo = Bg, =Viy.CY7CO056V PHELIMINAAY CY7C057V Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing! 2/28: 29! nt twe > ADDRESS * xK % TNL taw > CE,, CEB? 311 >< CHIP SELECT VALID xX e toa $$$$_____ tpw_ 29 ie tua RAV A t [32] ee THZWE" -<_ tzwe ~} DATA OUT < NOTE 33 ore 5 Ne p__ tgp ae-_ tH DATA IN Write Cycle No. 2: CE Controlled Timing!? 27, 2. 34] , twe ADDRESS * a: taw > CE,, CE, 31] CHIP SELECT VALID x < toa tsce tha RAW \ / ea tsp ate ty DATA IN Notes: 26. R/W must be HIGH during all address transitions. _ _ _ 27. Awrite occurs during the overlap (tgog or tpwe) of CEp=Vi_ and CEy=Vjy or SEM=V)_ and Bp_3 LOW. 28. ty, is measured from the earlier of CE9/CE, or RW or (SEM or RW) going HIGH at the end of Write Cycle. 29. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of toye or (Iuzye + tgp) to allow the I/O drivers to turn off and data to be placed on the bus for the required tgp. If OE is HIGH during an RW controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tpye. 30. To access RAM, CEg = Vi, CEy=SEM = Vip. 31. To access byte By, CE9 = Vi, By = Vi, CE=SEM = Vip. To access byte By, CE) = Vj,, By = Vi_, CEy=SEM = Vjy. To access byte Bo, CEg = Vi, Bo = Vi_, CEy=SEM = Vip. To access byte Bg, CE = Vj, Bg = Vi_, CEy=SEM = Vjy. 32. Transition is measured +150 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested. 33. During this period, the I/O pins are in the output state, and input signals must not be applied. 34. If the CEg LOW and CE, HIGH or SEM LOW transition occurs simultaneously with or after the RAW LOW transition, the outputs remain in the high-impedance state. 10CY7C056V pac PRELIMINARY CY7C057V Switching Waveforms (continued) Semaphore Read After Write Timing, Either Sidel?5] < tsaa> toHA works KOK amas KX KKK _wrmnenes KX XXX t<__ tay >! : [ACE t . SEM eee HA Ne is LW on OZ tsp V0 0 DATA VALID ) DATA yr VALID 7 tu > tsa tpwe > RAV T] L Y +~<_| tswapD + tboE > __ if A SAL AA J J. J > Vv, AZZ SAR / jua WRITE CYCLE pg_ READ CYCLE _}, Timing Diagram of Semaphore Contention 37, 36] op Aay MATCH x tsps Aon Aor MATCH x Notes: 35. CE g=HIGH and CE,=LOW for the duration of the above timing (both write and read cycle). 36. 1/OoR = Og, = LOW (request semaphore); CEgR=CE 9. =HIGH and CEy_=CE,, =LOW. 37. Semaphores are reset (available to both ports) at cycle start. 38. If tgpg is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable. 11PHELIMINAAY Switching Waveforms (continued) Timing Diagram of Write with BUSY (M/S=HIGH)*! CY7C056V CY7C057V in) twe > ADDRESS, * MATCH *K RW, < tpwe > R N\ Wn N teg__. ts). pteaep THD DATA IN., * *K VALID tps ADDRESS, * MATCH ~ BLA = <> toHA BUSY, K tapD > DATA on *K VALID at. twob > Write Timing with Busy Input (M/S=LOW) _ tpwe RAW < t t BUSY WB WH Note: 39. CEo. = CEor = LOW; CEL = CEiR= HIGH 12= CY7CO056V CYPRESS PRELIMINARY CY7C057V Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration)!40! CE, Valid First: ADDRESS, , x ADDRESS MATCH x CEo., CEy CHIP SELECT VALID 4 i- tps CEon, CEin CHIP SELECTIVALID taLe e t3HC BUSY , CE, Valid First: ADDRESS, , x ADDRESS MATCH x CEL, CEy. CHIP SELECT VALID Ke tps 2 CEon, CEin CHIP SELECT|VALID taLe tpHc BUSY Busy Timing Diagram No. 2 (Address Arbitration)!0! Left Address Valid First: tac or two 4+ ADDRESS, ADDRESS MATCH *K ADDRESS MISMATCH x ~ tps ADDRESS, x tBLA f itBHa BUSY Right Address Valid First: tac oF two. > ADDRESS, ADDRESS MATCH *K ADDRESS MISMATCH x tps ADDRESS, x < iBLA t BHA BUSY L Note: 40. If tpg is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.CY7C056V Pae PRELIMINARY CY7C057V ak ke OE Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INT, : < twe > ADDRESS, *K WRITE 3FFF (7FFF for CY7C057V) KX tual CEoL, CE, x CHIP SELECT VALID RW, aN IN INT, Right Side Clears INT, : fe tg 421 __S N k tec READ oFFF ADDRESS, (7FFF for CY7C057V) Eon: CEin ME CHIP SELECT VALID x <$<_____ tnrl42] a y OF, WNXK SY N / INT, / Right Side Sets INT_: two ADDRESS, *K WRITE 3FFE (7FFE for CY7C057V) Kx x Tar CEop, CE1a * CHIP SELECT VALID RW, aN N\ INT, 42 se je ty 2 Left Side Clears INT, : j# tro READ Sere ADDRESS, (7FFF for CY7C057V) CE, ,CEy, K CHIP SELECT VALID x tiyql42];. ______ RW, / / / / av4 OE, \\ XN aN / INT 7 Notes: 41. tya depends on which enable pin (CE9/CEy,_ or R/W/) is deasserted first. 42. ting OF tur depends on which enable pin (CE,/CE4, or R/W) is asserted last.PHELIMINAAY CY7C056V CY7C057V Architecture The CY7C056V and CY7057V consist of an array of 16K and 32K words of 36 bits each of dual-port RAM cells, I/O and address lines, and control signals (CEp/CE,, OE, RAW). These control pins permit independent access for reads or writes to any lo- cation in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two Interrupt (INT) pins can be utilized for port-to-port communication. Two Semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are out- puts) or as a slave (BUSY pins are inputs). The devices also have an automatic power-down feature controlled by CE)/CE,. Each port is provided with its own Output Enable Control (OE), which allows data to be read from the device. Functional Description Write Operation Data must be set up for a duration of tgp before the rising edge of RW in order to guarantee a valid write. A write operation is con- trolled by either the R/W pin (see Write Cycle No. 1 waveform) or the CE and CE, pins (see Write Cycle No. 2 waveform). Required inputs for non-contention operations are summarized in Table 7. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; other- wise the data read is not deterministic. Data will be valid on the port tppp after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CEE! pins. Data will be available tace after CE or tpo after OE is asserted. If the user wishes to access a semaphore flag, then the SEM pin mustbe asserted instead of the CES pin, and QE must also be asserted. Interrupts The upper two memory locations may be used for message passing. The highest memory location (3FFF for the CY7CO056V, 7FFF for the CY7C057V) is the mailbox for the right port and the second-highest memory location (3FFE for the CY7CO56V, 7FFE for the CY7C057V) is the mailbox for the left port. When one port writes to the other ports mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other ports mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processors interrupt request input pin. The operation of the interrupts and their interaction with Busy are summarized in Table 2. Busy The CY7CO56V and CY7057V provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports Chip Enables!l are asserted and an address match occurs within tps of each other, the busy logic will determine which 15 port has access. If tpg is violated, one port will definitely gain permis- sion to the location, but it is not predictable which port will get that permission. BUSY will be asserted tp 4 after an address match or tic after CE is taken LOW. Master/Slave A M/S pinis provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tg) or tg, a), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin al- lows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Semaphore Operation The CY7C056V and CY7057V provide eight semaphore latch- es, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports. The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero toa semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tgop before attempting to read the semaphore. The semaphore value will be available tgwrp + tpoE after the rising edge of the semaphore write. If the left port was suc- cessful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relin- quished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches. For normal semaphore access, CEP! must remain HIGH during SEM LOW. A CE active semaphore access is also available. The semaphore may be accessed through the right port with CEpp/CE,p active by assert- ting the Bus Match Select (BM) pin LOW and asserting the Bus Size Select (SIZE) pin HIGH. The semaphore may be accessed through the left port with CE9,/CE,, active by asserting all By_g Byte Select pins HIGH. Ag_ represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no ef- fect. When writing to the semaphore, only |/Opg is used. If a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the port showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both ports. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3shows sample semaphore operations. When reading a semaphore, data lines 0 through 8 output the semaphore value. The read value is latched in an output reg- ister to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tgps of each other, the semaphore will defintely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.CY7C056V pad PRELIMINARY CY7C057V Table 1. Non-Contending ReadMWrite!l Inputs Outputs CE | RW | OE Bo, By, Bo, Bg SEM VO gWVO55 Operation H Xx X X H High Z Deselected: Power-Down Xx Xx Xx AllH H High Z Deselected: Power-Down L L X H/L H Data In and High Z Write to Selected Bytes Only L L X AllL H Data In Write to All Bytes L H L H/L H Data Out and High Z Read Selected Bytes Only L H L AllL H Data Out Read All Bytes Xx Xx H X X High Z Outputs Disabled H H L X L Data Out Read Data in Semaphore Flag X H L AllH L Data Out Read Data in Semaphore Flag H xX xX L Data In Write Dino into Semaphore Flag Xx re Xx All H L Data In Write Dj into Semaphore Flag L Xx X Any L L Not Allowed Table 2. Interrupt Operation Example (assumes BUSY, =BUSY,=HIGH): 43] Left Port Right Port Function RW, | CE, | OE, Ag-13. INT, | RW, | CER | OER Aor_13R INTp Set Right INTp Flag L L xX 3FFF xX xX x x x L}5] Reset Right INTp Flag xX xX xX xX xX xX L L 3FFF HI44I Set Left INT, Flag xX xX xX xX L4) L L x 3FFE x Reset Left INT, Flag X L L 3FFE HII | x X X X X Table 3. Semaphore Operation Example Function V/Oo-/Og Left | 1/Og-l/Og Right Status No Action 1 1 Semaphore Free Left Port Writes 0 to Semaphore 0 1 Left Port Has Semaphore Token Right Port Writes 0 to 0 1 No Change. Right Side Has No Write Access to Semaphore Semaphore Left Port Writes 1 to Semaphore 1 0 Right Port Obtains Semaphore Token Left Port Writes 0 to Semaphore 1 0 No Change. Left Port Has No Write Access to Semaphore Right Port Writes 1 to 0 1 Left Port Obtains Semaphore Token Semaphore Left Port Writes 1 to Semaphore 1 1 Semaphore Free Right Port Writes 0 to 1 0 Right Port Has Semaphore Token Semaphore Right Port Writes 1 to 1 1 Semaphore Free Semaphore Left Port Writes 0 to Semaphore 0 1 Left Port Has Semaphore Token Left Port Writes 1 to Semaphore 1 1 Semaphore Free Notes: 43. AoL-14L and AoR-14R> 7FFF/7FFE for the CY7CO57V. 44. If BUSYp,=L, then no change. 45. If BUSY_=L, then no change. 16== CY7CO56V lO eS PRELIMINARY CY7C057V Right Port Configuration | 47. 4! BM SIZE Configuration I/O Pins Used 0 0 x36 (Standard) /Oo_35 0 1 x36 (CE Active SEM Mode) /O9_35 1 0 x18 /Oo_17 1 1 x9 /Oo_8 Right Port Operation Configuration WA BA Data Accessed!*! 1/0 Pins Used x36 X X DQo_235 1/O9_35 x18 0 x DQo_17 V/Oo_17 x18 1 Xx DQig 35 V/Oo_17 x9 0 0 DQo-8 I/Oo_g x9 0 1 DQg9_47 /Oo_g x9 1 0 DQi2 96 /Oo_g x9 1 1 DQo57_35 /Oo_g Left Port Operation Control Pin Effect Bo 1/Op_g Byte Control Bi /Og_47 Byte Control B2 1/049 96 Byte Control B3 1/O57_35 Byte Control Notes: 46. BM and SIZE must be configured one clock cycle before operation is guaranteed. 47. In x36 mode WA and BA pins are Don't Care. 48. In x18 mode BA pin is a Don't Care. 49. DQ represents data output of the chip. 17PHELIMINAAY CY7C056V CY7C057V (CYPRESS Bus Match Operation The right port of the CY7C057V 32Kx36 dual-port SRAM can be configured in a 36-bit long-word, 18-bit word, or 9-bit byte format for data I/O. The data lines are divided into four lanes, each consisting of 9 bits (byte-size data lines). BA WA CY7CO056V CY7C057V 16K/32Kx36 Dual Port x36 x9, x18, x36 BUS MODE BM SIZE The Bus Match Select (BM) pin works with Bus Size Select (SIZE) to select bus width (long-word, word, or byte) for the right port of the dual-port device. The data sequencing ar- rangement is selected using the Word Address (WA) and Byte Address (BA) input pins. A logic 0 applied to both the Bus Match Select (BM) pin and to the Bus Size Select (SIZE) pin will select long-word (36-bit) operation. A logic 1 level applied to the Bus Match Select (BM) pin will enable either byte or word bus width operation on the right port I/Os depending on the logic level applied to the SIZE pin. The level of Bus Match Select (BM) must be static throughout device operation. Normally, the Bus Size Select (SIZE) pin would have no stan- dard-cycle application when BM = LOW and the device is in long-word (36-bit) operation. A special mode has been add- ed however to disable ALL right port I/Os while the chip is active. This I/O disable mode is implemented when SIZE is forced to a logic 1 while BM is at a logic O. It allows the bus-matched port to support a chip enable dont care sema- phore read/write access similar to that provided on the left port of the device when all Byte Select (Bp_3) control inputs are deselected. The Bus Size Select (SIZE) pin selects either a byte or word data arrangement on the right port when the Bus Match Select (BM) pin is HIGH. A logic 1 on the SIZE pin when the BM pin is HIGH selects a byte bus (9-bit) data arrangement). A logic OQ on the SIZE pin when the BM pin is HIGH selects a word bus (18-bit) data arrangement. The level of the Bus Size Select (SIZE) must also be static throughout normal device operation. Note: Long-Word (36-bit) Operation Bus Match Select (BM) and Bus Size Select (SIZE) set to a logic O will enable standard cycle long-word (36-bit) opera- tion. In this mode, the right ports I/O operates essentially in an identical fashion as does the left port of the dual-port SRAM. However no Byte Select control is available. All 36 bits of the long-word are shifted into and out of the right ports I/O buffer stages. All read and write timing parameters may be identical with respect to the two data ports. When the right port is con- figured for a long-word size, Word Address (WA), and Byte Address (BA) pins have no application and their inputs are Don't Carel for the external user. Word (18-bit) Operation Word (18-bit) bus sizing operation is enabled when Bus Match Select (BM) is set to a logic 1 and the Bus Slze Select (SIZE) pin is set to a logic O. In this mode, 18 bits of data are ported through I/Ogp_47R- The level applied to the Word Address (WA) pin during word bus size operation determines whether the most-significant or least-significant data bits are ported through the l/Opp_17R pins in an Upper Word/Lower Word se- lect fashion (note that when the right port is configured for word size operation, the Byte Address pin has no application and its input is Dont Care 50) Device operation is accomplished by treating the WA pin as an additional address input and using standard cycle address and data setup/hold times. When transferring data in word (18-bit) bus match format, the unused |/O;gp_35p pins are tristated. Byte (9-bit) Operation Byte (9-bit) bus sizing operation is enabled when Bus Match Select (BM) is set to a logic 1 and the Bus Size Select (SIZE) pin is set to a logic 1. In this mode, data is ported through /Oor_gr in four groups of 9-bit bytes. A particular 9-bit byte group is selected according to the levels applied to the Word Address (WA) and Byte Address (BA) input pins. /0s Rank WA BA /(O27R_-35R Upper-MSB 1 1 /OigR-26R Lower-MSB 1 0 /Ogp_17R Upper-MSB 0 1 /Oor-8R Lower-MSB 0 0 Device operation is accomplished by treating the Word Ad- dress (WA) pin and the Byte Address (BA) pins as additional address inputs having standard cycle address and data set- up/hold times. When transferring data in byte (9-bit) bus match format, the unused I/Ogp_35p pins are three-stated. 50. Even though a logic level applied to a Don't Care input will not change the logical operation of the dual-port, inputs that are temporarily a Don't Care (along with unused inputs) must not be allowed to float. They must be forced either HIGH or LOW. 18CY7C056V meee PRELIMINARY CY7C057V ESS Ordering Information Speed Package Operating (ns) Ordering Code Name Package Type Range 12 CY7C056V-12AC A144 144-Pin Thin Quad Flat Pack Commercial CY7C056V12BAC BA144 144-Ball mini-Ball Grid Array (BGA) Commercial 15 CY7C056V-15AC A144 144-Pin Thin Quad Flat Pack Commercial CY7C056V-15Al A144 144-Pin Thin Quad Flat Pack Industrial CY7C056V15BAC BA144 144-Ball Mini-Ball Grid Array (BGA) Commercial CY7CO56V-15BAl BA144 144-Ball Mini-Ball Grid Array (BGA) Industrial 20 CY7C056V-20AC A144 144-Pin Thin Quad Flat Pack Commercial CY7CO056V-20Al A144 144-Pin Thin Quad Flat Pack Industrial CY7C056V-20BAC BA144 144-Ball Mini-Ball Grid Array (BGA) Commercial CY7CO56V-20BAl BA144 144-Ball Mini-Ball Grid Array (BGA) Industrial Speed Package Operating (ns) Ordering Code Name Package Type Range 12 CY7C057V-12AC A144 144-Pin Thin Quad Flat Pack Commercial CY7C057V-12BAC BA144 144-Ball Mini-Ball Grid Array (BGA) Commercial 15 CY7C057V-15AC A144 144-Pin Thin Quad Flat Pack Commercial CY7C057V15Al A144 144-Pin Thin Quad Flat Pack Industrial CY7C057V-15BAC BA144 144-Ball Mini-Ball Grid Array (BGA) Commercial CY7C057V-15BAl BA144 144-Ball Mini-Ball Grid Array (BGA) Industrial 20 CY7C057V-20AC A144 144-Pin Thin Quad Flat Pack Commercial CY7C057V-20AI A144 144-Pin Thin Quad Flat Pack Industrial CY7C057V-20BAC BA144 144-Ball Mini-Ball Grid Array (BGA) Commercial CY7C057V-20BAl BA144 144-Ball Mini-Ball Grid Array (BGA} Industrial Document #: 38-00742 19CY7CO056V PHELIMINAAY CY7C057V Package Diagrams 144-Pin Plastic Thin Quad Flat Pack (TQFP) A144 22.0020.100 SQ DIMENSIONS ARE IN MILLIMETERS. 0.2220.05 2 YP. R 0.08 MIN. 0 MIN. 020 MAX. STAND-OFF TN 0.05 MIN. 015 MAX GAUGE PLANE ' R 0.08 MIN. oz SEATING PLANE tare 0.20 MAX. 8x) 0.20 MIN. ris MAX. 9.602015 L. t 1.00 REF be , 4s i f DETAILA 51-B5047-A 020 MAX. [~ {4020.05 SEE DETAIL A 20CY7CO056V PRELIMINARY CY7C057V Package Diagrams (continued) 144-Ball Mini Ball Grid Array BA144 BOTTOM VIEW pin 1 CORNER 4 [e010 (S96 } ac.25 Scale] Fil 1 CORNER BO.S0+D.05(144x) 12 34 5 6 7 2 9 19 1I1Z 15 is121110 9 & cope ey, TOP VIEW i i ql A Poorer parnonos A B | my mom re Om moo oO B c oo oOoogooo ooo c oO moO m OG Dp oa mm mo oO oO E a ooand onoag E F ct o momo mmm oO F a ref a - - sy + -_ A | 4 G6 4 oS 85 a Cl 4 | H 5 pPoan ooog H c J 7 4) tp Om m O J i oO moO Oop oom oo Oo i ie) re a ym L o a ee) L M | DOCODOoOpPAOoBooOo9 M H eBeooo0on 1 Yom | i me H | Les | L [=8- aaa w 2 3.60 Ss : a = . ta} 12.004 0,20 a { [=] 0.2004) [ | oe a 5 = [:=) SEATING PLAHE 2 we 51-85104 m Me x & co s # oo Cl cl Con * THE BALL DIAMETER, BALL PITCH, STAMD-OFF & PACEAGE THIChMESS ARE DIFFERENT FROM JEDEC SPEC MOTS2 (LOW PROFILE BGA FAMILY) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. 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