TISP4xxxM3BJ Overvoltage Protector Series
TISP4070M3BJ THRU TISP4115M3BJ,
TISP4125M3BJ THRU TISP4220M3BJ,
TISP4240M3BJ THRU TISP4400M3BJ
BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS
*RoHS COMPLIANT
Device Symbol
ITU-T K.20/21/44/45 rating ................ 4 kV 10/700, 100 A 5/310
Ion-Implanted Breakdown Region
Precise and Stable Voltage
Low Voltage Overshoot under Surge
SMBJ Package (Top View)
Description
These devices are designed to limit overvoltages on the telephone line. Overvoltages are normally caused by a.c. power system or lightning
flash disturbances which are induced or conducted on to the telephone line. A single device provides 2-point protection and is typically used
for the protection of 2-wire telecommunication equipment (e.g. between the Ring and Tip wires for telephones and modems). Combinations of
devices can be used for multi-point protection (e.g. 3-point protection between Ring, Tip and Ground).
The protector consists of a symmetrical voltage-triggered bidirectional thyristor. Overvoltages are initially clipped by breakdown clamping until
the voltage rises to the breakover level, which causes the device to crowbar into a low-voltage on state. This low-voltage on state causes the
current resulting from the overvoltage to be safely diverted through the device. The high crowbar holding current helps prevent d.c. latchup as
the diverted current subsides.
Device VDRM
V
V(BO)
V
‘4070 58 70
‘4080 65 80
‘4095 75 95
‘4115 90 115
‘4125 100 125
‘4145 120 145
‘4165 135 165
‘4180 145 180
‘4200 155 200
‘4220 160 220
‘4240 180 240
‘4250 190 250
‘4265 200 265
‘4290 220 290
‘4300 230 300
‘4350 275 350
‘4360 290 360
‘4395 320 395
‘4400 300 400
Low Differential Capacitance ................................. 39 pF max.
............................................ UL Recognized Component
®
12
T(A)
R(B)
MDXXBGE
T
R
SD4XAA
Terminals T and R correspond to the
alternative line designators of A and B
Wave Shape Standard ITSP
A
2/10 μs GR-1089-CORE 300
8/20 μs IEC 61000-4-5 220
10/160 μs FCC Part 68 120
10/700 μs ITU-T K.20/21/45 100
10/560 μs FCC Part 68 75
10/1000 μs GR-1089-CORE 50
How To Order
Device Package Carrier
TISP4xxxM3BJ BJ (J-Bend DO-214AA/SMB) Embossed Tape Reeled
TISP4xxxM3BJR-S
Insert xxx value corresponding to protection voltages of 070, 080, 095, 115, etc.
Order As
NOVEMBER 1997 - REVISED MAY 2007
*RoHS Directive 2002/95/EC Jan. 27, 2003 including Annex.
Specifications are subject to change without notice. Users should verify actual device performance in their specific
applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the
last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
WARNING Cancer and Reproductive Harm
www.P65Warnings.ca.gov
The TISP4xxxM3BJ range consists of nineteen voltage variants to meet various maximum system voltage levels (58 V to 320 V). They are
guaranteed to voltage limit and withstand the listed international lightning surges in both polarities. These medium (M) current protection
devices are in a plastic package SMBJ (JEDEC DO-214AA with J-bend leads) and supplied in embossed tape reel pack. For alternative
voltage and holding current values, consult the factory. For higher rated impulse currents in the SMB package, the 100 A 10/1000
TISP4xxxH3BJ series is available.
TISP4xxxM3BJ Overvoltage Protector Series
Description (continued)
Absolute Maximum Ratings, TA = 25 °C (Unless Otherwise Noted)
tinUeulaVlobmySgnitaR
Repetitive peak off-state voltage, (see Note 1)
‘4070
‘4080
‘4095
‘4115
‘4125
‘4145
‘4165
‘4180
‘4200
‘4220
‘4240
‘4250
‘4265
‘4290
‘4300
‘4350
‘4360
‘4395
‘4400
V
DRM
± 58
± 65
± 75
± 90
±100
±120
±135
±145
±155
±160
±180
±190
±200
±220
±230
±275
±290
±320
±300
V
Non-repetitive peak on-state pulse current (see Notes 2, 3 and 4)
I
TSP
A
2/10 μs (GR-1089-CORE, 2/10 μ003)epahs evaw egatlov s
8/20 μ022)tnerruc 02/8 ,egatlov 05/2.1 ,rotareneg evaw noitanibmoc ,5-4-0001
6 CEI(s
10/160 μs(FCC Part 68, 10/160μ021)epahs evaw egatlov s
5/200 μs (VDE 0433, 10/700 μ011)epahs evaw egatlov s
0.2/310 μs (I3124, 0.5/700 μ001)epahs evaw egatlov s
5/310 μs (ITU-T K.20/21/45, K.44 10/700 μ001)ep
ahs evaw egatlov s
5/310 μs (FTZ R12, 10/700 μ001)epahs evaw egatlov s
10/560 μs (FCC Part 68, 10/560 μ57)epahs evaw egatlov s
10/1000 μs (GR-1089-CORE, 10/1000 μ05)epahs evaw egatlov s
Non-repetitive peak on-state current (see Notes 2, 3 and 5)
I
TSM
30
32
2.1
A
20 ms (50 Hz) full sine wave
16.7 ms (60 Hz) full sine wave
1000 s 50 Hz/60 Hz a.c.
Initial rate of rise of on-state current, Exponential current ramp, Maximum ramp value < 100 A di
T
/dt 300 A/μs
Junction temperature T
J
-40 to +150 °C
Storage temperature range T
stg
-65 to +150 °C
NOTES: 1. See Applications Information and Figure 11 for voltage values at lower temperatures.
2. Initially, the TISP4xxxM3BJ must be in thermal equilibrium with T
J
=25°C.
3. The surge may be repeated after the TISP4xxxM3BJ returns to its initial conditions.
4. See Applications Information and Figure 12 for current ratings at other temperatures.
5. EIA/JESD51-2 environment and EIA/JESD51-3 PCB with standard footprint dimensions connected with 5 A rated printed wiring
track widths. See Figure 9 for the current ratings at other durations. Derate current values at -0.61 %/°C for ambient temperatures
above 25 °C.
NOVEMBER 1997 - REVISED MAY 2007
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TISP4xxxM3BJ Overvoltage Protector Series
Electrical Characteristics, TA = 25 °C (Unless Otherwise Noted)
tinUxaMpyTniMsnoitidnoC tseTretemaraP
IDRM
Repetitive peak off-
state current VD = VDRM
TA = 25 °C
TA = 85 °C
±5
±10 μA
V(BO) Breakover voltage dv/dt = ±250 V/ms, R SOURCE =300Ω
‘4070
‘4080
‘4095
‘4115
‘4125
‘4145
‘4165
‘4180
‘4200
‘4220
‘4240
‘4250
‘4265
‘4290
‘4300
‘4350
‘4360
‘4395
‘4400
±70
±80
±95
±115
±125
±145
±165
±180
±200
±220
±240
±250
±265
±290
±300
±350
±360
±395
±400±342
V
V(BO)
Impulse breakover
voltage
dv/dt ≤±1000 V/μs, Linear voltage ramp,
Maximum ramp value = ±500 V
di/dt = ±20 A/μs, Linear current ramp,
Maximum ramp value = ±10 A
‘4070
‘4080
‘4095
‘4115
‘4125
‘4145
‘4165
‘4180
‘4200
‘4220
‘4240
‘4250
‘4265
‘4290
‘4300
‘4350
‘4360
‘4395
‘4400
±78
±88
±102
±122
±132
±151
±171
±186
±207
±227
±247
±257
±272
±298
±308
±359
±370
±405
±410
V
I(BO) Breakover current dv/dt = ±250 V/ms, R SOURCE = 300 Ω±0.15 ±0.6 A
A
VTOn-state voltage IT=±5A, t
W= 100 μs±3V
IHHolding current I T=±5A, di/dt=+/-30mA/ms ±0.15 ±0.35 A
dv/dt Critical rate of rise of
off-state voltage Linear voltage ramp, Maximum ramp value < 0.85VDRM ±5kV/μs
IDOff-state current VD=±TV05 A = 85 °C±10 μ
NOVEMBER 1997 - REVISED MAY 2007
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
Thermal Characteristics
TISP4xxxM3BJ Overvoltage Protector Series
Electrical Characteristics, TA = 25 °C (Unless Otherwise Noted)
Coff Off-state capacitance
f=1MHz, V
d=1V rms, V
D=0,
f=1MHz, V
d=1V rms, V
D=-1V
f=1MHz, V
d=1V rms, V
D=-2V
f=1MHz, V
d=1V rms, V
D=-50V
f=1MHz, V
d=1V rms, V
D=-100V
(see Note 6)
4070 thru ‘4115
‘4125 thru ‘4220
‘4240 thru ‘4400
‘4070 thru ‘4115
‘4125 thru ‘4220
‘4240 thru ‘4400
‘4070 thru ‘4115
‘4125 thru ‘4220
‘4240 thru ‘4400
‘4070 thru ‘4115
‘4125 thru ‘4220
‘4240 thru ‘4400
‘4125 thru ‘4220
‘4240 thru ‘4400
83
62
50
78
56
45
72
52
42
36
26
19
21
15
100
74
60
94
67
54
87
62
50
44
31
22
25
18
pF
NOTE 6: To avoid possible voltage clipping, the ‘4125 is tested with VD=-98V.
tin
UxaMpyTniMsnoitidnoC tseTretemaraP
tinUxaMpyTniMsnoitidnoC tseTretemaraP
RθJA Junction to free air thermal resistance
EIA/JESD51-3 PCB, IT = ITSM(1000),
TA = 25 °C, (see Note 7) 115
°C/W
265 mm x 210 mm populated line card,
4-layer PCB, IT = ITSM(1000), TA = 25 °C52
NOTE 7: EIA/JESD51-2 environment and PCB has standard footprint dimensions connected with 5 A rated printed wiring track widths.
NOVEMBER 1997 - REVISED MAY 2007
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TISP4xxxM3BJ Overvoltage Protector Series
Parameter Measurement Information
Figure 1. Voltage-Current Characteristic for T and R Terminals
All Measurements are Referenced to the R Terminal
-v VDRM
IDRM
VD
IH
IT
VT
ITSM
ITSP
V(BO)
I(BO)
ID
Quadrant I
I
Switching
Characteristic
+v
+i
V(BO)
I(BO)
VD
ID
IH
IT
VT
ITSM
ITSP
-i
Quadrant III
Switching
Characteristic PMXXAAB
VDRM
IDRM
NOVEMBER 1997 - REVISED MAY 2007
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TISP4xxxM3BJ Overvoltage Protector Series
Typical Characteristics
Figure 2.
OFF-STATE CURRENT
vs
JUNCTION TEMPERATURE
T
J - Junction Temperature - °C
-25 0 25 50 75 100 125 150
|ID| - Off-State Current - μA
0·001
0·01
0·1
1
10
100 TCMAG
VD = ±50 V
Figure 3.
NORMALIZED BREAKOVER VOLTAGE
vs
JUNCTION TEMPERATURE
TJ - Junction Temperature - °C
-25 0 25 50 75 100 125 150
Normalized Breakover Voltage
0.95
1.00
1.05
1.10 TC4MAF
Figure 4.
ON-STATE CURRENT
vs
ON-STATE VOLTAGE
VT - On-State Voltage - V
0.7 1.5 2 3 4 5 71110
IT - On-State Current - A
1.5
2
3
4
5
7
15
20
30
40
50
70
1
10
100
TA = 25 °C
tW
= 100 μs
TC4MACA
'4240
THRU
'4400
'4125
THRU
'4200
'4070
THRU
'4115
Figure 5.
NORMALIZED HOLDING CURRENT
vs
JUNCTION TEMPERATURE
T
J - Junction Temperature - °C
-25 0 25 50 75 100 125 150
Normalized Holding Current
0.4
0.5
0.6
0.7
0.8
0.9
1.5
2.0
1.0
TC4MAD
NOVEMBER 1997 - REVISED MAY 2007
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TISP4xxxM3BJ Overvoltage Protector Series
Typical Characteristics
Figure 6.
NORMALIZED CAPACITANCE
vs
OFF-STATE VOLTAGE
VD - Off-state Voltage - V
0.5 1 2 3 5 10 20 30 50 100 150
Capacitance Normalized to V
D = 0
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
TJ =
Vd = 1 Vrms
TC4MABB
'4240 THRU '4400
'4125 THRU '4220
'4070 THRU '4115
25 °C
Figure 7.
DIFFERENTIAL OFF-STATE CAPACITANCE
vs
RATED REPETITIVE PEAK OFF-STATE VOLTAGE
VDRM - Repetitive Peak Off-State Voltage - V
50 60 70 80 90 150 200 250 300 350100
ΔC - Differential Off-State Capacitance - pF
20
25
30
35
40
ΔC = Coff (-2 V ) - Coff (-50 V)
TCMAEB
Figure 8.
TYPICAL CAPACITANCE ASYMMETRY
vs
OFF-STATE VOLTAGE
V
D
— Off-State Voltage — V
0.5 0.7 2 3 4 5 7 20 30 4050011
|C
off(+VD)
- C
off(-VD)
| — Capacitance Asymmetry — pF
0
1
2
3
V
d
= 1 V rms, 1 MHz
V
d
= 10 mV rms, 1 MHz
TC4XBB
NOVEMBER 1997 - REVISED MAY 2007
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TISP4xxxM3BJ Overvoltage Protector Series
Rating and Thermal Information
Figure 10.
THERMAL IMPEDANCE
vs
POWER DURATION
t - Power Duration - s
0·1 1 10 100 1000
ZθA(t) - Transie nt Thermal Impedance - °C/W
4
5
6
7
8
9
15
20
30
40
50
60
70
80
90
150
10
100
TI4MAE
ITSM(t) APPLIED FOR TIME t
EIA/JESD51-2 ENVIRONMENT
EIA/JESD51-3 PCB
TA = 25 °C
Figure 9.
CURRENT DURATION
t - Current Duration - s
0·1 1 10 100 1000
ITSM(t) - Non-Repetitive Peak On-State Current - A
1.5
2
3
4
5
6
7
8
9
15
20
30
10
TI4MAC
VGEN = 600 Vrms, 50/60 Hz
RGEN = 1.4*VGEN /ITSM(t)
EIA/JESD51-2 ENVIRONMENT
EIA/JESD51-3 PCB
TA = 25 °C
Figure 11.
VDRM DERATING FACTOR
vs
MINIMUM AMBIENT TEMPERATURE
T
AMIN - Minimum Ambient Temperature - °C
-35 -25 -15 -5 5 15 25-40 -30 -20 -10 0 10 20
Derating Factor
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1.00 TI4MADA
'4125 THRU '4200
'4240 THRU '4400
'4070 THRU '4115
Figure 12.
IMPULSE RATING
vs
AMBIENT TEMPERATURE
T
A - Ambient Temperature - °C
-40-30-20-10 0 1020304050607080
Impulse Current - A
40
50
60
70
80
90
100
120
150
200
250
300
400
IEC 1.2/50, 8/20
ITU-T 10/700
FCC 10/560
BELLCORE 2/10
BELLCORE 10/1000
FCC 10/160
TC4MAA
NOVEMBER 1997 - REVISED MAY 2007
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TISP4xxxM3BJ Overvoltage Protector Series
These devices are two terminal overvoltage protectors. They may be used either singly to limit the voltage between two conductors (Figure 13)
or in multiples to limit the voltage at several points in a circuit (Figure 14).
APPLICATIONS INFORMATION
Deployment
Impulse Testing
To verify the withstand capability and safety of the equipment, standards require that the equipment is tested with various impulse wave forms.
The table below shows some common values.
Figure 13. Two Point Protection
Th1
Figure 14. Multi-Point Protection
Th3
Th2
Th1
In Figure 13, protector Th1 limits the maximum voltage between the two conductors to ±V(BO). This configuration is normally used to protect
circuits without a ground reference, such as modems. In Figure 14, protectors Th2 and Th3 limit the maximum voltage between each conduc-
tor and ground to the ±V(BO) of the individual protector. Protector Th1 limits the maximum voltage between the two conductors to its ±V(BO)
value. If the equipment being protected has all its vulnerable components connected between the conductors and ground, then protector Th1
is not required.
Standard
Peak Voltage
Setting
V
Voltage
Wave Shape
Peak Current
Value
A
Current
Wave Shape
TISP4XXXM3
25 °C Rating
A
Series
Resistance
GR-1089-CORE 2500 2/10 500 2/10 300 11
1000 10/1000 100 10/1000 50
FCC Part 68
(March 1998)
1500 10/160 200 10/160 120 2x5.6
800 10/560 100 10/560 75 3
1500 9/720 † 37.5 5/320 † 100 0
1000 9/720 † 25 5/320 † 100 0
I3124 1500 0.5/700 37.5 0.2/310 100 0
ITU-T K.20/K.21 1500
4000 10/700 37.5
100 5/310 100 0
† FCC Part 68 terminology for the waveforms produced by the ITU-T recommendation K.21 10/700 impulse generator
If the impulse generator current exceeds the protector’s current rating, then a series resistance can be used to reduce the current to the
protector’s rated value to prevent possible failure. The required value of series resistance for a given waveform is given by the following
calculations. First, the minimum total circuit impedance is found by dividing the impulse generator’s peak voltage by the protector’s rated
current. The impulse generator’s fictive impedance (generator’s peak voltage divided by peak short circuit current) is then subtracted from the
minimum total circuit impedance to give the required value of series resistance.
For the FCC Part 68 10/560 waveform, the following values result. The minimum total circuit impedance is 800/75 = 10.7 Ω and the generator’s
fictive impedance is 800/100 = 8 Ω. This gives a minimum series resistance value of 10.7 - 8 = 2.7 Ω. After allowing for tolerance, a 3 Ω ±10%
resistor would be suitable. The 10/160 waveform needs a standard resistor value of 5.6 Ω per conductor. These would be R1a and R1b in
Figure 16 and Figure 17. FCC Part 68 allows the equipment to be non-operational after the 10/160 (conductor to ground) and 10/560 (inter-
conductor) impulses. The series resistor value may be reduced to zero to pass FCC Part 68 in a non-operational mode, e.g. Figure 15. For this
type of design, the series fuse must open before the TISP4xxxM3 fails. For Figure 15, the maximum fuse i2t is 2.3 A2s. In some cases, the
equipment will require verification over a temperature range. By using the rated waveform values from Figure 12, the appropriate series resistor
value can be calculated for ambient temperatures in the range of -40 °C to 85 °C.
NOVEMBER 1997 - REVISED MAY 2007
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
The protector characteristic off-state capacitance values are given for d.c. bias voltage, VD, values of 0, -1 V, -2 V and -50 V. Where possible
values are also given for -100 V. Values for other voltages may be calculated by multiplying the VD = 0 capacitance value by the factor given in
Figure 6. Up to 10 MHz, the capacitance is essentially independent of frequency. Above 10 MHz, the effective capacitance is strongly
dependent on connection inductance. In many applications, such as Figure 16 and Figure 18, the typical conductor bias voltages will be about
-2 V and -50 V. Figure 7 shows the differential (line unbalance) capacitance caused by biasing one protector at -2 V and the other at -50 V.
Figure 8 shows the typical capacitance asymmetry; the difference between the capacitance measured with a positive value of VD and the
capacitance value when the polarity of VD is reversed. Capacitance asymmetry is an important parameter in ADSL systems where the
protector often has no d.c. bias and the signal level is in the region of ±10 V.
The protector can withstand currents applied for times not exceeding those shown in Figure 9. Currents that exceed these times must be
terminated or reduced to avoid protector failure. Fuses, PTC (Positive Temperature Coefficient) thermistors and fusible resistors are overcurrent
protection devices which can be used to reduce the current flow. Protective fuses may range from a few hundred milliamperes to one ampere.
In some cases, it may be necessary to add some extra series resistance to prevent the fuse opening during impulse testing. The current versus
time characteristic of the overcurrent protector must be below the line shown in Figure 9. In some cases, there may be a further time limit
imposed by the test standard (e.g. UL 1459 wiring simulator failure).
TISP4xxxM3BJ Overvoltage Protector Series
AC Power Testing
Capacitance
Normal System Voltage Levels
The protector should not clip or limit the voltages that occur in normal system operation. For unusual conditions, such as ringing without the
line connected, some degree of clipping is permissible. Under this condition, about 10 V of clipping is normally possible without activating the
ring trip circuit.
Figure 11 allows the calculation of the protector VDRM value at temperatures below 25 °C. The calculated value should not be less than the
maximum normal system voltages. The TISP4265M3BJ, with a VDRM of 200 V, can be used for the protection of ring generators producing
100 V rms of ring on a battery voltage of -58 V (Th2 and Th3 in Figure 18). The peak ring voltage will be 58 + 1.414*100 = 199.4 V. However,
this is the open circuit voltage and the connection of the line and its equipment will reduce the peak voltage. In the extreme case of an
unconnected line, clipping the peak voltage to 190 V should not activate the ring trip. This level of clipping would occur at the temperature
when the VDRM has reduced to 190/200 = 0.95 of its 25 °C value. Figure 11 shows that this condition will occur at an ambient temperature of
-28 °C. In this example, the TISP4265M3BJ will allow normal equipment operation provided that the minimum expected ambient temperature
does not fall below -28 °C.
JESD51 Thermal Measurement Method
To standardize thermal measurements, the EIA (Electronic Industries Alliance) has created the JESD51 standard. Part 2 of the standard
(JESD51-2, 1995) describes the test environment. This is a 0.0283 m3 (1 ft3) cube which contains the test PCB (Printed Circuit Board)
horizontally mounted at the center. Part 3 of the standard (JESD51-3, 1996) defines two test PCBs for surface mount components; one for
packages smaller than 27 mm on a side and the other for packages up to 48 mm. The SMBJ measurements used the smaller 76.2 mm x
114.3 mm (3.0 “ x 4.5 “) PCB. The JESD51-3 PCBs are designed to have low effective thermal conductivity (high thermal resistance) and
represent a worst case condition. The PCBs used in the majority of applications will achieve lower values of thermal resistance, and can
dissipate higher power levels than indicated by the JESD51 values.
NOVEMBER 1997 - REVISED MAY 2007
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TISP4xxxM3BJ Overvoltage Protector Series
Typical Circuits
Figure 15. Modem Inter-Wire Protection
FUSE
TISP4350
AI6XBMA
RING DETECTOR
HOOK SWITCH
D.C. SINK
SIGNAL
MODEM
RING
TIP
Figure 16. PROTECTION MODULE
R1a
R1b
RING
WIRE
TIP
WIRE
Th3
Th2
Th1
PROTECTED
EQUIPMENT
E.G. LINE CARD
AI6XBK
Figure 17. ISDN Protection
R1a
R1b
Th3
Th2
Th1
AI6XBL
SIGNAL
D.C.
Figure 18. Line Card Ring/Test Protection
TEST
RELAY
RING
RELAY
SLIC
RELAY
TEST
EQUIP-
MENT RING
GENERATOR
S1a
S1b
R1a
R1b
RING
WIRE
TIP
WIRE
Th3
Th2
Th1
Th4
Th5
SLIC
SLIC
PROTECTION
RING/TEST
PROTECTION
OVER-
CURRENT
PROTECTION
S2a
S2b
S3a
S3b
VBAT
C1
220 nF
AI6XBJ
TISP6xxxx,
TISPPBLx,
TISP6NTP2
NOVEMBER 1997 - REVISED MAY 2007
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TISP4xxxM3BJ Overvoltage Protector Series
Device Symbolization Code
Devices will be coded as below. As the device parameters are symmetrical, terminal 1 is not identified.
Device Symbolization
Code
TISP4070M3BJ 4070M3
TISP4080M3BJ 4080M3
TISP4095M3BJ 4095M3
TISP4115M3BJ 4115M3
TISP4125M3BJ 4125M3
TISP4145M3BJ 4145M3
TISP4165M3BJ 4165M3
TISP4180M3BJ 4180M3
TISP4200M3BJ 4200M3
TISP4220M3BJ 4220M3
TISP4240M3BJ 4240M3
TISP4250M3BJ 4250M3
TISP4265M3BJ 4265M3
TISP4290M3BJ 4290M3
TISP4300M3BJ 4300M3
TISP4350M3BJ 4350M3
TISP4360M3BJ 4360M3
TISP4395M3BJ 4395M3
TISP4400M3BJ 4400M3
“TISP” is a trademark of Bourns, Ltd., a Bourns Company, and is Registered in U.S. Patent and Trademark Office.
“Bourns” is a registered trademark of Bourns, Inc. in the U.S. and other countries.
NOVEMBER 1997 - REVISED MAY 2007
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
Legal Disclaimer Notice
This legal disclaimer applies to purchasers and users of Bourns® products manufactured by or on behalf of Bourns, Inc. and
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and complete before placing orders for Bourns® products.
The characteristics and parameters of a Bourns® product set forth in its data sheet are based on laboratory conditions, and
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