CAT5241YI25T2 - ON SEMICONDUCTOR

October, 2013 − Rev. 6

1Publication Order Number:

CAT34TS04/D

CAT34TS04

Digital Output Temperature

Sensor with On-board SPD

EEPROM

Description

The CAT34TS04 is a combination Temperature Sensor (TS) and

4−Kb of Serial Presence Detect (SPD) EEPROM, which implements

the JEDEC TSE2004av DDR4 specification and supports the Standard

(100 kHz), Fast (400 kHz) and Fast Plus (1 MHz) I2C protocols.

The TS measures temperature at least 10 times every second.

Temperature readings can be retrieved by the host via the serial

interface, and are compared to high, low and critical trigger limits

stored into internal registers. Over or under limit conditions can be

signaled on the open−drain EVENT pin.

One of the two available 2−Kb SPD EEPROM banks (referred to as

SPD pages in the TSE2004av specification) is activated for access at

power−up. After power−up, banks can be switched via software

command. Each of the four 1−Kb SPD EEPROM blocks can be Write

Protected by software command.

Features

•JEDEC TSE2004av Compliant Temperature Sensor

•Temperature Range: −20°C to +125°C

•DDR4 DIMM Compliant SPD EEPROM

•Supply Range: 1.7 V − 5.5 V (SPD EEPROM) and

2.2 V − 5.5 V (TS)

•I2C / SMBus Interface

•Schmitt Triggers and Noise Suppression Filters on SCL and SDA

Inputs

•16−Byte Page Write Buffer

•Low Power CMOS Technology

•2 x 3 x 0.75 mm TDFN Package and 2 x 3 x 0.5 mm UDFN Package

•These Devices are Pb−Free and are RoHS Compliant

Figure 1. Functional Symbol

SDA

SCL

CAT34TS04

VCC

VSS

A2, A1, A0EVENT

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PIN CONFIGURATION

SDA

EVENT

VCC

VSS

A01

See detailed ordering and shipping information in the package

dimensions section on page 18 of this data sheet.

ORDERING INFORMATION

SCL

TDFN (VP2), UDFN (HU4)

Device Address InputA0, A1, A2

Serial Data Input/OutputSDA

Serial Clock InputSCL

Open−drain Event OutputEVENT

Power SupplyVCC

GroundVSS

FunctionPin Name

PIN FUNCTIONS

For the location of Pin 1, please consult the

corresponding package drawing.

TDFN−8

VP2 SUFFIX

CASE 511AK

Backside Exposed DAP at VSS

DAP

MARKING DIAGRAM

4TA

ALL

4TA, 4UA = Specific Device Code

A = Assembly Location Code

LL = Assembly Lot Number (Last Two Digits)

Y = Production Year (Last Digit)

M = Production Month (1 − 9, O, N, D)

G= Pb−Free Package

= Pin 1 Indicator

UDFN−8

HU4 SUFFIX

CASE 517AZ

TDFN−8 UDFN−8

(Top View)

4UA

ALL

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Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter Rating Units

Operating Temperature −45 to +130 °C

Storage Temperature −65 to +150 °C

Voltage on any pin (except A0) with respect to Ground (Note 1) −0.5 to +6.5 V

Voltage on pin A0 with respect to Ground −0.5 to +10.5 V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. The A0 pin can be raised to a HV level for SWP

command execution. SCL and SDA inputs can be raised to the maximum limit, irrespective of VCC.

Table 2. RELIABILITY CHARACTERISTICS

Symbol Parameter Min Units

NEND (Note 2) Endurance (EEPROM) 1,000,000 Write Cycles

TDR Data Retention (EEPROM) 100 Years

2. Page Mode, VCC = 2.5 V, 25°C

Table 3. TEMPERATURE CHARACTERISTICS (VCC = 2.2 V to 3.6 V, TA = −20°C to +125°C, unless otherwise specified)

Parameter Test Conditions/Comments Max Unit

Temperature Reading Error +75°C ≤ TA ≤ +95°C, active range ±1.0 °C

+40°C ≤ TA ≤ +125°C, monitor range ±2.0 °C

−20°C ≤ TA ≤ +125°C, sensing range ±3.0 °C

ADC Resolution 12 Bits

Temperature Resolution 0.0625 °C

Conversion Time 100 ms

Thermal Resistance (Note 3) qJA Junction−to−Ambient (Still Air) 92 °C/W

3. Power Dissipation is defined as PJ = (TJ − TA)/qJA, where TJ is the junction temperature and TA is the ambient temperature. The thermal

resistance value refers to the case of a package being used on a standard 2−layer PCB.

Table 4. D.C. OPERATING CHARACTERISTICS (VCC = 2.2 V to 3.6 V, TA = −20°C to +125°C, unless otherwise specified)

Symbol Parameter Test Conditions/Comments Min Max Unit

ICC Supply Current TS active, SPD and Bus idle 1000 mA

SPD Write, TS shut−down 1000 mA

ISHDN Standby Current TS shut−down; SPD and Bus idle 10 mA

ILKG I/O Pin Leakage Current Pin at GND or VCC 2mA

VIL Input Low Voltage −0.5 0.3 x VCC V

VIH Input High Voltage 0.7 x VCC VCC + 0.5 V

VOL1 (Note 4) Output Low Voltage IOL = 3 mA, VCC > 2.2 V 0.4 V

VOL2 Output Low Voltage IOL = 1 mA, VCC < 2.2 V 0.2 V

4. The device is able to handle RL values corresponding to the specified rise time (see Figure 2).

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Table 5. A.C. CHARACTERISTICS (VCC = 2.2 V to 3.6 V, TA = −20°C to +125°C)

Symbol Parameter Min Max Units

FSCL (Note 5) Clock Frequency 0.01 1 MHz

tHIGH High Period of SCL Clock 260 ns

tLOW Low Period of SCL Clock 500 ns

tTIMEOUT (Note 6) SMBus SCL Clock Low Timeout 25 35 ms

tR (Note 7) SDA and SCL Rise Time 120 ns

tF (Note 7) SDA and SCL Fall Time 120 ns

tSU:DAT Input Data Setup Time 50 ns

tSU:STA START Condition Setup Time 260 ns

tHD:STA START Condition Hold Time 260 ns

tSU:STO STOP Condition Setup Time 260 ns

tBUF Bus Free Time Between STOP and START 500 ns

tHD:DAT Input Data Hold Time 0 ns

tDH (Note 7) Output Data Hold Time 120 300 ns

TiNoise Pulse Filtered at SCL and SDA Inputs 50 ns

tWR Write Cycle Time 5 ms

tPU (Note 8) Power-Up Delay to Valid Temperature Recording 100 ms

5. Timing reference points are set at 30%, respectively 70% of VCC, as illustrated in Figure 5. Bus loading must be such as to allow meeting

the VIL and VOL as well as all other timing requirements. The minimum clock frequency of 10 kHz is an SMBus recommendation; the minimum

operating clock frequency is limited only by the SMBus time−out. The device also meets the Fast and Standard I2C specifications, except

that Ti and tDH are shorter, as required by the 1 MHz Fast Plus protocol.

6. For the CAT34TS04, the interface will reset itself and will release the SDA line if the SCL line stays low beyond the tTIMEOUT limit. The time−out

count takes place when SCL is low in the time interval between START and STOP.

7. In a “Wired−OR” system (such as I2C or SMBus), SDA rise time is determined by bus loading. Since each bus pull−down device must be

able to sink the (external) bus pull−up current (in order to meet the VIL and/or VOL limits), it follows that SDA fall time is inherently faster than

SDA rise time. SDA rise time can exceed the standard recommended tR limit, as long as it does not exceed tLOW − tDH − tSU:DAT

, where tLOW

and tDH are actual values (rather than spec limits). A shorter tDH leaves more room for a longer SDA tR, allowing for a more capacitive bus

or a larger bus pull−up resistor.

8. The first valid temperature recording can be expected after tPU at nominal supply voltage.

Table 6. PIN CAPACITANCE (TA = 25°C, VCC = 3.6 V, f = 1 MHz)

Symbol Parameter Test Conditions/Comments Min Max Unit

CIN SDA, EVENT Pin Capacitance VIN = 0 8 pF

Input Capacitance (other pins) VIN = 0 6 pF

Figure 2. Pull−up Resistance vs. Load Capacitance

LOAD CAPACITANCE (pF)

10010

0.1

PULL−UP RESISTANCE (kW)

300 ns Rise Time

120 ns Rise Time

SDA

VCC

VSS

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Pin Description

SCL: The Serial Clock input pin accepts the Serial Clock

generated by the Master (Host).

SDA: The Serial Data I/O pin receives input data and transmits

data stored in SPD memory or in the TS registers. In transmit

mode, this pin is open drain. Data is acquired on the positive

edge, and is delivered on the negative edge of SCL.

A0, A1 and A2: The Address pins accept the device address.

These pins have on−chip pull−down resistors.

EVENT: The open−drain EVENT pin can be programmed

to signal over/under temperature limit conditions.

Power−On Reset (POR)

The CAT34TS04 incorporates Power−On Reset (POR)

circuitry which protects the device against powering up to an

undetermined logic state. As VCC exceeds the POR trigger

level, the TS component will power up into conversion

mode and the SPD component will power up into standby

mode. Both the TS and SPD components will power down

into Reset mode when VCC drops below the POR trigger

level. This bi−directional POR behavior protects the

CAT34TS04 against brown−out failure following a

temporary loss of power. The POR trigger level is set below

the minimum operating VCC level.

Device Interface

The CAT34TS04 supports the Inter−Integrated Circuit

(I2C) and the System Management Bus (SMBus) data

transmission protocols. These protocols describe serial

communication between transmitters and receivers sharing a

2−wire data bus. Data ﬂow is controlled by a Master device,

which generates the serial clock and the START and STOP

conditions. The CAT34TS04 acts as a Slave device. Master

and Slave alternate as transmitter and receiver. Up to 8

CAT34TS04 devices may be present on the bus

simultaneously, and can be individually addressed by

matching the logic state of the address inputs A0, A1, and A2.

I2C/SMBus Protocol

The I2C/SMBus uses two ‘wires’, one for clock (SCL) and

one for data (SDA). The two wires are connected to the VCC

supply via pull−up resistors. Master and Slave devices

connect to the bus via their respective SCL and SDA pins.

The transmitting device pulls down the SDA line to

‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’.

Data transfer may be initiated only when the bus is not

busy (see A.C. Characteristics).

During data transfer, the SDA line must remain stable

while the SCL line is HIGH. An SDA transition while SCL

is HIGH will be interpreted as a START or STOP condition

(Figure 3).

START

The START condition precedes all commands. It consists

of a HIGH to LOW transition on SDA while SCL is HIGH.

The START acts as a ‘wake−up’ call to all Slaves. Absent a

START, a Slave will not respond to commands.

STOP

The STOP condition completes all commands. It consists

of a LOW to HIGH transition on SDA while SCL is HIGH.

The STOP tells the Slave that no more data will be written

to or read from the Slave.

Device Addressing

The Master initiates data transfer by creating a START

condition on the bus. The Master then broadcasts an 8−bit

serial Slave address. The first 4 bits of the Slave address (the

preamble) determine whether the command is intended for

the Temperature Sensor (TS) or the EEPROM. The next 3

bits, A2, A1 and A0, select one of 8 possible Slave devices.

The last bit, R/W, specifies whether a Read (1) or Write (0)

operation is being performed.

Acknowledge

A matching Slave address is acknowledged (ACK) by the

Slave by pulling down the SDA line during the 9th clock

cycle (Figure 4). After that, the Slave will acknowledge all

data bytes sent to the bus by the Master. When the Slave is

the transmitter, the Master will in turn acknowledge data

bytes in the 9th clock cycle. The Slave will stop transmitting

after the Master does not respond with acknowledge

(NoACK) and then issues a STOP. Bus timing is illustrated

in Figure 5.

Figure 3. Start/Stop Timing

START BIT

SDA

STOP BIT

SCL

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Figure 4. Acknowledge Timing

ACKNOWLEDGE

START

SCL FROM

MASTER 89

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

30% 30%

70%

30%

70% 30%

30%

70% 70% 70%

70% 70%

70%

SCL

SDA IN

Figure 5. Bus Timing

tBUF

tSU:STO

tSU:STA tHD:STA

tHD:DAT

tSU:DAT

tLOW

tHIGH

tDH

SDA OUT 30%

70%

Table 7. COMMAND SET (Notes 9, 10)

Function Abbr

Function Specific Preamble Select Address R/W_n A0 Pin

b7 b6 b5 b4 b3 b2 b1 b0

Read Temperature Registers RTR 0 0 1 1 LSA2 LSA1 LSA0 10 or 1

Write Temperature Registers WTR 0

Read EE Memory RSPD 1 0 1 0 LSA2 LSA1 LSA0 10 or 1

Write EE Memory WSPD 0

Set Write Protection, block 0 SWP0 0 1 1 0 0 0 1 0 VHV

Set Write Protection, block 1 SWP1 1 0 0 0 VHV

Set Write Protection, block 2 SWP2 1 0 1 0 VHV

Set Write Protection, block 3 SWP3 0 0 0 0 VHV

Clear All Write Protection CWP 0 1 1 0 VHV

Read Protection Status, block 0 RPS0 0 0 1 1 0, 1 or VHV

Read Protection Status, block 1 RPS1 1 0 0 1 0, 1 or VHV

Read Protection Status, block 2 RPS2 1 0 1 1 0, 1 or VHV

Read Protection Status, block 3 RPS3 0 0 0 1 0, 1 or VHV

Set SPD Page Address to 0

(Select Lower Bank)

SPA0 1 1 0 0 0, 1 or VHV

Set SPD Page Address to 1

(Select Upper Bank)

SPA1 1 1 1 0 0, 1 or VHV

Read SPD Page Address RPA 1 1 0 1 0, 1 or VHV

Reserved −All Other Encodings

9. LSAx stands for Logic State of Address pin x.

10.If VHV is not applied on the A0 pin during SWP/CWP commands, the CAT34TS04 will respond with NoACK after the 3rd byte and will not

execute the SWP/CWP instruction. During RPS/SPA/RPA commands the state of pin A0 must be stable for the duration of the sequence.

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SPD EEPROM Bank Selection

Upon power−up, the address pointers for both the

Temperature Sensor (TS) and on−board EEPROM are

initialized to 00h. The TS address pointer will thus point to

the Capability Register and the EEPROM address pointer

will point to the first location in the lower 2−Kb bank (SPD

page 0).

Only one SPD page is visible (active) at any given time.

The lower SPD page is automatically selected at power−up.

The upper SPD page can be activated (and the lower one

implicitly de−activated) by executing the SPA1 utility

command. The SPA0 utility command can then be used to

re−activate the lower SPD page without powering down.

The identity of the active SPD page can be retrieved with the

RPA command.

SPD page selection related command details are

presented in Table 9c, Table 9d, Figure 13 and Figure 14.

Write Operations

EEPROM Byte and TS Register Write

To write data to a TS register, or to the on−board

EEPROM, the Master creates a START condition on the bus,

and then sends out the appropriate Slave address (with the

R/W bit set to ‘0’), followed by a starting data byte address

or TS register address, followed by data. The matching

Slave will acknowledge the Slave address, EEPROM byte

address or TS register address and the data byte(s), one for

EEPROM data (Figure 6) and two for TS register data

(Figure 7). The Master then ends the session by creating a

STOP condition on the bus. The STOP completes the

(volatile) TS register update or starts the internal Write cycle

for the (non−volatile) EEPROM data (Figure 8).

EEPROM Page Write

Each of the two 2−Kb banks is organized as 16 pages of

16 bytes each (not to be confused with the SPD page, which

refers to the entire 2−Kb bank). One of the 16 memory pages

is selected by the 4 most significant bits of the byte address,

while the 4 least significant bits point to the byte position

within the page. Up to 16 bytes can be written in one Write

cycle (Figure 9).

During data load, the internal byte position pointer is

automatically incremented after each data byte is loaded. If

the Master transmits more than 16 data bytes, then earlier

data will be replaced by later data in a ‘wrap−around’

fashion within the 16−byte wide data buffer. The internal

Write cycle then starts following the STOP.

Acknowledge Polling

Acknowledge polling can be used to determine if the

CAT34TS04 is busy writing to EEPROM, or is ready to

accept commands. Polling is executed by interrogating the

device with a ‘Selective Read’ command (see READ

OPERATIONS). The CAT34TS04 will not acknowledge

the Slave address as long as internal EEPROM Write is in

progress.

Delivery State

The CAT34TS04 is shipped ‘unprotected’, i.e. none of the

Software Write Protection (SWP) flags is set. The entire

memory is erased, i.e. all bytes are 0xFF.

Read Operations

Immediate Read

A CAT34TS04 presented with a Slave address containing

a ‘1’ in the R/W position will acknowledge the Slave address

and will then start transmitting SPD data or respectively TS

Master stops this transmission by responding with NoACK,

followed by a STOP (Figures 10a, 10b).

Selective Read

The Read operation can be started from a specific address,

by preceding the Immediate Read sequence with a ‘data less’

Write sequence. The Master sends out a START, Slave

address and byte or register address, but rather than

following up with data (as in a Write operation), the Master

then issues another START and continuous with an

Immediate Read sequence (Figures 11a, 11b).

Sequential EEPROM Read

EEPROM data can be read out indefinitely, as long as the

Master responds with ACK (Figure 12). The internal address

pointer is automatically incremented after every data byte

sent to the bus. If the end of the active 2−Kb bank is reached

during continuous Read, then the address count

‘wraps−around’ to the beginning of the active 2−Kb bank,

etc. Sequential Read works with either Immediate Read or

Selective Read, the only difference being that in the latter

case the starting address is intentionally updated.

Figure 6. EEPROM Byte Write

BYTE

ADDRESS

SLAVE

SPD

ADDRESS

DATA

BUS ACTIVITY:

MASTER

SLAVE

SDA LINE

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Figure 7. Temperature Sensor Register Write

SLAVE REGISTER

ADDRESS

BUS ACTIVITY:

MASTER

SDA LINE

SLAVE

DATA (MSB) DATA (LSB)

Figure 8. EEPROM Write Cycle Timing

STOP

CONDITION

START

CONDITION

ADDRESS

ACK8th Bit

Byte n

SCL

SDA

tWR

Figure 9. EEPROM Page Write

SDA LINE

BYTE

ADDRESS (n) DATA n DATA n+1

SLAVE

ADDRESS

SPD

NOTE: In this example n = XXXX 0000(B); X = 1 or 0

SLAVE

BUS ACTIVITY:

MASTER

DATA n+P

Figure 10a. EEPROM Immediate Read

SLAVE

ADDRESS

SPD

SDA LINE

SLAVE

BUS ACTIVITY:

MASTER

DATA

DATA (MSB) DATA (LSB)

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

SDA LINE

SLAVE

Figure 10b. Temperature Sensor Immediate Read

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SLAVE

ADDRESS

SDA LINE

BYTE

ADDRESS (n)

DATA n

SLAVE

ADDRESS

SLAVE

BUS ACTIVITY:

MASTER

BUS ACTIVITY:

MASTER SLAVE

ADDRESS

SDA LINE

DATA (MSB)

SLAVE

SLAVE DATA (LSB)

ADDRESS ADDRESS

SPD

Figure 11a. EEPROM Selective Read

Figure 11b. Temperature Sensor Selective Read

Figure 12. EEPROM Sequential Read

MASTER

SDA LINE

SLAVE

ADDRESS

SPD

SLAVE DATA n DATA n+1

BUS ACTIVITY:

DATA n+2 DATA n+x

Software Write Protection

Each 1−Kb memory block can be individually protected

against Write requests. Block identities are:

Block 0: byte address 0x00...0x7F (SPD page address = 0)

Block 1: byte address 0x80...0xFF (SPD page address = 0)

Block 2: byte address 0x00...0x7F (SPD page address = 1)

Block 3: byte address 0x80...0xFF (SPD page address = 1)

Block Software Write Protection (SWP) ﬂags can be set

or cleared in the presence of a very high voltage VHV on

address pin A0. The VHV condition must be established on

pin A0 before the START and maintained just beyond the

STOP. The D.C. OPERATING CONDITIONS for SWP

operations are shown in Table 8.

SWP command details are listed in Tables 9a and 9b.

SWP Slave addresses follow the standard I2C convention,

i.e. to read the state of a SWP ﬂag, the LSB of the Slave

address must be ‘1’, and to set or clear a ﬂag, it must be ‘0’.

For Set/Clear commands a dummy byte address and dummy

data byte must be provided (Figure 13). In contrast to a

regular memory Read, a SWP Read does not return data.

Instead the CAT34TS04 will respond with NoACK if the

ﬂag is set and with ACK if the ﬂag is not set (Figure 14).

Table 8. SWPn AND CWP D.C. OPERATION CONDITION

Symbol Parameter Test Conditions Min Max Units

DVHV A0 Overdrive (VHV − VCC)

1.7 V < VCC < 3.6 V

4.8 V

IHVD A0 High Voltage Detector Current 0.1 mA

VHV A0 Very High Voltage 7 10 V

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Table 9a. SWP SET COMMAND DETAIL (following Slave Address)

Command

Block(x)

Protection

Slave

Response

Address

Byte

Slave

Response Data Byte

Slave

Response

Write

Cycle

SWPx(Note 11) Not Set ACK (Dummy) ACK (Dummy) ACK Yes

Set NoACK (Dummy) NoACK (Dummy) NoACK No

CWP X ACK (Dummy) ACK (Dummy) ACK Yes

Table 9b. SWP QUERRY COMMAND DETAIL (following Slave Address)

Command

Block(x)

Protection

Slave

Response Data Byte

Master

(Response) Data Byte

Master

(Response)

RPSx (Nots 11, 12) Not Set ACK Dummy (NoACK) Dummy (NoACK)

Set NoACK Dummy (NoACK) Dummy (NoACK)

Table 9c. SPD PAGE SELECT COMMAND DETAIL (following Slave Address)

Command

SPD Active

Page

Slave

Response

Address

Byte

Slave

Response Data Byte

Slave

Response

Write

Cycle

SPAx (Notes 13, 14) X ACK (Dummy) ACK (Dummy) NoACK No

Table 9d. SPD ACTIVE PAGE QUERRY COMMAND DETAIL (following Slave Address)

Command

SPD Active

Page

Slave

Response Data Byte

Master

(Response) Data Byte

Master

(Response)

RPA (Notes 11, 12,

15)

0 ACK Dummy (NoACK) Dummy (NoACK)

1 NoACK Dummy (NoACK) Dummy (NoACK)

11. The Master can terminate the sequence by issuing a STOP once the CAT34TS04 responds with NoACK

12.The Master can terminate the sequence by responding with (NoACK) followed by STOP after any dummy data byte.

13.Setting the SPD Page Address to ‘0’ selects the lower 2−Kb EEPROM bank, setting it to ‘1’ selects the upper 2−Kb EEPROM bank.

14.The lower 2−Kb EEPROM bank (corresponding to SPD page address ‘0’) is active (visible) immediately following power−up.

15. The device will respond with ACK when the lower 2−Kb EEPROM bank is active and with NoACK when the upper 2−Kb EEPROM bank is

active.

Figure 13. SWP & SPA Timing

Figure 14. RPS & RPA Timing

Dummy

DATA

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

SDA LINE

SLAVE

X = Don’t Care

Dummy

ADDRESS

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

SDA LINE

SLAVE

X = Don’t Care

Dummy

DATA

Dummy

DATA

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Temperature Sensor Operation

The TS component in the CAT34TS04 combines a

Proportional to Absolute Temperature (PTAT) sensor with

a S−D modulator, yielding a 12 bit plus sign digital

temperature representation.

The TS runs on an internal clock, and starts a new

conversion cycle at least every 100 ms. The result of the

most recent conversion is stored in the Temperature Data

Shut−Down. Reading from the TDR does not interfere with

the conversion cycle.

The value stored in the TDR is compared against limits

stored in the High Limit Register (HLR), the Low Limit

(CTR). If the measured value is outside the alarm limits or

above the critical limit, then the EVENT pin may be

asserted. The EVENT output function is programmable, via

the Configuration Register for interrupt mode, comparator

mode and polarity.

The temperature limit registers can be Read or Written by

the host, via the serial interface. At power−on, all the

(writable) internal registers default to 0x0000, and should

therefore be initialized by the host to the desired values. The

EVENT output starts out disabled (corresponding to

polarity active low); thus preventing irrelevant event bus

activity before the limit registers are initialized. While the

TS is enabled (not shut−down), event conditions are

normally generated by a change in measured temperature as

recorded in the TDR, but limit changes can also trigger

events as soon as the new limit creates an event condition,

i.e. asynchronously with the temperature sampling activity.

In order to minimize the thermal resistance between

sensor and PCB, it is recommended that the exposed

backside die attach pad (DAP) be soldered to the PCB

ground plane.

Registers

The CAT34TS04 contains eight 16−bit wide registers

allocated to TS functions, as shown in Table 10. Upon

power−up, the internal address counter points to the

capability register.

Capability Register (User Read Only)

This register lists the capabilities of the TS, as detailed in

the corresponding bit map.

Configuration Register (Read/Write)

This register controls the various operating modes of the

TS, as detailed in the corresponding bit map.

Temperature Trip Point Registers (Read/Write)

The CAT34TS04 features 3 temperature limit registers,

the HLR, LLR and CLR mentioned earlier. The

temperature value recorded in the TDR is compared to the

various limit values, and the result is used to activate the

EVENT pin. To avoid undesirable EVENT pin activity, this

pin is automatically disabled at power−up to allow the host

to initialize the limit registers and the converter to complete

the first conversion cycle under nominal supply conditions.

Data format is two’s complement with the LSB representing

0.25°C, as detailed in the corresponding bit maps.

Temperature Data Register (User Read Only)

This register stores the measured temperature, as well as

trip status information. B15, B14, and B13 are the trip status

bits, representing the relationship between measured

temperature and the 3 limit values; these bits are not affected

by EVENT status or by Configuration register settings

regarding EVENT pin. Measured temperature is

represented by bits B12 to B0. Data format is two’s

complement, where B12 represents the sign, B11 represents

128°C, etc. and B0 represents 0.0625°C.

Manufacturer ID Register (Read Only)

The manufacturer ID assigned by the PCI−SIG trade

organization to the CAT34TS04 device is fixed at 0x1B09.

Device ID and Revision Register (Read Only)

This register contains manufacturer specific device ID

and device revision information.

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Table 10. THE TS REGISTERS

0x00 Capability Register 0x007F Read

0x01 Configuration Register 0x0000 Read/Write

0x02 High Limit Register 0x0000 Read/Write

0x03 Low Limit Register 0x0000 Read/Write

0x04 Critical Limit Register 0x0000 Read/Write

0x05 Temperature Data Register Undefined Read

0x06 Manufacturer ID Register 0x1B09 Read

0x07 Device ID/Revision Register 0x2200 Read

Table 11. CAPABILITY REGISTER

B15 B14 B13 B12 B11 B10 B9 B8

RFU

(Note 16)

RFU RFU RFU RFU RFU RFU RFU

B7 B6 B5 B4 B3 B2 B1 B0

EVSD TMOUT VHV TRES [1:0] RANGE ACC EVENT

16.RFU stands for Reserved for Future Use

Bit Description

B15:B8 Reserved for future use; can not be written; should be ignored; will read as 0

B7 (Note 17) 0: Configuration Register bit 4 is frozen upon Configuration Register bit 8 being set

(i.e. a TS shut−down freezes the EVENT output)

1: Configuration Register bit 4 is cleared upon Configuration Register bit 8 being set

(i.e. a TS shut−down de−asserts the EVENT output)

B6 0: Not used

1: The TS implements SMBus time−out within the range 25 to 35 ms

B5 0: Not used

1: Defined for compatibility with CAT34TS02 device (VHV is supported)

B4:B3 00: LSB = 0.50°C (9 bit resolution)

01: LSB = 0.25°C (10 bit)

10: LSB = 0.125°C (11 bit)

11: LSB = 0.0625°C (12 bit)

B2 0: Not used

1: The temperature monitor can read temperatures below 0°C and sets the sign bit appropriately

B1 0: Not used

1: The temperature monitor has ±1°C accuracy over the active range (75°C to 95°C) and ±2°C

accuracy over the monitoring range (40°C to 125°C)

B0 0: Not used

1: The device supports interrupt capabilities

17.Configuration Register bit 4 can be cleared (but not set) after Configuration Register bit 8 is set, by writing a “1” to Configuration Register

bit 5 (EVENT output can be de−asserted during TS shut−down periods)

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Table 12. CONFIGURATION REGISTER

B15 B14 B13 B12 B11 B10 B9 B8

RFU RFU RFU RFU RFU HYST [1:0] SHDN

B7 B6 B5 B4 B3 B2 B1 B0

TCRIT_LOCK ALARM_LOCK CLEAR EVENT_STS EVENT_CTRL TCRIT_ONLY EVENT_POL EVENT_MODE

Bit Description

B15:B11 Reserved for future use; can not be written; should be ignored; will read as 0

B10:B9 (Note 18) 00: Disable hysteresis

01: Set hysteresis at 1.5°C

10: Set hysteresis at 3°C

11: Set hysteresis at 6°C

B8 (Note 22) 0: Thermal Sensor is enabled; temperature readings are updated at sampling rate

1: Thermal Sensor is shut down; temperature reading is frozen to value recorded before SHDN

B7 (Note 21) 0: Critical trip register can be updated

1: Critical trip register cannot be modified; this bit can be cleared only at POR

B6 (Note 21) 0: Alarm trip registers can be updated

1: Alarm trip registers cannot be modified; this bit can be cleared only at POR

B5 (Note 20) 0: Always reads as 0 (self−clearing)

1: Writing a 1 to this position clears an event recording in interrupt mode only

B4 (Note 19) 0: EVENT output pin is not being asserted

1: EVENT output pin is being asserted

B3 (Note 18) 0: EVENT output disabled; polarity dependent: open−drain for B1 = 0; grounded for B1 = 1

1: EVENT output enabled

B2 (Note 24) 0: event condition triggered by alarm or critical temperature limit crossing

1: event condition triggered by critical temperature limit crossing only

B1 (Notes 18, 23) 0: EVENT output active low

1: EVENT output active high

B0 (Note 18) 0: Comparator mode

1: Interrupt mode

18.Can not be altered (set or cleared) as long as either one of the two lock bits, B6 or B7 is set.

19.This bit is a polarity independent ‘software’ copy of the EVENT pin, i.e. it is under the control of B3. This bit is read−only.

20.Writing a ‘1’ to this bit clears an event condition in Interrupt mode, but has no effect in comparator mode. When read, this bit always returns

0. Once the measured temperature exceeds the critical limit, setting this bit has no effect (see Figure 15).

21.Cleared at power−on reset (POR). Once set, this bit can only be cleared by a POR condition.

22. The TS powers up into active mode, i.e. this bit is cleared at power−on reset (POR). When the TS is shut down the ADC is disabled and the

temperature reading is frozen to the most recently recorded value. The TS can not be shut down (B8 can not be set) as long as either one

of the two lock bits, B6 or B7 is set. However, the bit can be cleared at any time.

23. The EVENT output is “open−drain” and requires an external pull−up resistor for either polarity. The “natural” polarity is “active low”, as it allows

“wired−or” operation on the EVENT bus.

24.Can not be set as long as lock bit B6 is set.

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Table 13. HIGH LIMIT REGISTER

B15 B14 B13 B12 B11 B10 B9 B8

0 0 0 Sign 128°C 64°C 32°C 16°C

B7 B6 B5 B4 B3 B2 B1 B0

8°C 4°C 2°C 1°C 0.5°C 0.25°C 0 0

Table 14. LOW LIMIT REGISTER

B15 B14 B13 B12 B11 B10 B9 B8

0 0 0 Sign 128°C 64°C 32°C 16°C

B7 B6 B5 B4 B3 B2 B1 B0

8°C 4°C 2°C 1°C 0.5°C 0.25°C 0 0

Table 15. TCRIT LIMIT REGISTER

B15 B14 B13 B12 B11 B10 B9 B8

0 0 0 Sign 128°C 64°C 32°C 16°C

B7 B6 B5 B4 B3 B2 B1 B0

8°C 4°C 2°C 1°C 0.5°C 0.25°C 0 0

Table 16. TEMPERATURE DATA REGISTER

B15 B14 B13 B12 B11 B10 B9 B8

TCRIT HIGH LOW Sign 128°C 64°C 32°C 16°C

B7 B6 B5 B4 B3 B2 B1 B0

8°C 4°C 2°C 1°C 0.5°C 0.25°C

(Note 25)

0.125°C

(Note 25)

0.0625°C

(Note 25)

25.When supported − as defined by Capability Register bits TRES (1:0); unsupported bits will read as 0

Bit Description

B15 0: Temperature is below the TCRIT limit

1: Temperature is equal to or above the TCRIT limit

B14 0: Temperature is equal to or below the High limit

1: Temperature is above the High limit

B13 0: Temperature is equal to or above the Low limit

1: Temperature is below the Low limit

B12 0: Positive temperature

1: Negative temperature

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The values used in the temperature data register and the 3

temperature trip point registers are expressed in two’s

complement format. The measured temperature value is

expressed with 12−bit resolution, while the 3 trip

temperature limits are set with 10−bit resolution. The total

temperature range is arbitrarily defined as 256°C, thus

yielding an LSB of 0.0625°C for the measured temperature

and 0.25°C for the 3 limit values. Bit B12 in all temperature

registers represents the sign, with a ‘0’ indicating a positive,

and a ‘1’ a negative value. In two’s complement format,

negative values are obtained by complementing their

positive counterpart and adding a ‘1’, so that the sum of

opposite signed numbers, but of equal absolute value, adds

up to zero.

Note that trailing ‘0’ bits, are ‘0’ irrespective of polarity.

Therefore the don’t care bits (B1 and B0) in the 10−bit

resolution temperature limit registers, are always ‘0’.

Table 17. 12−BIT TEMPERATURE DATA FORMAT

Binary (B12 to B0) Hex Temperature

1 1100 1001 0000 1C90 −55°C

1 1100 1110 0000 1CE0 −50°C

1 1110 0111 0000 1E70 −25°C

1 1111 1111 1111 1FFF −0.0625°C

0 0000 0000 0000 000 0°C

0 0000 0000 0001 001 +0.0625°C

0 0001 1001 0000 190 +25°C

0 0011 0010 0000 320 +50°C

0 0111 1101 0000 7D0 +125°C

Event Pin Functionality

The EVENT output reacts to temperature changes as

illustrated in Figure 15, and according to the operating mode

defined by the Configuration register.

In Interrupt Mode, the (enabled) EVENT output will be

asserted every time the temperature crosses one of the alarm

window limits, and can be de−asserted by writing a ‘1’ to the

clear event bit (B5) in the configuration register. Once the

temperature exceeds the critical limit, the EVENT remains

asserted as long as the temperature stays above the critical

limit and cannot be cleared. A clear request sent to the

CAT34TS04 while the temperature is above the critical limit

will be acknowledged, but will be executed only after the

temperature drops below the critical limit.

In Comparator Mode, the EVENT output is asserted

outside the alarm window limits, while in Critical

Temperature Mode, EVENT is asserted only above the

critical limit. Clear requests are ignored in this mode. The

exact trip limits are determined by the 3 temperature limit

settings and the hysteresis offsets, as illustrated in Figure 16.

Following a TS shut−down request, the converter is

stopped and the most recently recorded temperature value

present in the TDR is frozen; the EVENT output will continue

to reflect the state immediately preceding the shut−down

command. Therefore, if the state of the EVENT output

creates an undesirable bus condition, appropriate action must

be taken either before or after shutting down the TS. This may

require clearing the event, disabling the EVENT output or

perhaps changing the EVENT output polarity.

In normal use, events are triggered by a change in

recorded temperature, but the CAT34TS04 will also respond

to limit register changes. Whereas recorded temperature

values are updated at sampling rate frequency, limits can be

modified at any time. The enabled EVENT output will react

to limit changes as soon as the respective registers are

updated. This feature may be useful during testing.

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Figure 15. Event Detail

TEMPERATURE

CRITICAL

UPPER

LOWER

ALARM

WINDOW

TIME

HYSTERESIS AFFECTS

THESE TRIP POINTS

EVENT in “INTERRUPT” Mode

EVENT in “COMPARATOR” Mode

EVENT in “CRITICAL TEMP ONLY” Mode

Clear request executed immediately

Clear request acknowledged but execution delayed until measured temperature drops below the active Critical Temperature limit

Figure 16. Hysteresis Detail

BELOW

WINDOW BIT

ABOVE

WINDOW BIT

TL − HYST

TH − HYST

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PACKAGE DIMENSIONS

TDFN8, 2x3

CASE 511AK−01

ISSUE A

PIN#1

IDENTIFICATION

ebD

TOP VIEW SIDE VIEW BOTTOM VIEW

PIN#1 INDEX AREA

FRONT VIEW

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC MO-229.

SYMBOL MIN NOM MAX

A 0.70 0.75 0.80

A1 0.00 0.02 0.05

A3 0.20 REF

b 0.20 0.25 0.30

D 1.90 2.00 2.10

D2 1.30 1.40 1.50

E 3.00

E2 1.20 1.30 1.40

2.90

0.50 TYP

3.10

L 0.20 0.30 0.40

A2 0.45 0.55 0.65

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PACKAGE DIMENSIONS

UDFN8, 2x3 EXTENDED PAD

CASE 517AZ−01

ISSUE O

0.065 REF

Copper Exposed

PIN #1 INDEX AREA

PIN #1

IDENTIFICATION

DAP SIZE 1.8 x 1.8

DETAIL A

TOP VIEW SIDE VIEW

FRONT VIEW

DETAIL A

BOTTOM VIEW

0.065 REF

0.0 - 0.05A3

Notes:

(1) All dimensions are in millimeters.

(2) Refer JEDEC MO-236/MO-252.

SYMBOL MIN NOM MAX

A 0.45 0.50 0.55

A1 0.00 0.02 0.05

A3 0.127 REF

b 0.20 0.25 0.30

D 1.95 2.00 2.05

D2 1.35 1.40 1.45

E 3.00

E2 1.25 1.30 1.35

2.95

0.50 REF

3.05

L 0.25 0.30 0.35

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Example of Ordering Information

Device Order Number

Specific

Device Marking Package Type

Lead

Finish Shipping

Device

Revision

CAT34TS04VP2GT4A 4TA TDFN−8 NiPdAu Tape & Reel,

4,000 Units / Reel

CAT34TS04HU4GT4A 4UA UDFN−8 NiPdAu Tape & Reel,

4,000 Units / Reel

26.All packages are RoHS−compliant (Lead−free, Halogen−free)

27.The standard lead finish is NiPdAu.

28.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,

copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC

reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC

does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for

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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture

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CAT34TS04/D

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