SI34062-A-GMR - SILICON LABS

Si3406x Family Data Sheet

Fully-Integrated IEEE 802.3-Compliant POE+ PD Interface and

High-Efficiency Switching Regulators with Sleep, Wake, and LED

Drive

The Si3406x family integrates all power management and control functions required in

a Power-over-Ethernet Plus (PoE+) powered device (PD) application. These devices

convert the high voltage supplied over the 10/100/1000BASE-T Ethernet connection to

a regulated, low-voltage output supply. The optimized architecture of this device family

minimizes the solution footprint and external BOM cost and enables the use of low-cost

external components while maintaining high performance. The Si3406x family integra-

tes the required diode bridges and transient surge suppressor, thus enabling direct

connection of the IC to the Ethernet RJ-45 connector. The switching power FET and all

associated functions are also integrated. The integrated, current mode controlled

switching regulator supports isolated or non-isolated flyback and buck converter topolo-

gies. The switching frequency for the regulator is tunable with a simple external resistor

value to help avoid unwanted harmonics for better emissions control. A synchronous

driver is provided to optionally drive a secondary side FET to improve efficiency of pow-

er conversion. Connection to the PSE switch is maintained during sleep by an optional

automated maintain-power-signature (MPS) signal.

These devices fully support the IEEE 802.3at specification for the cases of single or

two event classification. Standard external resistors provide the proper IEEE 802.3 sig-

natures for the detection function and programming of the classification mode, and in-

ternal startup circuits ensure well-controlled soft-start initial operation of both the hots-

wap switch and the voltage regulator.

The Si34061 and Si34062 add main transformer bias winding support for ultra-high-effi-

ciency operation.

The Si34062 includes support for sleep modes with wake function, as well as LED drive

capability. These features can be utilized to minimize standby current, control sleep

and wake states, and provide application status information using an LED.

The Si3406 is available in a low-profile, 20-pin, 5 x 5 mm QFN package, and the

Si34061 and Si34062 are available in low-profile, 24-pin, 5 x 5 mm QFN packages.

KEY FEATURES

• Type 1 (PoE) or Type 2 (PoE+) power

•Full IEEE 802.3at compliance

• Synchronous secondary FET driver

• Current mode dc-dc converter

• Tunable switching frequency

• Auxiliary transformer winding support

• Auxiliary wall adapter support (12 V to 57 V)

• Internal hotswap and switching FET bypass

support

• Automated maintain-power-signature (MPS)

support

• Sleep mode augmented with wake pin,

mode control, and LED driver

• 120 V Absolute Max voltage performance

• Extended –40 to +85 °C temperature

• Compact ROHS-compliant 5 mm x 5 mm

QFN Package

APPLICATIONS

• Voice over IP telephones

•Wireless access points

• Security and surveillance IP cameras

• Lighting luminaires

• Point-of-sale terminals

• Internet appliances

• Network devices

silabs.com | Building a more connected world. Rev. 1.0

1. Ordering Guide

Table 1.1. Si3406x Ordering Guide

Ordering Part Number Package Temperature Range (Ambient) Applications

Si3406-A-GM

5 x 5 mm 20-QFN

Pb-free, RoHS-compliant

–40 to 85 °C Extended All Purposes

Si34061-A-GM

5 x 5 mm 24-QFN

Pb-free, RoHS-compliant

–40 to 85 °C Extended

Any high-power, high-efficiency

uses, such as Wireless Access

Points and IP Cameras

Si34062-A-GM

5 x 5 mm 24-QFN

Pb-free, RoHS-compliant

–40 to 85 °C Extended IP Phones with manual sleep

mode

Si3406x Family Data Sheet

Ordering Guide

silabs.com | Building a more connected world. Rev. 1.0 | 2

Table of Contents

1. Ordering Guide ..............................2

2. System Overview ..............................4

2.1 Block Diagrams..............................4

2.2 Power over Ethernet (PoE) Line-Side Interface ...................5

2.2.1 Surge Protection ............................5

2.2.2 Telephony Protection ..........................5

2.2.3 Detection and Classification ........................6

2.3 Hotswap Switch .............................6

2.4 HSSW State Machine ...........................7

2.4.1 External HSSW FET Driver ........................7

2.5 DC to DC Converter ............................8

2.5.1 Average Current Sensing, Overcurrent, Low-Current Detection, and Output Short Protection ..9

2.5.2 Sync FET Driver ............................9

2.6 Tunable Oscillator .............................9

2.7 Regulators ...............................10

2.8 Sleep Mode ...............................10

2.9 Special Sleep Mode ............................10

2.10 External Wall Adapter Support ........................11

3. Application Examples ...........................12

4. Electrical Specifications ..........................14

5. Pin Descriptions .............................19

5.1 Detailed Pin Descriptions ..........................21

6. Packaging ...............................26

6.1 Package Outline: Si3406 ..........................26

6.2 Land Pattern: Si3406 ............................28

6.3 Package Outline: Si34061/62 .........................29

6.4 Land Pattern: Si34061/62 ..........................31

7. Top Markings ..............................32

7.1 Si3406 Top Marking ............................32

7.2 Si34061 Top Marking ............................33

7.3 Si34062 Top Marking ............................34

8. Revision History .............................35

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2. System Overview

The following Block Diagrams will give the designer a sense for the internal arrangement of functional blocks, plus their relationships to

external pins. The Block Diagrams are followed by a description of the features of these integrated circuits.

2.1 Block Diagrams

CT1

CT2

SP1

SP2

VPOS

VNEG

DETECTION

RDET

OSCs

fixed: 250kHz

adjustable: 100...500kHz

CLASS

MPS

PoE

CONTROLLER

V11

HOT-SWAP

CONTROLLER

THERMAL

PROTECTION

HSO

11V

REGULATOR

RFREQ VDD

RCL

CURRENT

MODE

PWM

CONTROLLER

THERMAL

PROTECTION

VSS

SWO

EROUT

FBL

FBH

V11

SYNCL

DRV

nSLEEP

nT2P

TVS

100V

HSSW

250kHz

VPOS-1.32V

VSS+1.32V

IBIAS

Start

ISNS

IAVG

DC/DC

Figure 2.1. Si3406 Block Diagram

CT1

CT2

SP1

SP2

VPOS

VNEG

DETECTION

RDET

OSCs

fixed: 250kHz

adjustable: 100...500kHz

CLASS

MPS

PoE

CONTROLLER

V11

HOT-SWAP

CONTROLLER

THERMAL

PROTECTION

HSO

11V

REGULATOR

RFREQ VDD

RCL

CURRENT

MODE

PWM

CONTROLLER

THERMAL

PROTECTION

VSS

SWO

EROUT

FBL

V11

SYNCL

DRV

nSLEEP

nT2P

TVS

100V

HSSW

250kHz

VSS+1.32V

IBIAS

Start

ISNS

IAVG

DC/DC

VT15

AUX

WINDING

SUPPORT

VEHSSW

DRV

EXTHSW

V11

EXTGD

DRV

SWISNS

IPK

ASUP

Figure 2.2. Si34061 Block Diagram

Si3406x Family Data Sheet

System Overview

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CT1

CT2

SP1

SP2

VPOS

VNEG

DETECTION

RDET

OSCs

fixed: 250kHz

adjustable: 100...500kHz

CLASS

MPS

PoE

CONTROLLER

V11

HOT-SWAP

CONTROLLER

THERMAL

PROTECTION

HSO

11V

REGULATOR

RFREQ VDD

RCL

CURRENT

MODE

PWM

CONTROLLER

THERMAL

PROTECTION

VSS

SWO

EROUT

FBL

FBH

V11

SYNCL

DRV

nSLEEP

nT2P

TVS

100V

HSSW

250kHz

VPOS-1.32V

VSS+1.32V

IBIAS

Start

ISNS

IAVG

DC/DC

LEDMODEWAKE

VT15

AUX

WINDING

SUPPORT

Figure 2.3. Si34062 Block Diagram

2.2 Power over Ethernet (PoE) Line-Side Interface

The PoE line interface consists of diode bridges, internal surge protection, and the protocol interface support for detection and classifi-

cation.

Internal diode bridge maximum current is given by the specification, IRECT. For Class 1 and Class 2 applications, the internal diode

bridge can be used. For Class 3 and Class 4, an external diode bridge needs to be installed.

The external bridge should be connected in parallel to the internal bridge and the designer must ensure that the internal bridge will not

conduct significant current by using low-voltage-drop external diodes. For higher efficiency, Schottky diodes are recommended.

Instead of a diode bridge, a Mosfet based bridge can be used as well to further improve the overall efficiency.

The chip features active protection against surge transients and accidentally applied telephony voltages.

2.2.1 Surge Protection

The surge protection circuit is activated if the VPOS-VNEG voltage exceeds VPROT and the hotswap switch is off (dc-dc is not pow-

ered). If the hotswap switch is on, the surge power is sunk in the dc-dc input capacitance.

The internal surge protection can be overridden with an external TVS if higher than specified surge conditions need be tolerated. The

external surge device must be connected between VPOS an VNEG in parallel to the internal one; therefore, the designer must ensure

that the external surge protection will activate prior to the internal surge protection.

2.2.2 Telephony Protection

The Si3406x provides protection against telephony ringing voltage. The telephony ringing is much longer than the surge pulse but it has

less energy, therefore, the Si3406x has a switch parallel with the supply (between VPOS and VNEG). When the protection circuit is

activated, it turns ON the protection switch; the ringing energy then dissipates on this switch and ringing generator resistance (> 400 Ω).

Si3406x Family Data Sheet

System Overview

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2.2.3 Detection and Classification

When the Si3406x is connected via Ethernet cable to a PSE-enabled Ethernet switch, it must provide a characteristic resistance (~25

kΩ) to the PSE in a given voltage range (2.7–10.1 V). This is called detection. After the PSE detects the PD, the PSE increases the

voltage above the classification threshold 14.5 V. Then, the PD provides the classification current to inform the PSE about its required

power class (Class 1, 2, 3, or 4). Type 1 PSEs will recognize the Class 4 PD as Class 0, providing 15.4 W to the PD. Therefore, the

optimal Class 4 PD application is designed with two power modes: Low-Power mode (for Type 1 PSE) and High-Power mode (for Type

2 PSE). Type 2 PSEs have additional voltage steps before switching on the PD. After an initial classification voltage pulse, the Type 2

PSE reduces the voltage below the mark threshold level (10 V). At that point, the PD should provide a non-valid detection resistance.

Then, the PSE raises a voltage up again to the Class event range (Class 2). Last, before turning ON the dc-dc, the PSE reduces the

voltage again (Mark2). This sequence is recognized by the si3406x, and it pulls down its nT2P pin to inform the application about the

higher available power; otherwise, the application will need to operate in a reduced power consumption state (Type 1) if the PSE is

incapable of delivering Class 4 power.

2.7 V

10.1 V

14.5 V

20.5 V

37 V

57 V

Detection Classification/Mark PD turned ON

Voltage

Time

Reset

IEEE 802.3afstartup

IEEE 802.3atstartup

42 V

42.5 V – 57 V (at)

37 V - 57 V (af)

6.9 V

Class1 Class2

Mark1 Mark2

Figure 2.4. Powered Device Voltages

2.3 Hotswap Switch

The hotswap switch is a high-voltage device that separates the PoE inerface from the dc-dc converter domain. The internal hotswap

switch (HSSW) is turned on (conducting) when the PoE interface voltage goes above VUVLO_R. It provides limited inrush current until

the dc-dc side capacitor is charged. The hotswap switch turns off (open) if voltage on the HSSW switch (HSO-VNEG) is greater than

VHSSW_OFF.

In overload, the hotswap switch goes into current-limiting mode with a current limit of IOVL. It will turn back ON after TWAITHSSW elapses

and the dc-dc input capacitor is recharged, meaning the HSO-VNEG voltage is less than VHSSW_ON.

The hotswap switch (if it is in the on state and conducting) can detect if the current is lower than IMPSth. If automatic sleep mode is

enabled, the chip turns on MPS pulse generation, which ensures that the PSE will not disconnect.

With the Si34061, an external hotswap switch can be used to improve efficiency and reduce thermal stress in high current applications.

For Class 3 applications, using an external hotswap switch is recommended; for Class 4, it is mandatory because the internal hotswap

switch otherwise generates significant heat. When an external hotswap switch is used, intelligent switch control ensures that inrush cur-

rent limiting and automatic MPS request of the internal switch are still supported.

Si3406x Family Data Sheet

System Overview

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2.4 HSSW State Machine

The HSSW operates as simple 4-state state machine:

OFF

INRUSH ON

OVERLOAD

170 mA

10 mA

Figure 2.5. Hotswap Switch 4-State Machine

OFF State

HSSW turn-on is controlled by UVLO, the undervoltage lockout feature. When UVLO is engaged, the HSSW is OFF. In this state, the

HSSW is in idle mode, VNEG and HSO pins are disconnected. In normal operation, a complete detect/classification procedure pre-

cedes the HSSW turn-on, and the control of this sequence is implemented in the state machine logic of the chip.

INRUSH State

After the controller enables the HSSW, the block starts operation in the INRUSH state. In this state the switch itself is not directly turned

on, but operating in a closed-loop current limit mode to avoid high current peaks during the charging of the input capacitor of the dc-dc

converter.

If the VHSSW voltage drops below 380 mV (meaning the bypass cap is 99% charged), the HSSW will change state to ON either in

Type1 classification immediately, or in Type2 classification if the HSSW has been in the INRUSH state for at least 80 ms.

ON State

In ON state, the HSSW switch is completely turned on. The HSSW circuit continuously monitors VHSSW. HSSW will change to OVER-

LOAD state if VHSSW voltage increases over 3.5 V for at least 140 µs.

OVERLOAD State

In OVERLOAD state the HSSW operates in closed-loop low current limit mode. If the VHSSW voltage drops below 380 mV again, and

the HSSW has been in the OVERLOAD state for at least 80 ms, the HSSW will change back to the ON state.

2.4.1 External HSSW FET Driver

An external HSSW FET may be used to improve thermal operation of an Si34061 at very high power loading levels (the top end of

Class 4).

With the Si34061, the chip automatically detects if the EXTHSW pin is connected to VNEG or to a FET gate at startup. If the external

hotswap FET driver will not be used, the EXTHSW pin must be tied to VNEG.

For further information on using an external HSSW FET, please refer to "AN1130: Using the Si3406/Si34061/Si34062 PoE+ and Si3404

PoE PD Controller In Isolated and Non-Isolated Designs".

Si3406x Family Data Sheet

System Overview

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2.5 DC to DC Converter

The dc-dc converter is current-controlled for easier compensation and more robust protection of circuit magnetics. The controller has

the following features:

• High- and low-side error amplifier (supports Buck and Flyback topologies).

• <1 Ω internal switching FET

• Driver for optional synchronous rectification

• Overcurrent detection

• Low current detection

• Cycle skipping at low current and short circuit conditions

• Optional external switching FET driver (Si34061)

• Automatic non-overlap control

SWO

EROUT

FBL

FBH

V11

SYNCL

DRV

1.32 V

gmh

100 µs

gml

100 µs

gmpeak

50 µs

1.32 V

IPEAKLIMIT

VDD

DRV

Non-Overlap

Driver

1:1072

COMP

CLIPPING

VDD

COMP

-270 mV

-30 mV

COMP

LPF

ISNS

CSOFTS

RESET

LOOP COMP

VPOS

IAVG LIMIT

Low Current Detect

VDD

AND

VSS

VPOS

VDD

OSC

UVLO

Thermal

Shutdown

160 °C

Slope

Compensation

Blanking

Time

Short

Detect

Short

Detect

Soft Start

VEROUT Limit

Figure 2.6. Si3406x DC-DC Converter Block Diagram

When the internal switching FET is used with the converter, internal peak current detection is employed. When the EXTGD pin and an

external FET are used with Si34061, an external current sense resistor is used to measure the peak current connected to the SWISNS

pin. Changing that resistor allows the application to set the converter maximum peak current to protect the magnetic components (like

the transformer) from saturation.

Feedback to the dc-dc converter can be provided in three ways:

• High side, referenced to VPOS, connected to FBH pin (Buck converter)

• Low side, referenced to VSS, connected to FBL pin (nonisolated Flyback)

• Directly to EROUT pin by a voltage to current converter (isolated Flyback)

The EROUT pin provides current output (if FBL or FBH is used) and voltage input. Also, the loop compensation impedance is connec-

ted to EROUT. The active voltage range is VEROUT, which is proportional to the converter peak current.

The converter startup is not configurable; soft start is accomplished by internal circuitry. Soft start time is TSOFTSTART. The intelligent

soft start circuit dynamically adjusts the soft start time depending on the connected load.

Si3406x Family Data Sheet

System Overview

silabs.com | Building a more connected world. Rev. 1.0 | 8

2.5.1 Average Current Sensing, Overcurrent, Low-Current Detection, and Output Short Protection

The application average current is sensed by an external resistor (RSENSE) connected between VSS and ISNS. Overcurrent is detected

and triggered when the voltage on the sense resistor exceeds VISNS_OVC. Sizing the resistor allows the designer to set the overcurrent

limit according to application needs. When overcurrent is triggered, the dc-dc controller goes into reset until the overcurrent resolves.

When the overcurrent is no longer present, the controller starts up again with softstart.

This external sense resistor is also used to detect a low current situation. When the voltage on the sense resistor goes below VISNS_LC,

the dc-dc controller disables the sync FET and the external hotswap switch, allowing very low current consumption—the internal hots-

wap switch then measures the chip current internally. If the average current is lower than the PoE maintain power signature (MPS) limit,

and if automatic sleep mode is enabled (using the NSLEEP pin), the chip turns on the MPS generation. See the sleep mode section for

further detail.

The Si3406x integrates output short protection. When the output is shorted, the average input current remains in the normal operating

range. If the controller detects a high EROUT signal for more than 1 ms, it resets the dc-dc controller, and a new startup cycle with soft-

start turn ON follows.

2.5.2 Sync FET Driver

With the Si3406x family, an optional synchronous rectifying FET may be used in place of an output rectifier diode for improved power

conversion efficiency.

A gate driver is provided for this purpose. The synchronous rectifying FET driver is enabled by default in Si3406x configurations, but, if

a synchronous FET is not used in the design, the SYNCL pin must not be connected (do not connect SYNCL to any power or ground

rail). The synchronous rectifying FET driver is disabled only when the dc-dc converter measures low average current (meaning lower

than VISNS_LC on ISNS). This ensures low sleep mode current consumption.

2.6 Tunable Oscillator

The dc-dc frequency can be fixed to 250 kHz or tunable by an external resistor.

The tuning resistor must be connected between the RFREQ pin and VPOS. If RFREQ is shorted to VPOS, the fixed frequency oscillator

will provide the clock, FOSCINT, to the dc-dc converter; otherwise, the resistor will determine the frequency as shown in the curve below.

Figure 2.7. RFREQ Frequency Selector Diagram

Si3406x Family Data Sheet

System Overview

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2.7 Regulators

The chip provides a 5 V output to power LEDs or optocouplers. This is a closed-loop regulator, which ensures accurate output voltage.

The 5 V regulator is supplied by an internal 11 V open loop regulator, which also provides power for the external FET gate drivers. The

11 V regulator is supplied by a coarse regulator, which is also open-loop. With the Si34061 and Si34062, the VT15 pin can be used to

supply this regulator from an optional auxiliary transformer winding. The advantage of doing so is additional power saving since the

external FET drivers’ current is not generated from the PoE 50 V but, rather, from a transformer-provided 12–16.5 V. The application

must be designed to ensure that the absolute maximum rating voltage for the VT15 pin is not exceeded.

2.8 Sleep Mode

The Si3406 and Si34061 have automatic (consumption-based) and non-automatic sleep modes. When SLEEPb is tied to ground, the

automatic sleep mode is enabled, meaning that if the current consumption is lower than IMPSth, the chip will automatically generate

MPS pulses from the PSE. If SLEEPb is tied to VDD, then it will not generate MPS pulses, and the PSE will disconnect if total applica-

tion current consumption drops below 5–10 mA.

For non-automatic sleep mode, tie SLEEPb high at initial startup (right after the hotswap switch turns on). The chip turns OFF automatic

mode, but pulling SLEEPb low will force MPS generation as long as the pin is held low. Using this mode, the designer can control MPS

generation. For details on MPS generation connection, please refer to "AN1130: Using the Si3406/Si34061/Si34062 PoE+ and Si3404

PoE PD Controller In Isolated and Non-Isolated Designs".

2.9 Special Sleep Mode

In the Si34062, a special sleep mode is available which includes LED, WAKE, and MODE pin support. The LED pin drives a light emit-

ting diode to (for example) illuminate a button on the primary side of the application. The WAKE pin triggers wakeup, and the MODE

button controls if MPS generation is enabled in sleep. In the Si34062 case, nSLEEP is used to initiate sleep.

The sleep mode is initiated by a negative transition on nSLEEP. It is latched at that negative transition event together with MODE, so

their status is kept until wakeup even if the input changes on these pins due to the secondary side losing power. MPS generation is

enabled if MODE = 0 at the nSLEEP transition. The following figure shows the Si34062 sleep mode behavior.

Chip Sleep,

dc-dc Off

Mode?

Chip Awake,

dc-dc Runs

WAKE Pos. Edge

NSLEEP Neg.Edge

Low

High

Turn MPS

Generation ON

Figure 2.8. Si34062 Special Sleep Mode Behavior

Refer to Figure 3.3 Si34062 Isolated Flyback Application Diagram on page 13, which shows the connectivity for the Si34062 with the

special sleep mode.

For details on special sleep mode, please refer to "AN1130: Using the Si3406/Si34061/Si34062 PoE+ and Si3404 PoE PD Controller In

Isolated and Non-Isolated Designs".

Si3406x Family Data Sheet

System Overview

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2.10 External Wall Adapter Support

The Si3406x supports using a wide voltage range of external wall adapters as a primary or secondary supply. The controller is able to

provide a stable output voltage with PoE input voltage from the PSE, or with low voltage (12 V) in ASUP mode from the wall adapter.

However, if the transformer was designed and optimized for PoE voltages, then the same transformer will not be able to provide high

power to the application from a low-voltage adapter (12 V). To ensure operation from both PoE input and wall adapter in the full power

range, a high-voltage adapter is recommended.

For details on options and supported modes of adapter connection, please refer to "AN1130: Using the Si3406/Si34061/Si34062 PoE+

and Si3404 PoE PD Controller In Isolated and Non-Isolated Designs".

Si34061

ASUP

HSO

10nF

100k

RASUP

12 V–57 V

WALL ADAPTER

V_ASUP

V_WA D

Figure 2.9. Auxiliary Wall Adapter Connection Example

Si3406x Family Data Sheet

System Overview

silabs.com | Building a more connected world. Rev. 1.0 | 11

3. Application Examples

The following diagrams demonstrate the ease of use and straightforward BOM of the Si3406x Powered Device ICs. Detailed reference

designs are available in Evaluation KIT User Guides. Also refer to "AN1130: Using the Si3406/Si34061/Si34062 PoE+ and Si3404 PoE

PD Controller In Isolated and Non-Isolated Designs".

RFREQ

VPOS VSS

CIN

VPOS

RDET

CT1

CT2

SP1

SP2

RCLASS

EROUT

FBL

SYNCL

SWO

VDD

VNEG

Si3406

VNEG

CDET

VSS VSS VSS

VSS

RCOMP

CCOMP

COUT

syncFET

VOUT

RSENSE

ISNSHSO

VSS

ct1

ct2

sp1

sp2

Figure 3.1. Si3406 Non-Isolated Flyback Application Diagram

RFREQ

VPOS VSS

CIN

VPOS

RDET

CT1

CT2

SP1

SP2

RCLASS

EROUT

VDD

SYNCL

SWO

VDD

VNEG

Si34061

VNEG

CDET

VSS

RCOMP1

CCOMP1

COUT

syncFET

VOUT

VIN

EXTHSW HSO ISNS

RSENSE

VSS

VT15

VSS GNDI

GNDI

EXTHSW

VSS

RCOMP2 CCOMP2

TLV431 R2

GNDI

BIAS

VSS

*GNDI = ISOLATED GROUND

Figure 3.2. Si34061 Isolated Flyback Application Diagram

Si3406x Family Data Sheet

Application Examples

silabs.com | Building a more connected world. Rev. 1.0 | 12

RFREQ

VPOS VSS

CIN

VPOS

RDET

CT1

CT2

SP1

SP2

RCLASS

EROUT

VDD

SYNCL

SWO

VNEG

Si34062

VNEG

CDET

VSS

RCOMP1

CCOMP1

COUT

syncFET

VOUT

HSO ISNS

RSENSE

VSS

VT15

VSS GNDI

GNDI

VSS

RCOMP2 CCOMP2

TLV431 R2

GNDI

VSS GNDI

VDD

nsleep

VDD

'wake'

mode

SLEEP

GNDI

VOUT

WAKE

MODE

NSLEEP

LED

BIAS

nsleep

mode

VSS

VDD

*GNDI = ISOLATED GROUND

ct1

ct2

sp1

sp2

LED

Figure 3.3. Si34062 Isolated Flyback Application Diagram

Si3406x Family Data Sheet

Application Examples

silabs.com | Building a more connected world. Rev. 1.0 | 13

4. Electrical Specifications

Table 4.1. Absolute Maximum Ratings1

Type Description Min Max Units

Voltage

CT1–CT2 or SP1–SP2 –100 100 V

VNEG-VSS, VPOS-VNEG, HSO2, RDET3–0.7 100 V

SWO-VSS –0.7 120 V

ISNS, SWISNS –1 1 V

Low Voltage pins: FBH3, EROUT, FBL,

NSLEEP, RCL2, RFREQ3, ASUP3, WAKE,

MODE, LED

–0.7 6 V

Mid Voltage pins: SYNCL,VT15, EXTGD,

EXTHSW –0.7 18 V

Other Mid Voltage pin: V11 –0.7 12 V

Peak Current CT1, CT2, SP1, SP2, VPOS4–5 5 A

DC Current5CT1, CT2, SP1, SP2 –0.2 0.2 A

Temperature

Storage Temperature –65 150 °C

Ambient Operating Temperature –40 85 °C

Junction Tempertature — 150 °C

Note:

1. Unless otherwise noted, all voltages referenced to VSS. Permanent device damage may occur if the maximum ratings are excee-

ded. Functional operation should be restricted to those conditions specified in the operational sections of this data sheet. Expo-

sure to absolute maximum rating conditions for extended periods may adversely affect device reliability.

2. Voltage referenced to VNEG.

3. Voltage referenced to VPOS.

4. The Si340x provides internal protection from certain transient surge voltages on these pins. Refer to AN1130: Si3404/06x PoE-

PD Controller Design Guide for further details.

5. Higher dc current is possible in the application, but only utilizing external bridge diodes. Refer to reference design documentation

and AN1130: Si3404/06x PoE-PD Controller Design Guide for further details.

Si3406x Family Data Sheet

Electrical Specifications

silabs.com | Building a more connected world. Rev. 1.0 | 14

Table 4.2. Recommended Operating Conditions

Symbol Parameter (Condition) Min Typ Max Unit

VPORT |CT1 – CT2| or |SP1 – SP2| 2.7 — 57 V

VHV_OP VNEG-VSS, VNEG-HSO, VPOS-

VSS, VPOS-VNEG 1.5 — 57 V

VLV_OP VPOS referred low voltage pins:

RFREQ, RDET, FBH –5.5 — 0 V

VLV_OP

VSS referred low voltage pins: VDD,

FBL, EROUT, ASUP, nSLEEP,

nT2P, ASUP, WAKE, MODE, LED1

0 — 5.5 V

VISNS_OP VSS referred current sensing pins:

ISNS, SWISNS –0.5 — 0.5 V

VLV_OP VNEG referred low voltage pins:

RCL 0 — 5.5 V

VMV_OP VSS referred medium voltage pins

SYNCL, EXTGD, EXTHSW 0 — 13 V

VMV_VT15

VSS referred medium voltage pin

VT15212 14.5 16.5 V

IRECT

On chip rectifier current on CT1,

CT2, SP1, SP2—steady state3— — 176 mA

VRECT On chip rectifier voltage @ 200 mA,

2 diodes — 1.8 — V

IRECT_PK

Peak rectifier current Max 75 ms 5%

Duty Cycle4— — 231 mA

IAVG Allowable continuous current on

SWO, VSS, HSO, VNEG — — 600 mA

IMAX Maximum current on HSO, VNEG,

VPOS Max 75 ms 5% Duty Cycle — — 683 mA

Note:

1. For all digital inputs (MODE, NSLEEP, WAKE, ASUP) Voh low to high transition voltage max is 3.7 V; Vol high to low voltage min

is 1.6 V.

2. VMV_VT15 is relevant for Si34061 and Si34062 only when an external auxiliary winding from the primary side of the transformer is

being used to improve power conversion efficiency. This can be left undriven, in which case an internal regulator will be used.

3. For Class 3 and above operation, use external diode bridge rectifiers to bypass the internal input diode bridge rectifiers.

4. The IEEE 802.3at specification allows for higher peak current for transients.

Si3406x Family Data Sheet

Electrical Specifications

silabs.com | Building a more connected world. Rev. 1.0 | 15

Table 4.3. Electrical Characteristics

Excluding detection and classification and unless otherwise noted, 37 V < VPOS – VNEG ≤ 57 V; junction temperature = –40 to +125

°C; typical specs are measured at 25 °C. All voltages are with respect to VSS unless otherwise noted.

Symbol Parameter (Condition) Min Typ Max Unit

PoE PROTOCOL

Detection

VDET

Signature Range (at VPORT)2.7 — 10.1 V

Signature Resistance (at VPORT) 23.75 — 26.25 kΩ

Classification

VRESET Classification Reset (at VPORT)0 — 2.81 V

VCLASS

Classification ON threshold (at VPORT)— — 14.5 V

Classification OFF threshold (at VPORT) 20.5 — — V

IPortCLASS

Class 0 (RCLASS > 681 Ω) 0 — 4 mA

Class 1 (RCLASS = 140 Ω @ 1%) 9 — 12 mA

Class 2 (RCLASS = 75 Ω @ 1%) 17 — 20 mA

Class 3 (RCLASS = 48.7 Ω @ 1%) 26 — 30 mA

Class 4 (RCLASS = 33.2 Ω @ 1 %) 36 — 44 mA

Type 2 Classification

VMARK Mark event voltage (at VPORT)6.9 — 10.1 V

IMARK Mark event current 0.25 — 4 mA

Power On and UVLO

VUVLO_R Hotswap closed and converter on 34 37 40 V

VUVLO_F Hotswap open and converter off 30 32 34 V

VUVLO_HYST 3.5 4.5 6 V

Thermal Characteristics

TSHD Thermal shutdown — 160 — °C

THYST Thermal shutdown hysteresis — 20 — °C

On-Chip Transient Voltage Suppression/Protection

VPROT TVS protection activation voltage (VPOS-

VNEG) 100 — — V

Hotswap Switch

Iinrush Inrush current 100 170 200 mA

IMAXHSSW Maximum continuous operating current — — 600 mA

VHSSW_ON Switch ON voltage — 380 — mV

VHSSW_OFF Switch OFF voltage, HSSW goes to overload

cycle — 3.5 — V

Si3406x Family Data Sheet

Electrical Specifications

silabs.com | Building a more connected world. Rev. 1.0 | 16

Symbol Parameter (Condition) Min Typ Max Unit

IOVL Switch current limit in OVERLOAD State — 10.5 — mA

IMPSth MPS signal request current level threshold 14 20 26 mA

IEXT_DRV External hotswap driver peak current on

EXTHSW pin — — 10 mA

VEXT_DRV External hotswap driver voltage on EXTHSW

pin 9 11 13 V

TWAITHSSW Wait time in OVERLOAD and type 2 inrush 80 96 116 ms

RONHSSW Internal hotswap drain-source resistance while

0.65 1.5 2.9 Ω

DC-DC

ISWOPEAK Peak current limit of internal FET (SWO pin) 2.1 — 2.7 A

VEXTGD External FET driver voltage (EXTGD pin) 9 11 13 V

IEXTGD External FET driver peak current (EXTGD pin) — — 500 mA

FOSCINT Using internal Oscillator 215 250 290 kHz

FOSCEXT

Using external Oscillator,

RFREQ = 215 kΩ 75 95 115 kHz

Using external Oscillator,

RFREQ = 39 kΩ

420 470 520 kHz

DUC Output duty cycle of PWM — — 75 %

VDCDCUVLO DCDC UVLO level (Minimum adapter voltage-

ASUP mode) 10.75 11.3 11.85 V

VFBREF FBH (referenced to VPOS) and FBL (refer-

enced to VSS) reference voltage 1.28 1.32 1.36 V

VEROUT Operating voltage range of error input 1 — 4 V

THICCUP Output short protection if EROUT is max — 1 — ms

VISNS_OVC Overcurrent limit voltage on ISNS (ref. to VSS) –305 –270 –255 mV

VISNS_LC Low current limit voltage on ISNS (ref. to VSS) –45 –30 –15 mV

VSWISNSMAX External FET peak current sense — 240 — mV

TSOFTSTART Startup time1— 15 — ms

RONDCDC Internal DCDC switching FET drain-source re-

sistance while ON

— 0.9 1.2 Ω

Regulators

VT15 Override internal regulator with transformer

winding 12.5 — 16.5 V

VDD 5 V regulated output 4.9 5.2 5.5 V

VDDILIM DC current limit of VDD 9.7 11.2 — mA

CREG Filter capacitor on VDD and V11 82 100 220 nF

IMAXLED LED pin max current, reduces VDDILIM — 5 — mA

IMAXDO

Digital output max current (NT2P), reduces

VDDILIM 2 2.5 — mA

Si3406x Family Data Sheet

Electrical Specifications

silabs.com | Building a more connected world. Rev. 1.0 | 17

Symbol Parameter (Condition) Min Typ Max Unit

Power Dissipation2

PINTMAX DC-DC max power internal FET — 0.2 0.9 W

PMAX Total chip power — 0.5 — W

IPortOP Operating current (VPORT 57 V; 250 kHz) — 3 5 mA

Package Thermal Characteristics2

θJA QFN20 — 44 — C°/W

θJA QFN24 — 38.5 — C°/W

Note:

1. Depends on output load.

2. Assumes 4-Layer PCB with adequate layout.

Si3406x Family Data Sheet

Electrical Specifications

silabs.com | Building a more connected world. Rev. 1.0 | 18

5. Pin Descriptions

Si3406 Pinout

(Top View)

Si34061 Pinout

(Top View)

Si34062 Pinout

(Top View)

FBH

EROUT

FBL

VDD

nSLEEP

RDET

SP2

RCL

RFREQ

SP1

HSO

VPOS

CT2

CT1

VNEG

(ePad)

ISNS

VSS

SYNCL

nT2P

V11

SWO

56 7 8 9 10

16 15

1718

411

ISNS

EROUT

FBL

VDD

nSLEEP

RDET

SP2

RCL

RFREQ

SP1

HSO

VPOS

CT2

CT1

VNEG

(ePad)

SWISNS

VSS

SYNCL

V11

SWO

78 9 10

20 19

2122

11 12

EXTHSW

ASUP

nT2P

VT15

EXTGD

FBH

EROUT

FBL

VDD

nSLEEP

RDET

SP2

RCL

RFREQ

SP1

HSO

VPOS

CT2

CT1

VNEG

(ePad)

ISNS

VSS

SYNCL

V11

SWO

78 9 10

20 19

2122

11 12

LED

WAKE

nT2P

VT15

MODE

Table 5.1. Pin Descriptions

'06

Pins

'061

Pins

'062

Pins

Name Ref Dir. Vrange Description

24 24 SWISNS VSS I 0–1 External FET peak current sense resistor voltage input

20 1 ISNS VSS I -1–0 Chip average current sense resistor input

1 1 FBH VPOS I 0–5.5 High side (VPOS referred) dc-dc feedback (Buck converter)

2 2 2 EROUT VSS IO 0–5.5 Error amplifier current output, compensation impedance input

3 3 3 FBL VSS I 0–5.5 Low side (VSS referenced) dc-dc feedback (Flyback convert-

er)

4 4 4 VDD VSS O 0–5.5 5 V regulator output

5 LED VSS O 0–5.5 Output to drive sleep LED

5 EXTHSW VNEG O 0–11 External hotswap switch drive

6 WAKE VSS I 0–5.5 Wakeup from sleep mode

6 ASUP VSS I 0–5.5 AUX auxiliary adapter present

5 7 7 nSLEEP VSS I 0–5.5 Sleep, with pull-up, driven by open drain

6 8 8 RDET VPOS IO 0–100 Detection resistor

7 9 9 HSO VNEG IO 0–100 Hotswap switch output

8 10 10 RCL VNEG IO 0–5.5 Classification resistor

9 11 11 RFREQ VPOS IO 0–5.5 Oscillator frequency tuning resistor, tie to VPOS to select de-

fault frequency

10 12 12 SP2 SP1 I 0 - 100 High-voltage supply input from spare pair; polarity-insensitive

11 13 13 SP1 SP2 I 0–100 High-voltage supply input from spare pair; polarity-insensitive

12 14 14 VPOS — IO 0–100 Rectified high-voltage supply positive rail

13 15 15 CT2 CT1 I 0–100 High-voltage supply input from main pair; polarity-insensitive

14 16 16 CT1 CT2 I 0 - 100 High-voltage supply input from main pair; polarity-insensitive

Si3406x Family Data Sheet

Pin Descriptions

silabs.com | Building a more connected world. Rev. 1.0 | 19

'06

Pins

'061

Pins

'062

Pins

Name Ref Dir. Vrange Description

15 17 17 nT2P VSS O 0–5.5 Type II classification was successful

18 18 VT15 VSS I 0–16.5 dc-dc transformer bias winding input

16 19 19 SYNCL VSS O 0–11 Gate driver for synchronous rectification FET

17 20 20 V11 VSS IO 0–11 11 V regulator output for filter cap.

21 EXTGD VSS O 0–11 External FET gate drive.

When internal switching FET is in use, tie to VSS.

21 MODE VSS I 0–5.5 Controls MPS and LED switch behavior

18 22 22 SWO VSS O 0–120 Internal dc-dc switch output (NMOS drain)

19 23 23 VSS — IO 0 dc-dc converter primary ground

ePad ePad ePad VNEG — IO 0 Rectified high voltage supply ground

Si3406x Family Data Sheet

Pin Descriptions

silabs.com | Building a more connected world. Rev. 1.0 | 20

5.1 Detailed Pin Descriptions

Table 5.2. Circuit Equivalent and Description of Die Pads

Pin Name Detailed Description Circuit Detail

SWISNS

External dc-dc switching FET peak current sense resistor input. The maxi-

mum current of the switching FET should correspond to voltage VSWISN-

SMAX.

RSWISNS

VDD

SWISNS

VSS

ISNS

Average current sense resistor input. The resistor value will set the maxi-

mum allowed average current for the application. The overcurrent threshold

voltage VISNS_OVC. Note that this pin voltage goes below VSS.

VSS

ISNS

FBH High side dc-dc feedback input. Need to be tied to VPOS when not used.

See VFBREF.

VPOS

FBH

EROUT

dc-dc converter error output; current out, voltage sense. Loop compensat-

ing impedance should be connected here.

IEROUT = (VFBH – VFBREF) x 50 μA or

IEROUT = (VFBL – VFBREF) x 50 μA

VDD

EROUT

VSS

FBL Low side dc-dc feedback input. Need to be tied to VSS when not used. See

VFBREF

VDD

FBL

VSS

Si3406x Family Data Sheet

Pin Descriptions

silabs.com | Building a more connected world. Rev. 1.0 | 21

Pin Name Detailed Description Circuit Detail

VDD

Regulated 5 V relative to VSS. There is no foldback characteristic, reaching

VDDILIM the output voltage decreases.

The regulator needs CREG external capacitance.

VDD

VSS

LED LED driver output Max current is IMAXLED

VDD

LED

VSS

WAKE Wake-up input pin for sleep mode, used only in Si34062.

VDD

WAKE

VSS

ASUP Auxiliary supply adapter is present. Enables the operation of the dc-dc con-

troller without PoE supply being present (used only in Si34061).

VDD

ASUP

VSS

nSLEEP Sleep function input, see description in Sleep mode section.

VDD

nSLEEP

VSS

Si3406x Family Data Sheet

Pin Descriptions

silabs.com | Building a more connected world. Rev. 1.0 | 22

Pin Name Detailed Description Circuit Detail

RCL Classification resistor input. For class 0 this pin can be left floating. Pin is

active only at time of classification.

RCL

VNEG REXT

ICLASS

RFREQ

Used for adjusting the oscillator frequency.

The frequency is inversely proportional to the value of the connected resis-

tor.

RFREQ

REXT

IFREQ

VPOS

SP1, SP2

CT1, CT2

Main power inputs, goes to diode bridge producing VPOS and VNEG. Can

be used up to Class 1 and Class 2. For higher power classes, external

bridge is required.

VPOS

CT1,CT2

SP1,SP2

VNEG

VPOS,

VNEG

Main chip power output generated by the diode bridge. Note that VNEG

(the ePad on the bottom of the chip) also provides thermal relief.

VPOS

CT1,CT2

SP1,SP2

VNEG

nT2P

Pin main function is digital output; it is low if Type 2 classification was suc-

cessful and the application is allowed to draw class 4 current.

Output current is IMAXDO, but the load (e.g. an LED) should connected to

VDD not VSS; otherwise, it can cause false operation.

VDD

nT2P

VSS

Si3406x Family Data Sheet

Pin Descriptions

silabs.com | Building a more connected world. Rev. 1.0 | 23

Pin Name Detailed Description Circuit Detail

HSO Hotswap Switch Output. The switch shorts the VNEG and HSO pins, and in-

cludes several other functions. See hotswap switch section for details.

HSO

VNEG

100V

EXTGD,

SYNCL

EXTGD: Optional external switch driver of the dc-dc converter. When the in-

ternal switch is used this pin should be tied to VSS. This driver controls the

external switch with 10 V logic level, relative to VSS.

SYNCL: Optional synchronous rectifier switch driver of the dc-dc converter.

When not used the pin must be left floating. This driver controls the external

synchronous switch with 10 V logic level, relative to VSS.

V11

EXTGD/

SYNCL

VSS

VCASP

VCASN

EXTHSW

Optional external hotswap switch driver output. The maximum current of the

internal hotswap switch is IMAXHSSW, for higher currents an external NMOS

FET should be used in parallel with the internal HSSW (VNEG-HSO). When

EXTGD is not used the pin should be tied to VNEG. This driver controls the

external switch with 10 V logic level, relative to VNEG.

11V internal supply

EXTHSW

VNEG

VCAS

RDET

The user has to tie the RDET resistor between this pin and VPOS. During

detection, a high voltage switch pulls down RDET to VNEG. After detection,

the reference block uses RDET as absolute chip current reference, forcing

–750 mV relative to VPOS, creating 30 µA for the internal blocks.

VPOS

RDET

VNEG

100V

100V RDET

Si3406x Family Data Sheet

Pin Descriptions

silabs.com | Building a more connected world. Rev. 1.0 | 24

Pin Name Detailed Description Circuit Detail

VT15,

V11

VT15 is input for an optional 15 V supply generated by an auxiliary trans-

former bias winding. If the bias winding voltage is lower than VT15_MIN, the

internal 15 V coarse regulator will provide the current for the 11 V regulator.

The V11 pin is for filtering capacitor for the 11 V regulator. A capacitor of

value CREG is required.

VPOS

VT15

VSS

V11

MODE MPS mode control, used in Si34062.

VDD

MODE

VSS

SWO dc-dc converter switching transistor drain output, Vmax = 120 V.

SWO

VSS

VSS dc-dc converter ground.

VPOS

VSS

120V

ESD

CLAMP

Si3406x Family Data Sheet

Pin Descriptions

silabs.com | Building a more connected world. Rev. 1.0 | 25

6. Packaging

6.1 Package Outline: Si3406

The figure below illustrates the package details for the Si3406. The table lists the values for the dimensions shown in the illustration.

Figure 6.1. 20-Pin, QFN Package

Table 6.1. Package Diagram Dimensions

Dimension Min Nom Max

A 0.80 0.85 0.90

A1 0.00 0.02 0.05

b 0.25 0.30 0.35

D 5.00 BSC.

D2 2.60 2.70 2.80

e 0.80 BSC.

E 5.00 BSC.

E2 2.60 2.70 2.80

L 0.50 0.55 0.60

L1 0.00 — 0.10

aaa — — 0.10

bbb — — 0.10

ccc — — 0.08

ddd — — 0.10

Si3406x Family Data Sheet

Packaging

silabs.com | Building a more connected world. Rev. 1.0 | 26

Dimension Min Nom Max

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VHHB-1.

Si3406x Family Data Sheet

Packaging

silabs.com | Building a more connected world. Rev. 1.0 | 27

6.2 Land Pattern: Si3406

The figure below illustrates the land pattern details for the Si3406. The table lists the values for the dimensions shown in the illustration.

Figure 6.2. 20-Pin, QFN Land Pattern

Table 6.2. Land Pattern Dimensions

Dimension Max

C1 4.70

C2 4.70

X1 0.35

X2 2.80

Y1 1.00

Y2 2.80

e 0.80

Note:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This land pattern design is based on the IPC-7351 guidelines.

Solder Mask Design

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm

minimum, all the way around the pad.

Stencil Design

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.

Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

Si3406x Family Data Sheet

Packaging

silabs.com | Building a more connected world. Rev. 1.0 | 28

6.3 Package Outline: Si34061/62

The figure below illustrates the package details for the Si34061/62. The table lists the values for the dimensions shown in the illustra-

tion.

Figure 6.3. 24-Pin, QFN Package

Table 6.3. Package Diagram Dimensions

Symbol Min Nom Max

A 0.80 0.85 0.90

A1 0.00 0.02 0.05

b 0.25 0.30 0.35

A3 0.20 REF

D 5.00 BSC.

e 0.65 BSC.

E 5.00 BSC.

Si3406x Family Data Sheet

Packaging

silabs.com | Building a more connected world. Rev. 1.0 | 29

Symbol Min Nom Max

D2 2.90 3.00 3.10

E2 2.90 3.00 3.10

L 0.35 0.40 0.45

K 0.20 — —

aaa 0.15

bbb 0.10

ccc 0.10

ddd 0.05

eee 0.08

fff 0.10

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

Si3406x Family Data Sheet

Packaging

silabs.com | Building a more connected world. Rev. 1.0 | 30

6.4 Land Pattern: Si34061/62

The figure below illustrates the land pattern details for the Si34061/62. The table lists the values for the dimensions shown in the illus-

tration.

Figure 6.4. 24-Pin, QFN Land Pattern

Table 6.4. Land Pattern Dimensions

Dimension mm

C1 4.90

C2 4.90

X1 0.35

X2 3.10

Y1 0.85

Y2 3.10

e 0.65

Note:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted

2. This land pattern design is based on the IPC-7351 guidelines

Solder Mask Design

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm

minimum, all the way around the pad.

Stencil Design

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release

2. The stencil thickness should be 0.125 mm (5 mils)

3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.

Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

Si3406x Family Data Sheet

Packaging

silabs.com | Building a more connected world. Rev. 1.0 | 31

7. Top Markings

7.1 Si3406 Top Marking

Figure 7.1. Si3406 Top Marking

Table 7.1. Si3406 Top Marking Explanation

Mark Method: Laser

Pin 1 Mark: Circle = 0.50 mm Diameter (Lower-Left Corner)

Font Size: 2.0 Point (28 mils)

Line 1 Mark Format: Device Part Number Si3406

Line 2 Mark Format: Device Type A = Device Revision A

G = Extended temperature range

M = QFN package

Line 3 Mark Format: TTTTTT Manufacturing Trace Code (assigned at assembly)

Line 4 Mark Format: YY = Year

WW = Work Week

Assembly Year

Assembly Week

Si3406x Family Data Sheet

Top Markings

silabs.com | Building a more connected world. Rev. 1.0 | 32

7.2 Si34061 Top Marking

Figure 7.2. Si34061 Top Marking

Table 7.2. Si34061 Top Marking Explanation

Mark Method: Laser

Pin 1 Mark: Circle = 0.50 mm Diameter (Lower-Left Corner)

Font Size: 2.0 Point (28 mils)

Line 1 Mark Format: Device Part Number Si34061

Line 2 Mark Format: Device Type A = Device Revision A

G = Extended temperature range

M = QFN package

Line 3 Mark Format: TTTTTT Manufacturing Trace Code (assigned at assembly)

Line 4 Mark Format: YY = Year

WW = Work Week

Assembly Year

Assembly Week

Si3406x Family Data Sheet

Top Markings

silabs.com | Building a more connected world. Rev. 1.0 | 33

7.3 Si34062 Top Marking

Figure 7.3. Si34062 Top Marking

Table 7.3. Si34062 Top Marking Explanation

Mark Method: Laser

Pin 1 Mark: Circle = 0.50 mm Diameter (Lower-Left Corner)

Font Size: 2.0 Point (28 mils)

Line 1 Mark Format: Device Part Number Si34062

Line 2 Mark Format: Device Type A = Device Revision A

G = Extended temperature range

M = QFN package

Line 3 Mark Format: TTTTTT Manufacturing Trace Code (assigned at assembly)

Line 4 Mark Format: YY = Year

WW = Work Week

Assembly Year

Assembly Week

Si3406x Family Data Sheet

Top Markings

silabs.com | Building a more connected world. Rev. 1.0 | 34

8. Revision History

Revision 1.0

December, 2018

• Renamed and reordered sections 2.6, 2.7, 2.8, 2.9, and 2.10. Removed section V0.5 section 2.6 and merged with 2.4.1.

• Replaced Figure 2.4 Powered Device Voltages on page 6 with revised version.

• Replaced Figure 2.5 Hotswap Switch 4-State Machine on page 7 with new version.

• Replaced Figure 2.6 Si3406x DC-DC Converter Block Diagram on page 8 with new version.

• Updated 2.10 External Wall Adapter Support with further detail on external wall adapter support.

• Updated Figure 2.9 Auxiliary Wall Adapter Connection Example on page 11.

• Updated 4. Electrical Specifications,

• Added min and max current to Peak Current spec.

•Updated Table 4.1 Absolute Maximum Ratings1 on page 14.

• Added junction temperature.

• Updated Table 4.2 Recommended Operating Conditions on page 15.

• Added VPOS-VNEG to VHV_OP spec and updated min voltage based on final characterization data

• Added note on transition voltages for digital input pins.

• Updated Table 4.3 Electrical Characteristics on page 16.

• Reworded and corrected VDET spec.

• Reworded and corrected VCLASS spec.

• Removed IMARK typ spec.

• Added min and max specs to VUVLO_R, VUVLO_F, and VUVLO_HYST based on final characterization data.

• Removed IOVL max and min specs.

• Added max voltage spec to VEXT_DRV based on final characterization data.

• Added min and max frequency to FOSCINT based on final characterization data.

• Removed TBD on DUC.

• Added min and max spec to VFBREF based on final characterization data.

• Added THICCUP spec.

• Added min and max specs to VISNS_OVC and VISNS_LC based on final characterization data.

• Updated TSOFTSTART based on application data and added note.

• Updated all Regulators specs based on final characterization data.

• Updated package thermal characteristics based on final characterization data.

• Added electrical and junction temperature conditions.

• PINTMAX specification typical value corrected to 0.2 W.

• Updated Table 5.1 Pin Descriptions on page 19.

• Updated Vrange.

• Updated Table 5.2 Circuit Equivalent and Description of Die Pads on page 21.

• Updated V15 and V11 descriptions.

Revision 0.5

February, 2018

• Updated 2. System Overview and 3. Application Examples.

• Added theory of operation and application content.

•Updated Table 4.1 Absolute Maximum Ratings1 on page 14, Table 4.2 Recommended Operating Conditions on page 15, and Table

4.3 Electrical Characteristics on page 16.

• Clarified multiple parameters.

• Added 5.1 Detailed Pin Descriptions.

• Added 6. Packaging including outline and land pattern.

Si3406x Family Data Sheet

Revision History

silabs.com | Building a more connected world. Rev. 1.0 | 35

Revision 0.1

August, 2016

•Initial release.

Si3406x Family Data Sheet

Revision History

silabs.com | Building a more connected world. Rev. 1.0 | 36

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intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"

parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes

without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included

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