1/34April 2004
M93S66, M93S56
M93S46
4K bi t , 2K bi t and 1Kbit (16-bit wi de)
MICROWIRE Ser i al Access EEPROM with Block Protectio n
FEAT URES SUMMAR Y
■Indu stry Standard MICROWIR E Bus
■Sin gle Supply Vo ltage:
– 4.5 to 5.5V for M 93S x6
– 2.5 to 5.5V for M 93Sx 6-W
– 1.8 to 5.5V for M 93Sx 6-R
■Sin gle Organization: by Word (x16)
■Programming Instructions that work on: Word
or Entire Memory
■Self-timed Programm ing Cycle with Auto-
Erase
■U ser Defined Write Protected Area
■Pag e Write Mode (4 words)
■Ready/Busy Signal During Programming
■Speed:
– 1MHz Clock Rate, 1 0ms Write Time
(Current product, identified by process
identification letter F or M)
– 2MHz Clock Rate, 5ms Write Time (New
Product , identified by process
identification letter W or G)
■Seq uent ial Read Oper ation
■Enh anced ESD/ Latch -Up Behavior
■More than 1 Million Erase/Write Cycles
■More than 40 Yea r Data Retention
Figure 1. Packages
PDIP8 (BN)
8
1
SO8 (MN)
150 mil width
8
1
TSSOP8 (DW)
169 mil width
TSSOP8 (DS)
3x3mm body size
M93S66, M93S56, M93S46
2/34
TABLE OF CONTENTS
FEATUR ES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUM MARY DESCRIPT ION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signa l Na mes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. DIP, SO a nd T SSOP Con nections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
POWER-ON DATA PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
INST RUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Instruction Set for the M93S46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 3. Instruction Set for the M93S66 , M93S56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. READ, WRITE, WEN and WDS S equences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. PAWRITE an d WRAL Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
Figure 6. PREAD, PRW RIT E and PREN Sequenc es. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. PRCLEA R and PRDS Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
WRITE PROTECTION AND THE PROTECTION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection Reg ister Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection Reg ister Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
Protection Reg ister Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
Protection Reg ister Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection Reg ister Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
COMMON I/O OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Write Sequence with One Clock Glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CLOCK PUL SE COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
MAXIMU M RATING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC AND AC PARAM ETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7
Table 5. Operating Conditions (M93Sx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Operating Conditions (M93Sx6-W ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. Operating Conditions (M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. A C Measurem ent Condition s (M93S x6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. A C Measurem ent Condition s (M93S x6-W and M93Sx 6-R). . . . . . . . . . . . . . . . . . . . . . . 17
3/34
M93S66, M93S56, M93S46
Figure 9. AC Testing Inpu t Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. Capa citan ce. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. DC Charac teristics (M93Sx6, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 12. DC Charac teristics (M93Sx6, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 13. DC Charact eristics (M93Sx6-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 14. DC Charact eristics (M93Sx6-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 15. DC Characteristics (M93Sx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 16. AC Characteristics (M93Sx6, Device Grade 6 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 17. AC Characteristics (M93Sx6-W, De vice G rade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 18. AC Characteristics (M93Sx6-W, De vice G rade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 19. AC Characteri stics (M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 10.S ync hronous Timing (Start and Op-Code Input). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11.S ync hronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12.S ync hronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 13.P DIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outlin e . . . . . . . . . . . . . . . . . 28
Table 20. P DIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package M echanical Data. . . . . . . . . . 28
Figure 14.S O8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 29
Table 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
29
Figure 15.TSS OP 8 3x3m m² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline
30
Table 22. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outl ine, 3x3mm² body size, Mechanical Data
30
Figure 16.TSS OP 8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 31
Table 23. TSSOP8 – 8 lead Thin Shrink Sma ll Outline, Packag e Mechani ca l Data . . . . . . . . . . . . 31
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 24. Orde ring Inform ation Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 25. How to Identify Current and New Products by the Process Identification Letter . . . . . . . 32
REVISION HISTO RY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 26. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
M93S66, M93S56, M93S46
4/34
SUMMA RY DESCR IPTION
This specification covers a range of 4K, 2K, 1K bit
serial Electrically Erasable Program mable M emo-
ry (EEPROM) products (respe ct ively for M93S66,
M93S56, M93S46). In this text, these product s are
collectively referred to as M93Sx6.
Figure 2. Logic Diagram
Table 1. Signal Names
The M93Sx6 is accessed through a serial input (D)
and out put (Q ) us in g the MICR OWI RE b us prot o-
col. The memory is divided into 256, 128 , 64 x16
bit words (respectively for M93S66, M93S56,
M93S46).
The M93Sx6 is accessed by a set of instructions
which includes Read, W rite, Page Write, W rite A ll
and instructions used to set the memory protec-
tion. These are summarized in Table 2. and Table
3.).
A Read Data from Memory (READ) instruction
loads the address of the first word to be read into
an internal address pointer. The data cont ained at
this address is then clocked out serially. The ad-
dress pointer is automatically incremented after
the data is out put and, if t he Chi p S elect In put (S)
is held High, the M 93Sx6 can output a sequenti al
stream of data words. In this way, t he m emory can
be read as a data stream f rom 16 to 4096 bit s (for
the M93S66), or continuously as the address
counter automatically rolls over to 00h when the
highest address is reached.
Within the time required by a programming cycle
(tW), up to 4 words may be written with help of the
Page Write instruction. the whole memory may
also be erased, or set to a predetermined pattern,
by using the Write All instruction.
Within the memory, a user defined area may be
protected against further Write instructions. The
size of this area i s defined by the content of a Pro-
tection Register, located outside of the memory ar-
ray. As a final protection step, data may be
permanently protected by programming a One
Time Programming bit (OTP bit) which locks the
Protection Register content.
Programming is internal ly self-timed (the external
clock signal on Serial Clock (C) may be stopped or
left running after the start of a Write cycle) and
does not requ ire an erase cycle prior to the Write
instruction. The Write instruction writes 16 bits at a
time into one of the word locations of the M93Sx6,
the Page Write instruction writes up to 4 words of
16 bits to sequential locations, assuming in both
cases that all addresses are outside the Write Pro-
tected area. A fter the start of the programming c y-
cle, a Busy/Ready signal is available on Serial
Data Output (Q) when Chip Select Input (S) is driv-
en High.
Figure 3. DIP, SO and TSSOP Connections
Note: See PACKAGE MECHANICAL section for package dimen-
si ons, and how to ide nt i fy pi n-1.
S Chip Select Input
D Serial Data Input
Q Serial Data Outp ut
C Serial Clock
PRE Protection Register Enable
W Write Enable
VCC Supply Voltage
VSS Ground
AI02020
D
VCC
M93Sx6
VSS
C Q
PRE
W
S
VSS
QW
PREC
SV
CC
D
AI02021
M93Sx6
1
2
3
4
8
7
6
5
5/34
M93S66, M93S56, M93S46
An internal Po wer-on Dat a Prot ec tion m echani sm
in the M93Sx6 inhibits the device when the supply
is too low.
POWER-ON DATA PROTECTION
To prevent data corruption and inadvertent write
operations during power-up, a Power-On Reset
(POR) circuit resets all internal programming cir-
cuitry, and sets the device in the Write Disable
mode.
– At Power-up and Power-down, t he device
must not be selected (that is, Chip Select Input
(S) must be driven Low) until the supply
voltag e reaches the operating value VCC
sp ecif ied in Table 5. to Table 6..
– When VCC reaches its valid level, the device is
properly reset (in the Write Disable mode) and
is ready to decode and execute incoming
instructions.
For the M93Sx6 devices (5V range) the POR
threshold voltage is a round 3V. For the M93Sx6-
W (3V r ange) and M93Sx6-R (2V range) the POR
threshold voltage is around 1.5V.
INSTRUCTIONS
The instruction set of the M93Sx6 devices con-
tains seven instructions, as summarized in Table
2. to Table 3.. Each instruction co nsists of t he fol-
lowing parts, as sh own in F igure 4.:
■Each instruc tion is preceded by a rising edge
on Chip Select Input (S) with Serial Clock (C)
being held Low.
■A start bit, which is the first ‘1’ read on Serial
Dat a Input (D) duri ng the rising edge of Serial
Clock (C).
■Two op-c ode bits, read on Serial Data Input
(D) during the risi ng edge of Serial Clock (C).
(Some instructions also use the first t wo bits of
the address to define the op-code).
■The address bits of the byte or word that is to
be accessed. For the M93S46, the address is
made up of 6 bit s (see T able 2.). F o r th e
M93S56 and M93S66, the address is made up
of 8 bits (see Table 3.).
The M93Sx6 devices are fabricated in CMOS
technology and are therefore able to run as slow
as 0 Hz (static input signals) or as fast as the max-
imum ratings specified in Table 16. to Table 19..
M93S66, M93S56, M93S46
6/34
Table 2. Instruction Set fo r the M93 S4 6
Note: 1. X = Don’t Care bit.
Instruction Description W PRE Start
bit Op-
Code Address1Data Required
Clock
Cycles
Additional
Comments
READ Read Data
from Memory X 0 1 10 A5-A0 Q15-Q0
WRITE Write Data to
Memory 1 0 1 01 A5-A0 D15-D0 25
Write is executed if
the address is not
inside the Protected
area
PAWRITE Page Write to
Memory 10 1 11 A5-A0 N x
D15-D0 9 + N x 16
Write is executed if
all the N addresses
are not inside the
Protected area
WRAL
Write All
Memory
with same
Data
10 1 0001 XXXXD15-D0 25 Write all data if the
Protection Regis ter
is cleared
WEN Write Enable 1 0 1 00 11 XXXX 9
WDS Write Disable X 0 1 00 00 XXXX 9
PRREAD Protection
Register Read X 1 1 10 XXXXXX Q5-Q0
+ Flag
Data Output =
Protection Regis ter
content + Protection
Flag bit
PRWRITE Protection
Register Write 11 1 01 A5-A0 9 Data above specified
address A5-A0 are
protected
PRCLEAR Protection
Register Clear 1 1 1 11 111111 9 Protect Flag is also
cleared (cleared
Flag = 1)
PREN Protection
Register
Enable 1 1 1 00 11XXXX 9
PRDS Protection
Register
Disable 1 1 1 00 000000 9 OTP bit is set
permanently
7/34
M93S66, M93S56, M93S46
Table 3. Instruction Set for th e M93 S6 6, M93S 56
Note: 1. X = Don’t Care bit.
2. Address bi t A7 is not dec oded b y t he M 93S56.
Instruction Description W PRE Start
bit Op-
Code Address1,2 Data Required
Clock
Cycles
Additional
Comments
READ Read Data
from Memory X 0 1 10 A7-A0 Q15-Q0
WRITE Write Data to
Memory 1 0 1 01 A7-A0 D15-D0 27
Write is executed if
the address is not
inside the
Protected area
PAWRITE Page Write to
Memory 10 1 11 A7-A0 N x
D15-D0 11 + N x 16
Write is executed if
all the N
addresses are not
inside the
Protected area
WRAL
Write All
Memory
with same
Data
1 0 1 00 01XXXXXX D15-D0 27 Write all data if the
Protection
Register is cleared
WEN Write Enable 1 0 1 00 11XXXXXX 11
WDS Write Disable X 0 1 00 00XXXXXX 11
PRREAD Protection
Register Read X 1 1 10 XXXXXXXX Q7-Q0
+ Flag
Data Output =
Protection
Register content +
Protection Flag bit
PRWRITE Protection
Register Write 11 1 01 A7-A0 11
Data above
specified address
A7-A0 are
protected
PRCLEAR Protection
Register Clear 1 1 1 11 11111111 11 Protect Flag is also
cleared (clear ed
Flag = 1)
PREN Protection
Register
Enable 1 1 1 00 11XXXXXX 11
PRDS Protection
Register
Disable 1 1 1 00 00000000 11 OTP bit is set
permanently
M93S66, M93S56, M93S46
8/34
Figure 4 . READ, WRITE, W EN and WDS Sequences
Note: For the meanings of An, Xn, Qn and Dn, see Ta bl e 2. and T abl e 3. .
AI00889D
1 1 0 An A0
Qn Q0
DATA OUT
D
S
Q
S
WRITE
ADDR
OP
CODE
10An A0
DATA IN
D
Q
OP
CODE
Dn D01
BUSY READY
S
WRITE
ENABLE
10XnX0
D
OP
CODE
101
S
WRITE
DISABLE
10XnX0
D
OP
CODE
0 00
CHECK
STATUS
ADDR
PREREAD
PRE
W
PRE
W
PRE
9/34
M93S66, M93S56, M93S46
Read
The Read Data from Memory (READ) instruction
outputs serial data on Serial Data Output (Q).
When the instruction is received, the op-co de and
address are decoded, and the data f rom the mem-
ory is transferred to an output shift register. A dum-
my 0 bit is output first, followed by the 16-bit word,
with the most significant bit first. Output data
changes a re tri ggered b y the rising edge of Se rial
Clock (C). The M93Sx6 automatically increments
the internal address register and clocks out the
next byte (or word) as long as the Chip Select In-
put (S) is held Hig h. In this case, the dummy 0 bit
is not out put betwe en by tes (or words) and a con-
tinuous stream of data can be read.
Write Enable and Write Disable
The Write Enable (WEN) instruction enables the
future execution of write instructions, and the Write
Disable (WDS) instruction disables it. When power
is firs t ap p lied, th e M9 3S x 6 initia liz es its elf so that
write instructions are disabled. After an Write En-
able ( WEN) instruction has been executed, writing
remains enabled until an Write Disable (WDS) in-
struction is e xecu ted, or until VCC falls below the
power-on reset threshold voltage. To protect the
memory contents from accidental corruption, it is
advisable to issue the Write Disable (WDS) in-
struction after every write cycle. The Read Data
from Memory (READ) instruction is not affected by
the Write Enable (WEN) or Write Disable (WDS)
instructions.
Write
The Write Data to Memory (WRITE) in st ructi on is
composed of the Start bit plus the op-code fol-
lowed by the address and the 16 data bits to be
written.
Write Enable (W) must be held High before and
during the i nstruction. Input a ddress and data, on
Serial Data Input (D) are sampled on the rising
edge of Serial Clock (C).
After the last data bit has bee n s amp led, the C hip
Select Input (S) must be taken Low before the next
rising edge of Seri al Clock (C). If Chip Select Input
(S) is brought Low before or after this specific time
frame, the self-timed programming cycle will not
be started, and the address ed location will not be
programmed.
While the M9 3Sx6 is performing a write c ycle, but
after a delay (tSLSH) before the status informat ion
becomes available, Chip Select Input (S) can be
driven High to monitor t he status of the write cycle:
Serial Data Output (Q) is driven Low while the
M93Sx6 is still busy, and High when the cycle is
complete, and the M93Sx6 is ready to receive a
new instruction. The M93Sx 6 igno res any data on
the bus wh ile it is busy on a write cycle. O nce t he
M93Sx6 is Ready, Serial Data Output (Q) is driven
High, and remains in this state unt i l a new st art bit
is decode d or the Chi p S elect I nput (S) is brought
Low.
Programming is internally self-timed, so the ext er-
nal Serial Clock (C) may be disconnected or left
running after the start of a write cycle.
M93S66, M93S56, M93S46
10/34
Figu re 5. P AW R I TE and W RA L Seque n c e
Note: F or the m eanings of An, Xn and Dn, pleas e see Tabl e 2. and Table 3..
Page Write
A Page Write to Memory (PAWRITE) instruction
contains the first address to be written, followed by
up to 4 data words .
After the recei pt of each data w ord, bits A 1-A0 of
the internal address regist er are increm ent ed, the
high order bits remaining unchanged (A7-A2 for
M93S66, M93S56; A5-A2 for M93S46). Users
must take care, in the soft ware, to ensure that the
last word address has the same upper order ad-
dress bits as the initial address transmitted to
avoid address roll-over.
The Page Write to Memory (PAWRITE) instruction
will not be executed if any of the 4 words address-
es the protected area.
Write Enable (W) must be held High before and
during the i nstruction. Input a ddress and data, on
Serial Data Input (D) are sampled on the rising
edge of Serial Clock (C).
After the last data bit has bee n s amp led, the C hip
Select Input (S) must be taken Low before the next
rising edge of Seri al Clock (C). If Chip Select Input
(S) is brought Low before or after this specific time
frame, the self-timed programming cycle will not
AI00890C
S
PAGE
WRITE
11An A0
DATA IN
D
Q
OP
CODE
Dn D01
BUSY READY
CHECK
STATUS
ADDR
PRE
W
S
WRITE
ALL
10XnX0
DATA IN
D
Q
OP
CODE
Dn D00
BUSY READY
CHECK
STATUS
ADDR
PRE
W
01
11/34
M93S66, M93S56, M93S46
be started, and the address ed location will not be
programmed.
While the M9 3Sx6 is performing a write c ycle, but
after a delay (tSLSH) before the status information
becomes available, Chip Select Input (S) can be
driven High to monitor t he status of the write cycle:
Serial Data Output (Q) is driven Low while the
M93Sx6 is still busy, and High when the cycle is
complete, and the M93Sx6 is ready to receive a
new instruction. The M93Sx 6 igno res any data on
the bus wh ile it is busy on a write cycle. O nce t he
M93Sx6 is Ready, Serial Data Output (Q) is driven
High, and remains in this state unt i l a new st art bit
is decode d or the Chi p S elect I nput (S) is brought
Low.
Programming is internally self-timed, so the ext er-
nal Serial Clock (C) may be disconnected or left
running after the start of a write cycle.
Wr ite Al l
The Write All Memory with same Data (WRAL) in-
struction is va lid only after the Protection Regi ster
has been cleared by executing a Protection Reg-
ister Clear (PRCLEAR) instruction. The Write All
Me mory with same Data (WRAL) inst ruction simul-
taneously writes the whole memory with the same
data word given in the instruction.
Write Enable (W) must be held High before and
during the i nstruction. Input a ddress and data, on
Serial Data Input (D) are sampled on the rising
edge of Serial Clock (C).
After the last data bit has bee n s amp led, the C hip
Select Input (S) must be taken Low before the next
rising edge of Seri al Clock (C). If Chip Select Input
(S) is brought Low before or after this specific time
frame, the self-timed programming cycle will not
be started, and the address ed location will not be
programmed.
While the M9 3Sx6 is performing a write c ycle, but
after a delay (tSLSH) before the status informat ion
becomes available, Chip Select Input (S) can be
driven High to monitor t he status of the write cycle:
Serial Data Output (Q) is driven Low while the
M93Sx6 is still busy, and High when the cycle is
complete, and the M93Sx6 is ready to receive a
new instruction. The M93Sx 6 igno res any data on
the bus wh ile it is busy on a write cycle. O nce t he
M93Sx6 is Ready, Serial Data Output (Q) is driven
High, and remains in this state unt i l a new st art bit
is decode d or the Chi p S elect I nput (S) is brought
Low.
Programming is internally self-timed, so the ext er-
nal Serial Clock (C) may be disconnected or left
running after the start of a write cycle.
M93S66, M93S56, M93S46
12/34
Figure 6 . PREAD, PRWRITE and PREN Sequences
Note: F or the m eanings of An, Xn and Dn, pleas e see Tabl e 2. and Table 3..
AI00891D
1 1 0 Xn X0
DATA
OUT
D
S
Q
S
Protect
Register
WRITE
ADDR
OP
CODE
10An A0D
Q
OP
CODE
1
BUSY READY
S
Protect
Register
ENABLE
10XnX0
D
OP
CODE
101
CHECK
STATUS
ADDR
PREProtect
Register
READ
PRE
W
PRE
W
An A0 F
F = Protect Flag
M93S66, M93S56, M93S46
14/34
WRITE PROTECTION AND THE PROTECTION REGISTER
The Protection Register on the M93Sx6 is used to
adjust the amount of memory that is to be write
protected. The write prote cted a rea extends from
the addr ess given in t he Protection Register, up to
the top address in the M93Sx6 device.
Two flag bits are used to indicate the Protection
Register status :
– Protect ion Flag: this is used to enable/disable
pro tection of the write-protected area of the
M9 3 S x 6 memory
– OTP bi t: when set, this disables access to the
Protec tion Register, and thus prevents any
further modification s to the value in th e
Protec tion Register.
The lower-bound memory address is wri tten to the
Protection Register using the Protection Register
Write (PRWRITE) instruction. It can be read using
the Protection Register Read (PRREAD) instruc-
tion.
The Protection Register Enable (PREN) instruc-
tion must be executed before any PRCLEAR,
PRWRITE or PRDS instruction, and wi th appropri-
ate levels applied to the Protection Enable (PRE)
and Write Enable (W) s ign als.
Write-access to the Protection Register is
achieved by execut ing the f ollowing sequence:
– Execut e the Write Enable (WEN) instruction
– Execut e the Protection Regi ster Enable
(PREN) instruction
– Execu te one PR WRI TE , PR CL EAR or PRDS
instructions, to set a new boundary address in
the Protection Register, to clear the protection
address (to al l 1s), or permanently to freeze
the value held in the Protection Register.
Protection Regi ster Read
The Protection Register Read (PRREAD) instruc-
tion outputs, on Serial Data Output (Q), the con-
tent of the Protection Register, followed by the
Protection Flag bit. The Protection Enable (PRE)
signal must be driven High before and during the
instruction.
As with the Read Data from Memory (READ) in-
struction, a dummy 0 b it is outp ut first. Since it is
not possible to distinguish bet ween the Protec tion
Register being cleared (all 1s) or having been writ-
ten with all 1s, the user must check the Protection
Flag status (and not the Protection Register con-
tent) to ascertain the setting of the memory protec-
tion.
Protection Register Enable
The Protection Register Enable (PREN) instruc-
tion is used to authorize the use of instructions that
modify the Protection Register (PRWRITE,
PRCLEAR, PRDS). The Protection Register En-
able (PREN) instruction does not modify the Pro-
tection Flag bit value.
Note: A Write Enable (WEN) instruction must be
executed before the Protection Register Enable
(PREN) instruction. Both the Protection Enable
(PRE) and Writ e Enable (W) signals m ust be driv-
en High during the instruction execution.
Protection Regi ster Clear
The Protection Register Clear (PRCLEAR) in-
struction clears the address stored in the Protec-
tion Register to all 1s, so that none of the memory
is write-protected by the Protection Register. How-
ever, it should be noted that all the memory re-
mains protected, in the normal way, using the
Write Enable (WEN) and Write Disable (WDS) in-
structions.
The Protection Register Clear (PRCLEAR) in-
struction clears the Protec tion Flag to 1. B oth the
Protection Enable (PRE) and Write Enable (W)
signals must be driven High during the i nstruct ion
execution.
Note: A Protection Register Enable (PREN) in-
struction must immediately precede the P rotection
Register Clear (PRCLEAR) instruction.
P rote ction Register Write
The Protection Register Write (PRWRITE) instruc-
tion is used to write an address into t he Protection
Register. This i s the addr ess of the first word to be
protected. After the Protection Register Write
(PRWRITE) instruction has been executed, all
memory locations equal to and above the speci-
fied address are protected from writing.
The Protection Flag bit is set to 0, and can be read
with Protection Register Rea d (P RREAD) instruc-
tion. Both the Protection Enable (PRE) and Write
Enable (W) signals must be driven High during the
instruction execution.
Note: A Protection Register Enable (PREN) in-
struction must immediately precede the P rotection
Register Write (PRWRITE) instruction, but it is not
necessary to execute first a Protection Register
Clear (PRCL EAR).
Protection Regi ster Disable
The Protection Register Disable (PRDS) instruc-
tion sets the One Time Programmable (OTP) bit.
This instruction is a ONE TIME O NLY i nstruction
which latches the Protection Register content, this
content is therefore unalterable in the future. Both
the Protection Enable (PRE) and Write Enable (W)
signals must be driven High during the i nstruct ion
execution. The OTP bi t c annot be di rectly read, it
can be checked by reading the content of t he Pro-
tection Register, using the Protection Register
Read (PRREAD) instruction, then by writing this
same value back into the Protect ion Register, us-
15/34
M93S66, M93S56, M93S46
ing the Protection Register Write (PRWRITE) in-
struction. When the OTP bit is set, the Ready/Busy
status cannot appear on Serial Data Output (Q).
When the OTP bit is not set, the Busy status ap-
pears on Serial Data Output (Q).
Note: A Protection Register Enable (PREN) in-
struction must immediately precede the P rotection
Register Disable (PRDS) ins truction.
COMMON I/O OPERATION
Serial Data Output (Q) and Serial Data Input (D)
can be conne cted toget her, through a c urrent lim-
iting resistor, to form a common, single-wire data
bus. Some precautions must be taken when oper-
ating the memory in this way, mostly to prevent a
short circuit current from flowing when the last ad-
dress bit (A0) clashes with t he first data bi t on Se-
rial Data Output (Q). Please see the application
note AN394 for details.
Figure 8. Write Sequence with One Clock Glitch
CL OCK PULSE CO UNTER
In a noisy environment, the number of pulses re-
ceived on Serial Clock (C) may be greater than the
number delivered by the Bus Master (the micro-
controller). This ca n lea d to a misalignment of the
instruction of one or more bits (as shown in Figure
8.) and may lead to the writing of erroneous data
at an erroneous address.
To combat this problem, the M93Sx6 has an on-
chip counter that counts the clock pulse s from the
start bit until the f alling edge of the Chip Select In-
put (S). If the number of clock pulses received is
not the num ber expec t ed, th e WRITE , P AW RITE,
WRALL, PRWRITE or PRCLEAR instruction is
aborted, and the contents of the memory are not
modified.
The numbe r of clock cycles expe ct ed for each in-
struction, and for each member of the M93Sx6
family, are summarized in Table 2. to Table 3.. For
example, a Write Data to Memory (WRITE) in-
struction on the M93S56 (or M93S 66) expects 27
clock cycles from the start bit to the falling edge of
Chip Select Input (S). That is:
1 Start bit
+ 2 Op-code bits
+ 8 Address bits
+ 16 Data bits
AI01395
S
An-1
C
D
WRITE
START D0"1""0"
An
Glitch
An-2
ADDRESS AND DATA
ARE SHIFTED BY ONE BIT
M93S66, M93S56, M93S46
16/34
MAXI MUM RAT IN G
Stressing the device ab ove t he rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at t hese or
any other con ditions ab ove those i ndicated in t he
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rat ing con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 4. Absolute Maximum Ratings
Note : 1. Com pl iant wi th JE DEC S td J- STD- 020 B (for s mall bod y, Sn-P b or Pb as sem bly), the ST EC OPA CK ® 7191395 specificat i on, and
the Eu ropea n di rectiv e on Restr i ct i ons on Hazardous Sub st ances (RoHS ) 2002/95/EU
2. JED EC St d JESD22-A114A (C 1=100 pF, R1=1500 Ω, R2=500 Ω)
Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 150 °C
TLEAD Lead Temperature during Soldering See note 1°C
VOUT Output range (Q = VOH or Hi-Z) –0.50 VCC+0.5 V
VIN Input range –0.50 VCC+1 V
VCC Supply Voltage –0.50 6.5 V
VESD Electrostatic Discharge Voltage (Human Body model) 2–4000 4000 V
17/34
M93S66, M93S56, M93S46
DC AND AC PARAM ETERS
This section summarizes the operating and mea-
surement condition s, and the DC a nd AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Des igners shoul d c heck that the operating
conditions in t heir circuit matc h the measurem ent
conditions when relying on the quoted parame-
ters.
Table 5. Operating Conditions (M93Sx6)
Table 6. Operating Conditions (M93Sx6-W )
Table 7. Operating Conditions (M93Sx6-R )
Table 8. AC Measuremen t Conditions (M93Sx6)
Note: Output Hi- Z is define d as t he point wher e data out is no longer driven.
Table 9. AC Measuremen t Conditions (M93Sx6-W and M93Sx6 -R)
Note: Output Hi- Z is define d as t he point wher e data out is no longer driven.
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 4.5 5.5 V
TAAmbient Operating Temperature (Device Grade 6) –40 85 °C
Ambient Operating Temperature (Device Grade 3) –40 125 °C
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 2.5 5.5 V
TAAmbient Operating Temperature (Device Grade 6) –40 85 °C
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 1.8 5.5 V
TAAmbient Operating Temperature (Device Grade 6) –40 85 °C
Symbol Parameter Min. Max. Unit
CLLoad Capacitance 100 pF
Input Rise and Fall Times 50 ns
Input Pulse Voltages 0.4 V to 2.4 V V
Input Timing Reference Voltages 1.0 V and 2.0 V V
Output Timing Refer ence Volta ges 0.8 V and 2.0 V V
Symbol Parameter Min. Max. Unit
CLLoad Capacitance 100 pF
Input Rise and Fall Times 50 ns
Input Pulse Voltages 0.2VCC to 0.8VCC V
Input Timing Reference Voltages 0.3VCC to 0.7VCC V
Output Timing Refer ence Volta ges 0.3VCC to 0.7VCC V
M93S66, M93S56, M93S46
18/34
Figure 9. AC Testing Input Output Waveforms
Table 10. Capacitanc e
Note: Samp l ed only, not 100% tested , at TA= 25°C and a frequency of 1 MHz.
Symbol Parameter Test Condition Min Max Unit
COUT Output
Capacitance VOUT = 0V 5pF
CIN Input
Capacitance VIN = 0V 5pF
AI02791
2.4V
0.4V
2.0V
0.8V
2V
1V
INPUT OUTPUT
0.8VCC
0.2VCC
0.7VCC
0.3VCC
M93SXX-W & M93SXX-R
M93SXX
19/34
M93S66, M93S56, M93S46
Table 11. DC Characteristics (M93 Sx6 , Device Grade 6)
Note: 1. Current product: identified by Process Identification letter F or M.
2. New product: id ent i fied by Pr ocess I dentification l etter W or G.
Table 12. DC Characteristics (M93 Sx6 , Device Grade 3)
Note: 1. Current product: identified by Process Identification letter F or M.
2. New product: id ent i fied by Pr ocess I dentification l etter W or G.
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leaka ge Curren t 0V ≤ VIN ≤ VCC ±2.5 µA
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA
ICC Supply Current
VCC = 5V, S = VIH, f = 1 MHz, Current
Product 1 1.5 mA
VCC = 5V, S = VIH, f = 2 MHz, New
Product 2 2 mA
ICC1 Supply Current (Stand-by)
VCC = 5V, S = VSS, C = VSS,
Current Product 1 50 µA
VCC = 5V, S = VSS, C = VSS,
New Product 2 15 µA
VIL Input Low Vol tage VCC = 5V ± 10% –0.45 0.8 V
VIH Input High Voltage VCC = 5V ± 10% 2VCC + 1 V
VOL Output Low Voltage VCC = 5V, IOL = 2.1mA 0.4 V
VOH Output High Voltage VCC = 5V, IOH = –40 0µA 2.4 V
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leaka ge Curren t 0V ≤ VIN ≤ VCC ±2.5 µA
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA
ICC Supply Current
VCC = 5V, S = VIH, f = 1 MHz, Current
Product 1 1.5 mA
VCC = 5V, S = VIH, f = 2 MHz, New
Product 2 2 mA
ICC1 Supply Current (Stand-by)
VCC = 5V, S = VSS, C = VSS,
Current Product 1 50 µA
VCC = 5V, S = VSS, C = VSS,
New Product 2 15 µA
VIL Input Low Vol tage VCC = 5V ± 10% –0.45 0.8 V
VIH Input High Voltage VCC = 5V ± 10% 2VCC + 1 V
VOL Output Low Voltage VCC = 5V, IOL = 2.1mA 0.4 V
VOH Output High Voltage VCC = 5V, IOH = –40 0µA 2.4 V
M93S66, M93S56, M93S46
20/34
Table 13. DC Characteristics (M93 Sx6 -W, Device Grade 6)
Note: 1. Current product: identified by Process Identification letter F or M.
2. New product: id ent i fied by Pr ocess I dentification l etter W or G.
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2.5 µA
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA
ICC Supply Current (CMOS
Inputs)
VCC = 5V, S = VIH, f = 1 MHz, Current
Product 1 1.5 mA
VCC = 2.5V, S = VIH, f = 1 MHz, Current
Product 1 1 mA
VCC = 5V, S = VIH, f = 2 MHz, New
Product 2 2 mA
VCC = 2.5V, S = VIH, f = 2 MHz, New
Product 2 1 mA
ICC1 Supply Current (Stand-by)
VCC = 2.5V, S = VSS, C = VSS,
Current Product 1 10 µA
VCC = 2.5V, S = VSS, C = VSS,
New Product 2 5 µA
VIL Input Low Voltage (D, C, S) –0.45 0.2 VCC V
VIH Input High Voltage (D, C, S) 0.7 VCC VCC + 1 V
VOL Output Low Voltage (Q) VCC = 5V, IOL = 2.1mA 0.4 V
VCC = 2.5V, IOL = 100µA 0.2 V
VOH Output High Voltage (Q) VCC = 5V, IOH = –40 0µA 2.4 V
VCC = 2.5V, IOH = –100µA VCC–0.2 V
21/34
M93S66, M93S56, M93S46
Table 14. DC Characteristics (M93 Sx6 -W, Device Grade 3)
Note: 1. New product : i dentified by Proces s I dentification l etter W or G.
Table 15. DC Characteristics (M93Sx6-R)
Note: 1. Prel i m i n ary Dat a: this product is under develo pm ent. For m ore infomat i on, pl ease contact your nearest S T sales off i ce.
Symbol Parameter Test Condition Min 1.Max.
1 Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2.5 µA
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA
ICC Supply Current (CMOS
Inputs) VCC = 5V, S = VIH, f = 2 MHz 2 mA
VCC = 2.5V, S = VIH, f = 2 MHz 1 mA
ICC1 Supply Current (Stand-by) VCC = 2.5V, S = VSS, C = VSS 5 µA
VIL Input Low Voltage (D, C, S) –0.45 0.2 VCC V
VIH Input High Voltage (D, C, S) 0.7 VCC VCC + 1 V
VOL Output Low Voltage (Q) VCC = 5V, IOL = 2.1mA 0.4 V
VCC = 2.5V, IOL = 100µA 0.2 V
VOH Output High Voltage (Q) VCC = 5V, IOH = –40 0µA 2.4 V
VCC = 2.5V, IOH = –100µA VCC–0.2 V
Symbol Parameter Test Condition Min. 1 Max. 1 Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2.5 µA
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA
ICC Supply Current (CMOS
Inputs) VCC = 5V, S = VIH, f = 2 MHz 2 mA
VCC = 1.8V, S = VIH, f = 1 MHz 1 mA
ICC1 Supply Current (Stand-by) VCC = 1.8V, S = VSS, C = VSS 2 µA
VIL Input Low Voltage (D, C, S) –0.45 0.2 VCC V
VIH Input High Voltage (D, C, S) 0.8 VCC VCC + 1 V
VOL Output Low Voltage (Q) VCC = 1.8V, IOL = 100µA 0.2 V
VOH Output High Voltage (Q) VCC = 1.8V, IOH = –100µA VCC–0.2 V
M93S66, M93S56, M93S46
22/34
Table 16. AC Character istics (M93Sx6 , Device Grad e 6 or 3)
Note: 1. tCHCL + tCLCH ≥ 1 / fC.
2. Chi p Sel ect Input (S ) m ust be brought Low for a m i ni m um of tS LSH betw een consecut i ve i nstru ct i on cycles.
3. Current product: identified by Process Identification letter F or M.
4. New product: id ent i fied by Pr ocess I dentification l etter W or G.
Test conditions specified in Table 8. and Table 5.
Symbol Alt. Parameter Min.3Max.3Min.4Max.4Unit
fCfSK Clock Frequenc y D. C. 1 D.C. 2 MHz
tPRVCH tPRES Protect Enable Valid to Clock High 50 50 ns
tWVCH tPES Write Enable Valid to Clock High 50 50 ns
tCLPRX tPREH Clock Low to Protect Enable Transition 0 0 ns
tSLWX tPEH Chip Select Low to Write Enable
Transition 250 250 ns
tSLCH Chip Select Low to Clock High 250 50 ns
tSHCH tCSS
Chip Select Set-up Time
M93C46, M93C56, M93C66 50 50 ns
Chip Select Set-up time
M93C76, M93C86 100 50 ns
tSLSH2tCS Chip Select Low to Chip Select High 250 200 ns
tCHCL1tSKH Cl ock High Time 250 200 ns
tCLCH1tSKL Cl ock Low Time 250 200 ns
tDVCH tDIS Data In Set-up Time 100 50 ns
tCHDX tDIH Data In Hold Time 100 50 ns
tCLSH tSKS Clock Set-up Time (relative to S) 100 50 ns
tCLSL tCSH Chip Select Hold Time 0 0 ns
tSHQV tSV Chip Select to Ready/Busy Status 400 200 ns
tSLQZ tDF Chip Select Low to Output Hi-Z 200 100 ns
tCHQL tPD0 Delay to Output Low 400 200 ns
tCHQV tPD1 Delay to Output Valid 400 200 ns
tWtWP Erase/Wr ite Cycle time 10 5 ms
23/34
M93S66, M93S56, M93S46
Table 17. AC Characteristics (M93 Sx6 -W, Device Grade 6)
Note: 1. tCHCL + tCLCH ≥ 1 / fC.
2. Chi p Sel ect Input (S ) m ust be brought Low for a m i ni m um of tS LSH betw een consecut i ve i nstru ct i on cycles.
3. Current product: identified by Process Identification letter F or M.
4. New product: id ent i fied by Pr ocess I dentification l etter W or G.
Test conditions specified in Table 9. and Table 6.
Symbol Alt. Parameter Min.3Max.3Min.4Max.4Unit
fCfSK Clock Frequenc y D. C. 1 D.C. 2 MHz
tPRVCH tPRES Protect Enable Valid to Clock High 50 50 ns
tWVCH tPES Write Enable Valid to Clock High 50 50 ns
tCLPRX tPREH Clock Low to Protect Enable Transition 0 0 ns
tSLWX tPEH Chip Select Low to Write Enable
Transition 250 250 ns
tSLCH Chip Select Low to Clock High 250 50 ns
tSHCH tCSS Chip Select Set-up Time 100 50 ns
tSLSH2tCS Chip Select Low to Chip Select High 1000 200 ns
tCHCL1tSKH Cl ock High Time 350 200 ns
tCLCH1tSKL Clock Low Time 250 200 ns
tDVCH tDIS Data In Set-up Time 100 50 ns
tCHDX tDIH Data In Hold Time 100 50 ns
tCLSH tSKS Clock Set-up Time (relative to S) 100 50 ns
tCLSL tCSH Chip Select Hold Time 0 0 ns
tSHQV tSV Chip Select to Ready/Busy Status 400 200 ns
tSLQZ tDF Chip Select Low to Output Hi-Z 200 100 ns
tCHQL tPD0 Delay to Output Low 400 200 ns
tCHQV tPD1 Delay to Output Valid 400 200 ns
tWtWP Erase/Wr ite Cycle time 10 5 ms
M93S66, M93S56, M93S46
24/34
Table 18. AC Characteristics (M93 Sx6 -W, Device Grade 3)
Note: 1. tCHCL + tCLCH ≥ 1 / fC.
2. Chi p Sel ect Input (S ) m ust be brought Low for a m i ni m um of tS LSH betw een consecut i ve i nstru ct i on cycles.
3. New product: id ent i fied by Pr ocess I dentification l etter W or G.
Test conditions specified in Table 9. and Table 6.
Symbol Alt. Parameter Min.3Max.3Unit
fCfSK Clock Frequen cy D.C. 2 MH z
tPRVCH tPRES Protect Enable Valid to Clock High 50 ns
tWVCH tPES Write Enable Valid to Clock High 50 ns
tCLPRX tPREH Clock Low to Protect Enable Transition 0 ns
tSLWX tPEH Chip Select Low to Write Enable Transition 250 ns
tSLCH Chip Select Low to Clock High 50 ns
tSHCH tCSS Chip Select Set-up Time 50 ns
tSLSH2tCS Chip Select Low to Chip Select High 200 ns
tCHCL1tSKH Clock High Time 200 ns
tCLCH1tSKL Clock Low Tim e 200 ns
tDVCH tDIS Data In Set-up Time 50 ns
tCHDX tDIH Data In Hold Time 50 ns
tCLSH tSKS Clock Set-up Time (relative to S) 50 ns
tCLSL tCSH Chip Select Hold Time 0 ns
tSHQV tSV Chip Select to Ready/Busy Status 200 ns
tSLQZ tDF Chip Select Low to Output Hi-Z 100 ns
tCHQL tPD0 Delay to Output Low 200 ns
tCHQV tPD1 Delay to Output Valid 200 ns
tWtWP Erase/Write Cycle time 5 ms
25/34
M93S66, M93S56, M93S46
Table 19. AC Characteristics (M93Sx6-R)
Note: 1. tCHCL + tCLCH ≥ 1 / fC.
2. Chi p Sel ect Input (S ) m ust be brought Low for a m i ni m um of tS LSH betw een consecut i ve i nstru ct i on cycles.
3. Pr el i m i nary Dat a: this product i s under dev el opment. For mo re info m ation, pl ease contact yo ur near est ST sal es office.
Test conditions specified in Table 9. and Table 7.
Symbol Alt. Parameter Min.3Max.3Unit
fCfSK Clock Frequen cy D.C. 1 MH z
tPRVCH tPRES Protect Enable Valid to Clock High 50 ns
tWVCH tPES Write Enable Valid to Clock High 50 ns
tCLPRX tPREH Clock Low to Protect Enable Transition 0 ns
tSLWX tPEH Chip Select Low to Write Enable Transition 250 ns
tSLCH Chip Select Low to Clock High 250 ns
tSHCH tCSS Chip Select Set-up Time 50 ns
tSLSH2tCS Chip Select Low to Chip Select High 250 ns
tCHCL1tSKH Clock High Time 250 ns
tCLCH1tSKL Clock Low Tim e 250 ns
tDVCH tDIS Data In Set-up Time 100 ns
tCHDX tDIH Data In Hold Time 100 ns
tCLSH tSKS Clock Set-up Time (relative to S) 100 ns
tCLSL tCSH Chip Select Hold Time 0 ns
tSHQV tSV Chip Select to Ready/Busy Status 400 ns
tSLQZ tDF Chip Select Low to Output Hi-Z 200 ns
tCHQL tPD0 Delay to Output Low 400 ns
tCHQV tPD1 Delay to Output Valid 400 ns
tWtWP Erase/Write Cycle time 10 ms
M93S66, M93S56, M93S46
26/34
Figu re 10 . Sync h ronou s Ti m in g ( Start and Op -Code Inp ut)
Figu re 11 . Sy nchronous Ti m in g (R ea d or W rite )
PRE
W
C
S
DOP CODE OP CODESTART
START OP CODE INPUT
tCHDXtDVCH
tCLSH tCLCH
tCHCLtWVCH
tPRVCH
AI02025
tSHCH
AI002026
C
D
Q
ADDRESS INPUT
Hi-Z
tDVCH
tCLSL
A0
S
DATA OUTPUT
tCHQVtCHDX
tCHQL
An
tSLSH
tSLQZ
Q15 Q0
27/34
M93S66, M93S56, M93S46
Figu re 12 . Sy nchronous Ti m in g (R ea d or W rite )
PRE
W
C
S
D
Hi-Z
tW
tDVCH
AI02027
Q
tCLPRX
tSLWX
tCLSL
tCHDX
tSLSH
tSLQZ
BUSY
tSHQV
READY
WRITE CYCLEADDRESS/DATA INPUT
An A0/D0
tSLCH
M93S66, M93S56, M93S46
28/34
P ACKAGE MECHANICAL
Figure 13. P DIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Packag e Outlin e
No te : Dra wi ng is not to scale.
Table 20. PDIP8 – 8 pin Plastic DIP, 0. 25mm lead fram e, Pac kage Mechanical Data
Symb. mm inches
Typ. Min. Max. Typ. Min. Max.
A 5.33 0.210
A1 0.38 0.015
A2 3.30 2.92 4.95 0.130 0.115 0.195
b 0.46 0.36 0.56 0.018 0.014 0.022
b2 1.52 1.14 1.78 0.060 0.045 0.070
c 0.25 0.20 0.36 0.010 0.008 0.014
D 9.27 9.02 10.16 0.365 0.355 0.400
E 7.87 7.62 8.26 0.310 0.300 0.325
E1 6.35 6.10 7.11 0.250 0.240 0.280
e2.54––0.100––
eA 7.62 – – 0.300 – –
eB 10.92 0.430
L 3.30 2.92 3.81 0.130 0.115 0.150
PDIP-B
A2
A1
A
L
be
D
E1
8
1
c
eA
b2
eB
E
29/34
M93S66, M93S56, M93S46
Figure 14. S O8 nar row – 8 lead Plastic Small Outline, 150 mils body width , Packag e Outline
No te : Dra wi ng is not to scale.
Table 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
Symb. mm inches
Typ. Min. Max. Typ. Min. Max.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e1.27––0.050––
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α0° 8° 0° 8°
N8 8
CP 0.10 0.004
SO-a
E
N
CP
Be
A
D
C
LA1 α
1H
h x 45˚
M93S66, M93S56, M93S46
30/34
Figure 15. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline
No te : Dra wi ng is not to scale.
Table 22. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mech anical Data
Symbol mm inches
Typ. Min. Max. Typ. Min. Max.
A 1.100 0.0433
A1 0.050 0.150 0.0020 0.0059
A2 0.850 0.750 0.950 0.0335 0.0295 0.0374
b 0.250 0.400 0.0098 0.0157
c 0.130 0.230 0.0051 0.0091
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
E 4.900 4.650 5.150 0.1929 0.1831 0.2028
E1 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
CP 0.100 0.0039
L 0.550 0.400 0.700 0.0217 0.0157 0.0276
L1 0.950 0.0374
α0° 6° 0° 6°
TSSOP8BM
1
8
CP
c
L
EE1
D
A2A
α
eb
4
5
A1
L1
31/34
M93S66, M93S56, M93S46
Figure 16. TSS OP8 – 8 lead Thin Shrink S mall Outline, Packa ge Ou tline
No te : Dra wi ng is not to scale.
Table 23. TSSOP8 – 8 l ead Thi n Shrink Small Outl ine, Package Mechanical Data
Symbol mm inches
Typ. Min. Max. Typ. Min. Max.
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
α0° 8° 0° 8°
TSSOP8AM
1
8
CP
c
L
EE1
D
A2A
α
eb
4
5
A1
L1
M93S66, M93S56, M93S46
32/34
PART NUMBERING
Table 24. Ordering Information Scheme
Note: 1 . ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Cer-
tified F l ow (HRCF) is described in the quality not e QNEE9 801. Please ask your nearest ST sales off i ce f or a copy.
2. Avail able on l y on new products: identi f i ed by the P roc ess Ide ntificat i on letter W or G.
Devices are shipped from the factory with the
memory content set at al l 1s (FFh). For a list of available options (speed, package,
etc.) or for further i nf ormation on any aspect of this
device, please con tact your nearest ST Sales O f-
fice.
Table 25. H ow to Identify Current and New Products by the Process Identification Letter
Note: 1. Thi s ex ample comes fro m the S08 pac kage. Ot her packages have simi l ar i nform ation . For f urther i nform at i on, ple ase ask yo ur ST
Sales Office for P roc ess Change Not i ce PCN MP G/EE/0059 (P CEE00 59).
Example: M93S66 – W MN 6 T P
Device Type
M93 = MICROWIRE serial access EEPROM (x16) with
Block Protection
Device Function
66 = 4 Kbit (256 x 16)
56 = 2 Kbit (128 x 16)
46 = 1 Kbit (64 x 16)
Operating Voltage
blank = VCC = 4.5 to 5.5V
W = VCC = 2.5 to 5.5V
R = VCC = 1.8 to 5.5V
Package
BN = PDIP8
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
DS2 = TSSOP8 (3x3mm body size)
Device Grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
3 = Automotive: device tested with High Reliability Certified Flow1 over –40 to 125 °C
Option
blank = Standard Packing
T = Tape & Reel Packing
Plating Technology
blank = Standard SnPb plating
P = Lead-Free and RoHS compliant
G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free
Markings on Current Products1Markings on New Products1
M93S46W6
AYWWF (or AYWWM)M93S46W6
AYWWW (or AYWWG)
33/34
M93S66, M93S56, M93S46
REVISION HISTORY
Table 26. Document Revi sion History
Date Rev. Description of Revision
07-Mar-2002 2.0
Document reformatted, and re worded, using the new template. Temperature range 1 removed.
TSSOP8 (3x3mm) package added. New products, identified by the process letter W, added,
with fc(max) increased to 1MHz for -R voltage range, and to 2MHz for all other ranges (and
correspon ding parame ters adjuste d).
26-Mar-2003 2.1 Value of standby current (max) corrected in DC characteristics tables for -W and -R ranges
VOUT and VIN separated from VIO in the Absolute Maximum Ratings table
14-Apr-2003 2.2 Values corrected in AC characteristics tables for -W range (tSLSH, tDVCH, tCLSL) for devices
with Process Identification Letter W.
23-May-2003 2.3 Standby current corrected for -R range. Four missing parameters restored to all AC
Characteristics tables
24-Nov-2003 3.0 Table of contents, and Pb-free options added. VIL(min) improved to -0.45V.
19-Apr-2004 4.0 Absolute Maximum Ratings for V IO(min) and VCC(min) changed. Soldering temperature
information clarified for RoHS compliant devices. Device Grade 3 clarified, with reference to
HRCF and automotive environments. Process identification letter “G” information added
M93S66, M93S56, M93S46
34/34
Information furnished is believed to b e accurate and reliable. However, S TMicroelectronics assumes no re sponsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication ar e s ub j ect
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authori zed for us e as c ri tical compon ents in lif e support devices or sys te m s without express wr itt en app roval of STMicr oel ectro nics.
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