dsPIC33FJ256MCX06A/X08A/X10A dsPIC33FJ256MCX06A/X08A/X10A Family Silicon Errata and Data Sheet Clarification The dsPIC33FJ256MCX06A/X08A/X10A family devices that you have received conform functionally to the current Device Data Sheet (DS70594C), except for the anomalies described in this document. For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 3 or PICkitTM 3: 1. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. 2. The errata described in this document will be addressed in future revisions of the dsPIC33FJ256MCX06A/X08A/ X10A silicon. Note: 3. 4. This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision (A3). Note: Data Sheet clarifications and corrections start on page 6, following the discussion of silicon issues. SILICON DEVREV VALUES Part Number Device ID(1) dsPIC33FJ256MC510A 0x07B7 dsPIC33FJ256MC710A 0x07BF Note 1: 2: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The Device and Revision ID values for the various dsPIC33FJ256MCX06A/X08A/X10A silicon revisions are shown in Table 1. The silicon revision level can be identified using the current version of MPLAB(R) IDE and Microchip's programmers, debuggers and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: Using the appropriate interface, connect the device to the MPLAB ICD 3 programmer/debugger or PICkit 3. From the main menu in MPLAB IDE, select Configure>Select Device, and then select the target part number in the dialog box. Select the MPLAB hardware tool (Debugger>Select Tool). Perform a "Connect" operation to the device (Debugger>Connect). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. Revision ID for Silicon Revision(2) A2 A3 0x3002 0x3003 The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in program memory. Refer to the "dsPIC33F/PIC24H Flash Programming Specification" (DS70152) for detailed information on Device and Revision IDs for your specific device. (c) 2009-2011 Microchip Technology Inc. DS80484F-page 1 dsPIC33FJ256MCX06A/X08A/X10A TABLE 2: Module SILICON ISSUE SUMMARY Feature Item Number Affected Revisions(1) Issue Summary A2 A3 X ECANTM WAKIF bit 1. The WAKIF bit in the CxINTF register cannot be cleared by software instruction after the device is interrupted from Sleep due to activity on the CAN bus. X ECAN DMA 2. False DMA Error Traps may be generated in applications that perform both transmissions and receptions using ECAN with DMA. X QEI Timer Gated Accumulation 3. When Timer Gated Accumulation is enabled, the QEI does not generate an interrupt on every falling edge. X X QEI Timer Gated Accumulation 4. When Timer Gated Accumulation is enabled, and an external signal is applied, the POSCNT increments and generates an interrupt after a match with MAXCNT. X X UART Break Characters 5. The UART module will not generate consecutive break characters. X X ADC DONE bit 6. The ADC Conversion Status bit (DONE) does not work when External Interrupt is selected as the ADC trigger source. X X SPI TBF bit 7. Writing to the SPIBUF register as soon as the TBF bit is cleared will cause the SPI module to ignore the written data. X X DMA Controller CPU Write Collision Detection 8. DMA CPU write collisions will not be detected. ADC Current Consumption in Sleep Mode 9. If the ADC module is in an enabled state when the device enters Sleep mode, the power-down current (IPD) of the device may exceed the device data sheet specifications. X X All 150C Operation 10. Affected revisions of silicon only support 140C operation instead of 150C for extended operating temperature. X X CPU Interrupt Disable 11. When a previous DISI instruction is active (i.e., the DISICNT register is non-zero), and the value of the DISICNT register is updated manually, the DISICNT register freezes and disables interrupts permanently. X X CPU div.sd 12. When using the div.sd instruction, the overflow bit is not getting set when an overflow occurs. X X UART TX Interrupt 13. A transmit (TX) Interrupt may occur before the data transmission is complete. X X JTAG Flash Programming 14. JTAG Flash programming is not supported. X X Note 1: X Only those issues indicated in the last column apply to the current silicon revision. DS80484F-page 2 (c) 2009-2011 Microchip Technology Inc. dsPIC33FJ256MCX06A/X08A/X10A Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A3). 1. Module: ECANTM The WAKIF bit in the CxINTF register cannot be cleared by software instruction after the device is interrupted from Sleep due to activity on the CAN bus. When the device wakes up from Sleep due to CAN bus activity, the ECAN module is placed in operational mode. The ECAN Event interrupt occurs due to the WAKIF flag. Trying to clear the flag in the Interrupt Service Routine (ISR) may not clear the flag. The WAKIF bit being set will not cause repetitive Interrupt Service Routine execution. Work around Although the WAKIF bit does not clear, the device Sleep and ECAN Wake functions continue to work as expected. If the ECAN event is enabled, the CPU will enter the Interrupt Service Routine due to the WAKIF flag getting set. The application can maintain a secondary flag, which tracks the device Sleep and Wake events. Affected Silicon Revisions A2 A3 X X 2. Module: ECAN In user applications that perform both transmissions and receptions using ECAN with DMA, intermittent DMA Write Collisions might get generated, resulting in the generation of DMA Error Traps. The ECAN messages would be transmitted and received correctly even when these DMA Error Traps occur. Work around Within the DMA Error Trap service routine in the application software, read the DMACS0 register and inspect the two XWCOLn (n = 0, 1, ...,7) bits corresponding to the DMA channels being used for ECAN transmission and reception. For example, if DMA Channel 1 is used for ECAN Reception and DMA Channel 2 is used for ECAN Transmission, inspect the XWCOL1 and XWCOL2 bits. If either of these bits is found to be set, clear the DMACERR bit in the INTCON1 register and return from the DMA Error Trap service routine. Affected Silicon Revisions A2 A3 X 3. Module: QEI When the TQCS and TQGATE bits in the QEIxCON register are set, a QEI interrupt should be generated after an input pulse on the QEA input. This interrupt is not generated in the affected silicon. Work around None. Affected Silicon Revisions (c) 2009-2011 Microchip Technology Inc. A2 A3 X X DS80484F-page 3 dsPIC33FJ256MCX06A/X08A/X10A 4. Module: QEI 7. Module: SPI When the TQCS and TQGATE bits in the QEIxCON register are set, the POSCNT counter should not increment but erroneously does, and if allowed to increment to match MAXCNT, a QEI interrupt will be generated. Writing to the SPIxBUF register as soon as the TBF bit is cleared will cause the SPI module to ignore the written data. Applications that use SPI with DMA are not affected by this erratum. Work around After the TBF bit is cleared, wait for a minimum duration of one SPI clock before writing to the SPIxBUF register. To prevent the erroneous increment of POSCNT while running the QEI in Timer Gated Accumulation mode, initialize MAXCNT = 0. Affected Silicon Revisions A2 A3 X X 5. Module: UART The UART module will not generate consecutive break characters. Trying to perform a back-to-back Break character transmission will cause the UART module to transmit the dummy character used to generate the first Break character instead of transmitting the second Break character. Break characters are generated correctly if they are followed by non-Break character transmission. Work around None. Affected Silicon Revisions A2 A3 X X 6. Module: ADC The ADC Conversion Status (DONE) bit (ADxCON1<0>) does not indicate completion of conversion when External Interrupt is selected as the ADC trigger source (ADxCON1<SSRC> = 1). Work around Alternatively, do one of the following: * Poll the RBF bit and wait for it to get set before writing to the SPIxBUF register * Poll the SPI Interrupt flag and wait for it to get set before writing to the SPIxBUF register * Use an SPI Interrupt Service Routine * Use DMA Affected Silicon Revisions A2 A3 X X 8. Module: DMA Controller DMA CPU write collisions will not be detected, and the corresponding XWCOLn bit (n = 0, 1, ..., 7) will not be set. As a result, a CPU write collision event will not generate a DMA Error Trap. Work around None. Before writing to any memory location in DMA RAM, ensure that none of the enabled DMA channels is using the same memory location for data transfers from a peripheral. Affected Silicon Revisions A2 A3 X Work around Use an ADC interrupt or poll ADxIF bit in the IFSx registers to determine the completion of conversion. Affected Silicon Revisions A2 A3 X X DS80484F-page 4 (c) 2009-2011 Microchip Technology Inc. dsPIC33FJ256MCX06A/X08A/X10A 9. Module: ADC 12. Module: CPU If the ADC module is in an enabled state when the device enters Sleep mode as a result of executing a PWRSAV #0 instruction, the device power-down current (IPD) may exceed the specifications listed in the device data sheet. This may happen even if the ADC module is disabled by clearing the ADON bit prior to entering Sleep mode. When using the Signed 32-by-16-bit Division instruction, div.sd, the overflow bit does not always get set when an overflow occurs. Work around Affected Silicon Revisions In order to remain within the IPD specifications listed in the device data sheet, the user software must completely disable the ADC module by setting the ADC Module Disable bit in the corresponding Peripheral Module Disable register (PMDx), prior to executing a PWRSAV #0 instruction. Affected Silicon Revisions A2 A3 X X 10. Module: All The affected silicon revisions listed below are not warranted for operation at 150C. Work around Only use the affected revisions of silicon for Hi-Temp operating range from -40C to +140C. Affected Silicon Revisions A2 A3 X X 11. Module: CPU When a previous DISI instruction is active (i.e., the DISICNT register is non-zero), and the value of the DISICNT register is updated manually, the DISICNT register freezes and disables interrupts permanently. Work around Avoid updating the DISICNT register manually. Instead, use the DISI #n instruction with the required value for `n'. Work around Test for and handle overflow conditions outside of the div.sd instruction. A2 A3 X X 13. Module: UART When using UTXISEL = 01 (Interrupt when last character is shifted out of the Transmit Shift Register) and the final character is being shifted out through the Transmit Shift Register, the Transmit (TX) Interrupt may occur before the final bit is shifted out. Work around If it is critical that the interrupt processing occur only when all transmit operations are complete. Hold off the interrupt routine processing by adding a loop at the beginning of the routine that polls the Transmit Shift Register Empty bit (TRMT) before processing the rest of the interrupt. Affected Silicon Revisions A2 A3 X X 14. Module: JTAG JTAG Flash programming is not supported. Work around None. Affected Silicon Revisions A2 A3 X X Affected Silicon Revisions A2 A3 X X (c) 2009-2011 Microchip Technology Inc. DS80484F-page 5 dsPIC33FJ256MCX06A/X08A/X10A Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS70594C): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. No issues to report at this time. DS80484F-page 6 (c) 2009-2011 Microchip Technology Inc. dsPIC33FJ256MCX06A/X08A/X10A APPENDIX A: REVISION HISTORY Rev A Document (9/2009) Initial release of this document; issued for revision A2 silicon. Includes silicon issues 1-2 (ECANTM), 3-4 (QEI), 5 (UART), 6 (ADC) and 7 (SPI). Rev B Document (12/2009) Added Rev. A3 silicon information. Added silicon issue 8 (DMA Controller). Rev C Document (6/2010) Added silicon issue 9 (ADC) and data sheet clarification 1 (DC Characteristics: I/O Pin Input Specifications). Rev D Document (9/2010) Added silicon issue 10 (All). Rev E Document (3/2011) Removed data sheet clarification 1. Rev F Document (11/2011) Added silicon issues 11 (CPU), 12 (CPU), 13 (UART), and 14 (JTAG). (c) 2009-2011 Microchip Technology Inc. DS80484F-page 7 dsPIC33FJ256MCX06A/X08A/X10A NOTES: DS80484F-page 8 (c) 2009-2011 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009-2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-814-7 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2009-2011 Microchip Technology Inc. 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