Teledynee2vSemiconductorsSAS2017
EV12DS460AZP
CommercialandIndustrialGrade
Lowpower12‐bit6.0GSpsDigitaltoAnalog
Converterwith4/2 :1Multiplexer
DatasheetDS1167
WhilstTeledynee2vSemiconductorsSAShastakencaretoensuretheaccuracyoftheinformationcontainedhereinitacceptsnoresponsibilityforthe
consequencesofanyusethereofandalsoreservestherighttochangethespecificationofgoodswithoutnotice.Teledynee2vSemiconductorsSASaccepts
noliabilitybeyondthesetoutinitsstandardconditionsofsaleinrespectofinfringementofthirdpartypatentsarisingfromtheuseofthedevicesin
accordancewithinformationcontainedherein.
Teledynee2vSemiconductorsSAS,avenuedeRochepleine38120Saint‐Egrève,FranceHoldingCompany:Teledynee2vSemiconductorsSAS
Telephone:+33(0)476583000
ContactTeledynee2vbye‐mail:hotline‐bdc@teledyne‐e2v.comorvisitwww.teledyne‐e2v.comforglobalsalesandoperationscentres
MAINFEATURES
•12‐bitresolution
•6.0GSpsguaranteedconversionrate
•7.0GSpsoperation
•‐3dBAnalogoutputBandwidthof7.5GHz
(30psriseandfalltimeonDACoutputstepresponse)
•SupportRFsignalsynthesisupto12GHz(X‐band)
•SupportRFsignalsynthesisupto24GHz(withreduced
outputpower)
•4:1or2:1integratedparallelMUX(selectable)
•Selectableoutputmodes:
ReturnToZero(RTZ),NonReturntoZero(NRZ),Narrow
ReturnToZero(NRTZ)andRadioFrequency(RF)
•Lowlatencytime:3clockcycles
•2.6WattPowerDissipation(in4:1MUX)
•3WiresSerialInterface
•Functions:
– SelectableMUXratio4:1(upto6.0GSps),2:1(upto
3.2 GSps)
–User‐friendlyfunctions,digitallycontrolledthrougha
3WSIserialinterface:
•GainAdjustment
• Outputclockdivisionselection(possibilitytochange
thedivisionratiooftheDSPclock)(OCDS)
•ReshapedPulseWidth(RPW)andReshapedPulse
Begin(RPB)adjustmentsforperformance
optimization
•ClockphaseshiftselectforsynchronizationwithDSP
(PSS[2:0])
• InputUnderClockingModeby1/2/4(IUCM)
•DirectaccessavailableforbitOCDSandPSS
• InputdatacheckbitfortiminginterfacewithFPGA
check(IDC)
•Timingviolationflag(setuporhold)forFPGA
• communicationmonitoring(TVF)
•LVDSdifferentialdatainputandDSPclockoutput.
•Analogoutputdifferentialswing:1Vpp(100differential
impedance)
•ExternalSYNCthatcanbeusedforsynchronizationof
multipleDACs
•Powersupplies:3.3V(Digital),3.3V&5V(Analog)
•FpBGApackage(15x15mmbodysize,1mmpitch)
PERFORMANCES@6.0GSps
•SFDR
–1
stNyquist(NRTZ‐2940MHz):SFDR=56dBc
–2
ndNyquist(RF‐5940MHz):SFDR=58dBc
–3
rdNyquist(RF‐8940MHz):SFDR=49dBc
–4
thNyquist(RF‐11950MHz):SFDR=49dBc
–7
thNyquist(RF‐18070MHz):SFDR=43dBc
–8
thNyquist(RF‐23950MHz):SFDR=38dBc
•IMD3Dual‐tone
–1
stNyquist(NRTZ‐2850&2860MHz):IMD3=73dBc
–2
ndNyquist(RF‐5750&5760MHz):IMD3=64dBc
–3
rdNyquist(RF‐8850&8860MHz):IMD3=57dBc
–4
thNyquist(RF‐11850&11860MHz):IMD3=58dBc
•BroadbandNPRat‐14dBFSLoadingFactor(90%offull
Nyquistzone)
–1
stNyquist(NRTZ):NPR=44dB,8.8BitEquivalent
–2
ndNyquist(NRTZ):NPR=39.5dB,8.1BitEquivalent
–3
rdNyquist(RF):NPR=36.5dB,7.6BitEquivalent
•ACPR=42dBc,channelwidth=10MHzQPSK,carrier
frequency=10.6GHz(X‐Band)
•DOCSIS3.0Compatible
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1. BLOCKDIAGRAM
Figure1‐1. Simplifiedblockdiagram
2. DESCRIPTION
TheEV12DS460Aisa12‐bit6.0GSpsDACwithanintegrated4:1or2:1multiplexerand7.5GHzoutput
bandwidth,allowingeasyinterfacewithstandardFPGAsthankstouserfriendlyfeaturessuchasDSP
clock,OCDS,PSS,TVF.
Itembeds4differentoutputmodes(NRZ,RTZ,NRTZandRF)thatallowperformanceoptimizations
dependingontheNyquistzoneofinterest.
1st
M/S 2nd
M/S
DAC
Core
(NRZ,
RTZ,
NRTZ,
RF)
DSP CLOCK
PHASE SHIFT
CLOCK
DIV/X
CLOCK
BUFFER
PSS[2:0]
DSP
DSPN
24
1
24
24
24
2
CLK, CLKN
Port Select
24 2
Latches Latches MODE
[1:0]
MUX
TVF
SYNC,
SYNCN
FPGA
GA
A
B
C
D
24
24
24
24
OUT,
OUTN
DIODE
4 data ports
(12-bit
differential)
IDC_P
IDC_N
OCDS
FPGA
TIMING
2
23WSI
3
sclk,
sdata,
sld_n
Reset_n
3
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3. ELECTRICAL CHARACTERISTICS
3.1 AbsoluteMaximumratings
Notes: 1. Absolutemaximumratingsarelimitingvalues(referencedtoGND=0V),tobeappliedindividually,whileother
parametersarewithinspecifiedoperatingconditions.Longexposuretomaximumratingmayaffectdevicereliability.
2. AllintegratedcircuitshavetobehandledwithappropriatecaretoavoiddamagesduetoESD.Damagecausedby
inappropriatehandlingorstoragecouldrangefromperformancesdegradationtocompletefailure.
3. MaximumratingsenableactiveinputswithDACpoweredoff.
4. MaximumratingsenablefloatinginputswithDACpoweredon.
5. DSPclockandTVFoutputbuffersmustnotbeshortedtogroundorpositivepowersupply.
Table3‐1. Absolutemaximumratings
Parameter Symbol
Value Unit
min max
VCCA5analogsupplyvoltage VCCA5 –0.6 6.0 V
VCCA3analogsupplyvoltage VCCA3 –0.6 4.0 V
VCCDdigitalsupplyvoltage VCCD –0.6 4.0 V
Digitalinput(oneachsingle‐endedinput),IDCand
SYNCsignal
[P0..P11],
[P0N..P11N],
IDC_P,IDC_N,
SYNC,SYNCN
0V
CCA3 V
Digitalinputmaximumdifferentialswing
PortP=A,B,C,D2.0 Vpp
Masterclockinput(oneachsingleendedinput) CLK,CLKN 1.0 4.0 V
Masterclockmaximumdifferentialswing 3 Vpp
Controlfunctioninputsvoltage
PSS[0..2],OCDS,
reset_n,sclk,
sdata,sld_n
–0.4 VCCD+0.4 V
Junctiontemperature TJ170 °C
Parameter Symbol Value Unit
Electrostaticdischargehumanbodymodel ESDHBM JESD22‐A114‐EClass1C
(1000Vto<2000V)
V
Electrostaticdischargemachinemodel ESDMM JESD22‐A115‐CClassM2
(100Vto<200V)
Latchup JEDEC78B
ClassI&ClassII
Moisturesensitivitylevel MSL 3
Storagetemperaturerange Tstg –65to+150 °C
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3.2 Recommendedconditionsofuse
Notes: 1. SeeSection8.8onpage83forpoweronrequirement
2. Nopower‐downsequencingisrequired
3. Clockinputpowercanbedecreasedwhenclockfrequencyisloweraslongasitrespectsthespecification.
4. AgoodcompromiseforRPB&RPWvaluesisdefinedfora6.0GHzclockfrequency.Thiscoupleofvaluesdependsonthe
clockfrequency.TheserecommendedRPB/RPWcoupleshavebeenchosentooffergoodperformancesovertheNyquist
ofuse(1stand2ndinNRTZmode,2ndand3rdinRFmode)atFclock=6.0GHz.Forspecificcondition(forexamplelooking
attheSFDRataparticularoutputfrequency),aRPB/RPWoptimizationcanincreaseperformances.
Table3‐2. Recommendedconditionsofuse
Parameter Symbol
Recommended
Value Unit Note
VCCA5analogsupplyvoltage VCCA5 5.0 V (1)(2)
VCCA3analogsupplyvoltage VCCA3 3.3 V (1)(2)
VCCDdigitalsupplyvoltage VCCD 3.3 V (1)(2)
Digitalinput(oneachsingleendedinput),IDCandSYNCsignal
PortP=A,B,C,D
VIL
VIH
Digitalinputdifferentialswing
[P0..P11],
[P0N..P11N],
IDC_P,IDC_N,
SYNC,SYNCN
1.075
1.425
350
V
V
mVp
MasterClockinputdifferentialmodeswing CLK,CLKN 1.4 Vpp
MasterClockinputpowerlevel
(differentialmode) PCLK 4dBm
(3)
Controlfunctioninputs
VIL
VIH
PSS[0..2],OCDS,
reset_n,
sclk,sdata,sld_n
0
VCCD
V
V
RPB&RPWsettingsforenhanceddynamicperformance6.0GSpsin
NRTZmode
RPB
RPW
RPB2
RPW0
–
–
(4)
RPB&RPWsettingsforenhanceddynamicperformance6.0GSpsin
RFmode
RPB
RPW
RPB1
RPW0
–
–
(4)
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3.3 DCElectricalCharacteristics
Unlessotherwisespecified:VCCA5=5V,VCCA3=3.3V,VCCD=3.3V,4:1MUXratio,roomtemperature,
typicalswingoninputdata,typicalPclk,masterclockinputjitterisbelow100fsrmsintegratedover
11 GHzbandwidth.
Table3‐3. DCElectricalcharacteristics
Parameter Symbol Min Typ Max Unit Notes
Test
level(1)
RESOLUTION 12 bit
POWERREQUIREMENTS
PowerSupplyvoltage
‐Analog
‐Analog
‐Digital
VCCA5
VCCA3
VCCD
4.75
3.15
3.15
5
3.3
3.3
5.25
3.45
3.45
V
V
V
(2) 1
PowerSupplycurrent(4:1MUX)
‐Analog
‐Analog
‐Digital
ICCA5
ICCA3
ICCD
85
170
360
100
205
425
115
240
490
mA
mA
mA
(8) 1
PowerSupplycurrent(2:1MUX)
‐Analog
‐Analog
‐Digital
ICCA5
ICCA3
ICCD
85
170
310
100
205
370
115
240
430
mA
mA
mA
(8) 1
Powerdissipation(4:1MUX) PD4 2.2 2.6 3 W (8) 1
Powerdissipation(2:1MUX) PD2 2 2.4 2.8 W (8) 1
DIGITALDATAINPUTS,SYNCandIDCINPUTS
Logiccompatibility LVDS
Digitalinputvoltages:
‐Differentialinputvoltage
‐Commonmode
VID
VICM
100
1
350
1.25
500
1.6
mVp
V
1
1
Inputcapacitancefromeachsingleinputtoground 2 pF 5
Differentialinputresistance 80 100 120 1
CLOCKINPUTS
Inputvoltages(Differentialoperationswing) 0.6 1.4 2.4 Vpp 1
Powerlevel(Differentialoperation) –4 4 +8.5 dBm (3) 1
Commonmode 2.4 2.5 2.6 V 1
Inputcapacitancefromeachsingleinputtoground(at
dielevel) 2pF 5
DifferentialInputresistance: 80 100 120 1
DSPCLOCKOUTPUT
Logiccompatibility LVDS
Outputvoltages:
‐Differentialoutputvoltage
‐Commonmode
VOD
VOCM
240
1.125
350
1.250
450
1.375
mVp
V
(10) 1
1
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Notes: 1. SeeSection3.6onpage18forexplanationoftestlevels.
ANALOGOUTPUT
Full‐scaleDifferentialoutputvoltage(100differentially
terminated) 0.92 1 1.08 Vpp 1
Full‐scaleoutputpower(differentialoutputon100)+1dBm
(4) 1
Single‐endedmid‐scaleoutputvoltage(50
terminated)VCCA5–0.50 VCCA5–0.43 VCCA5–0.36 V (5) 1
Outputcapacitance 1.5 pF 5
NominalOutputinternaldifferentialresistance 90 100 110 1
OutputVSWR(usingTeledynee2v’sevaluationboard)
2.25GHz
4.5GHz
6.0GHz
1.2
1.4
1.7
4
–3dBAnalogOutputbandwidth 7.5 GHz 4
FUNCTIONS
Digitalfunctions:sdata,sld_n,sclk,reset_n,OCDS,PSS
‐Logic0
‐Logic1
VIL
VIH 1.6
0
VCCD
0.8 V
V
1
sdata,sld_n,sclk,reset_n
‐LowLevelinputcurrent
‐HighLevelinputcurrent
IIL
IIH
–120
10
–55
80
–10
120
µA
µA
1
OCDS,PSS:
‐LowLevelinputcurrent
‐HighLevelinputcurrent
IIL
IIH
–150
50
–100
100
–50
150
µA
µA
1
DigitaloutputfunctionTVF
‐Logic0
‐Logic1
VOL
VOH 2.3
0.6 V
V
(8) 1
IOL
IOH
500
500
µA
µA5
DCACCURACY
DifferentialNon‐Linearity DNL+ 0.4 0.8 LSB 1
DifferentialNon‐Linearity DNL‐–0.8 –0.4 LSB 1
IntegralNon‐Linearity INL+ 0.7 2.5 LSB 1
IntegralNon‐Linearity INL‐–2.5 –0.7 LSB 1
DCGAIN
DACoutputvoltage(@defaultvalue) 0.92 1.08 Vpp (6) 1
DACoutputvoltageadjustmentstep –5 0.3 +5 mV 1
DACoutputvoltageafteroptimum3WSIadjustment 0.995 1 1.005 Vpp (6) 1
DACoutputvoltagesensitivitytosupplies 3.2 5 % (7) 1
DACoutputvoltagedriftovertemperature 45 55 mVpp (9) 4
Table3‐3. DCElectricalcharacteristics(Continued)
Parameter Symbol Min Typ Max Unit Notes
Test
level(1)
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2. SeeSection8.8onpage83forpowerupsequencing.
3. ForuseinhigherNyquistzone,itisrecommendedtousehigherpowerclockwithinthelimit.
4. InNRZmodeonly.Fortheotherreshapedmodes,theoutputpowerwillbelowerbyconstruction.SeeFigure5‐2and
Figure5‐3.
5. Thesevaluesaremainlyforinformationassingle‐endedoperationinnotrecommended.
6. TheDACoutputvoltagecanbeadjustedcloseto1VppthankstotheGAINcontrolregisterinthe3WSI.
7. DACoutputvoltagesensitivitytosupplies=DACoutputvoltageatVmax‐DACoutputatVmin.Measurementdonewith
DACGainAdjustatitsdefaultvalue(3WSIGAregisterdefaultvalue=0x200)
MinandMaxvaluesaregivenversussuppliesatroomtemperature
8. TestedwithIOL&IOH=500µA
9. DACoutputvoltagesensitivitytotemperature=DACoutputvoltageatTmax‐DACoutputvoltageatTmin.
MeasurementdonewithDACGainAdjustatitsdefaultvalue(3WSIGAregisterdefaultvalue=0x200)
MinandMaxvaluesaregivenversustemperaturewithtypicalsupplies
10. Ithasbeennotedthatatextremelowtemperatureand/orVCCDmin,theswingoftheDSPclocksignalisreduced.
Howeveritstaysabovethe100mVpgenerallyspecifiedforLVDSinputswingandthusshouldnotbeanissueatthe
systemlevel.
3.4 ACElectricalCharacteristics
Unlessotherwisespecified:VCCA5=5V,VCCA3=3.3V,VCCD=3.3V,4:1MUXratio,roomtemperature,
typicalswingoninputdata,typicalPclk,masterclockinputjitterisbelow100fsrmsintegratedover
11 GHzbandwidth.
Importantnoteonexpectedperformances:
FiguresforperformancesinNRTZandRFmodesaregivenforrecommendedvalueofRPW(Reshaping
PulseWidth).TuningofRPWbycustomerisrecommended.IncreasingRPWimproveslinearity(SFDR)
attheexpenseofcarrieroutputpower(SNR).DecreasingRPWimprovescarrieroutputpower(SNR)at
theexpenseoflinearity(SFDR).
FiguresforperformanceinRTZ,NRTZandRFmodesaregivenforrecommendedvalueofRPB
(ReshapingPulseBegin)whicharedigitallyprogrammablethroughthe3WiresSerialInterface(3WSI).
ValuesbetweenbracketsaregivenforoptimumRPB/RPWvalues.Optimumsettingsmaydifferfrom
parttopart.
SeeSection5.3onpage27formoreinformationonRPWandRPBsettings.Recommendedvaluesfor
RPBandRPWaregiveninTable3‐2.
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.
Table3‐4. ACElectricalCharacteristicsNRZMode(FirstNyquistZone)
Parameter Symbol Min Typ Max Unit Notes
Test
level(1)
Single‐toneSpuriousFreeDynamicRange
4:1MUX
Fs=6.0GSps@Fout=60MHz0dBFS
Fs=6.0GSps@Fout=2940MHz0dBFS
Fs=3.0GSps@Fout=30MHz0dBFS
Fs=3.0GSps@Fout=1470MHz0dBFS
|SFDR|
64
51
66
49
71
58
dBc (2)(3)
4
4
1
1
2:1MUX
Fs=3.2GSps@Fout=32MHz0dBFS
Fs=3.2GSps@Fout=1568MHz0dBFS
Fs=1.5GSps@Fout=15MHz0dBFS
Fs=1.5GSps@Fout=735MHz0dBFS
|SFDR|
65
57
70
55
75
64
dBc (2)(3)
4
4
1
1
Highestspurlevel
4:1MUX
Fs=6.0GSps@Fout=60MHz0dBFS
Fs=6.0GSps@Fout=2940MHz0dBFS
Fs=3.0GSps@Fout=30MHz0dBFS
Fs=3.0GSps@Fout=1470MHz0dBFS
–65
–54
–70
–61
dBm
4
4
1
1
2:1MUX
Fs=3.2GSps@Fout=32MHz0dBFS
Fs=3.2GSps@Fout=1568MHz0dBFS
Fs=1.5GSps@Fout=15MHz0dBFS
Fs=1.5GSps@Fout=735MHz0dBFS
–70
–60
–74
–66
dBm
4
4
1
1
SignalindependentSpur(clock‐relatedspur)with4:1MUX
Fc/2@6.0GSps –80 dBm 4
Fc/4@6.0GSps –75 dBm 4
Self‐NoiseDensityatcode0or4095@6.0GSps <–160 dBm/Hz 4
NoisePowerRatio
–14dBFSpeaktormsloadingfactor
Fs=6.0GSps
2.667GHzbroadbandpattern,
33.3MHznotchwidth
NPR 41.5 dB (4)(5) 4
EquivalentENOB(ComputedfromNPRfigure) ENOB 8.4 Bit 4
SignaltoNoiseRatio(ComputedfromNPRfigure) SNR 52.5 dB 4
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Note: 1. SeeSection3.6onpage18forexplanationoftestlevels.
2. RefertoFigure7‐40forSFDRvariationversustemperature.
3. RefertoFigure7‐39forSFDRvariationversussupplies.
4. RefertoFigure7‐64forNPRvariationversustemperature.
5. RefertoFigure7‐63forNPRvariationversussupplies.
NoisePowerRatio
–14dBFSpeaktormsloadingfactor
Fs=3GSps
1.33GHzbroadbandpattern,17MHznotchwidth
NPR 43 46 dB 1
EquivalentENOB(ComputedfromNPRfigure) ENOB 8.7 9.2 Bit 1
SignaltoNoiseRatio(ComputedfromNPRfigure) SNR 54 57 dB 1
Table3‐4. ACElectricalCharacteristicsNRZMode(FirstNyquistZone)(Continued)
Parameter Symbol Min Typ Max Unit Notes
Test
level(1)
Table3‐5. ACElectricalCharacteristicsNRTZMode(First&SecondNyquistZone)
Parameter Symbol Min Typ Max Unit Notes
Test
level(1)
Single‐toneSpuriousFreeDynamicRange
4:1MUX
Fs=6.0GSps@Fout=60MHz0dBFS
Fs=6.0GSps@Fout=2940MHz0dBFS
Fs=6.0GSps@Fout=5940MHz0dBFS
Fs=3.0GSps@Fout=30MHz0dBFS
Fs=3.0GSps@Fout=1470MHz0dBFS
Fs=3.0GSps@Fout=2970MHz0dBFS
|SFDR|
62
60
55
69(69)
55(56)
51(59)
75
65
60
dBc (2)(3)
4
4
4
1
1
1
2:1MUX
Fs=3.2GSps@Fout=32MHz0dBFS
Fs=3.2GSps@Fout=1568MHz0dBFS
Fs=3.2GSps@Fout=3168MHz0dBFS
Fs=1.5GSps@Fout=15MHz0dBFS
Fs=1.5GSps@Fout=735MHz0dBFS
Fs=1.5GSps@Fout=1485MHz0dBFS
|SFDR|
65
63
51
76
63
62
77
73
57
dBc (2)(3)
4
4
4
1
1
1
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Highestspurlevel(Singletone)
4:1MUX
Fs=6.0GSps@Fout=60MHz0dBFS
Fs=6.0GSps@Fout=2940MHz0dBFS
Fs=6.0GSps@Fout=5940MHz0dBFS
Fs=3.0GSps@Fout=30MHz0dBFS
Fs=3.0GSps@Fout=1470MHz0dBFS
Fs=3.0GSps@Fout=2970MHz0dBFS
–72(–72)
–62(–63)
–66(–75)
–76
–69
–76
dBm
4
4
4
1
1
1
2:1MUX
Fs=3.2GSps@Fout=32MHz0dBFS
Fs=3.2GSps@Fout=1568MHz0dBFS
Fs=3.2GSps@Fout=3168MHz0dBFS
Fs=1.5GSps@Fout=15MHz0dBFS
Fs=1.5GSps@Fout=735MHz0dBFS
Fs=1.5GSps@Fout=1485MHz0dBFS
–77
–67
–80
–76
–76
–78
dBm
4
4
4
1
1
1
Dual‐toneoverFullNyquist
4:1MUX
Fs=6.0GSps@Fout1=2850MHz,
Fout2=2860MHz‐8dBFSeachtone
IMD
IMD3
(54)
(73)
dBc
dBc
4
4
Highestspurlevel(Dual‐tone)
4:1MUX
Fs=6.0GSps@Fout1=2850MHz,
Fout2=2860MHz‐8dBFSeachtone
IMDspur
IMD3spur
(–69)
(–88)
dBm
dBm
4
4
SignalindependentSpur(clock‐relatedspur)with4:1MUX
Fc@6.0GSps –37 dBm 4
Fc/2@6.0GSps –89 dBm 4
Fc/4@6.0GSps –80 dBm 4
Self‐NoiseDensityatcode0or4095@6.0GSps –149 dBm/Hz 4
NoisePowerRatio(1stNyquist)
–14dBFSpeaktormsloadingfactor
Fs=6.0GSps
2.667GHzbroadbandpattern,33.3MHznotchwidth
NPR 44 dB (4)(5) 4
EquivalentENOB(ComputedfromNPRfigure) ENOB 8.8 Bit 4
SignaltoNoiseRatio(ComputedfromNPRfigure) SNR 55 dB 4
Table3‐5. ACElectricalCharacteristicsNRTZMode(First&SecondNyquistZone)(Continued)
Parameter Symbol Min Typ Max Unit Notes
Test
level(1)
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Note: 1. SeeSection3.6onpage18forexplanationoftestlevels.
2. RefertoFigure7‐40forSFDRvariationversustemperature.
3. RefertoFigure7‐39forSFDRvariationversussupplies.
4. RefertoFigure7‐64forNPRvariationversustemperature.
5. RefertoFigure7‐63forNPRvariationversussupplies.
NoisePowerRatio(1stNyquist)
–14dBFSpeaktormsloadingfactor
Fs=3GSps
1.33GHzbroadbandpattern,17MHznotchwidth
NPR 47 50 dB 1
EquivalentENOB(ComputedfromNPRfigure) ENOB 9.3 9.8 Bit 1
SignaltoNoiseRatio(ComputedfromNPRfigure) SNR 58 61 dB 1
NoisePowerRatio(2ndNyquist)
–14dBFSpeaktormsloadingfactor
Fs=6.0GSps
2.667GHzbroadbandpattern,33.3MHznotchwidth
NPR 39.5 dB 4
EquivalentENOB(ComputedfromNPRfigure) ENOB 8.1 Bit 4
SignaltoNoiseRatio(ComputedfromNPRfigure) SNR 50.5 dB 4
NoisePowerRatio(2ndNyquist)
–14dBFSpeaktormsloadingfactor
Fs=3GSps
1.33GHzbroadbandpattern,17MHznotchwidth
NPR 41 43.5 dB 1
EquivalentENOB(ComputedfromNPRfigure) ENOB 8.3 8.8 Bit 1
SignaltoNoiseRatio(ComputedfromNPRfigure) SNR 52 54.5 dB 1
Table3‐5. ACElectricalCharacteristicsNRTZMode(First&SecondNyquistZone)(Continued)
Parameter Symbol Min Typ Max Unit Notes
Test
level(1)
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Note: 1. SeeSection3.6onpage18forexplanationoftestlevels.
2. RefertoFigure7‐40forSFDRvariationversustemperature.
3. RefertoFigure7‐39forSFDRvariationversussupplies.
4. RefertoFigure7‐64forNPRvariationversustemperature.
5. RefertoFigure7‐63forNPRvariationversussupplies.
Table3‐6. ACElectricalCharacteristicsRTZMode(SecondNyquistZone)
Parameter Symbol Min Typ Max Unit Notes
Test
level(1)
Single‐toneSpuriousFreeDynamicRange
4:1MUX
Fs=6.0GSps@Fout=5940MHz0dBFS
Fs=3.0GSps@Fout=2970MHz0dBFS
|SFDR|
59
56
64
dBc (2)(3) 4
1
2:1MUX
Fs=3.2GSps@Fout=3168MHz0dBFS
Fs=1.5GSps@Fout=1485MHz0dBFS
|SFDR|
59
59
66
(2)(3) 4
1
Highestspurlevel
4:1MUX
Fs=6.0GSps@Fout=5940MHz0dBFS
Fs=3.0GSps@Fout=2970MHz0dBFS
–68
–74
dBm 4
1
2:1MUX
Fs=3.2GSps@Fout=3168MHz0dBFS
Fs=1.5GSps@Fout=1485MHz0dBFS
–72
–75
dBm 4
1
SignalindependentSpur(clock‐relatedspur)with4:1MUX
Fc@6.0GSps–36 dBm 4
Fc/2@6.0GSps–87 dBm 4
Fc/4@6.0GSps–80 dBm 4
Self‐NoiseDensityatcode0or4095@6.0GSps –138 dBm/Hz 4
NoisePowerRatio(2ndNyquist)
–14dBFSpeaktormsloadingfactor
Fs=6.0GSps
2.667GHzbroadbandpattern,33.3MHznotch
width
NPR 38 dB (4)(5) 4
EquivalentENOB(ComputedfromNPRfigure) ENOB 7.8 Bit 4
SignaltoNoiseRatio(ComputedfromNPRfigure) SNR 49 dB 4
NoisePowerRatio(2ndNyquist)
–14dBFSpeaktormsloadingfactor
Fs=3GSps
1.33GHzbroadbandpattern,17MHznotchwidth
NPR 43.5 46 dB 1
EquivalentENOB(ComputedfromNPRfigure) ENOB 8.8 9.2 Bit 1
SignaltoNoiseRatio(ComputedfromNPRfigure) SNR 54.5 57 dB 1
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Table3‐7. ACElectricalCharacteristicsRFMode(SecondtoEighthNyquistZones)
Parameter Symbol Min Typ Max Unit Notes
Test
level(1)
Single‐toneSpuriousFreeDynamicRange
4:1MUX
Fs=6.0GSps@Fout=5940MHz0dBFS
Fs=6.0GSps@Fout=8940MHz0dBFS
Fs=6.0GSps@Fout=11940MHz0dBFS
Fs=6.0GSps@Fout=17940MHz0dBFS
Fs=6.0GSps@Fout=18040MHz0dBFS
Fs=6.0GSps@Fout=23920MHz0dBFS
Fs=3.0GSps@Fout=2970MHz0dBFS
Fs=3.0GSps@Fout=4470MHz0dBFS
|SFDR|
61
49
56(58)
41(49)
42(50)
38(41)
38(43)
33(38)
65
58
dBc
(2)(3)
4
4
4
4
4
4
1
1
2:1MUX
Fs=3.2GSps@Fout=3168MHz0dBFS
Fs=3.2GSps@Fout=4768MHz0dBFS
Fs=1.5GSps@Fout=1485MHz0dBFS
Fs=1.5GSps@Fout=2235MHz0dBFS
|SFDR|
64
60
58
54
70
65
dBc
(2)(3)
(6)
4
4
1
1
4:1MUXwithIUCM2
Fs=6.0GSps@Fout=5940MHz0dBFS |SFDR| 54 58 dBc (7) 1
Highestspurlevel(Singletone)
4:1MUX
Fs=6.0GSps@Fout=6940MHz0dBFS
Fs=6.0GSps@Fout=8940MHz0dBFS
Fs=6.0GSps@Fout=11940MHz0dBFS
Fs=6.0GSps@Fout=17940MHz0dBFS
Fs=6.0GSps@Fout=18040MHz0dBFS
Fs=6.0GSps@Fout=23920MHz0dBFS
Fs=3.0GSps@Fout=2970MHz0dBFS
Fs=3.0GSps@Fout=4470MHz0dBFS
–64(–73)
–60(–69)
–74(–79)
–76(–78)
–77(–82)
–79(–77)
–69
–67
dBm
4
4
4
4
4
4
1
1
2:1MUX
Fs=3.2GSps@Fout=1568MHz0dBFS
Fs=3.2GSps@Fout=4768MHz0dBFS
Fs=1.5GSps@Fout=1485MHz0dBFS
Fs=1.5GSps@Fout=2235MHz0dBFS
–65
–66
–73
–75
dBm
4
4
1
1
4:1MUXwithIUCM2
Fs=6.0GSps@Fout=5940MHz0dBFS –64 dBm (7) 1
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SignalindependentSpur(clock‐relatedspur)with4:1MUX
Fc@6.0GSps–37 dBm 4
Fc/2@6.0GSps–87 dBm 4
Fc/4@6.0GSps–85 dBm 4
Dual‐toneoverFullNyquist
4:1MUX
Fs=6.0GSps@Fout1=2850MHz,
Fout2=2860MHz‐8dBFSeachtone
Fs=6.0GSps@Fout1=5750MHz,
Fout2=5760MHz‐8dBFSeachtone
Fs=6.0GSps@Fout1=8850MHz,
Fout2=8860MHz‐8dBFSeachtone
Fs=6.0GSps@Fout1=11850MHz,
Fout2=11860MHz‐8dBFSeachtone
IMD
IMD3
IMD
IMD3
IMD
IMD3
IMD
IMD3
(54)
(73)
(53)
(64)
(44)
(57)
(41)
(58)
dBc
4
4
4
4
4
4
4
4
Highestspurlevel(Dual‐tone)
4:1MUX
Fs=6.0GSps@Fout1=2850MHz,
Fout2=2860MHz‐8dBFSeachtone
Fs=6.0GSps@Fout1=5750MHz,
Fout2=5760MHz‐8dBFSeachtone
Fs=6.0GSps@Fout1=8850MHz,
Fout2=8860MHz‐8dBFSeachtone
Fs=6.0GSps@Fout1=11850MHz,
Fout2=11860MHz–8dBFSeachtone
IMDspur
IMD3spur
IMDspur
IMD3spur
IMDspur
IMD3spur
IMDspur
IMD3spur
(–69)
(–88)
(–73)
(–84)
(–73)
(–86)
(–75)
(–92)
dBm
4
4
4
4
4
4
4
4
Self‐NoiseDensityatcode0or4095@6.0GSps –135 dBm/
Hz 4
NoisePowerRatio(2ndNyquist)
–14dBFSpeaktormsloadingfactor
Fs=6.0GSps
2.667GHzbroadbandpattern,33.3MHznotch
width
NPR 37.5 dB (4)(5) 4
EquivalentENOB(ComputedfromNPRfigure) ENOB 7.8 Bit 4
SignaltoNoiseRatio(ComputedfromNPRfigure) SNR 48.5 dB 4
Table3‐7. ACElectricalCharacteristicsRFMode(SecondtoEighthNyquistZones)(Continued)
Parameter Symbol Min Typ Max Unit Notes
Test
level(1)
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Notes: 1. SeeSection3.6onpage18forexplanationoftestlevels.
2. RefertoFigure7‐40forSFDRvariationversustemperature.
3. RefertoFigure7‐39forSFDRvariationversussupplies.
4. RefertoFigure7‐64forNPRvariationversustemperature.
5. RefertoFigure7‐63forNPRvariationversussupplies.
6. ThismeasurementatFs=1.5GSpsisdonewithRPB1andRPW1.
7. Thecorrespondingspectrumshowsanoutputfrequencyat5940MHzwithinan1500MHzwideNyquistzone.
NoisePowerRatio(2ndNyquist)
–14dBFSpeaktormsloadingfactor
Fs=3GSps
1.33GHzbroadbandpattern,17MHznotchwidth
NPR 42.5 45 dB 1
EquivalentENOB(ComputedfromNPRfigure) ENOB 8.6 9.0 Bit 1
SignaltoNoiseRatio(ComputedfromNPRfigure) SNR 53.5 56 dB 1
NoisePowerRatio(3rdNyquist)
–14dBFSpeaktormsloadingfactor
Fs=6.0GSps
2.667GHzbroadbandpattern,33.3MHznotch
width
NPR 36.5 dB 4
EquivalentENOB(ComputedfromNPRfigure) ENOB 7.6 Bit 4
SignaltoNoiseRatio(ComputedfromNPRfigure) SNR 47.5 dB 4
NoisePowerRatio(3rdNyquist)
–14dBFSpeaktormsloadingfactor
Fs=3GSps
1.33GHzbroadbandpattern,17MHznotchwidth
NPR 39 42 dB 1
EquivalentENOB(ComputedfromNPRfigure) ENOB 8.0 8.5 Bit 1
SignaltoNoiseRatio(ComputedfromNPRfigure) SNR 50 53 dB 1
Table3‐7. ACElectricalCharacteristicsRFMode(SecondtoEighthNyquistZones)(Continued)
Parameter Symbol Min Typ Max Unit Notes
Test
level(1)
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3.5 TimingCharacteristicsandSwitchingPerformances
Unlessotherwisespecified:VCCA5=5V,VCCA3=3.3V,VCCD=3.3V,4:1MUXratio,roomtemperature,
typicalswingoninputdata,typicalPclk,Masterclockinputjitterisbelow100fsrmsintegratedover
11 GHzbandwidth.
Table3‐8. TimingcharacteristicsandSwitchingPerformances
Parameter Symbol Value Unit Note TestLevel(1)
SWITCHINGPERFORMANCEANDCHARACTERISTICS
Maximumoperatingclockfrequency
4:1MUXmode 6.0 GHz 4
2:1MUXmode 3.2 GHz 4
Minimumoperatingclockfrequency 300 MHz (2) 5
Parameter Symbol Min Typ Max Unit Note TestLevel(1)
TIMINGCHARACTERISTICS
InputDatatiming
Inputdatasetupandholdtime tSH 360 ps (3) 4
Inputdatarate(4:1MUX) 1500 Msps 4
Inputdatarate(2:1MUX) 1600 Msps 4
Dataclockoutputtiming(DSP,DSPN)
DSPclockphasetuningsteps PSS 0.5 Tclock 5
MasterclocktoDSPtiming
Pipeline(4:1MUX) 3
Tclock
(4)
5
Pipeline(2:1MUX) 3 5
Delay4:1MUX
tPD
540
ps
4
Delay2:1MUX 540 4
SYNCtoDSP,DSPN
SyncfallingedgetoDSPrisingedge
Pipelinein4:1MUX 3Tclock
(5)
5
SyncfallingedgetoDSPrisingedge
Pipelinein2:1MUX 3Tclock5
SyncfallingedgetoDSPrisingedge
Delaywith2:1MUX
tSDSP
640 ps 4
Delaywith4:1MUX 640 ps 4
SyncrisingedgetoDSPfallingedgetSDSPF TCLK+1/2TDSP ps 5
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Notes: 1. SeeSection3.6onpage18forexplanationoftestlevels.
2. MinimumoperatingclockfrequencycanbeDC.ItdependsontheclockinputACcouplingcapacitorusedinthefinal
applicationandlimitationduetotheenvironmentascircuititselfdisplaysnolowerclockfrequencylimitation.
3. SetupandholdtimeweremeasuredonTeledynee2vevaluationboardandassuchincludetheimpactfromFPGA(jitter
andskew)andPCBskewontheboard.RefertoFigure7‐66onSection7.3onpage78.tSHvariationovertemperature
rangeisaround20ps.
4. SeeFigure3‐1andFigure3‐2below.
5. SeeFigure3‐3below.
6. SeeFigure3‐4below.
Figure3‐1. TimingDiagramfor4:1MUXprincipleof operation OCDS1, IUCM1
Figure3‐2. TimingDiagramfor2:1MUXprincipleofoperationOCDS1,IUCM1
SYNCtiming
MinimumSyncpulsewidth 3 Tclock 4
SYNCsetupandholdtime tSSH 15 ps
(6)
4
SYNCforbiddenarealowerbound t1100 ps 4
SYNCforbiddenareaupperbound t2t1–tSSH ps 4
Analogoutputtiming
Analogoutputrisetime(20‐80%) tOR 30 ps 4
Analogoutputfalltime(20‐80%) tOF 30 ps 4
Pipeline(4:1MUX) 3
Tclock (4) 5
Pipeline(2:1MUX) 3 5
Analogoutputdelay tOD 560 ps (4) 4
Parameter Symbol Min Typ Max Unit Note TestLevel(1)
External CLK
Data input A
Data input B
Data input C
Data input D
Pipeline + t
PD
DSP with PSS[000]
DSP with PSS[001]
Pipeline + t
OD
OUT
xxx N+5 N+6 N+7 N+8N N+1 N+2 N+3 N+4
x x x N+2 N+6 N+10 N+1 4
x x x N+3 N+7 N+11 N+1 5
xxx N N+4 N+8 N+12
x x x N+1 N+5 N+9 N+1 3
External CLK
Data input A
Data input B
Pipeline + t
PD
DSP with PSS[000]
DSP with PSS[001]
Pipeline + t
OD
OUT
N+7 N+8
N+13 N+15
x x x N N+1 N+2 N+3 N+4 N+5 N+6
N+10 N+12 N+14
xxx N+1 N+3 N+5 N+7 N+9 N+11
xxx N N+2 N+4 N+6 N+8
N+1
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Figure3‐3. TimingrelationshipbetweenSYNCandDSP
Figure3‐4. SYNCTimingDiagram
3.6 ExplanationofTestLevels
OnlyMINandMAXvaluesareguaranteed.
Note: 1. Unlessotherwisespecified.
Pipeline + tSDSP
SYNC
DSP
tSDSPF
SYNC OK OK
NOK NOK
t1
t2
SYNC OK
SYNC NOK
SYNC NOK
Master Clk
t2
t1
tSSH
Table3‐9. Testlevels
1100%productiontestedat+25°C(1)
2100%productiontestedat+25°C(1),andsampletestedatspecifiedtemperatures.
3Sampletestedonlyatspecifiedtemperatures
4Parameterisguaranteedbycharacterizationtesting(thermalsteady‐stateconditionsatspecified
temperature).
5 Parametervalueisonlyguaranteedbydesign
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3.7 DigitalInputCodingTable
Table3‐10. CodingTable(Theoricalvalues)
Digitaloutput
msb………..lsb
Differential
analogoutput
000000000000 –500mV
010000000000 –250mV
011000000000 –125mV
011111111111 –0.122mV
100000000000 0.122mV
101000000000 +125mV
110000000000 +250mV
111111111111 +500mV
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4. DEFINITIONOFTERMS
Table4‐1. DefinitionofTerms
Abbreviation Term Definition
(SFDR) Spuriousfreedynamicrange
RatioexpressedindBCofthesignalpower,setatFullScale,tothepowerofthehighest
spuriousspectralcomponentovertheNyquistzone.Thepeakspuriouscomponentmayormay
notbeaharmonic.
(HSL) HighestSpurLevel PowerofthehighestspuriousspectralcomponentexpressedindBm.
(ENOB) EffectiveNumberOfBits
ENOBiscalculatedfromNPRmeasurementusingtheformula:
ENOB=(NPR[dB]+|LF[dB]|‐3‐1.76)/6.02
WhereLFistheloadingfactori.e.theratiobetweentheGaussiannoisestandarddeviation
versusamplitudefullscaleoftheNPRpattern.
(SNR) Signaltonoiseratio
SNRiscalculatedfromNPRmeasurementusingtheformula:
SNR[dB]=NPR[dB]+|LF[dB]|‐3
WhereLFistheloadingfactori.e.theratiobetweentheGaussiannoisestandarddeviation
versusamplitudefullscaleoftheNPRpattern.
(NPR) NoisePowerRatio
TheNPRismeasuredtocharacterizetheDACperformanceinresponsetobroadbandsignals.
Whenapplyinganotch‐filteredbroadbandwhite‐noisepatternattheinputoftheDACunder
test,theNoisePowerRatioisdefinedastheratiobetweentheaveragenoisemeasuredonthe
shoulderofthenotchandinsidethenotch,usingthesameintegrationbandwidth.
(DNL) Differentialnonlinearity
TheDifferentialNonLinearityforagivencodeiisthedifferencebetweenthemeasuredstep
sizeofcodeiandtheidealLSBstepsize.DNL(i)isexpressedinLSBs.DNListhemaximumvalue
ofallDNL(i).DNLerrorspecificationoflessthan1LSBguaranteesthatthereisnomissingpoint
andthatthetransferfunctionismonotonic.
(INL) Integralnonlinearity
TheIntegralNonLinearityforagivencodeiisthedifferencebetweenthemeasuredvoltageat
whichthetransitionoccursandtheidealvalueofthistransition.
INL(i)isexpressedinLSBs,andisthemaximumvalueofall|INL(i)|.
(VSWR) VoltageStandingWaveRatio TheVSWRcorrespondstotheinsertionlosslinkedtothepowerreflection.ForexampleaVSWR
of1.2correspondstoa20dBreturnloss(i.e.99%powertransmittedand1%reflected).
(IUCM) InputUnderClockingMode TheIUCMprincipleistoapplyaselectabledivisionratiobetweentheDACclocksectionandthe
MUXclocksection.
(PSS) PhaseShiftSelect ThePhaseShiftSelectfunctionisusedtotunethephaseoftheDSPclock.
(OCDS) OutputClockDivisionSelect ItallowsdividingtheDSPclockfrequencybytheOCDScodedvaluefactor.
(NRZ) NonReturntoZero NonReturntoZeromodeonanalogoutput.
(RF) RadioFrequency RFmodeonanalogoutput.
(RTZ) ReturnToZero Returntozeromodeonanalogoutput.
(NRTZ) NarrowReturnToZero Narrowreturntozeromodeonanalogoutput.
(RPB) ReshapedPulseBegin FunctioncontrollingwhenthetransitionoftheDACanalogoutputoccurs.(applicableinNRTZ,
RTZandRFmode)
(RPW) ReshapedPulseWidth FunctioncontrollingthewidthofthereshapingoftheDACanalogoutput.
(applicableinNRTZandRFmode)
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5. FUNCTIONALDESCRIPTION
Figure5‐1. DACfunctionaldiagram
Table5‐1. Functionsdescription
Name Function Name Function
VCCD 3.3Vdigitalpowersupply CLK In‐phasemasterclock
VCCA5 5Vanalogpowersupply CLKN Invertedphasemasterclock
VCCA3 3.3Vanalogpowersupply DSP_CK In‐phaseoutputclock
DGND Digitalground DSP_CKN Invertedphaseoutputclock
AGND AnaloggroundPSS[0..2] Phaseshiftselect
A[11…0] In‐phasedigitalinputportA Reset_n Resetof3WSIregisters
A[11..0]N InvertedphasedigitalinputportAsld_n 3WSIselect
B[11…0] In‐phasedigitalinputportBsclk,sdata 3WSIclockanddatainputs
B[11..0]N InvertedphasedigitalinputportBTVF Setup/holdtimeviolationflag
C[11…0] In‐phasedigitalinputportCIDC_P,IDC_N Inputdatacheck
C[11..0]N InvertedphasedigitalinputportC OCDS OutputClockDivisionfactorSelection
D[11…0] In‐phasedigitalinputportDDiode Diodefortemperaturemonitoring
D[11..0]N InvertedphasedigitalinputportDSYNC/
SYNCN Synchronizationsignal(activehigh)
OUT In‐phaseanalogoutput OUTN Invertedphaseanalogoutput
OUT, OUTP
DSP_CK,
DSP_CKN
DIODE
TVF
DGND AGND
V
CCA5
V
CCA3
V
CCD
CLK, CLKN
SYNC
A[0...11]
A[0...11]N
B[0...11]
B[0...11]N
C[0...11]
C[0...11]N
D[0...11]
D[0...11]N
EV12DS460
PSS
OCDS
sclk, sdata
sld_n
IDC_P, IDC_N
Reset_n
2
2
2
2
3
3
2
2x12
2x12
2x12
2x12
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Note: 1. PSSandOCDSarecontrolledthroughtheexternalpinifECDCbitof3WSIstateregisterissettolevel 1
(defaultvalue).SeeSection5.13.3onpage44formoreinformation.
5.1 Multiplexer
Twomultiplexerratios(N)areallowed:
•N=4:4:1MUX,whichallowsoperationupto6.0GSps;
•N=2:2:1MUX,whichallowsoperationupto3.2GSps.
In2:1MUXratio,theunuseddataports(portsCandD)canbeleftopen.
Table5‐2. DACoverviewfunctionalityandcontrols
Function Description Controllability
MUX MUXratioselection(4:1or2:1) 3WSI
MODE Outputreshapingmodeselection:
NRZ,NRTZ,RTZorRF 3WSI
RPW ReshapingPulseWidth(applicableinNRTZandRFmode) 3WSI
RPB ReshapingPulseBegin(applicableinNRTZ,RTZandRFmode) 3WSI
PSS PhaseShiftSelect:shifttheDSPclockbystepsofTCLK/2 forFPGA
synchronization
3WSI/external
pins
OCDS OutputClockDivisionSelect:RatioofdivisionbetweenDSPclockand
masterclock
3WSI/external
pins
IUCM
InternalUnderClockingModeratioselection:
AllowtoworkwithdatarateequaltoFCLKdividedby1,2or4witha
DACclockedatFCLK
3WSI
GA DACGainAdjust 3WSI
Label Value Description Defaultsetting
MUX 0 4:1mode(N=4) 0(4:1MUXmode)
12:1mode(N=2)
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5.2 ModeFunction
TheMODEfunctionallowschoosingbetweenNRZ,NRTZ,RTZandRFmodes.
Idealequationsdescribingmaximumavailableoutputpowerversusanalogoutputfrequencyinthe
fourmodesaregivenhereafter,withXbeingthenormalisedoutputfrequency(i.e.Fout/FCLK,thusthe
edgesoftheNyquistzonesareatX=0,½,1,3/2,2,…).
Infact,duetolimitedbandwidth,anextratermmustbeaddedtotakeintoaccountafirstorderlow
passfilterwitha7.5GHzcut‐offfrequency.
Inthefollowingformula,Pout(X)isexpressedindBm
NRZmode:
wheresinc(x)=sin(x)/x,andk=1
NRTZmode:
wherek=1‐RPW/TCLKandRPWisthewidthofreshapingpulse
RTZmode:
wherekisthedutycycleoftheclockpresentedattheDACinput.Pleasenotethatduetophase
mismatchinbalunusedtoconvertsingleendedclocktodifferentialclockthefirstzeromaymove
aroundthelimitofthe4thandthe5thNyquistzone.Ideallyk=1/2.
RFmode:
wherek=1‐RPW/TCLKandRPWisthewidthofreshapingpulse.
Asaconsequence:
•NRZmodeoffersmaximumoutputpowerfor1stNyquistoperation;
•RTZmodehaveaslowrollofffor2ndNyquistoperation;
•RFmodeoffersmaximumpowerover2ndand3rdNyquistzones;
Label Value Description Defaultsetting
MODE[1:0]
00 NRZmode
01(NRTZ)
01 NarrowRTZ(a.k.a.NRTZ)mode
10 RTZMode(50%)
11 RFmode
Pout(X) 20 log10
ksinckX
0.893
------------------------------------------
=
Pout(X) 20 log10
ksinckX
0.893
---------------------------------------------
=
Pout(X) 20 log10
ksinckX
0.893
---------------------------------------------
=
Pout(X) 20 log10
ksinc
kX
2
-------------------
kX
2
-------------------
sin
0.893
------------------------------------------------------------------------------------
=
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•NRTZmodeoffersoptimumpoweroverthe1standthefirsthalfofthe2ndNyquistzones.Itisthe
mostrelevantmodeintermsofperformanceforoperationover1standbeginningof2ndNyquist
zones.
InthetwofollowingFigure5‐2andFigure5‐3,thepinklineistheidealequation’sresult,andthegreen
lineincludesafirstorder7.5GHzcut‐offlowpassfiltertotakeintoaccountthebandwidtheffectdue
todieandpackage.
Figure5‐2. Maxavailableoutputpower(Pout)atnominalgainvsoutputfrequency(Fout)inthefouroutputmodesat
6.0 GSps,overeightNyquistzones,computedfordifferentRPWsteps
Figure5‐3. Maxavailableoutputpower(Pout)atnominalgainvsoutputfrequency(Fout)inthefouroutputmodesat
3.2 GSps,overeightNyquistzones,computedfordifferentRPWsteps
NZ1 NZ2 NZ3 NZ4 NZ1 NZ2 NZ3 NZ4
NZ1 NZ2 NZ3 NZ4 NZ1 NZ2 NZ3 NZ4
7.5 7.5
7.5 7.5
7.5 GHz 7.5 GHz
7.5 GHz 7.5 GHz
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5.2.1 NRZoutputmode
Thismodedoesnotallowforoperationinthe2ndNyquistzonebecauseofthesin(x)/xnotch.
Theadvantageisthatitgivesgoodresultsatthebeginningofthe1stNyquistzone(lessattenuation
thaninRTZmode);italsoremovestheparasiticspurattheclockfrequency(indifferential).
Thislegacymodeprovidesthehighestoutputpoweratthebeginningofthe1stNyquistzone.
Figure5‐4. NRZtimingdiagram
5.2.2 NarrowRTZ(NRTZ)outputmode
Thismodehasthefollowingadvantages:
• Optimizedpowerinthe1stNyquistzoneandbeginningofthe2ndNyquistzone;
• Extendeddynamicandlinearitythrougheliminationofnoiseontransitionedges;
•Trade‐offbetweenNRZandRTZ;
• Possibleoperationinthe4thand5thNyquistzones.
Andweaknesses:
•Notchinthe3rdNyquistzone.Infact,notchesareatN*(1/(TCLK‐RPW)),whereTCLKistheexternal
clockperiodandRPWisthereshapingpulsewidth;
•ByconstructionclockspuratFCLK.
Figure5‐5. NarrowRTZtimingdiagram
TheRPBandRPWsettingsareapplicableinthismode;theyareprogrammablethroughthe3wire
serialinterface.FormoreinformationonRPBandRPWseeSection5.3onpage27.
CLK
Samples
V
Analog output
NN+2
N+3
N+1
N+2 N+3
V
tOD TCLK
N N+1
CLK
Samples
V
Analog output
N
N+1
N N+1
N+2
N+3
N+2 N+3
V
tOD + RPB TCLK - RPW
RPW RPW RPW RPW
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5.2.3 RTZoutputMode
TheadvantageoftheRTZmodeisthatitenablestheoperationinthe2ndNyquistzonebutthe
drawbackisthatitattenuatesmorethesignalinthefirstNyquistzone.
Advantages:
• Extendedrolloffofsin(x)/x;
• Extendeddynamicandlinearitythrougheliminationofnoiseontransitionedges;
Weakness:
•ByconstructionstrongclockspuratFCLK.
Figure5‐6. RTZtimingdiagram
TheRPBsettingisapplicableinthismode;itisprogrammablethroughthe3wiresserialinterface.For
moreinformationonRPBseeSection5.3onpage27.
5.2.4 RFoutputmode
RFmodeisoptimalforoperationathighoutputfrequency,sincethedecaywithfrequencyoccursat
higherfrequencythanforRTZ.UnlikeNRZorRTZmodes,theRFmodepresentsnotchesatDCand
2N*(1/(TCLK–RPW),andminimumattenuationforFout=1/(TCLK–RPW).
Advantages:
• Optimizedforoperationsoverthesecondhalfofthe2ndNyquistzoneoroverthe3rdNyquistzone;
• Extendeddynamicandlinearitythrougheliminationofnoiseontransitionedges;
• Possibleoperationproveninthefirsthalfofthe4thNyquistzone.
Weakness:
•ByconstructionclockspuratFCLK.
•Nextclockspurpushedto2.FCLK.
CLK
Samples
V
Analog output
N
N+1
N+2
N+3
N N+1 N+2 N+3
tOD + RPB 1/2 TCLK
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Figure5‐7. RFtimingdiagram
RPBandRPWsettingsareapplicableinthismode;theyareprogrammablethroughthe3wireserial
interface.FormoreinformationonRPBandRPWseeSection5.3.
5.3 RPWandRPBFeature
RPB(ReshapingPulseBegin)andRPW(ReshapingPulseWidth)arenewfeaturesoftheEV12DS460A.
TheycanbeusedtofinetunetheperformanceofthedifferentmodesoftheDAC.Theirobjectiveisto
controltherejectionofthesignaltransitions.
These2settingsarecontrolledviathe3WSIinterface.SeeSection5.13onpage41formore
informationonthe3WSIinterface.Thedifferentvaluestheycantakearespecifiedbymodeinthe
followingparagraphs.
Note:Inthefollowingfigures,theperturbationontheanalogoutputintimedomainhasbeen
exaggeratedtofacilitatethecomprehension.
NRZMode:
SeebelowtheoutputoftheDACinNRZmodeintimedomain:
Figure5‐8. DACoutputinNRZandtimedomain
Ascanbeseenabove,inNRZmode,thetransitioncontainsalotofperturbationsthattranslatesinto
harmonicsinthespectrum.Howevertheoutputpowerismaximum.RPBorRPWsettingsarenot
availableinthismode.
CLK
Samples
V
Analog output
N+2 (-)
N+3 (+)
N+3 (-)
N N+1 N+2 N+3
N (+)
N (-)
N+1 (+)
N+1 (-)
N+2 (+)
t
OD
+ RPB
RPW RPW RPW RPW
t
CLK
- RPW
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RTZMode:
InRTZmode,theoutputison50%ofthesamplingperiodandofftheremaining50%ofthesampling
period.PerdefinitionoftheRTZmode,itsoutputpowerishalftheoneoftheNRZoutputpower.Inthis
mode,theDACfeaturestheRPBfunctionwhichcontrolswhenthetransitionbetween50%onand50%
offoccurs.Usingthisfeature,theRTZoutputlinearityperformancecanbeincreased.Seebelowthe
outputoftheDACinRTZmodeandtimedomain,whetherRPBiscorrectlyconfiguredornot(theNRZ
outputmodeistracedtoshowthedifferencebetweenNRZandRTZmode):
Figure5‐9. DACoutputinRTZmodeandtimedomainwhenRPBisoptimum
Figure5‐10. DACoutputinRTZmodeandtimedomainwhenRPBisnotoptimum
TuningRPBasdepictedinFigure5‐9willimprovethelinearityoftheoutputbecausethetransitionwill
becompletelyrejected.IfRPBisnottunedtorejectthetransitions(seeFigure5‐10),theoutput
harmonicswillbedegraded(mainlyH3).
TheRPWsettingisnotavailableinRTZmode.SeeSection5.13.3onpage44fortheavailablevaluesfor
RPBinRTZmode.
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NRTZMode:
TheNRTZmodeisacompromisebetweentheNRZandtheRTZmodes.Itsobjectiveistohavethebest
possiblelinearitythroughtheremovalofthetransitionswhilekeepingahighoutputpower.Thus,only
thetransitionsshouldbecancelled.InthismodebothRPBandRPWsettingsareavailable.TheRPB
settingcontrolsthepositionwherethesignaliscancelled.TheRPWsettingcontrolsthewidenessof
thecancelledsignal.SeebelowanexamplewhereRPBandRPWareoptimuminNRTZmode(theNRZ
outputmodeistracedtoshowthedifferencebetweenNRZandNRTZmode):
Figure5‐11. DACoutputinNRTZmodeandtimedomainwhenRPB/RPWareoptimum
Inthecaseabove,theoutputhasabetterlinearitythaninNRZmodeoverthecompletespectrum
whilesufferingfromaslightoutputpowerreduction.
Figure5‐12. DACoutputinNRTZmodeandtimedomainwhenRPBisnotoptimum
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Figure5‐13. DACoutputinNRTZmodeandtimedomainwhenRPWisnotoptimum
IncaseRPBisnotoptimum(Figure5‐12),theharmonicswillbedegraded(mainlyH3).IncaseRPWis
smallerthantheoptimum(Figure5‐13),thelinearityoftheoutputwillbedegraded.IncaseRPWis
largerthantheoptimum,theDACwillhavehighlinearityperformancebutloweroutputpower.
TheRPWsettingimpactsthefrequencyresponseofthemode.SeebelowthePoutvsFoutfigurein
NRTZmodewithdifferentRPWvalues:
Figure5‐14. PoutvsFout@6.0GSpsinNRTZmodeover4NyquistzoneswithfiveRPWvalues
SeeSection5.13.3onpage44fortheavailablevaluesforRPBandRPWinNRTZmode.
7.5
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RFMode:
TheRFmodeisusedinhigherNyquistzones(2ndand3rd).Itsprincipleisthattheoutputisatitsvalue
duringhalfthesamplingperiodandatitsoppositevalueduringtheremaininghalf.Toimprovelinearity
ofthismodebothRPBandRPWsettingsareavailable.SeebelowanexamplewhereRPBandRPWare
optimuminRFmode(theNRZoutputmodeistracedtoshowthedifferencebetweenNRZandRF
mode):
Figure5‐15. DACoutputinRFmodeandtimedomainwhenRPBandRPWareoptimum
IncaseRPBisnotoptimum,theharmonicswillbedegraded(mainlyH3).IncaseRPWissmallerthan
theoptimum,thelinearityoftheoutputwillbedegraded.IncaseRPWislargerthantheoptimum,the
DACwillhavehighlinearityperformancebutloweroutputpower.
TheRPWsettingimpactsthefrequencyresponseofthemode.SeebelowthePoutvsFoutfigureinRF
modewithdifferentRPWvalues:
Figure5‐16. PoutvsFout@6.0GSpsinRFmodeover4NyquistzoneswithfiveRPWvalues
SeeSection5.13.3onpage44fortheavailablevaluesforRPBandRPWinRFmode.
7.5
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5.4 PhaseShiftSelectfunction(PSS)
ItispossibletoadjustthetimingbetweenthesamplingclockandtheoutputDSPclock.
TheDSPclockoutputphasecanbetunedoverarangeof3.5inputclockcycles(7stepsofhalfaclock
cycle)inadditiontotheintrinsicpropagationdelaybetweentheDSPclock(DSP,DSPN)andthe
samplingclock(CLK,CLKN).
Threebitsareprovidedforthephaseshiftfunction:PSS[2:0].
Bysettingthese3bitsto0or1,onecanaddadelayontheDSPclockinordertoproperlysynchronize
theinputdataoftheDACandthesamplingclock(theDSPclockshouldbeappliedtotheFPGAand
shouldbeusedtoclocktheDACdigitalinputdata).
These3bitsareeitherdrivendirectlythroughthepinsPSS[2:0]orthroughthe3WSIdependingonthe
ECDCbitinthestateregisterofthe3WSI.
InordertodeterminehowmuchdelayneedstobeaddedontheDSPclocktoensurethe
synchronizationbetweentheinputdataandthesamplingclockwithintheDAC,theTVFbitshouldbe
monitored.
Note: In4:1MUXmodethe8settingsarerelevant,in2:1MUXonlythefourfirstsettingsare
relevant;thefourlastsettingswillyieldthesameresults.
Figure5‐17. PSStimingdiagramfor4:1MUX,OCDS=0
Table5‐3. PSScodingtable
Label Value Description
PSS[2:0] 000 NoadditionaldelayonDSPclock(Defaultvalue)
001 0.5inputclockcycledelayonDSPclock
010 1inputclockcycledelayonDSPclock
011 1.5inputclockcycledelayonDSPclock
100 2inputclockcyclesdelayonDSPclock
101 2.5inputclockcyclesdelayonDSPclock
110 3inputclockcyclesdelayonDSPclock
111 3.5inputclockcyclesdelayonDSPclock
External CLK
Internal CLK/4 is used to clock the Data input A, B, C, D into MUXDAC
Internal CLK/4
DSP clock is internal CLK/4 delay by MUXDAC (by step of 0,5 CLK via the PSS function) to be used as DDR clock for the FPGA
DSP with PSS[000]
t=0.5xT
CLK
DSP with PSS[001]
DSP with PSS[010]
DSP with PSS[011]
DSP with PSS[110]
DSP with PSS[111]
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Figure5‐18. PSStimingdiagramfor2:1MUX,OCDS=0
5.5 OutputClockDivisionSelectfunction(OCDS)
ItispossibletochangetheDSPclockinternaldivisionfactorfrom1to2withrespecttothesampling
clock/(2*N*M)whereNistheMUXratio(2or4),andMistheIUCMratio(1,2or4).Thisispossiblevia
theOCDS"OutputClockDivisionSelect"bitthroughthe3WSIortheexternalpinsiftheECDCbitis
high.
OCDSisusedtoobtainasynchronizationclockfortheFPGAslowenoughtoallowtheFPGAtooperate
withnofurtherinternaldivisionofthisclock,thusitsinternalphaseisdeterminedbytheDSPclock
phase.ThisisusefulinasystemwithmultipleDACsandmultipleFPGAstoguaranteedeterministic
phaserelationshipmoreeasilybetweentheFPGAsafterasynchronizationofalltheDACs.
Figure5‐19. OCDStimingdiagramfor4:1MUXandIUCM1mode
Figure5‐20. OCDStimingdiagramfor2:1MUXandIUCM1mode
External CLK
Internal CLK/2 is used to clock the Data input A, B into DAC
Internal CLK/2
DSP clock is internal CLK/2 delay by MUXDAC (by step of 0,5 CLK via the PSS function) to be used as DDR clock for the FPGA
DSP with PSS[000]
t=0.5xT
CLK
DSP with PSS[001]
DSP with PSS[010]
DSP with PSS[011]
DSP with PSS[110]
DSP with PSS[111]
Table5‐4. OCDScodingtable
Label Value Description Defaultsetting
OCDS 0 OCDS1:DSPclock=SamplingClock/(2*N*M) 0(OCDS1)
1OCDS2:DSPclock=SamplingClock/(2*N*M*2)
External CLK
Internal CLK/4 is used to clock the Data input A, B, C, D into
Internal CLK/4
DSP clock is internal CLK/4 divided by OCDS selection. This clock could be used as DDR clock for the
DSP with OCDS=0
DSP with OCDS=1
External CLK
Internal CLK/2 is used to clock the Data input A, B into DAC
Internal CLK/2
DSP clock is internal CLK/2 delay divided by OCDS selection. This clock could to be used as DDR clock for the FPGA
DSP with OCDS=0
DSP with OCDS=1
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5.6 InputUnderClockingMode(IUCM)
ThreeInputUnderClockingModesareavailableforspecificusewheretheinputdataareappliedtothe
DACathalfthenominalrate(orafourthofthenominalrate)withrespecttotheDACsamplingrate.
Thesemodesareavailableforboth4:1MUXmodeand2:1MUXmode.
Theprincipleistoapplyaselectabledivisionratio(1,2or4)betweentheDACclocksectionandthe
MUXclocksection.
Thusthereare3IUCMmodesselectablethroughthe3WSI(see3WSIdescription):
•IUCM1:MUXisdrivenbythesameclockthantheDACsection(defaultmode).
•IUCM2:MUXisdrivenbyadividedby2clockcomingfromtheDACsection
•IUCM4:MUXisdrivenbyadividedby4clockcomingfromtheDACsection
Detailedexplanationisgivenhere‐afterforIUCM2mode.IUCM4modeisoperatingonthesame
principlebutwitha4divisionratio.
InIUCM1modetheDACexpectsdataathalfthenominalrate:iftheDACworksatFssamplingrate,
thenin4:1MUXmode,theinputdatarateshouldbeFs/4andtheDSPclockisFs/(2N*X),withN=MUX
ratio(2or4)andX=OCDSratio(1or2).
WhentheIUCM2modeisselected,theinputdataratecanbeFs/8andtheDSPclockfrequencyis
Fs/(2N*X*2),withN=MUXratio(2or4)andX=OCDSratio(1or2).Thismeansthatininputunder
clockingmode,theDACiscapabletotreatdataathalfthenominalrate.Inthiscase,theDSPclockis
alsohalfitsnominalspeed.However,thesamplingfrequencyisstillFs.
TheIUCM2modeaffectsspectralresponseofthedifferentmodes.
ThefirsteffectisthatNyquistzoneedgesarenolongeratn*Fclock/2butatn*/Fclock/4(thisisthe
directconsequenceofthedivisionby2ofthedatarate).
Thesecondeffectisthemodificationoftheequationsrulingthespectralresponsesinthedifferent
modes.
IdealequationsdescribingmaximumavailablePoutvsFoutinthefouroutputmodeswhenIUCM2
modeisselectedaregivenhereafter,withX=normalisedoutputfrequency(i.e.Fout/Fclock,theedges
oftheNyquistzonesarethenatX=0,¼,½,¾,1,…)
Infact,duetolimitedbandwidth,anextratermmustbeaddedtotakeinaccountafirstorderlowpass
filterwithan7.5GHzcut‐offfrequency.
Assumingsinc(x)=sin(x)/x;
NRZmode:Pout(X)=20*log10(|sinc(*X)*cos(*X)|/0.893)
NRTZmode: Pout(X)=20*log10(|k*sinc(k**X)*cos(*X)|/0.893)
Wherek=1‐RPW/TclockandRPWiswidthofreshapingpulse.
Label LogicValue Description Defaultsetting
IUCM<1:0>
00or01 IUCM1:InputUnderClockingModeinactive
00(IUCM1)10 IUCM2:clockdivisionratiobetweenDACcoreandMUX:2
11 IUCM4:clockdivisionratiobetweenDACcoreandMUX:4
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RTZmode: Pout(X)=20*log10(|k*sinc(k**X)*cos(*X)|/0.893)
WherekistheDACinputclockdutycycle.Pleasenotethatduetophasemismatchinthebalunusedto
convertsingleendedclockintodifferentialclock,thethirdzeromaymovearoundthelimitofthe8th
andthe9thNyquistzones.Ideallyk=1/2.
RFmode:Pout(x)=20*log10(|k*sinc(k**X/2)*sin(k**X/2)*cos(*X)|/0.893)
wherek=1‐RPW/TclockandRPWiswidthofreshapingpulse.
Figure5‐21. MaxavailablePoutatnominalgainvsFoutinthefouroutputmodesat6.0GSps,combinedwithIUCM2,
overeightNyquistzones,computedfordifferentRPWsteps
Figure5‐22. MaxavailablePoutatnominalgainvsFoutinthefouroutputmodesat3.2GSps,combinedwithIUCM2,
overeightNyquistzones,computedfordifferentRPWsteps
NZ1 NZ2 NZ3 NZ4 NZ5 NZ6 NZ7 NZ8 NZ1 NZ2 NZ3 NZ4 NZ5 NZ6 NZ7 NZ8
NZ1 NZ2 NZ3 NZ4 NZ5 NZ6 NZ7 NZ8 NZ1 NZ2 NZ3 NZ4 NZ5 NZ6 NZ7 NZ8
7.5 7.5
7.5
7.5
7.5 GHz 7.5 GHz
7.5 GHz 7.5 GHz
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Figure5‐23. MaxavailablePoutatnominalgainvsFoutinthefouroutputmodesat6.0GSps,combinedwithIUCM4,
over16Nyquistzones,computedfordifferentRPWsteps
Figure5‐24. MaxavailablePoutatnominalgainvsFoutinthefouroutputmodesat3.2GSps,combinedwithIUCM4,
over16Nyquistzones,computedfordifferentRPWsteps
NZ1 NZ4 NZ8 NZ12 NZ16
NZ1 NZ4 NZ8 NZ12 NZ16
NZ1 NZ4 NZ8 NZ12 NZ16
NZ1 NZ4 NZ8 NZ12 NZ16
7.5 7.5
7.5
7.5
7.5 GHz 7.5 GHz
7.5 GHz
7.5 GHz
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5.7 SynchronizationFPGA‐DAC:IDC_P,IDC_NandTVFfunction
•IDC_P,IDC_N:InputDataCheckfunction(LVDSsignal).
•TVF:TimingViolationFlag.
TheIDC_P,IDC_NsignalareLVDSsignals.Thissignalshouldbetogglingateachcyclesynchronously
withotherdatabits.
ThissignalshouldbegeneratedbytheFPGAsothattheDACcancheckinreal‐timeifthetimings
betweentheFPGAandtheDACarecorrect.Theinformationonthesynchronizationisthengivenby
theTVFflag.
IDCshouldberoutedasthedatasignals(samelayoutrulesandsamelength).Itshouldbedriventoan
LVDSloworhighlevelifnotused.
Figure5‐25. IDCtimingvsdatainput:
Figure5‐26. FPGAtoDACsynoptic
TVFisa3.3VoutputsignalthatindicatesiftheDACandtheFPGAaresynchronised.
Table5‐5. TVFcodingtable
Label Value Description
TVF 0 SYNCHROOK
1Datasetuporholdtimeviolationdetected
IDC_P,
IDC_N
Data
Xi, XiN
IDC
Port A
Port B
Port C
Port D
TVF
OCDS
2
24
24
24
24
2
DSP
3
PSS
DIV
2
2
OUT, OUTN
CLK, CLKN
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PrincipleofOperation:
TheIDCsignalissampledinparallelby2clocks.Oneisdelayedpositivelybyhalfaclockperiod,the
otheroneisdelayednegativelybyhalfaclockperiod.TheresultofthesamplingoftheIDCinputby
boththeseclocksisthencompared.
Ifbothsampledoutputsareequivalent,thenTVFisat"0"toindicatethatDACandFPGAare
synchronised.Ifnot,TVFissetto"1"whichmeansthattheedgeoftheinternalsamplingclockisinside
thiswindow.
Inthatcaseitisrecommendedtoeither:
•ShifttheDSPclocktiming(possiblebyusingthePSSfunctioninsidetheDAC).
•ShiftthephaseoftheFPGAPLL(ifthisfunctionalityisavailableintheFPGA)tochangethetimingof
thedigitaldatacomparedtotheDACclock.
5.8 DSPoutputclock
TheDSPoutputclockDSP,DSPNisanLVDSsignalwhichisusedtosynchronizetheFPGAgeneratingthe
digitalpatternswiththeDACsamplingclock.
TheDSPclockfrequencyisafractionofthesamplingclockfrequency.Thedivisionfactordependson
OCDSandIUCMsettings.TheDSPclockfrequencyisequalto(samplingfrequency/[2N*X*M])where
NistheMUXratio(2or4)andXistheoutputclockdivisionfactor(1or2),determinedbytheOCDSbit
andMistheIUCMdivisionratio(1,2or4)determinedbytheIUCM[1..0]value.
Forexample,ina4:1MUXratioapplicationwithasamplingclockat4GHzandOCDSsetto"0"(i.e.
Factorof1)andinIUCM1,thentheinputdatarateis1000MSpsandtheDSPclockfrequencyis
500 MHz.
ThisDSPclockisusedintheFPGAtocontrolthedigitaldatasequencing.Itsphasecanbeadjusted
thankstothePSS[2:0]bitsinordertoensureapropersynchronizationbetweenthedatacomingtothe
DACandthesamplingclock.
TheTVFbitshouldbeusedtocheckwhetherthetimingbetweentheFPGAandtheDACiscorrect.
WhentheIDCinputisprovided,theTVFwillindicateiftherearesetuporholdviolationattheDAC
inputs.IfanyviolationisdetectedthroughTVF,thePSSsettingshouldbeincreasedby4inMUX4and
by2inMUX2.
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5.9 OCDS,IUCMandMUXcombinationssummary
ThetablehereaftergivestheDSPclockdivisionratiowithrespecttotheDACinputclock.
DSPclk=FCLK/(2*N*M*X)
DataRate=FCLK/(N*M)
WhereN:MUXRatio(2or4),M:IUCMRatio(1,2or4),X:OCDSRatio(1or2)
Notes: 1. BehaviouraccordingtoMUX,OCDS,IUCMandPSScombinationisindependentofoutputmode.
2. In2:1MUX,only4stepsofPSSareuseful,the4othergivesthesameresult.
5.10 Synchronizationfunction
ThetimeroftheDACmustberesetafterthefollowingchangesofconfiguration:
•Atpower‐on;
• Wheneveroneofthefollowingparameterismodified:OCDS,MUXorIUCM;
• Wheneverthemasterclockismodified(amplitude,frequency...).
TherearetwoSYNCfunctionsintegratedinthisDACwhichresetitstimer:
•Apowerupreset,whichistriggeredbythepowersuppliesifthededicatedpowerupsequenceis
appliedVCCD‐>VCCA3‐>VCCA5(theclockmustbesuppliedtotheDACpriortothispowerupsequence
beinggenerated);
•AnexternalSYNC,whichistriggeredbyapulseappliedtothedifferentialSYNC/SYNCNinputs.
Atpower‐on,thereare2possibilities:
•Thepower‐upsequenceoftheDACisVCCD,VCCA3thenVCCA5.Inthatcaseaninternalpoweronreset
isgeneratedbytheDAC.ThereisnoneedtosendaSYNCpulseaslongasOCDS,MUXorIUCMand
themasterclockarenotmodified(seeSection8.8onpage83formoreinformation).
•Ifthepower‐upsequenceisdifferentfromtheoneabove,aSYNCpulsemustbesenttotheDAC.
Table5‐6. OCDS,MUX,IUCMandPSScombinationssummary
MUXRatio IUCMRatio OCDSRatio PSSRange/Steps InputDataRate
4:1 0
IUCM1 00
OCDS1:DSPClock=FCLK/8 0 0to7/ ( 2 * F CLK)
1/(2*FCLK)steps FCLK/4
OCDS2:DSPClock=FCLK/16 1
IUCM2 10
OCDS1:DSPClock=FCLK/16 0 0to7/ ( 2 * F CLK)
1/(2*FCLK)steps FCLK/8
OCDS2:DSPClock=FCLK/32 1
IUCM4 11
OCDS1:DSPClock=FCLK/32 0 0to7/ ( 2 * F CLK)
1/(2*FCLK)steps FCLK/16
OCDS2:DSPClock=FCLK/6 4 1
2:1 1
IUCM1 00
OCDS1:DSPClock=FCLK/4 0 0to7/ ( 2 * F CLK)
1/(2*FCLK)steps FCLK/2
OCDS2:DSPClock=FCLK/8 1
IUCM2 10
OCDS1:DSPClock=FCLK/8 0 0to7/ ( 2 * F CLK)
1/(2*FCLK)steps FCLK/4
OCDS2:DSPClock=FCLK/16 1
IUCM4 11
OCDS1:DSPClock=FCLK/16 0 0to7/ ( 2 * F CLK)
1/(2*FCLK)steps FCLK/8
OCDS2:DSPClock=FCLK/32 1
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TheexternalSYNCisLVDScompatible.Itisactivehigh.AftertheapplicationoftheSYNCsignal,theDSP
clockfromtheDACwillstopandafteraconstantandknowntime(tDSP);theDSPclockwillstartup
again.
TheexternalSYNCcanalsobeusedtosynchronizemultipleDACs.
Thepulsedurationshouldbeatleastof3masterclockcyclesinOCDS1andIUCM1.
DependingonthesettingsofOCDS,IUCMandalsoontheMUXratiothewidthoftheSYNCpulsemust
begreaterthanacertainnumberofexternalclockpulses.Itisalsonecessarythatthesyncpulsewidth
shallbeawholenumberofclockcycles.
5.11 GainAdjustfunction
ThisfunctionallowstheadjustmentoftheinternalgainoftheDACsothatitcanbetunedtotheunity
gain.
ThegainoftheDACcanbeadjustedbysettingtheGAINregisterthroughthe3WSI.Thegaincanbe
adjustedby1024steps.GAminisgivenforGAIN=0x000andGAmaxforGAIN=0x3FF.Defaultvalueis
GAtypgivenforGAIN=0x200.
Note: ThegainvoltagestepisindicatedinSection3.3onpage5Table3‐3.
5.12 Diodefunction
Adiodefordiejunctiontemperaturemonitoring,isavailableinthisDAC.Forthemeasurementofdie
junctiontemperature,atemperaturesensorcanbeused.
Figure5‐27. Temperaturediodeimplementation
DAC Temperature sensor
Diode
DGND
D+
D-
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In characterization measurement a current of 1 mA is applied on the DIODE pin. The voltage across the DIODE pin
and the DGND pin gives the junction temperature using the intrinsic diode characteristics below.
Figure5‐28. Diode Characteristics for Die Junction Temperature Monitoring
5.13 DAC3WSIDescription(DACControls)
5.13.1 3WSItimingdescription
The 3WSI is a synchronous write only serial interface made of 4 signals:
"reset_n": asynchronous 3WSI reset, active low
"sclk": serial clock input
"sld_n": serial load enable input
"sdata": serial data input.
The 3WSI gives a "write-only" access to up to 16 different internal registers of up to 12 bits each. The
input format is fixed with 4 bits of register address followed by 12 bits of data. Address and data are
sent MSB first.
The write procedure is fully synchronous with the clock rising edge of "sclk" and described in the
following chronogram.
"sld_n" and "sdata" are sampled on each rising clock edge of "sclk" (clock cycle).
"sld_n" must be set at "1" when no write procedure is done.
A write starts on the first clock cycle when "sld_n" is at "0". "sld_n" must stay at "0" during the
complete write procedure.
In the first 4 clock cycles with "sld_n" at "0", 4 bits of register address from MSB (a[3]) to LSB (a[0]) are
entered.
In the next 12 clock cycles with "sld_n" at "0", 12 bits of data from MSB (d[11]) to LSB (d[0]) are
entered.
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This gives 16 clock cycles with "sld_n" at "0" for a normal write procedure.
A minimum of one clock cycle with "sld_n" returned at "1" is requested to end the write procedure,
before the interface is ready for a new write procedure. Any clock cycle with "sld_n" at "1" before the
write procedure is completed interrupts this procedure and no data transfer to internal registers is
done. It is possible to have only one clock cycle with "sld_n" at "1" between two following write
procedures. Additional clock cycles with "sld_n" at "0" after the parallel data have been transferred to
the register do not affect the write procedure and are ignored.
12 bits of data must always be sent, even if the internal addressed register has less than 12 bits.
Unused bits (usually MSB’s) are ignored. Bit signification and bit position for the internal registers are
detailed in the section "Registers".
The "reset_n" pin combined with the "sld_n" pin can be used as a reset to program the chip to the
"reset setting".
"reset_n" high: no effect
"reset_n" low and "sld_n" low: programming of registers to default values
Figure5‐29. 3WSI Timing Diagram
Timings related to 3WSI are given in the table below
Previous
setting
a[3] a[2] a[1] a[0] d[11] d[3] d[2]d[4]
Default setting New
Setting
reset_n
sclk
sld_n
sdata
Internal
Register
Value
12 431613 14 1512
11
5
d[0]d[1]
Table5‐7. 3WSI Timings
Name Parameter Min Typ Max Unit Note
Tsclk Period of sclk 1 µs
Twsclk High or low time of sclk 0.5 µs
Tssld_n Setup time of sld_n before rising edge of sclk 4 µs
Thsld_n Hold time of sld_n after rising edge of sclk 2 µs
Tssdata Setup time of sdata before rising edge of sclk 4 ns
Thsdata Hold time of sdata after rising edge of sclk 2 ns
Twlreset Minimum low pulse width of reset_n 5 ns
Tdreset Minimum delay between an edge of reset_n and the
rising edge of sclk 5µs
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5.13.2 3WSI:AddressandDataDescription
This 3WSI is activated with the control bit sld_n going low (please refer to "write timing" in next
section).
The length of the word is 16 bits: 12 for the data and 4 for the address.
The maximum serial logic clock frequency is 1 MHz.
Table5‐8. Registers Mapping
Address Label Description DefaultSetting
0000 State Register
MUX ratio Selection
Output MODE selection
IUCM ratio selection
External Control for DSP Clock
Reshaping Pulse Width (RPW) adjust
Reshaping Pulse Begin (RPB) adjust
0x922
0001 GA Register Gain Adjust register 0x200
0010 Not available
0011 Not available
0100 Not available
0101 DSP Register PSS, OCDS controls 0x080
0110 Not available
0111 Not available
1000 to 1111 Not available
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5.13.3 StateRegister(address0000)
Default value: 0x922
Table5‐9. State register Mapping (Address 0000)
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RPW<2:0> RPB<2:0> ECDC IUCM<1:0> MODE<1:0> MUX
Table5‐10. State register Coding (Address 0000)
Label Coding Description
Default
Value Notes
MUX D0 0 4:1 MUX mode 0 (1)
12:1 MUX mode
MODE<1:0> D2, D1 00 NRZ mode 01 (1)
01 Narrow RTZ (a.k.a. NRTZ) mode
10 RTZ Mode
11 RF mode
IUCM<1:0> D4, D3 00 IUCM1 (MUX at DAC core speed) 00 (1)
01 IUCM1 (MUX at DAC core speed)
10 IUCM2 (MUX at DAC core speed/2)
11 IUCM4 (MUX at DAC core speed/4)
ECDC D5 0 OCDS and PSS ruled by DSP register at address 0101 1 (1)(2)
1 OCDS and PSS externally controlled
RPB<2:0> D8, D7, D6 000 RPB2 = 38 ps 100 (3)
001 RPB2 = 38 ps
010 RPB0 = 12ps
011 RPB1 = 25 ps
100 RPB2 = 38 ps
101 RPB3 = 51 ps
110 RPB4 = 64 ps
111 RPB2 = 38 ps
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Notes: 1. Default mode is 4:1 MUX, NRTZ output mode, IUCM1, and PSS & OCDS externally controlled. Default mode is
programmed by power up reset or low level pulse on reset_n pin while sld_n pin is low.
2. ECDC: when ECDC is High the timing of the DSP clock is controlled externally through pins PSS<2:0> and OCDS; when
ECDC is low, this functionality is controlled through the 3WSI by the DSP register at address 0101.
3. RPB setting is applicable in NRTZ, RTZ and RF modes. RPB values are design values.
4. RPW setting is applicable in NRTZ and RF modes. RPW values are typical values measured on one part.
5. From design, in case RPW> Tclk/2, the RPW value becomes equal to Tclk - RPW. For example at Fclk = 6.0 GHz, it affects the
largest RPW value (100ps) which will then be 166.6 - 100 = 66.6 ps. This largest RPW value will be affected for Fclk above
5 GHz (for which RPW becomes superior to Tclk/2).
5.13.4 GARegister(address0001)
Default value: 0x200
RPW<2:0> D11, D10, D9 000 RPW2
66 ps in NRTZ mode / 68 ps in RF mode 100 (4)
001 RPW2
66 ps in NRTZ mode / 68 ps in RF mode
010 RPW0
43 ps in NRTZ mode / 52 ps in RF mode
011 RPW1
49 ps in NRTZ mode / 60 ps in RF mode
100 RPW2
66 ps in NRTZ mode / 68 ps in RF mode
101 RPW3
78 ps in NRTZ mode / 86 ps in RF mode
110 RPW4
66 ps in NRTZ mode / 76 ps in RF mode
(5)
111 RPW2
66 ps in NRTZ mode / 68 ps in RF mode
Table5‐10. State register Coding (Address 0000) (Continued)
Label Coding Description
Default
Value Notes
Table5‐11. GA register Mapping (Address 0001)
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
GA<9:0>
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5.13.5 DSPRegister(address0101)
Default value: 0x080 (OCDS = 0, PSS = 000)
Table5‐12. DSP register Mapping (Address 0101)
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
<reserved> PSS<2:0> OCDS
Table5‐13. Registers 0000 to 0101 Summary
Address Description
Default
register
value
Default
parameter
value
Register
valuefor
maxvalue
Parameter
maxvalue
Register
valuefor
minvalue
Parameter
minvalue Step
0000 RPB Adjust 0x922 RPB2 0x9A2 RPB4 0x8A2 RPB0 1 bit
0000 RPW Adjust 0x922 RPW2 0xD22 RPW4 0x522 RPW0 1 bit
0000 ECDC 0x922 ECDC1 0x922 ECDC1 0x902 ECDC0 N/A
0000 IUCM 0x922 IUCM1 0x93A IUCM4 0x922 IUCM1 N/A
0000 MODE 0x922 NRTZ 0x926 RF 0x920 NRZ N/A
0000 MUX 0x922 4:1 MUX 0x923 2:1 MUX 0x922 4:1 MUX N/A
0001 Gain Adjust 0x200 1 0x3FF 1.15 0x000 0.85 300ppm
0101 PSS 0x080 PSS0 0x09C PSS7 0x080 PSS0 N/A
0101 OCDS 0x080 OCDS1 0x081 OCDS2 0x080 OCDS1 N/A
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6. PINDESCRIPTION
Figure6‐1. Pinout view fpBGA196 (Top view)
1234567891011121314
A DGND B5 B6 B6N B9 B9N B11 C11 C9N C9 C6N C6 C5 DGND A
B
B3 B4 B5N B7 B8 B10 B11N C11N C10 C8 C7 C5N C4 C3
B
C
B1N B3N B4N B7N B8N B10N DGND DGND C10N C8N C7N C4N C3N C1N
C
D
B1 B2 B2N DGNDDGNDVCCDVCCDVCCDVCCDDGNDDGND C2N C2 C1
D
E
A10N B0 B0N DGNDDGNDVCCDVCCDVCCDVCCDDGNDDGND C0N C0 D10N
E
F
A10 A11 A11N VCCD VCCD AGND AGND AGND AGND VCCD VCCD D11N D11 D10
F
GA8 A8N A9 A9N DGND AGND AGND AGND AGND DGND D9N D9 D8N D8 G
HA6 A6N A7 A7N DGND AGND AGND AGND AGND DGND D7N D7 D6N D6 H
J
A3N A5 A5N VCCA3 VCCA3 AGND AGND AGND AGND VCCA3 VCCA3 D5N D5 D3N
J
K
A3 A4 A4N DGND DGND AGND VCCA5 VCCA5 AGND DGND DGND D4N D4 D3
K
L
A1N A2 A2N DGND Diode VCCA5 VCCA5 VCCA5 VCCA5 DGND sldn D2N D2 D1N
L
M
A1 A0N NC TVF reset_n VCCA5 VCCA5 AGND AGND sdata sclk PSS2 D0N D1
M
N
A0 DSPN IDC_P SYNCN CLKN AGND AGND AGND AGND AGND AGND
iref_test
OCDS D0
N
P
DGND DSP IDC_N SYNC CLK AGND AGND AGND OUT OUTN AGND PSS0 PSS1 DGND
P
1234567891011121314
Table6‐1. Pinout Table fpBGA196
Signalname Pinnumber Description Direction EquivalentSimplifiedschematics
Powersupplies
VCCA5
K7, K8, L6, L7, L8, L9,
M6, M7
5.0V analog power supplies
Referenced to AGND N/A
VCCA3 J4, J5, J10, J11 3.3V analog power supply
Referenced to AGND N/A
VCCD
D6, D7, D8, D9, E6, E7,
E8, E9, F4, F5, F10, F11
3.3V digital power supply
Referenced to DGND N/A
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AGND
F6, F7, F8, F9, G6, G7,
G8, G9, H6, H7, H8, H9,
J6, J7, J8, J9, K6, K9,
M8, M9, N6, N7, N8,
N9, N10, N11, P6, P7,
P8, P11
Analog Ground
N/A
DGND
A1, A14, C7, C8, D4,
D5, D10, D11, E4, E5,
E10, E11, G5, G10, H5,
H10, K4, K5, K10, K11,
L4, L10, P1, P14
Digital Ground
N/A
Clocksignals
CLK
CLKN
P5
N5
Master sampling clock input
(differential) with internal
common mode at 2.5V
It should be driven in AC
coupling.
Equivalent internal
differential 100 input
resistor.
I
DSP
DSPN
P2
N2
Output clock (in-phase and
inverted phase)
If not used, should be 100
terminated.
O
Table6‐1. Pinout Table fpBGA196 (Continued)
Signalname Pinnumber Description Direction EquivalentSimplifiedschematics
CLK
CLKN
50Ω
50Ω
AGND
3.75 pF
2.5V
10KΩ
VCCD
AGND
3.2KΩ
VCCD
DGND
DSPN
DSP
3.625mA
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Analogoutputsignal
OUT
OUTN
P9
P10
In phase and inverted phase
analog output signal
(differential termination
required)
O
DigitalInputsignals
A0, A0N
A1, A1N
A2, A2N
A3, A3N
A4, A4N
A5, A5N
A6, A6N
A7, A7N
A8, A8N
A9, A9N
A10, A10N
A11, A11N
N1, M2
M1, L1
L2, L3
K1, J1
K2, K3
J2, J3
H1, H2
H3, H4
G1, G2
G3, G4
F1, E1
F2, F3
Differential Digital input
Port A
Data A0, A0N is the LSB
Data A11, A11N is the MSB
I
B0, B0N
B1, B1N
B2, B2N
B3, B3N
B4, B4N
B5, B5N
B6, B6N
B7, B7N
B8, B8N
B9, B9N
B10, B10N
B11, B11N
E2, E3
D1, C1
D2, D3
B1, C2
B2, C3
A2, B3
A3, A4
B4, C4
B5, C5
A5, A6
B6, C6
A7, B7
Differential Digital input
Port B
Data B0, B0N is the LSB
Data B11, B11N is the MSB
I
Table6‐1. Pinout Table fpBGA196 (Continued)
Signalname Pinnumber Description Direction EquivalentSimplifiedschematics
OUT
OUTN
V
CCA5
Current
Switches
50Ω
AGND
INN
IN
1.25V
50Ω
50Ω
GND
3.75 pF
V
CCD
20.4 KΩ
K
AGND
2 K
12.4 KΩ
VCC3
= 3.3V
DGND
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C0, C0N
C1, C1N
C2, C2N
C3, C3N
C4, C4N
C5, C5N
C6, C6N
C7, C7N
C8, C8N
C9, C9N
C10, C10N
C11, C11N
E13, E12
D14, C14
D13, D12
B14, C13
B13, C12
A13, B12
A12, A11
B11, C11
B10, C10
A10, A9
B9, C9
A8, B8
Differential Digital input
Port C
Data C0, C0N is the LSB
Data C11, C11N is the MSB
I
D0, D0N
D1, D1N
D2, D2N
D3, D3N
D4, D4N
D5, D5N
D6, D6N
D7, D7N
D8, D8N
D9, D9N
D10, D10N
D11, D11N
N14, M13
M14, L14
L13, L12
K14, J14
K13, K12
J13, J12
H14, H13
H12, H11
G14, G13
G12, G11
F14, E14
F13, F12
Differential Digital input
Port D
Data D0, D0N is the LSB
Data D11, D11N is the MSB
I
Controlsignals
SYNC,
SYNCN
P4
N4
In phase and Inverted phase
reset signal I
Table6‐1. Pinout Table fpBGA196 (Continued)
Signalname Pinnumber Description Direction EquivalentSimplifiedschematics
INN
IN
1.25V
50Ω
50Ω
GND
3.75 pF
V
CCD
20.4 KΩ
K
AGND
2 K
12.4 KΩ
VCC3
= 3.3V
DGND
SYNC
SYNCN
1.25V
50Ω
50Ω
GND
3.75 pF
10.2 KΩ
K
AGND
2 K
6.2 KΩ
VCC3
DGND
V
CCD
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IDC_P,
IDC_N
N3
P3 Input data check I
sdata M10 3WSI serial data input. I
sclk M11 3WSI clock.
reset_n M5 Reset for the 3WSI registers
sld_n L11 3WSI serial load enable input.
OCDS N13 Output Clock Division Select I Driven by resistor: 10 or 10 K
Driven by voltage: <0.5 V or > 2 V
PSS0
PSS1
PSS2
P12
P13
M12
Phase Shift Select (PSS2 is the
MSB)
Table6‐1. Pinout Table fpBGA196 (Continued)
Signalname Pinnumber Description Direction EquivalentSimplifiedschematics
INN
IN
1.25V
50Ω
50Ω
GND
3.75 pF
20.4 KΩ
K
AGND
2 K
12.4 KΩ
VCC3
= 3.3V
DGND
VCCD
32uA 320nA
320nA
28.14 KΩ
8 KΩ
8 KΩ
INP
14 KΩ
GND
20 KΩ
~3.2V
~1.6V
VCCD
VCC3
DGND
IN
Vp
200 Ω
13 kΩ
20 kΩ
33 kΩ
8 kΩ8 kΩ
8 kΩ
4 kΩ
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TVF M4 Setup/Hold time violation flag O
Diode L5 Diode for die junction
temperature monitoring I
Iref test N12
Bandgap output for test
purpose. To leave
unconnected
O
NC M3 Not connected
Table6‐1. Pinout Table fpBGA196 (Continued)
Signalname Pinnumber Description Direction EquivalentSimplifiedschematics
1 KΩ
V
CCD
10 KΩ
500Ω
DGND
100uA / 0µA
0uA / 100µA
DGND
10 KΩ
TVF
V
CCD
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7. CHARACTERIZATIONRESULTS
7.1 Staticperformances
7.1.1 INL/DNL
Figure7‐1. INL & DNL measurements at Fout = 100 kHz, Fclock = 3 GHz
7.1.2 DCGain
Figure7‐2. Output Voltage variations versus Gain Adjust
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Figure7‐3. Output voltage variation vs Power supplies & temperature vs Gain Adjust
7.2 ACperformances
7.2.1 AvailableOutputPowervsFout.
NRZ mode offers max power for 1st Nyquist operation.
NRTZ mode offers optimum power over full 1st and first half of 2nd Nyquist zones.
RTZ mode offers slow roll off for 2nd Nyquist operation.
RF mode offers maximum power over 2nd and 3rd Nyquist operation. It is globally the most suitable
mode for operation up to the 8th Nyquist.
7.2.1.1 MUX2:1at3.2GSps
Figure7‐4. Pout vs Fout from 50 MHz to 8950 MHz in the 4
output modes at 6.0 GSps in MUX4:1
Figure7‐5. Pout vs Fout from 32 MHz to 4768 MHz in
the 4 output modes at 3.2 GSps in MUX2:1
0
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
Pout (dBm)
Fout (MHz)
Pout = f(Fout) @3.2GSps – MUX2:1
NRZ
NRTZ
RTZ
RF
1st Nyquist 3rd Nyquist
2nd Nyquist
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
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7.2.1.2 MUX4:1at6.0GSps
Measurements from DC to 12 GHz are carried out with Krytar 1G-12.4 GHz balun (ref 4010124)
Measurements from 12 to 26 GHz are carried out with Krytar 6G-20 GHz balun (ref 4060200)
Note: Pout fluctuations (~2 GHz period equivalent) are due to Teledyne e2v evaluation board (100
differential output lines)
Figure7‐6. Pout vs Fout @ 6.0 GSps from DC to 9 GHz vs modes
Figure7‐7. Pout vs Fout @ 6.0 GSps from 8 GHz to 26 GHz vs modes
(8 GHz to 26 GHz Fout frequency range includes X-Band, Ku-Band and K Band)
Note: the Pout attenuation below 200 MHz is due to Krytar balun Bandpass characteristic
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Figure7‐8. Pout vs Fout @ 6.0 GSps from 8 GHz to 12 GHz vs modes (X-Band)
Figure7‐9. Pout vs Fout @ 6.0 GSps from 12 GHz to 18 GHz vs modes (Ku-Band)
Figure7‐10. Pout vs Fout @ 6.0 GSps from 12 GHz to 26 GHz vs modes (K-Band)
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7.2.1.3 MUX4:1at7.0GSps
Measurements conditions are identical to the ones shown at 6.0 GSps
Figure7‐11. Pout vs Fout @ 7.0 GSps from DC to 9 GHz vs modes
Figure7‐12. Pout vs Fout @ 7.0 GSps from 8 GHz to 12 GHz vs modes (X-Band)
Figure7‐13. Pout vs Fout @ 7.0 GSps from 12GHz to 18 GHz vs modes (Ku-Band)
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Figure7‐14. Pout vs Fout @ 7.0 GSps from 18 GHz to 26 GHz vs modes (K-Band)
7.2.2 SingleToneSFDRMeasurementsversusFout
Figure 7-15 summarizes SFDR measurements in MUX4:1 mode, for an Fout sweep from 50 MHz to
8999 MHz.
Figure 7-16 summarizes SFDR measurements in MUX2:1 mode, for an Fout sweep from 32 MHz to
4768 MHz.
Figure 7-17 summarizes SFDR measurements in MUX4:1 mode, for an Fout sweep from 5 GHz to
24 GHz in RF mode.
Figure7‐15. SFDR in the 4 output modes at 6.0 GSps in
MUX4:1
Figure7‐16. SFDR in the 4 output modes at 3.2 GSps in
MUX2:1
0
10
20
30
40
50
60
70
80
0
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
SFDR (dBc)
Fout (MHz)
SFDR @3.2GSps – MUX2:1
NRTZ
NRZ
RTZ
RF
1st Nyquist 3rd Nyquist
2nd Nyquist
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Figure7‐17. SFDR (dBc) vs Fout from 5 GHz to 24 GHz (covering X-Band, Ku-Band, K-Band) @ 6.0 GSps in MUX4:1,
RF mode
7.2.3 SingleToneSpectrumversusFoutandOutputModes
7.2.3.1 MUX4:1at6.0GSps
Following figures are given with optimum RPB/RPW settings
Figure7‐18. Typical SFDR spectrum in NRTZ mode with Fout = 2940 MHz (1st Nyquist), MUX4:1, Fs = 6.0 GSps,
SFDR = 56 dBc
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Figure7‐19. Typical SFDR spectrum in NRTZ mode with Fout = 5940 MHz (2nd Nyquist), MUX4:1, Fs = 6.0 GSps,
SFDR = 58 dBc
Figure7‐20. Typical SFDR spectrum in RF mode with Fout = 8940 MHz (3rd Nyquist), MUX4:1, Fs = 6.0 GSps,
SFDR = 49 dBc
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Figure7‐21. Typical SFDR spectrum in RF mode with Fout = 11950 MHz (4th Nyquist), MUX4:1, Fs = 6.0 GSps,
SFDR = 50 dBc
Figure7‐22. Typical SFDR spectrum in RF mode with Fout = 18060 MHz (7th Nyquist), MUX4:1, Fs = 6.0 GSps,
SFDR = 45 dBc
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Figure7‐23. Typical SFDR spectrum in RF mode with Fout = 23950 MHz (8th Nyquist), MUX4:1, Fs = 6.0 GSps,
SFDR = 36 dBc
7.2.3.2 MUX4:1at7.0GSps
Following figures are given with optimum RPB/RPW settings
Figure7‐24. Typical SFDR spectrum in NRTZ mode with Fout = 3430 MHz (1st Nyquist), MUX4:1, Fs = 7.0 GSps,
SFDR = 55 dBc
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Figure7‐25. Typical SFDR spectrum in RF mode with Fout = 6930 MHz (2nd Nyquist), MUX4:1, Fs = 7.0 GSps,
SFDR = 58 dBc
Figure7‐26. Typical SFDR spectrum in RF mode with Fout = 10430 MHz (3rd Nyquist), MUX4:1, Fs = 7.0 GSps,
SFDR = 50 dBc
Figure7‐27. Typical SFDR spectrum in RF mode with Fout = 13930 MHz (4th Nyquist), MUX4:1, Fs = 7.0 GSps,
SFDR = 48 dBc
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Figure7‐28. Typical SFDR spectrum in RF mode with Fout = 17430 MHz (5th Nyquist), MUX4:1, Fs = 7.0 GSps,
SFDR = 41 dBc
Figure7‐29. Typical SFDR spectrum in RF mode with Fout = 20930 MHz (6th Nyquist), MUX4:1, Fs = 7.0 GSps,
SFDR = 36 dBc
Figure7‐30. Typical SFDR spectrum in RF mode with Fout = 24430 MHz (7th Nyquist), MUX4:1, Fs = 7.0 GSps,
SFDR = 37 dBc
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7.2.3.3 MUX2:1at3.2GSps
Figure7‐31. Typical SFDR spectrum in NRZ mode.
Fout = 32 MHz (1st Nyquist), MUX2:1,
Fs = 3.2 GSps. SFDR = 70 dBc
Figure7‐32. Typical SFDR spectrum in NRTZ mode.
Fout = 32 MHz (1st Nyquist), MUX2:1,
Fs = 3.2 GSps. SFDR = 76 dBc
Figure7‐33. Typical SFDR spectrum in NRTZ mode.
Fout = 1568 MHz (1st Nyquist), MUX2:1,
Fs = 3.2 GSps. SFDR = 65 dBc
Figure7‐34. Typical SFDR spectrum in RTZ mode.
Fout = 3168 MHz (2nd Nyquist), MUX2:1,
Fs = 3.2 GSps. SFDR = 59 dBc
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7.2.4 SingleToneSFDRMeasurementsversusFclock(MUX4:1)
The following figures show typical SFDR performance of an EV12DS460A device versus sampling rate.
RPB and RPW settings are set in order to maximize SFDR values (RPB and RPW parameters are there-
fore not constant versus Fclk).
Figure7‐35. Typical SFDR spectrum in RF mode.
Fout = 3168 MHz (2nd Nyquist), MUX2:1,
Fs = 3.2 GSps. SFDR = 58 dBc
Figure7‐36. Typical SFDR spectrum in RF mode.
Fout = 4768 MHz (3rd Nyquist), MUX2:1,
Fs = 3.2 GSps. SFDR = 53 dBc
Figure7‐37. SFDR versus Fclk in 1st Nyquist zone for 4
output modes. Fout = Fclk/2 - Fclk/100
Figure7‐38. SFDR versus Fclk in 2nd Nyquist zone for 3
output modes. Fout = Fclk - Fclk/100
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7.2.5 SFDRvsPowersupplies&Temperature
7.2.6 DualTonesSpectra
7.2.6.1 Dual‐toneSpectraat6.0GSps
Following figures are given with optimum RPB/RPW settings.
Figure7‐41. Typical Dual-tone spectrum in NRTZ mode with Fout1,Fout2 = 2850 MHz,2860 MHz (1st Nyquist), MUX4:1,
Fs = 6.0 GSps, IMD3 - = 73 dBc, IMD full Nyquist = 54 dBc
Figure7‐39. SFDR vs Power supplies vs modes Figure7‐40. SFDR vs temperature vs modes
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Figure7‐42. Typical Dual-tone spectrum in RF mode with Fout1,Fout2 = 5750 MHz,5760 MHz, (2nd Nyquist), MUX4:1,
Fs = 6.0 GSps, IMD3 - = 64 dBc, IMD full Nyquist = 53 dBc
Figure7‐43. Typical Dual-tone spectrum in RF mode with Fout1,Fout2 = 8850 MHz,8860 MHz (3rd Nyquist), MUX4:1,
Fs = 6.0 GSps, IMD3 - = 57 dBc, IMD full Nyquist = 43 dBc
Figure7‐44. Typical Dual-tone spectrum in RF mode with Fout1,Fout2 = 11850 MHz,11860 MHz (4th Nyquist), MUX4:1,
Fs = 6.0 GSps, IMD3 - = 58 dBc, IMD full Nyquist = 45 dBc
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7.2.6.2 Dual‐toneSpectraat7.0GSps
Following figures are given with optimum RPB/RPW settings.
Figure7‐45. Typical Dual-tone spectrum in NRTZ mode with Fout1,Fout2 = 3450 MHz, 3460 MHz (1st Nyquist), MUX4:1,
Fs = 7.0 GSps, IMD3 - = 53 dBc, IMD full Nyquist = 51 dBc
Figure7‐46. Typical Dual-tone spectrum in RF mode with Fout1,Fout2 = 6950 MHz,6960 MHz (2nd Nyquist), MUX4:1,
Fs = 7.0 GSps, IMD3 - = 64 dBc, IMD full Nyquist = 59 dBc
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Figure7‐47. Typical Dual-tone spectrum in RF mode with Fout1,Fout2 = 10450 MHz,10460 MHz (3rd Nyquist), MUX4:1,
Fs = 7.0 GSps, IMD3 - = 52 dBc, IMD full Nyquist = 44 dBc
Figure7‐48. Typical Dual-tone spectrum in NRTZ mode with Fout1,Fout2 = 13950 MHz,13960 MHz, (4th Nyquist),
MUX4:1, Fs = 7.0 GSps, IMD3 - = 54 dBc, IMD full Nyquist = 48 dBc
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7.2.7 ACPRmeasurements@6.0GSps(10MHzQPSK)
Figure7‐49. Adjacent Channel Power Ratio (ACPR) @ 6.0 GSps, 10 MHz QPSK, 1.6 GHz Center frequency, ACPR = 59 dBc,
NRTZ mode
Figure7‐50. Adjacent Channel Power Ratio (ACPR) @ 6.0 GSps, 10 MHz QPSK, 4.6 GHz Center frequency, ACPR = 52 dBc,
NRTZ mode
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Figure7‐51. Adjacent Channel Power Ratio (ACPR)@ 6.0 GSps, 10 MHz QPSK, 10.6 GHz Center frequency,
ACPR = 42 dBc, RF mode
Figure7‐52. Adjacent Channel Power Ratio (ACPR) @ 6.0 GSps, 10 MHz QPSK, 16.6 GHz Center frequency,
ACPR = 36.7 dBc, RF mode
Figure7‐53. Adjacent Channel Power Ratio (ACPR) @ 6.0 GSps, 10 MHz QPSK, 22.6 GHz Center frequency,
ACPR = 30 dBc, RF mode
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Figure7‐54. Adjacent Channel Power Ratio (ACPR) @ 7.0 GSps, 10 MHz QPSK, 22.9 GHz Center frequency,
ACPR = 35 dBc, RF mode
7.2.8 NPRperformance
7.2.8.1 NPRvsLoadingFactor(LF)
NPR pattern covers a 2.667 GHz bandwidth (166.67 MHz to 2833.33 MHz) with a 33.3 MHz notch width
centered at 1466.67 MHz.
Figure 7-55 shows NPR evolution versus loading factor. Optimum NPR value is achieved for
LF = –14 dBFS.
Figure7‐55. NPR versus Loading Factor @ 6.0 Gsps
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7.2.8.2 NPRover3Nyquistzonesversusmode
NPR measurements have been carried out at optimum loading factor (LF) for a 12 bit DAC, that is
–14 dBFS.
SNR can be computed from NPR measurement with the formula: SNR[dB] = NPR[dB] + ILF[dB]I - 3.
ENOB can be computed with the formula: ENOB = (SNR[dB] - 1.76) / 6.02.
7.2.8.2.1NPRat6.0GSps
Figure7‐56. NPR in 1st Nyquist Zone, 166.67 MHz to 2833.33 MHz Noise Pattern with a 33.3 MHz Notch Centered on
1466.67 MHz, NRTZ mode
Measured average NPR: 43.5 dB, therefore SNR = 55 dB and ENOB = 8.8 bit
Figure7‐57. NPR in 2nd Nyquist Zone, 3200 MHz to 5866.67 MHz Noise Pattern with a 33.3 MHz Notch Centered on
4533.33 MHz, NRTZ mode.
Measured average NPR: 40.5 dB, therefore SNR = 51.5 dB and ENOB = 8.3 bit
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Figure7‐58. NPR in 2nd Nyquist Zone, 3200 MHz to 5866.67 MHz Noise Pattern with a 33.33 MHz Notch Centered on
4533.3 MHz, RF mode.
Measured average NPR: 37.5 dB, therefore SNR = 48.5 dB and ENOB = 7.8 bit
Figure7‐59. NPR in 3rd Nyquist Zone, 6133.3 MHz to 8800 MHz Noise Pattern with a 33.3 MHz Notch Centered on
7466.67 MHz, RF mode.
Measured average NPR: 36 dB, therefore SNR = 47 dB and ENOB = 7.5 bit
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7.2.8.2.2NPRat7.0GSps
Figure7‐60. NPR @ 7.0 GSps in 1st Nyquist, 3150 MHz pattern, NPR = 42.6 dB (= 8.6 Bit equivalent ENOB), NRTZ mode
Figure7‐61. NPR @ 7.0 GSps in 2nd Nyquist, 3150 MHz pattern, NPR = 36.2 dB (= 7.6 Bit equivalent ENOB), NRTZ mode
Figure7‐62. NPR @ 7.0 GSps in 3rd Nyquist, 3150 MHz pattern, NPR = 33.3 dB (= 7.1 Bit equivalent ENOB), RF mode
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7.2.8.3 NPRvsPowersupplies&Temperature
7.2.8.4 NPRover8Nyquistzonesversusmodeat6.0GSps
Figure7‐65. NPR vs Output Frequency from 1 GHz to 23 GHz, vs modes (covering X-Band, Ku-Band,
K-Band)
Figure7‐63. NPR vs power supply in the 4 output modes
at room temperature.
min: VCCA5: 4.75V // VCCA3 = VCCD = 3.15V;
Typ: VCCA5: 5.00V // VCCA3 = VCCD = 3.30V;
MAX: VCCA5: 5.25V // VCCA3 = VCCD = 3.45V
Figure7‐64. NPR versus temperature at 6.0 GSps For
the 4 output modes from
Tc = –40°C to Tc = 80°C (Tj = –2°C to 110°C)
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7.3 InputDataSet‐upandHoldtimevsInputDataRate
The figure below shows tSH variation versus input data rate.
Figure7‐66. tSH vs input data rate
7.4 Analogoutputriseandfalltime
The figure below shows the DAC output step response with rise and fall time of 30 ps after probe de-
embedding.
Figure7‐67. Analog output step response (Full Scale 1Vpp)
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8. APPLICATIONINFORMATION
8.1 Analogoutput(OUT/OUTN)
The analog output should be used as a differential signal, as described in the figures below.
If the application requires a single-ended analog output, then a balun is necessary to generate a single
ended signal from the differential output of the DAC.
Figure8‐1. Analog output differential termination
Figure8‐2. Analog output using a 1/sqrt(2) Balun
Note: The AC coupling capacitors should be chosen as broadband capacitors with a value depending
on the application.
MUXDAC
VCCA5
100nF
100nF
OUT
OUTN
Current
Switches and
sources
AGND
50Ω
50Ω lines 50Ω lines
AGND
50Ω
Receiver
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8.2 ClockInput(CLK/CLKN)
The DAC input clock (sampling clock) should be provided as a differential signal as described in the
following figures:
Figure8‐3. Clock input differential termination
Note: The buffer is internally pre-polarized to 2.5V (buffer between VCCA5 and AGND).
Figure8‐4. Clock input differential with balun
The AC coupling capacitors should be chosen as broadband capacitors with a value depending on the
application).
100Ω
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8.3 DigitalData,SYNCandIDCinputs
LVDS buffers are used for the digital input data, the SYNC signal (active high) and the IDC signal. They
are all internally terminated by 2 × 50 to ground via a 3.75 pF capacitor.
Figure8‐5. Digital data, SYNC and IDC input differential termination
Notes: 1. In the case when only two ports are used (2:1 MUX ratio), then the unused data can be left floating
(unconnected).
2. Data and IDC signals should be routed on board with the same layout rules and the same length than
the data
3. In case the SYNC is not used, it is recommended to bias the SYNC to 1.1V and SYNCN to 1.4V.
8.4 DSPClock
The DSP, DSPN output clock signals are LVDS compatible.
If not used, they have to be terminated via a differential 100 termination as described in the follow-
ing figure:
Figure8‐6. DSP output differential termination
LVDS Output
Buffer
In
InN
DAC Data and Sync Input Buffer
50Ω
50Ω
DGND
3.75 pF
50Ω line
50Ω line
1.25V
DAC Output DSP
Differential Output
buffers
Z0 = 50Ω
Z0 = 50Ω
100ΩTermination
DSP
DSPN
To Load
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8.5 Controlsignalsettings
The PSS and OCDS control signals use the same static input buffer.
Logic ‘1’ = 200 K to Ground, or tied to VCCD = 3.3V or left open
Logic ‘0’ = 10 to Ground or Grounded
Figure8‐7. Control signal output differential termination
The control signals can be driven by an FPGA.
Figure8‐8. Control signal settings with FPGA
Logic "1" > VIH or VCCD = 3.3V
Logic "0" < VIL or 0V
8.6 TVFControlsignal
The TVF control signal is a 3.3V CMOS output signal.
This signal could be acquired by FPGA.
Figure8‐9. Control signal settings with FPGA
In order to modify the VOL/VOH value, pull up and pull down resistor or a potential divider could be
used.
8.7 PowerSupplyDecouplingandBypassing
The DAC requires 3 distinct power supplies:
VCCA5 = 5.0V (for the analog core)
VCCA3 = 3.3V (for the analog part)
VCCD = 3.3V (for the digital part)
It is recommended to decouple all power supplies to ground as close as possible to the device balls with
100 pF in parallel to 10nF capacitors. The minimum number of decoupling pairs of capacitors can be
calculated as the minimum number of groups of neighbouring pins.
4 pairs of 100pF in parallel to 10 nF capacitors are required for the decoupling of VCCA5. 4 pairs for the
VCCA3 and 10 pairs are necessary for VCCD.
10Ω200 KΩ
GND GND
Control
Signal Pin
Control
Signal Pin
Control
Signal Pin
Not
Connected
Active Low Level (‘0’) Inactive High Level (‘1’)
Control
Signal Pin
FPGA
TVF Control Signal
FPGA
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Figure8‐10. Power Supplies Decoupling Scheme
Each power supply has to be bypassed as close as possible to its source and accessed by 100 nF in
parallel to 22 µF capacitors (the optimum value depends on the regulators).
8.8 Poweron/offrequirementandpoweronresetfunction
The DAC timing circuitry must be reset either by a power on reset (see below) or through the use of the
SYNC input to set it to the right state. Refer to Section 5.10 on page 39.
At power-up a reset pulse is internally and automatically generated when the following sequence is
satisfied: VCCD, VCCA3 then VCCA5.
This pulse has two effects:
• Resetting of the 3WSI interface registers to their default values.
• Synchronizing the timing circuitry.
To cancel the SYNC pulse at power-up, it is necessary to apply the sequence: VCCA5 then VCCA3 and VCCD.
Any other sequence may not have a deterministic SYNC behaviour but can be used.
There is no specific requirement to power down the device.
B B
VCCA5
VCCA3
B
B B
AGND
AGND
DGND
100 pF
10 nF
100 pF
10 nF
100 pF
10 nF
X 4 (min)
X 4 (min)
X 10 (min)
VCCD
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9. PACKAGEDESCRIPTION
9.1 fpBGA196Outline
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9.2 ThermalCharacteristics
Assumptions:
• Still air
• Pure conduction
• No radiation
• Heating zone = 8.9% of die surface
Rth Junction - bottom of Balls = 13°C/W
Rth Junction - board (JEDEC JESD-51-8) = 17.3°C/W
Rth Junction - top of case = 14°C/W
Assumptions:
• Heating zone = 8.9% of die surface
• Still air, JEDEC condition
Rth Junction - ambient (JEDEC) = 32.0 °C/W
The hot spot point is 6°C above the temperature given by the diode
10. ORDERINGINFORMATION
Table10‐1. Ordering Information
PartNumber Package TemperatureRange ScreeningLevel Comments
EVX12DS460AZPY FpBGA196 RoHS Ambient General Sample Prototype
EV12DS460ACZPY FpBGA196 RoHS 0°C < Tc, Tj < 90°C Commercial "C" Grade
EV12DS460AVZPY FpBGA196 RoHS –40°C < Tc, Tj < 110°C Industrial "V" Grade
EV12DS460AMZPY FpBGA196 RoHS –55°C < Tc, Tj < 125°C Military "M" Grade Refer to datasheet 1168
EV12DS460ACZP FpBGA196 0°C < Tc, Tj < 90°C Commercial "C" Grade
EV12DS460AVZP FpBGA196 –40°C < Tc, Tj < 110°C Industrial "V"Grade
EV12DS460AMZP FpBGA196 –55°C < Tc, Tj < 125°C Military "M" Grade Refer to datasheet 1168
EV12DS4xxAZPY-EB FpBGA196 RoHS Ambient Prototype Evaluation Board
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11. REVISIONHISTORY
This table provides revision history for this document.
Table11‐1. Revision History
Rev.No Date SubstantiveChange(s)
1167E July 2017
Section 3.3, Section 3.4 and Section 3.5: Master clock input jitter is integrated over 11GHz
bandwidth.
Table 5-10: clarification about MSB/LSB labels
Figure 8-3: differential sinewave source is 100 and not 50
1167D November 2016 Minor formatting corrections
1167C October 2016
BW = 7.5 GHz instead of 7.0 GHz
Table 3-5 and Table 3-7 : add SFDR and Pout performances with optimum RPB & RPW values
Add characterization results at 6.0 GSps and 7.0 GSps in Section 7.2
Add Section 7.4 about output rise and fall time
1167B July 2016 Datasheet completed with dynamic performances values and characterization data
illustrations.
1167AX November 2015 Initial Revision
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TableofContents
MAIN FEATURES ...................................................................................... 1
PERFORMANCES @ 6.0 GSps ................................................................ 1
1 Block Diagram .......................................................................................... 2
2 Description ............................................................................................... 2
3 Electrical characteristics ........................................................................ 3
3.1 Absolute Maximum ratings .......................................................................................3
3.2 Recommended conditions of use ............................................................................. 4
3.3 DC Electrical Characteristics .................................................................................... 5
3.4 AC Electrical Characteristics ....................................................................................7
3.5 Timing Characteristics and Switching Performances .............................................16
3.6 Explanation of Test Levels .....................................................................................18
3.7 Digital Input Coding Table ......................................................................................19
4 Definition of Terms ................................................................................ 20
5 Functional Description .......................................................................... 21
5.1 Multiplexer ..............................................................................................................22
5.2 Mode Function ........................................................................................................ 23
5.3 RPW and RPB Feature .......................................................................................... 27
5.4 Phase Shift Select function (PSS) ..........................................................................32
5.5 Output Clock Division Select function (OCDS) .......................................................33
5.6 Input Under Clocking Mode (IUCM) .......................................................................34
5.7 Synchronization FPGA-DAC: IDC_P, IDC_N and TVF function ............................37
5.8 DSP output clock ....................................................................................................38
5.9 OCDS, IUCM and MUX combinations summary ....................................................39
5.10 Synchronization function ......................................................................................39
5.11 Gain Adjust function ............................................................................................. 40
5.12 Diode function ......................................................................................................40
5.13 DAC 3WSI Description (DAC Controls) ................................................................ 41
6 Pin Description ...................................................................................... 47
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7 CHARACTERIZATION RESULTS .......................................................... 53
7.1 Static performances ............................................................................................... 53
7.2 AC performances ................................................................................................... 54
7.3 Input Data Set-up and Hold time vs Input Data Rate .............................................78
7.4 Analog output rise and fall time ..............................................................................78
8 Application information ........................................................................ 79
8.1 Analog output (OUT/OUTN) ................................................................................... 79
8.2 Clock Input (CLK/CLKN) ........................................................................................80
8.3 Digital Data, SYNC and IDC inputs ........................................................................ 81
8.4 DSP Clock ..............................................................................................................81
8.5 Control signal settings ............................................................................................82
8.6 TVF Control signal ..................................................................................................82
8.7 Power Supply Decoupling and Bypassing ..............................................................82
8.8 Power on/off requirement and power on reset function ..........................................83
9 Package Description ............................................................................. 84
9.1 fpBGA 196 Outline .................................................................................................84
9.2 Thermal Characteristics .........................................................................................85
10 Ordering Information ............................................................................. 85
11 Revision History .................................................................................... 86
